On 11/09/2019 15:42, Robin Murphy wrote:
> In principle, Midgard GPUs supporting smaller VA sizes should only
> require 3-level pagetables, since the address bits resolved at level 0
> (47:40) will never change. However, the kbase driver does not appear to
> have any notion of a variable start level, and empirically T720 and T820
> rapidly blow up with translation faults unless given a full 4-level
> table, despite only supporting a 33-bit VA size.
Midgard 'LPAE' isn't really LPAE and does indeed always require all
levels of page tables. The 33-bit VA size is really only limiting the
storage of virtual addresses in the GPU and not affecting the MMU.
> The 'real' IAS value is still valuable in terms of validating addresses
> on map/unmap, so tweak the allocator to allow smaller values while still
> forcing the resultant tables to the full 4 levels.
>
> Signed-off-by: Robin Murphy
Reviewed-by: Steven Price
Steve
> ---
> drivers/iommu/io-pgtable-arm.c | 7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
> index 9e35cd991f06..77f41c9dd9be 100644
> --- a/drivers/iommu/io-pgtable-arm.c
> +++ b/drivers/iommu/io-pgtable-arm.c
> @@ -1022,7 +1022,7 @@ arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg,
> void *cookie)
> if (cfg->quirks)
> return NULL;
>
> - if (cfg->ias != 48 || cfg->oas > 40)
> + if (cfg->ias > 48 || cfg->oas > 40)
> return NULL;
>
> cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
> @@ -1031,6 +1031,11 @@ arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg
> *cfg, void *cookie)
> if (!data)
> return NULL;
>
> + /* Mali seems to need a full 4-level table regardless of IAS */
> + if (data->levels < ARM_LPAE_MAX_LEVELS) {
> + data->levels = ARM_LPAE_MAX_LEVELS;
> + data->pgd_size = sizeof(arm_lpae_iopte);
> + }
> /*
>* MEMATTR: Mali has no actual notion of a non-cacheable type, so the
>* best we can do is mimic the out-of-tree driver and hope that the
>
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