On 11/09/2019 15:42, Robin Murphy wrote:
> Midgard GPUs have ACE-Lite master interfaces which allows systems to
> integrate them in an I/O-coherent manner. It seems that from the GPU's
> viewpoint, the rest of the system is its outer shareable domain, and it
> will only emit snoop signals for outer shareable accesses. As such,
> setting the TTBR_SHARE_OUTER bit does indeed get coherent pagetable
> walks working nicely.
>
> Making data accesses coherent seems to be more of a challenge...
>
> Signed-off-by: Robin Murphy
Reviewed-by: Steven Price
Note the terminology in the GPU is *very* confusing here. Midgard refers
to the system's inner shareable domain as "outer shareable", and uses
"inner shareable" to mean purely within the GPU.
For data access kbase sets up a different default MEMATTR if ACE is
available:
/* Set to implementation defined, outer caching */
#define AS_MEMATTR_LPAE_OUTER_IMPL_DEF0x88ull
[...]
#define AS_MEMATTR_INDEX_DEFAULT_ACE 3
[...]
/* Outer coherent, inner implementation defined policy */
#define AS_MEMATTR_INDEX_OUTER_IMPL_DEF3
Steve
> ---
> drivers/iommu/io-pgtable-arm.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
> index 77f41c9dd9be..2794d4661339 100644
> --- a/drivers/iommu/io-pgtable-arm.c
> +++ b/drivers/iommu/io-pgtable-arm.c
> @@ -1061,6 +1061,9 @@ arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg,
> void *cookie)
> cfg->arm_mali_lpae_cfg.transtab = virt_to_phys(data->pgd) |
> ARM_MALI_LPAE_TTBR_READ_INNER |
> ARM_MALI_LPAE_TTBR_ADRMODE_TABLE;
> + if (cfg->coherent_walk)
> + cfg->arm_mali_lpae_cfg.transtab |=
> ARM_MALI_LPAE_TTBR_SHARE_OUTER;
> +
> return &data->iop;
>
> out_free_data:
>
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