[PATCH 3/6] iommu/qcom: Properly reset the IOMMU context
From: AngeloGioacchino Del Regno
To avoid context faults reset the context entirely on detach and
to ensure a fresh clean start also do a complete reset before
programming the context for domain initialization.
Signed-off-by: AngeloGioacchino Del Regno
Signed-off-by: Marijn Suijten
Signed-off-by: Konrad Dybcio
---
drivers/iommu/arm/arm-smmu/qcom_iommu.c | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c
b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
index 75f353866c40..129e322f56a6 100644
--- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c
+++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
@@ -223,6 +223,23 @@ static irqreturn_t qcom_iommu_fault(int irq, void *dev)
return IRQ_HANDLED;
}
+static void qcom_iommu_reset_ctx(struct qcom_iommu_ctx *ctx)
+{
+ iommu_writel(ctx, ARM_SMMU_CB_FAR, 0);
+ iommu_writel(ctx, ARM_SMMU_CB_FSR, 0);
+ iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR1, 0);
+ iommu_writel(ctx, ARM_SMMU_CB_PAR, 0);
+ iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR0, 0);
+ iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0);
+ iommu_writel(ctx, ARM_SMMU_CB_TCR2, 0);
+ iommu_writel(ctx, ARM_SMMU_CB_TCR, 0);
+ iommu_writeq(ctx, ARM_SMMU_CB_TTBR0, 0);
+ iommu_writeq(ctx, ARM_SMMU_CB_TTBR1, 0);
+
+ /* Should we issue a TLBSYNC there instead? */
+ wmb();
+}
+
static int qcom_iommu_init_domain(struct iommu_domain *domain,
struct qcom_iommu_dev *qcom_iommu,
struct device *dev)
@@ -273,6 +290,8 @@ static int qcom_iommu_init_domain(struct iommu_domain
*domain,
ctx->secure_init = true;
}
+ qcom_iommu_reset_ctx(ctx);
+
/* TCR */
iommu_writel(ctx, ARM_SMMU_CB_TCR2,
arm_smmu_lpae_tcr2(&pgtbl_cfg));
@@ -406,8 +425,8 @@ static void qcom_iommu_detach_dev(struct iommu_domain
*domain, struct device *de
for (i = 0; i < fwspec->num_ids; i++) {
struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain,
fwspec->ids[i]);
- /* Disable the context bank: */
- iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0);
+ /* Disable and reset the context bank */
+ qcom_iommu_reset_ctx(ctx);
ctx->domain = NULL;
}
--
2.36.1
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[PATCH 3/6] iommu/qcom: Properly reset the IOMMU context
From: AngeloGioacchino Del Regno
To avoid context faults reset the context entirely on detach and
to ensure a fresh clean start also do a complete reset before
programming the context for domain initialization.
Signed-off-by: AngeloGioacchino Del Regno
---
drivers/iommu/qcom_iommu.c | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/qcom_iommu.c b/drivers/iommu/qcom_iommu.c
index 8431fb97a50f..2f31da2e7add 100644
--- a/drivers/iommu/qcom_iommu.c
+++ b/drivers/iommu/qcom_iommu.c
@@ -198,6 +198,23 @@ static irqreturn_t qcom_iommu_fault(int irq, void *dev)
return IRQ_HANDLED;
}
+static void qcom_iommu_reset_ctx(struct qcom_iommu_ctx *ctx)
+{
+ iommu_writel(ctx, ARM_SMMU_CB_FAR, 0);
+ iommu_writel(ctx, ARM_SMMU_CB_FSR, 0);
+ iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR1, 0);
+ iommu_writel(ctx, ARM_SMMU_CB_PAR, 0);
+ iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR0, 0);
+ iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0);
+ iommu_writel(ctx, ARM_SMMU_CB_TCR2, 0);
+ iommu_writel(ctx, ARM_SMMU_CB_TCR, 0);
+ iommu_writeq(ctx, ARM_SMMU_CB_TTBR0, 0);
+ iommu_writeq(ctx, ARM_SMMU_CB_TTBR1, 0);
+
+ /* Should we issue a TLBSYNC there instead? */
+ mb();
+}
+
static int qcom_iommu_init_domain(struct iommu_domain *domain,
struct qcom_iommu_dev *qcom_iommu,
struct iommu_fwspec *fwspec)
@@ -245,6 +262,8 @@ static int qcom_iommu_init_domain(struct iommu_domain
*domain,
ctx->secure_init = true;
}
+ qcom_iommu_reset_ctx(ctx);
+
/* TCR */
iommu_writel(ctx, ARM_SMMU_CB_TCR2,
(pgtbl_cfg.arm_lpae_s1_cfg.tcr >> 32) |
@@ -390,8 +409,8 @@ static void qcom_iommu_detach_dev(struct iommu_domain
*domain, struct device *de
for (i = 0; i < fwspec->num_ids; i++) {
struct qcom_iommu_ctx *ctx = to_ctx(fwspec, fwspec->ids[i]);
- /* Disable the context bank: */
- iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0);
+ /* Disable and reset the context bank */
+ qcom_iommu_reset_ctx(ctx);
ctx->domain = NULL;
}
--
2.21.0
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