Re: [PATCH v12 2/2] iommu/mediatek: Allow page table PA up to 35bit

2022-07-04 Thread Yong Wu via iommu 
On Thu, 2022-06-30 at 17:29 +0800, yf.w...@mediatek.com wrote:
> From: Yunfei Wang 
> 
> Single memory zone feature will remove ZONE_DMA32 and ZONE_DMA. So
> add
> the quirk IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT to let level 1 and level
> 2
> pgtable support at most 35bit PA.
> 
> Signed-off-by: Ning Li 
> Signed-off-by: Yunfei Wang 

Reviewed-by: Yong Wu 

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Re: [PATCH v12 2/2] iommu/mediatek: Allow page table PA up to 35bit

2022-06-30 Thread Robin Murphy 

On 2022-06-30 10:29, yf.w...@mediatek.com wrote:

From: Yunfei Wang 

Single memory zone feature will remove ZONE_DMA32 and ZONE_DMA. So add
the quirk IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT to let level 1 and level 2
pgtable support at most 35bit PA.


FWIW,

Reviewed-by: Robin Murphy 


Signed-off-by: Ning Li 
Signed-off-by: Yunfei Wang 
---
  drivers/iommu/mtk_iommu.c | 13 +++--
  1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index bb9dd92c9898..3b9f4bdb15b7 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -34,7 +34,6 @@
  #include 
  
  #define REG_MMU_PT_BASE_ADDR			0x000

-#define MMU_PT_ADDR_MASK   GENMASK(31, 7)
  
  #define REG_MMU_INVALIDATE			0x020

  #define F_ALL_INVLD   0x2
@@ -138,6 +137,7 @@
  /* PM and clock always on. e.g. infra iommu */
  #define PM_CLK_AO BIT(15)
  #define IFA_IOMMU_PCIE_SUPPORTBIT(16)
+#define PGTABLE_PA_35_EN   BIT(17)
  
  #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask)	\

pdata)->flags) & (mask)) == (_x))
@@ -596,6 +596,9 @@ static int mtk_iommu_domain_finalise(struct 
mtk_iommu_domain *dom,
.iommu_dev = data->dev,
};
  
+	if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN))

+   dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT;
+
if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE))
dom->cfg.oas = data->enable_4GB ? 33 : 32;
else
@@ -684,8 +687,7 @@ static int mtk_iommu_attach_device(struct iommu_domain 
*domain,
goto err_unlock;
}
bank->m4u_dom = dom;
-   writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK,
-  bank->base + REG_MMU_PT_BASE_ADDR);
+   writel(dom->cfg.arm_v7s_cfg.ttbr, bank->base + 
REG_MMU_PT_BASE_ADDR);
  
  		pm_runtime_put(m4udev);

}
@@ -1366,8 +1368,7 @@ static int __maybe_unused mtk_iommu_runtime_resume(struct 
device *dev)
writel_relaxed(reg->int_control[i], base + 
REG_MMU_INT_CONTROL0);
writel_relaxed(reg->int_main_control[i], base + 
REG_MMU_INT_MAIN_CONTROL);
writel_relaxed(reg->ivrp_paddr[i], base + REG_MMU_IVRP_PADDR);
-   writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK,
-  base + REG_MMU_PT_BASE_ADDR);
+   writel(m4u_dom->cfg.arm_v7s_cfg.ttbr, base + 
REG_MMU_PT_BASE_ADDR);
} while (++i < data->plat_data->banks_num);
  
  	/*

@@ -1401,7 +1402,7 @@ static const struct mtk_iommu_plat_data mt2712_data = {
  static const struct mtk_iommu_plat_data mt6779_data = {
.m4u_plat  = M4U_MT6779,
.flags = HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | WR_THROT_EN |
-MTK_IOMMU_TYPE_MM,
+MTK_IOMMU_TYPE_MM | PGTABLE_PA_35_EN,
.inv_sel_reg   = REG_MMU_INV_SEL_GEN2,
.banks_num= 1,
.banks_enable = {true},

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[PATCH v12 2/2] iommu/mediatek: Allow page table PA up to 35bit

2022-06-30 Thread yf.wang--- via iommu 
From: Yunfei Wang 

Single memory zone feature will remove ZONE_DMA32 and ZONE_DMA. So add
the quirk IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT to let level 1 and level 2
pgtable support at most 35bit PA.

Signed-off-by: Ning Li 
Signed-off-by: Yunfei Wang 
---
 drivers/iommu/mtk_iommu.c | 13 +++--
 1 file changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index bb9dd92c9898..3b9f4bdb15b7 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -34,7 +34,6 @@
 #include 
 
 #define REG_MMU_PT_BASE_ADDR   0x000
-#define MMU_PT_ADDR_MASK   GENMASK(31, 7)
 
 #define REG_MMU_INVALIDATE 0x020
 #define F_ALL_INVLD0x2
@@ -138,6 +137,7 @@
 /* PM and clock always on. e.g. infra iommu */
 #define PM_CLK_AO  BIT(15)
 #define IFA_IOMMU_PCIE_SUPPORT BIT(16)
+#define PGTABLE_PA_35_EN   BIT(17)
 
 #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask)   \
pdata)->flags) & (mask)) == (_x))
@@ -596,6 +596,9 @@ static int mtk_iommu_domain_finalise(struct 
mtk_iommu_domain *dom,
.iommu_dev = data->dev,
};
 
+   if (MTK_IOMMU_HAS_FLAG(data->plat_data, PGTABLE_PA_35_EN))
+   dom->cfg.quirks |= IO_PGTABLE_QUIRK_ARM_MTK_TTBR_EXT;
+
if (MTK_IOMMU_HAS_FLAG(data->plat_data, HAS_4GB_MODE))
dom->cfg.oas = data->enable_4GB ? 33 : 32;
else
@@ -684,8 +687,7 @@ static int mtk_iommu_attach_device(struct iommu_domain 
*domain,
goto err_unlock;
}
bank->m4u_dom = dom;
-   writel(dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK,
-  bank->base + REG_MMU_PT_BASE_ADDR);
+   writel(dom->cfg.arm_v7s_cfg.ttbr, bank->base + 
REG_MMU_PT_BASE_ADDR);
 
pm_runtime_put(m4udev);
}
@@ -1366,8 +1368,7 @@ static int __maybe_unused mtk_iommu_runtime_resume(struct 
device *dev)
writel_relaxed(reg->int_control[i], base + 
REG_MMU_INT_CONTROL0);
writel_relaxed(reg->int_main_control[i], base + 
REG_MMU_INT_MAIN_CONTROL);
writel_relaxed(reg->ivrp_paddr[i], base + REG_MMU_IVRP_PADDR);
-   writel(m4u_dom->cfg.arm_v7s_cfg.ttbr & MMU_PT_ADDR_MASK,
-  base + REG_MMU_PT_BASE_ADDR);
+   writel(m4u_dom->cfg.arm_v7s_cfg.ttbr, base + 
REG_MMU_PT_BASE_ADDR);
} while (++i < data->plat_data->banks_num);
 
/*
@@ -1401,7 +1402,7 @@ static const struct mtk_iommu_plat_data mt2712_data = {
 static const struct mtk_iommu_plat_data mt6779_data = {
.m4u_plat  = M4U_MT6779,
.flags = HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN | WR_THROT_EN |
-MTK_IOMMU_TYPE_MM,
+MTK_IOMMU_TYPE_MM | PGTABLE_PA_35_EN,
.inv_sel_reg   = REG_MMU_INV_SEL_GEN2,
.banks_num= 1,
.banks_enable = {true},
-- 
2.18.0

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