Re: [PATCH] Documentation: x86: rework IOMMU documentation
Joerg Roedel writes: > Acked-by: Joerg Roedel > > Jonathan, will you merge that through the documentation tree? Done. Thanks, jon ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH] Documentation: x86: rework IOMMU documentation
On Fri, Apr 22, 2022 at 04:06:07PM -0400, Alex Deucher wrote: > Add preliminary documentation for AMD IOMMU and combine > with the existing Intel IOMMU documentation and clean > up and modernize some of the existing documentation to > align with the current state of the kernel. > > Signed-off-by: Alex Deucher > --- > > V2: Incorporate feedback from Robin to clarify IOMMU vs DMA engine (e.g., > a device) and document proper DMA API. Also correct the fact that > the AMD IOMMU is not limited to managing PCI devices. > v3: Fix spelling and rework text as suggested by Vasant > v4: Combine Intel and AMD documents into a single document as suggested > by Dave Hansen > v5: Clarify that keywords are related to ACPI, grammatical fixes > v6: Make more stuff common based on feedback from Robin > > Documentation/x86/index.rst | 2 +- > Documentation/x86/intel-iommu.rst | 115 > Documentation/x86/iommu.rst | 143 ++ > 3 files changed, 144 insertions(+), 116 deletions(-) > delete mode 100644 Documentation/x86/intel-iommu.rst > create mode 100644 Documentation/x86/iommu.rst Acked-by: Joerg Roedel Jonathan, will you merge that through the documentation tree? ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
RE: [PATCH] Documentation: x86: rework IOMMU documentation
[Public] > -Original Message- > From: Jacob Pan > Sent: Tuesday, April 26, 2022 12:45 PM > To: Deucher, Alexander > Cc: linux-...@vger.kernel.org; linux-ker...@vger.kernel.org; > cor...@lwn.net; h...@zytor.com; x...@kernel.org; > dave.han...@linux.intel.com; b...@alien8.de; mi...@redhat.com; > t...@linutronix.de; j...@8bytes.org; Suthikulpanit, Suravee > ; w...@kernel.org; iommu@lists.linux- > foundation.org; robin.mur...@arm.com; Hegde, Vasant > ; jacob.jun@intel.com; Lu, Baolu > > Subject: Re: [PATCH] Documentation: x86: rework IOMMU documentation > > Hi Alex, > > Thanks for doing this, really helps to catch up the current state. Please see > my > comments inline. > > On Fri, 22 Apr 2022 16:06:07 -0400, Alex Deucher > wrote: > > > Add preliminary documentation for AMD IOMMU and combine with the > > existing Intel IOMMU documentation and clean up and modernize some of > > the existing documentation to align with the current state of the > > kernel. > > > > Signed-off-by: Alex Deucher > > --- > > > > V2: Incorporate feedback from Robin to clarify IOMMU vs DMA engine (e.g., > > a device) and document proper DMA API. Also correct the fact that > > the AMD IOMMU is not limited to managing PCI devices. > > v3: Fix spelling and rework text as suggested by Vasant > > v4: Combine Intel and AMD documents into a single document as suggested > > by Dave Hansen > > v5: Clarify that keywords are related to ACPI, grammatical fixes > > v6: Make more stuff common based on feedback from Robin > > > > Documentation/x86/index.rst | 2 +- > > Documentation/x86/intel-iommu.rst | 115 > > Documentation/x86/iommu.rst | 143 > ++ > > 3 files changed, 144 insertions(+), 116 deletions(-) delete mode > > 100644 Documentation/x86/intel-iommu.rst create mode 100644 > > Documentation/x86/iommu.rst > > > > diff --git a/Documentation/x86/index.rst b/Documentation/x86/index.rst > > index f498f1d36cd3..6f8409fe0674 100644 > > --- a/Documentation/x86/index.rst > > +++ b/Documentation/x86/index.rst > > @@ -21,7 +21,7 @@ x86-specific Documentation > > tlb > > mtrr > > pat > > - intel-iommu > > + iommu > > intel_txt > > amd-memory-encryption > > pti > > diff --git a/Documentation/x86/intel-iommu.rst > > b/Documentation/x86/intel-iommu.rst deleted file mode 100644 index > > 099f13d51d5f.. > > --- a/Documentation/x86/intel-iommu.rst > > +++ /dev/null > > @@ -1,115 +0,0 @@ > > -=== > > -Linux IOMMU Support > > -=== > > - > > -The architecture spec can be obtained from the below location. > > - > > - > https://nam11.safelinks.protection.outlook.com/?url=http%3A%2F%2Fwww. > > > intel.com%2Fcontent%2Fdam%2Fwww%2Fpublic%2Fus%2Fen%2Fdocuments > %2Fprodu > > ct-specifications%2Fvt-directed-io- > spec.pdf&data=05%7C01%7Calexand > > > er.deucher%40amd.com%7C929847a4b2524432d1a608da27a3c9b0%7C3dd > 8961fe488 > > > 4e608e11a82d994e183d%7C0%7C0%7C637865881851295857%7CUnknow > n%7CTWFpbGZs > > > b3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0 > %3D > > > %7C3000%7C%7C%7C&sdata=KaPkvBSHWbn1cKBRzyk9H%2BuNDll%2Bq > 3wPfR3SFVA > > LwkU%3D&reserved=0 > > - > > -This guide gives a quick cheat sheet for some basic understanding. > > - > > -Some Keywords > > - > > -- DMAR - DMA remapping > > -- DRHD - DMA Remapping Hardware Unit Definition > > -- RMRR - Reserved memory Region Reporting Structure > > -- ZLR - Zero length reads from PCI devices > > -- IOVA - IO Virtual address. > > - > I feel this combined document only focus on IOVA and DMA APIs, it is > considered as legacy DMA after scalable mode is introduced by Intel to > support DMA with PASID, shared virtual addressing (SVA). > Perhaps, we can also combine ./Documentation/x86/sva.rst I think it would make sense to take that up in a separate patch set. > > With scalable mode, it affects boot messages, fault reporting, etc. I am not > saying no to this document, just suggesting. I don't know where AMD is at in > terms of PASID support but there are lots of things in common between VT-d > and ARM's SMMU in terms of PASID/SVA. Should we broaden the purpose of > this document even further? I think that would make sense for a future clean up. I'd like to land the current clean up first. AMD's IOMMU driver has supported PASID for probably 8
Re: [PATCH] Documentation: x86: rework IOMMU documentation
Hi Alex, Thanks for doing this, really helps to catch up the current state. Please see my comments inline. On Fri, 22 Apr 2022 16:06:07 -0400, Alex Deucher wrote: > Add preliminary documentation for AMD IOMMU and combine > with the existing Intel IOMMU documentation and clean > up and modernize some of the existing documentation to > align with the current state of the kernel. > > Signed-off-by: Alex Deucher > --- > > V2: Incorporate feedback from Robin to clarify IOMMU vs DMA engine (e.g., > a device) and document proper DMA API. Also correct the fact that > the AMD IOMMU is not limited to managing PCI devices. > v3: Fix spelling and rework text as suggested by Vasant > v4: Combine Intel and AMD documents into a single document as suggested > by Dave Hansen > v5: Clarify that keywords are related to ACPI, grammatical fixes > v6: Make more stuff common based on feedback from Robin > > Documentation/x86/index.rst | 2 +- > Documentation/x86/intel-iommu.rst | 115 > Documentation/x86/iommu.rst | 143 ++ > 3 files changed, 144 insertions(+), 116 deletions(-) > delete mode 100644 Documentation/x86/intel-iommu.rst > create mode 100644 Documentation/x86/iommu.rst > > diff --git a/Documentation/x86/index.rst b/Documentation/x86/index.rst > index f498f1d36cd3..6f8409fe0674 100644 > --- a/Documentation/x86/index.rst > +++ b/Documentation/x86/index.rst > @@ -21,7 +21,7 @@ x86-specific Documentation > tlb > mtrr > pat > - intel-iommu > + iommu > intel_txt > amd-memory-encryption > pti > diff --git a/Documentation/x86/intel-iommu.rst > b/Documentation/x86/intel-iommu.rst deleted file mode 100644 > index 099f13d51d5f.. > --- a/Documentation/x86/intel-iommu.rst > +++ /dev/null > @@ -1,115 +0,0 @@ > -=== > -Linux IOMMU Support > -=== > - > -The architecture spec can be obtained from the below location. > - > -http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/vt-directed-io-spec.pdf > - > -This guide gives a quick cheat sheet for some basic understanding. > - > -Some Keywords > - > -- DMAR - DMA remapping > -- DRHD - DMA Remapping Hardware Unit Definition > -- RMRR - Reserved memory Region Reporting Structure > -- ZLR - Zero length reads from PCI devices > -- IOVA - IO Virtual address. > - I feel this combined document only focus on IOVA and DMA APIs, it is considered as legacy DMA after scalable mode is introduced by Intel to support DMA with PASID, shared virtual addressing (SVA). Perhaps, we can also combine ./Documentation/x86/sva.rst With scalable mode, it affects boot messages, fault reporting, etc. I am not saying no to this document, just suggesting. I don't know where AMD is at in terms of PASID support but there are lots of things in common between VT-d and ARM's SMMU in terms of PASID/SVA. Should we broaden the purpose of this document even further? > -Basic stuff > > - > -ACPI enumerates and lists the different DMA engines in the platform, and > -device scope relationships between PCI devices and which DMA engine > controls -them. > - > -What is RMRR? > -- > - > -There are some devices the BIOS controls, for e.g USB devices to perform > -PS2 emulation. The regions of memory used for these devices are marked > -reserved in the e820 map. When we turn on DMA translation, DMA to those > -regions will fail. Hence BIOS uses RMRR to specify these regions along > with -devices that need to access these regions. OS is expected to setup > -unity mappings for these regions for these devices to access these > regions. - > -How is IOVA generated? > --- > - > -Well behaved drivers call pci_map_*() calls before sending command to > device -that needs to perform DMA. Once DMA is completed and mapping is > no longer -required, device performs a pci_unmap_*() calls to unmap the > region. - > -The Intel IOMMU driver allocates a virtual address per domain. Each PCIE > -device has its own domain (hence protection). Devices under p2p bridges > -share the virtual address with all devices under the p2p bridge due to > -transaction id aliasing for p2p bridges. > - > -IOVA generation is pretty generic. We used the same technique as > vmalloc() -but these are not global address spaces, but separate for each > domain. -Different DMA engines may support different number of domains. > - > -We also allocate guard pages with each mapping, so we can attempt to > catch -any overflow that might happen. > - > - > -Graphics Problems? > --- > -If you encounter issues with graphics devices, you can try adding > -option intel_iommu=igfx_off to turn off the integrated graphics engine. > -If this fixes anything, please ensure you file a bug reporting the > problem. - > -Some exceptions to IOVA > > -Interrupt ranges are not address translated, (0xfee0 - 0xfeef). >
Re: [PATCH] Documentation: x86: rework IOMMU documentation
On 2022-04-22 21:06, Alex Deucher wrote: Add preliminary documentation for AMD IOMMU and combine with the existing Intel IOMMU documentation and clean up and modernize some of the existing documentation to align with the current state of the kernel. FWIW, Reviewed-by: Robin Murphy Signed-off-by: Alex Deucher --- V2: Incorporate feedback from Robin to clarify IOMMU vs DMA engine (e.g., a device) and document proper DMA API. Also correct the fact that the AMD IOMMU is not limited to managing PCI devices. v3: Fix spelling and rework text as suggested by Vasant v4: Combine Intel and AMD documents into a single document as suggested by Dave Hansen v5: Clarify that keywords are related to ACPI, grammatical fixes v6: Make more stuff common based on feedback from Robin Documentation/x86/index.rst | 2 +- Documentation/x86/intel-iommu.rst | 115 Documentation/x86/iommu.rst | 143 ++ 3 files changed, 144 insertions(+), 116 deletions(-) delete mode 100644 Documentation/x86/intel-iommu.rst create mode 100644 Documentation/x86/iommu.rst diff --git a/Documentation/x86/index.rst b/Documentation/x86/index.rst index f498f1d36cd3..6f8409fe0674 100644 --- a/Documentation/x86/index.rst +++ b/Documentation/x86/index.rst @@ -21,7 +21,7 @@ x86-specific Documentation tlb mtrr pat - intel-iommu + iommu intel_txt amd-memory-encryption pti diff --git a/Documentation/x86/intel-iommu.rst b/Documentation/x86/intel-iommu.rst deleted file mode 100644 index 099f13d51d5f.. --- a/Documentation/x86/intel-iommu.rst +++ /dev/null @@ -1,115 +0,0 @@ -=== -Linux IOMMU Support -=== - -The architecture spec can be obtained from the below location. - -http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/vt-directed-io-spec.pdf - -This guide gives a quick cheat sheet for some basic understanding. - -Some Keywords - -- DMAR - DMA remapping -- DRHD - DMA Remapping Hardware Unit Definition -- RMRR - Reserved memory Region Reporting Structure -- ZLR - Zero length reads from PCI devices -- IOVA - IO Virtual address. - -Basic stuff - -ACPI enumerates and lists the different DMA engines in the platform, and -device scope relationships between PCI devices and which DMA engine controls -them. - -What is RMRR? -- - -There are some devices the BIOS controls, for e.g USB devices to perform -PS2 emulation. The regions of memory used for these devices are marked -reserved in the e820 map. When we turn on DMA translation, DMA to those -regions will fail. Hence BIOS uses RMRR to specify these regions along with -devices that need to access these regions. OS is expected to setup -unity mappings for these regions for these devices to access these regions. - -How is IOVA generated? --- - -Well behaved drivers call pci_map_*() calls before sending command to device -that needs to perform DMA. Once DMA is completed and mapping is no longer -required, device performs a pci_unmap_*() calls to unmap the region. - -The Intel IOMMU driver allocates a virtual address per domain. Each PCIE -device has its own domain (hence protection). Devices under p2p bridges -share the virtual address with all devices under the p2p bridge due to -transaction id aliasing for p2p bridges. - -IOVA generation is pretty generic. We used the same technique as vmalloc() -but these are not global address spaces, but separate for each domain. -Different DMA engines may support different number of domains. - -We also allocate guard pages with each mapping, so we can attempt to catch -any overflow that might happen. - - -Graphics Problems? --- -If you encounter issues with graphics devices, you can try adding -option intel_iommu=igfx_off to turn off the integrated graphics engine. -If this fixes anything, please ensure you file a bug reporting the problem. - -Some exceptions to IOVA -Interrupt ranges are not address translated, (0xfee0 - 0xfeef). -The same is true for peer to peer transactions. Hence we reserve the -address from PCI MMIO ranges so they are not allocated for IOVA addresses. - - -Fault reporting -When errors are reported, the DMA engine signals via an interrupt. The fault -reason and device that caused it with fault reason is printed on console. - -See below for sample. - - -Boot Message Sample - -Something like this gets printed indicating presence of DMAR tables -in ACPI. - -ACPI: DMAR (v001 A M I OEMDMAR 0x0001 MSFT 0x0097) @ 0x7f5b5ef0 - -When DMAR is being processed and initialized by ACPI, prints DMAR locations -and any RMRR's processed:: - - ACPI DMAR:Host address width 36 - ACPI DMAR:DRHD (flags: 0x)base: 0xfed9 - ACPI DMAR:DRHD (flags: 0x)base: 0xfed91000 - ACP
