Re: [PATCH] iommu/dma: Add support for DMA_ATTR_SYS_CACHE
The definition makes very little sense. Any without a user in the same series it is a complete no-go anyway. ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH] iommu/dma: Add support for DMA_ATTR_SYS_CACHE
On 2019-10-25 22:30, Christoph Hellwig wrote: The definition makes very little sense. Can you please clarify what part doesn’t make sense, and why? This is really just an extension of this patch that got mainlined, so that clients that use the DMA API can use IOMMU_QCOM_SYS_CACHE as well: https://patchwork.kernel.org/patch/10946099/ Any without a user in the same series it is a complete no-go anyway. IOMMU_QCOM_SYS_CACHE does not have any current users in the mainline, nor did it have it in the patch series in which it got merged, yet it is still present? Furthermore, there are plans to upstream support for one of our SoCs that may benefit from this, as seen here: https://www.spinics.net/lists/iommu/msg39608.html. Thanks, Isaac ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH] iommu/dma: Add support for DMA_ATTR_SYS_CACHE
On Sat, Oct 26, 2019 at 03:12:57AM -0700, isa...@codeaurora.org wrote: > On 2019-10-25 22:30, Christoph Hellwig wrote: >> The definition makes very little sense. > Can you please clarify what part doesn’t make sense, and why? It looks like complete garbage to me. That might just be because it uses tons of terms I've never heard of of and which aren't used anywhere in the DMA API. It also might be because it doesn't explain how the flag might actually be practically useful. > This is > really just an extension of this patch that got mainlined, so that clients > that use the DMA API can use IOMMU_QCOM_SYS_CACHE as well: > https://patchwork.kernel.org/patch/10946099/ >> Any without a user in the same series it is a complete no-go anyway. > IOMMU_QCOM_SYS_CACHE does not have any current users in the mainline, nor > did it have it in the patch series in which it got merged, yet it is still > present? Furthermore, there are plans to upstream support for one of our > SoCs that may benefit from this, as seen here: > https://www.spinics.net/lists/iommu/msg39608.html. Which means it should have never been merged. As a general policy we do not add code to the Linux kernel without actual users. ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH] iommu/dma: Add support for DMA_ATTR_SYS_CACHE
Hi Christoph, On Mon, Oct 28, 2019 at 08:41:56AM +0100, Christoph Hellwig wrote: > On Sat, Oct 26, 2019 at 03:12:57AM -0700, isa...@codeaurora.org wrote: > > On 2019-10-25 22:30, Christoph Hellwig wrote: > >> The definition makes very little sense. > > Can you please clarify what part doesn’t make sense, and why? > > It looks like complete garbage to me. That might just be because it > uses tons of terms I've never heard of of and which aren't used anywhere > in the DMA API. It also might be because it doesn't explain how the > flag might actually be practically useful. Agreed. The way I /think/ it works is that on many SoCs there is a system/last-level cache (LLC) which effectively sits in front of memory for all masters. Even if a device isn't coherent with the CPU caches, we still want to be able to allocate into the LLC. Why this doesn't happen automatically is beyond me, but it appears that on these Qualcomm designs you actually have to set the memory attributes up in the page-table to ensure that the resulting memory transactions are non-cacheable for the CPU but cacheable for the LLC. Without any changes, the transactions are non-cacheable in both of them which assumedly has a performance cost. But you can see that I'm piecing things together myself here. Isaac? > > This is > > really just an extension of this patch that got mainlined, so that clients > > that use the DMA API can use IOMMU_QCOM_SYS_CACHE as well: > > https://patchwork.kernel.org/patch/10946099/ > >> Any without a user in the same series it is a complete no-go anyway. > > IOMMU_QCOM_SYS_CACHE does not have any current users in the mainline, nor > > did it have it in the patch series in which it got merged, yet it is still > > present? Furthermore, there are plans to upstream support for one of our > > SoCs that may benefit from this, as seen here: > > https://www.spinics.net/lists/iommu/msg39608.html. > > Which means it should have never been merged. As a general policy we do > not add code to the Linux kernel without actual users. Yes, in this case I was hoping a user would materialise via a different tree, but it didn't happen, hence my post last week about removing this altogether: https://lore.kernel.org/linux-iommu/20191024153832.ga7...@jcrouse1-lnx.qualcomm.com/T/#t which I suspect prompted this patch that unfortunately fails to solve the problem. Will ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH] iommu/dma: Add support for DMA_ATTR_SYS_CACHE
On Mon, Oct 28, 2019 at 11:24:58AM +, Will Deacon wrote: > Agreed. The way I /think/ it works is that on many SoCs there is a > system/last-level cache (LLC) which effectively sits in front of memory for > all masters. Even if a device isn't coherent with the CPU caches, we still > want to be able to allocate into the LLC. Why this doesn't happen > automatically is beyond me, but it appears that on these Qualcomm designs > you actually have to set the memory attributes up in the page-table to > ensure that the resulting memory transactions are non-cacheable for the CPU > but cacheable for the LLC. Without any changes, the transactions are > non-cacheable in both of them which assumedly has a performance cost. > > But you can see that I'm piecing things together myself here. Isaac? If that is the case it sounds like we'd want to drive this through DT properties, not the driver API. But again, without an actual consumer it pretty much is a moot point anyway. ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH] iommu/dma: Add support for DMA_ATTR_SYS_CACHE
On 28/10/2019 11:24, Will Deacon wrote: Hi Christoph, On Mon, Oct 28, 2019 at 08:41:56AM +0100, Christoph Hellwig wrote: On Sat, Oct 26, 2019 at 03:12:57AM -0700, isa...@codeaurora.org wrote: On 2019-10-25 22:30, Christoph Hellwig wrote: The definition makes very little sense. Can you please clarify what part doesn’t make sense, and why? It looks like complete garbage to me. That might just be because it uses tons of terms I've never heard of of and which aren't used anywhere in the DMA API. It also might be because it doesn't explain how the flag might actually be practically useful. Agreed. The way I /think/ it works is that on many SoCs there is a system/last-level cache (LLC) which effectively sits in front of memory for all masters. Even if a device isn't coherent with the CPU caches, we still want to be able to allocate into the LLC. Why this doesn't happen automatically is beyond me, but it appears that on these Qualcomm designs you actually have to set the memory attributes up in the page-table to ensure that the resulting memory transactions are non-cacheable for the CPU but cacheable for the LLC. Without any changes, the transactions are non-cacheable in both of them which assumedly has a performance cost. But you can see that I'm piecing things together myself here. Isaac? FWIW, that's pretty much how Pratik and Jordan explained it to me - the LLC sits directly in front of memory and is more or less transparent, although it might treat CPU and device accesses slightly differently (I don't remember exactly how the inner cacheablility attribute interacts). Certain devices don't get much benefit from the LLC, hence the desire for finer-grained control of their outer allocation policy to avoid more thrashing than necessary. Furthermore, for stuff in the video/GPU/display area certain jobs benefit more than others, hence the desire to go even finer-grained than a per-device control in order to maximise LLC effectiveness. Robin. This is really just an extension of this patch that got mainlined, so that clients that use the DMA API can use IOMMU_QCOM_SYS_CACHE as well: https://patchwork.kernel.org/patch/10946099/ Any without a user in the same series it is a complete no-go anyway. IOMMU_QCOM_SYS_CACHE does not have any current users in the mainline, nor did it have it in the patch series in which it got merged, yet it is still present? Furthermore, there are plans to upstream support for one of our SoCs that may benefit from this, as seen here: https://www.spinics.net/lists/iommu/msg39608.html. Which means it should have never been merged. As a general policy we do not add code to the Linux kernel without actual users. Yes, in this case I was hoping a user would materialise via a different tree, but it didn't happen, hence my post last week about removing this altogether: https://lore.kernel.org/linux-iommu/20191024153832.ga7...@jcrouse1-lnx.qualcomm.com/T/#t which I suspect prompted this patch that unfortunately fails to solve the problem. Will ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH] iommu/dma: Add support for DMA_ATTR_SYS_CACHE
On Mon, Oct 28, 2019 at 11:59:04AM +, Robin Murphy wrote: > On 28/10/2019 11:24, Will Deacon wrote: > >Hi Christoph, > > > >On Mon, Oct 28, 2019 at 08:41:56AM +0100, Christoph Hellwig wrote: > >>On Sat, Oct 26, 2019 at 03:12:57AM -0700, isa...@codeaurora.org wrote: > >>>On 2019-10-25 22:30, Christoph Hellwig wrote: > The definition makes very little sense. > >>>Can you please clarify what part doesn’t make sense, and why? > >> > >>It looks like complete garbage to me. That might just be because it > >>uses tons of terms I've never heard of of and which aren't used anywhere > >>in the DMA API. It also might be because it doesn't explain how the > >>flag might actually be practically useful. > > > >Agreed. The way I /think/ it works is that on many SoCs there is a > >system/last-level cache (LLC) which effectively sits in front of memory for > >all masters. Even if a device isn't coherent with the CPU caches, we still > >want to be able to allocate into the LLC. Why this doesn't happen > >automatically is beyond me, but it appears that on these Qualcomm designs > >you actually have to set the memory attributes up in the page-table to > >ensure that the resulting memory transactions are non-cacheable for the CPU > >but cacheable for the LLC. Without any changes, the transactions are > >non-cacheable in both of them which assumedly has a performance cost. > > > >But you can see that I'm piecing things together myself here. Isaac? > > FWIW, that's pretty much how Pratik and Jordan explained it to me - the LLC > sits directly in front of memory and is more or less transparent, although > it might treat CPU and device accesses slightly differently (I don't > remember exactly how the inner cacheablility attribute interacts). Certain > devices don't get much benefit from the LLC, hence the desire for > finer-grained control of their outer allocation policy to avoid more > thrashing than necessary. Furthermore, for stuff in the video/GPU/display > area certain jobs benefit more than others, hence the desire to go even > finer-grained than a per-device control in order to maximise LLC > effectiveness. Robin's description is correct. And we did have a patch for an in-kernel user but it got lost in the wash. I'm hoping Sharat can get a respin in time for 5.5. https://lore.kernel.org/linux-arm-msm/1538744915-25490-8-git-send-email-smase...@codeaurora.org/ Jordan -- The Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
Re: [PATCH] iommu/dma: Add support for DMA_ATTR_SYS_CACHE
On Mon, Oct 28, 2019 at 12:37:28PM +0100, Christoph Hellwig wrote: > On Mon, Oct 28, 2019 at 11:24:58AM +, Will Deacon wrote: > > Agreed. The way I /think/ it works is that on many SoCs there is a > > system/last-level cache (LLC) which effectively sits in front of memory for > > all masters. Even if a device isn't coherent with the CPU caches, we still > > want to be able to allocate into the LLC. Why this doesn't happen > > automatically is beyond me, but it appears that on these Qualcomm designs > > you actually have to set the memory attributes up in the page-table to > > ensure that the resulting memory transactions are non-cacheable for the CPU > > but cacheable for the LLC. Without any changes, the transactions are > > non-cacheable in both of them which assumedly has a performance cost. > > > > But you can see that I'm piecing things together myself here. Isaac? > > If that is the case it sounds like we'd want to drive this through > DT properties, not the driver API. But again, without an actual consumer > it pretty much is a moot point anyway. I think there's certainly a DT aspect to it so that the driver knows that the SoC is hooked up this way, but I agree that we need a consumer so that we can figure out how dynamic this needs to be. If it's just a fire-and-forget thing then it needn't escape the IOMMU layer, but I fear that it's probably more flexible than that. If nothing shows up for 5.6, I'll send a patch to remove it (since Jordan said there was something coming soon [1]) Will [1] http://lkml.kernel.org/r/20191024153832.ga7...@jcrouse1-lnx.qualcomm.com ___ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu
