[PATCH v5 2/7] PCI: Scan all functions when running over Jailhouse
From: Jan Kiszka
Per PCIe r4.0, sec 7.5.1.1.9, multi-function devices are required to
have a function 0. Therefore, Linux scans for devices at function 0
(devfn 0/8/16/...) and only scans for other functions if function 0
has its Multi-Function Device bit set or ARI or SR-IOV indicate
there are more functions.
The Jailhouse hypervisor may pass individual functions of a
multi-function device to a guest without passing function 0, which
means a Linux guest won't find them.
Change Linux PCI probing so it scans all function numbers when
running as a guest over Jailhouse.
This is technically prohibited by the spec, so it is possible that
PCI devices without the Multi-Function Device bit set may have
unexpected behavior in response to this probe.
Derived from original patch by Benedikt Spranger.
CC: Benedikt Spranger
Signed-off-by: Jan Kiszka
Acked-by: Bjorn Helgaas
Reviewed-by: Andy Shevchenko
---
arch/x86/pci/legacy.c | 4 +++-
drivers/pci/probe.c | 22 +++---
2 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/arch/x86/pci/legacy.c b/arch/x86/pci/legacy.c
index 1cb01abcb1be..dfbe6ac38830 100644
--- a/arch/x86/pci/legacy.c
+++ b/arch/x86/pci/legacy.c
@@ -4,6 +4,7 @@
#include
#include
#include
+#include
#include
/*
@@ -34,13 +35,14 @@ int __init pci_legacy_init(void)
void pcibios_scan_specific_bus(int busn)
{
+ int stride = jailhouse_paravirt() ? 1 : 8;
int devfn;
u32 l;
if (pci_find_bus(0, busn))
return;
- for (devfn = 0; devfn < 256; devfn += 8) {
+ for (devfn = 0; devfn < 256; devfn += stride) {
if (!raw_pci_read(0, busn, devfn, PCI_VENDOR_ID, 2, &l) &&
l != 0x && l != 0x) {
DBG("Found device at %02x:%02x [%04x]\n", busn, devfn,
l);
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index ef5377438a1e..3c365dc996e7 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -16,6 +16,7 @@
#include
#include
#include
+#include
#include
#include
#include "pci.h"
@@ -2518,14 +2519,29 @@ static unsigned int pci_scan_child_bus_extend(struct
pci_bus *bus,
{
unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0;
unsigned int start = bus->busn_res.start;
- unsigned int devfn, cmax, max = start;
+ unsigned int devfn, fn, cmax, max = start;
struct pci_dev *dev;
+ int nr_devs;
dev_dbg(&bus->dev, "scanning bus\n");
/* Go find them, Rover! */
- for (devfn = 0; devfn < 0x100; devfn += 8)
- pci_scan_slot(bus, devfn);
+ for (devfn = 0; devfn < 256; devfn += 8) {
+ nr_devs = pci_scan_slot(bus, devfn);
+
+ /*
+* The Jailhouse hypervisor may pass individual functions of a
+* multi-function device to a guest without passing function 0.
+* Look for them as well.
+*/
+ if (jailhouse_paravirt() && nr_devs == 0) {
+ for (fn = 1; fn < 8; fn++) {
+ dev = pci_scan_single_device(bus, devfn + fn);
+ if (dev)
+ dev->multifunction = 1;
+ }
+ }
+ }
/* Reserve buses for SR-IOV capability */
used_buses = pci_iov_bus_range(bus);
--
2.13.6
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[PATCH v5 4/7] x86: Align x86_64 PCI_MMCONFIG with 32-bit variant
From: Jan Kiszka Allow to enable PCI_MMCONFIG when only SFI is present and make this option default on. This will help consolidating both into one Kconfig statement. Signed-off-by: Jan Kiszka --- arch/x86/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index eb7f43f23521..c19f5342ec2b 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -2659,7 +2659,8 @@ config PCI_DOMAINS config PCI_MMCONFIG bool "Support mmconfig PCI config space access" - depends on X86_64 && PCI && ACPI + default y + depends on X86_64 && PCI && (ACPI || SFI) config PCI_CNB20LE_QUIRK bool "Read CNB20LE Host Bridge Windows" if EXPERT -- 2.13.6 -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to jailhouse-dev+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[PATCH v5 6/7] x86/jailhouse: Allow to use PCI_MMCONFIG without ACPI
From: Jan Kiszka
Jailhouse does not use ACPI, but it does support MMCONFIG. Make sure the
latter can be built without having to enable ACPI as well. Primarily, we
need to make the AMD mmconf-fam10h_64 depend upon MMCONFIG and ACPI,
instead of just the former.
Saves some bytes in the Jailhouse non-root kernel.
Signed-off-by: Jan Kiszka
---
arch/x86/Kconfig | 6 +-
arch/x86/kernel/Makefile | 2 +-
arch/x86/kernel/cpu/amd.c | 2 +-
3 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 8986a6b6e3df..b53340e71f84 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -2643,7 +2643,7 @@ config PCI_DIRECT
config PCI_MMCONFIG
bool "Support mmconfig PCI config space access" if X86_64
default y
- depends on PCI && (ACPI || SFI)
+ depends on PCI && (ACPI || SFI || JAILHOUSE_GUEST)
depends on X86_64 || (PCI_GOANY || PCI_GOMMCONFIG)
config PCI_OLPC
@@ -2659,6 +2659,10 @@ config PCI_DOMAINS
def_bool y
depends on PCI
+config MMCONF_FAM10H
+ def_bool y
+ depends on X86_64 && PCI_MMCONFIG && ACPI
+
config PCI_CNB20LE_QUIRK
bool "Read CNB20LE Host Bridge Windows" if EXPERT
depends on PCI
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index 29786c87e864..73ccf80c09a2 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -146,6 +146,6 @@ ifeq ($(CONFIG_X86_64),y)
obj-$(CONFIG_GART_IOMMU)+= amd_gart_64.o aperture_64.o
obj-$(CONFIG_CALGARY_IOMMU) += pci-calgary_64.o tce_64.o
- obj-$(CONFIG_PCI_MMCONFIG) += mmconf-fam10h_64.o
+ obj-$(CONFIG_MMCONF_FAM10H) += mmconf-fam10h_64.o
obj-y += vsmp_64.o
endif
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index f0e6456ca7d3..12bc0a1139da 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -716,7 +716,7 @@ static void init_amd_k8(struct cpuinfo_x86 *c)
static void init_amd_gh(struct cpuinfo_x86 *c)
{
-#ifdef CONFIG_X86_64
+#ifdef CONFIG_MMCONF_FAM10H
/* do this for boot cpu */
if (c == &boot_cpu_data)
check_enable_amd_mmconf_dmi();
--
2.13.6
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[PATCH v5 0/7] jailhouse: Enhance secondary Jailhouse guest support /wrt PCI
Basic x86 support [1] for running Linux as secondary Jailhouse [2] guest is currently pending in the tip tree. This builds on top and enhances the PCI support for x86 and also ARM guests (ARM[64] does not require platform patches and works already). Key elements of this series are: - detection of Jailhouse via device tree hypervisor node - function-level PCI scan if Jailhouse is detected - MMCONFIG support for x86 guests As most changes affect x86, I would suggest to route the series also via tip after the necessary acks are collected. Changes in v5: - fix build breakage of patch 6 on i386 Changes in v4: - slit up Kconfig changes - respect pcibios_last_bus during mmconfig setup - cosmetic changes requested by Andy Changes in v3: - avoided duplicate scans of PCI functions under Jailhouse - reformated PCI_MMCONFIG condition and rephrase related commit log Changes in v2: - adjusted commit log and include ordering in patch 2 - rebased over Linus master Jan [1] https://lkml.org/lkml/2017/11/27/125 [2] http://jailhouse-project.org CC: Benedikt Spranger CC: Juergen Gross CC: Mark Rutland CC: Otavio Pontes CC: Rob Herring Jan Kiszka (6): jailhouse: Provide detection for non-x86 systems PCI: Scan all functions when running over Jailhouse x86: Align x86_64 PCI_MMCONFIG with 32-bit variant x86: Consolidate PCI_MMCONFIG configs x86/jailhouse: Allow to use PCI_MMCONFIG without ACPI MAINTAINERS: Add entry for Jailhouse Otavio Pontes (1): x86/jailhouse: Enable PCI mmconfig access in inmates Documentation/devicetree/bindings/jailhouse.txt | 8 MAINTAINERS | 7 +++ arch/x86/Kconfig| 12 +++- arch/x86/include/asm/jailhouse_para.h | 2 +- arch/x86/include/asm/pci_x86.h | 2 ++ arch/x86/kernel/Makefile| 2 +- arch/x86/kernel/cpu/amd.c | 2 +- arch/x86/kernel/jailhouse.c | 8 arch/x86/pci/legacy.c | 4 +++- arch/x86/pci/mmconfig-shared.c | 4 ++-- drivers/pci/probe.c | 22 +++--- include/linux/hypervisor.h | 17 +++-- 12 files changed, 74 insertions(+), 16 deletions(-) create mode 100644 Documentation/devicetree/bindings/jailhouse.txt -- 2.13.6 -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to jailhouse-dev+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[PATCH v5 1/7] jailhouse: Provide detection for non-x86 systems
From: Jan Kiszka
Implement jailhouse_paravirt() via device tree probing on architectures
!= x86. Will be used by the PCI core.
CC: Rob Herring
CC: Mark Rutland
CC: Juergen Gross
Signed-off-by: Jan Kiszka
Reviewed-by: Juergen Gross
---
Documentation/devicetree/bindings/jailhouse.txt | 8
arch/x86/include/asm/jailhouse_para.h | 2 +-
include/linux/hypervisor.h | 17 +++--
3 files changed, 24 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/jailhouse.txt
diff --git a/Documentation/devicetree/bindings/jailhouse.txt
b/Documentation/devicetree/bindings/jailhouse.txt
new file mode 100644
index ..2901c25ff340
--- /dev/null
+++ b/Documentation/devicetree/bindings/jailhouse.txt
@@ -0,0 +1,8 @@
+Jailhouse non-root cell device tree bindings
+
+
+When running in a non-root Jailhouse cell (partition), the device tree of this
+platform shall have a top-level "hypervisor" node with the following
+properties:
+
+- compatible = "jailhouse,cell"
diff --git a/arch/x86/include/asm/jailhouse_para.h
b/arch/x86/include/asm/jailhouse_para.h
index 875b54376689..b885a961a150 100644
--- a/arch/x86/include/asm/jailhouse_para.h
+++ b/arch/x86/include/asm/jailhouse_para.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL2.0 */
/*
- * Jailhouse paravirt_ops implementation
+ * Jailhouse paravirt detection
*
* Copyright (c) Siemens AG, 2015-2017
*
diff --git a/include/linux/hypervisor.h b/include/linux/hypervisor.h
index b19563f9a8eb..fc08b433c856 100644
--- a/include/linux/hypervisor.h
+++ b/include/linux/hypervisor.h
@@ -8,15 +8,28 @@
*/
#ifdef CONFIG_X86
+
+#include
#include
+
static inline void hypervisor_pin_vcpu(int cpu)
{
x86_platform.hyper.pin_vcpu(cpu);
}
-#else
+
+#else /* !CONFIG_X86 */
+
+#include
+
static inline void hypervisor_pin_vcpu(int cpu)
{
}
-#endif
+
+static inline bool jailhouse_paravirt(void)
+{
+ return of_find_compatible_node(NULL, NULL, "jailhouse,cell");
+}
+
+#endif /* !CONFIG_X86 */
#endif /* __LINUX_HYPEVISOR_H */
--
2.13.6
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[PATCH v5 7/7] MAINTAINERS: Add entry for Jailhouse
From: Jan Kiszka Signed-off-by: Jan Kiszka --- MAINTAINERS | 7 +++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 4623caf8d72d..6dc0b8f3ae0e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -7523,6 +7523,13 @@ Q: http://patchwork.linuxtv.org/project/linux-media/list/ S: Maintained F: drivers/media/dvb-frontends/ix2505v* +JAILHOUSE HYPERVISOR INTERFACE +M: Jan Kiszka +L: jailhouse-dev@googlegroups.com +S: Maintained +F: arch/x86/kernel/jailhouse.c +F: arch/x86/include/asm/jailhouse_para.h + JC42.4 TEMPERATURE SENSOR DRIVER M: Guenter Roeck L: linux-hw...@vger.kernel.org -- 2.13.6 -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to jailhouse-dev+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[PATCH v5 5/7] x86: Consolidate PCI_MMCONFIG configs
From: Jan Kiszka
Since e279b6c1d329 ("x86: start unification of arch/x86/Kconfig.*"), we
have two PCI_MMCONFIG entries, one from the original i386 and another
from x86_64. This consolidates both entries into a single one.
Signed-off-by: Jan Kiszka
---
arch/x86/Kconfig | 11 ---
1 file changed, 4 insertions(+), 7 deletions(-)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index c19f5342ec2b..8986a6b6e3df 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -2641,8 +2641,10 @@ config PCI_DIRECT
depends on PCI && (X86_64 || (PCI_GODIRECT || PCI_GOANY || PCI_GOOLPC
|| PCI_GOMMCONFIG))
config PCI_MMCONFIG
- def_bool y
- depends on X86_32 && PCI && (ACPI || SFI) && (PCI_GOMMCONFIG ||
PCI_GOANY)
+ bool "Support mmconfig PCI config space access" if X86_64
+ default y
+ depends on PCI && (ACPI || SFI)
+ depends on X86_64 || (PCI_GOANY || PCI_GOMMCONFIG)
config PCI_OLPC
def_bool y
@@ -2657,11 +2659,6 @@ config PCI_DOMAINS
def_bool y
depends on PCI
-config PCI_MMCONFIG
- bool "Support mmconfig PCI config space access"
- default y
- depends on X86_64 && PCI && (ACPI || SFI)
-
config PCI_CNB20LE_QUIRK
bool "Read CNB20LE Host Bridge Windows" if EXPERT
depends on PCI
--
2.13.6
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[PATCH v5 3/7] x86/jailhouse: Enable PCI mmconfig access in inmates
From: Otavio Pontes
Use the PCI mmconfig base address exported by jailhouse in boot
parameters in order to access the memory mapped PCI configuration space.
Signed-off-by: Otavio Pontes
[Jan: rebased, fixed !CONFIG_PCI_MMCONFIG, used pcibios_last_bus]
Signed-off-by: Jan Kiszka
Reviewed-by: Andy Shevchenko
---
arch/x86/include/asm/pci_x86.h | 2 ++
arch/x86/kernel/jailhouse.c| 8
arch/x86/pci/mmconfig-shared.c | 4 ++--
3 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h
index eb66fa9cd0fc..959d618dbb17 100644
--- a/arch/x86/include/asm/pci_x86.h
+++ b/arch/x86/include/asm/pci_x86.h
@@ -151,6 +151,8 @@ extern int pci_mmconfig_insert(struct device *dev, u16 seg,
u8 start, u8 end,
phys_addr_t addr);
extern int pci_mmconfig_delete(u16 seg, u8 start, u8 end);
extern struct pci_mmcfg_region *pci_mmconfig_lookup(int segment, int bus);
+extern struct pci_mmcfg_region *__init pci_mmconfig_add(int segment, int start,
+ int end, u64 addr);
extern struct list_head pci_mmcfg_list;
diff --git a/arch/x86/kernel/jailhouse.c b/arch/x86/kernel/jailhouse.c
index b68fd895235a..fa183a131edc 100644
--- a/arch/x86/kernel/jailhouse.c
+++ b/arch/x86/kernel/jailhouse.c
@@ -124,6 +124,14 @@ static int __init jailhouse_pci_arch_init(void)
if (pcibios_last_bus < 0)
pcibios_last_bus = 0xff;
+#ifdef CONFIG_PCI_MMCONFIG
+ if (setup_data.pci_mmconfig_base) {
+ pci_mmconfig_add(0, 0, pcibios_last_bus,
+setup_data.pci_mmconfig_base);
+ pci_mmcfg_arch_init();
+ }
+#endif
+
return 0;
}
diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c
index 96684d0adcf9..0e590272366b 100644
--- a/arch/x86/pci/mmconfig-shared.c
+++ b/arch/x86/pci/mmconfig-shared.c
@@ -94,8 +94,8 @@ static struct pci_mmcfg_region *pci_mmconfig_alloc(int
segment, int start,
return new;
}
-static struct pci_mmcfg_region *__init pci_mmconfig_add(int segment, int start,
- int end, u64 addr)
+struct pci_mmcfg_region *__init pci_mmconfig_add(int segment, int start,
+int end, u64 addr)
{
struct pci_mmcfg_region *new;
--
2.13.6
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Re: shared memory application to run on non rootcell
On 2018-03-06 19:19, anilapp...@gmail.com wrote: > Jan, > we are tying to access( read & write) from shared memory region between root > cell and non rootcell. I cant use ivshm-shared.bin file because I want to > load another linux kernel on non rootcell. After booting into non rootcell, > how can I write into shared memory region and trigger interrupt so that root > cell can receive it. I am using minimal file system in non rootcell and I > cant compile and create some application on non rootcell. > Can I create ivshm-shared memory application instead of binary in rootcell. > If yes, I can use this application to run on non rootcell to write into share > memory region. > please suggest me is there any way to achieve this. Have a look at Documentation/inter-cell-communication.txt and specifically also https://github.com/henning-schild-work/ivshmem-guest-code. Jan -- Siemens AG, Corporate Technology, CT RDA IOT SES-DE Corporate Competence Center Embedded Linux -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to jailhouse-dev+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [PATCH] Update required QEMU version to be >= 2.8
On 2018-03-05 17:37, Adeel Ahmad wrote: > The current version mentioned in README.md (2.7) does not support the > x-buggy-eim property. > > Signed-off-by: Adeel Ahmad > --- > README.md | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/README.md b/README.md > index 42fd8c0..a96f99c 100644 > --- a/README.md > +++ b/README.md > @@ -13,7 +13,7 @@ Quickstart > The host-side requirements are: > > - Docker (tested with 17.09.1-ce) > -- QEMU 2.7 (for x86 image) > +- QEMU >= 2.8 (for x86 image) > - Kernel >= 4.4 with KVM support (for x86 image) > > To build all images, just run ```build-images.sh```. A QEMU image can then be > ...and applied to jailhouse-images as well. Thanks, Jan -- Siemens AG, Corporate Technology, CT RDA IOT SES-DE Corporate Competence Center Embedded Linux -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to jailhouse-dev+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[siemens/jailhouse] 28cc7c: Documentation: update required QEMU version to be ...
Branch: refs/heads/next Home: https://github.com/siemens/jailhouse Commit: 28cc7ce508123fd21e3a1da0da561f7bd35a6244 https://github.com/siemens/jailhouse/commit/28cc7ce508123fd21e3a1da0da561f7bd35a6244 Author: Adeel Ahmad Date: 2018-03-06 (Tue, 06 Mar 2018) Changed paths: M README.md Log Message: --- Documentation: update required QEMU version to be >= 2.8 The "x86 Demonstration in QEMU/KVM" section currently lists QEMU version to be 2.7 or newer, as the x-buggy-eim property was introduced in version 2.8, this version won't work. Signed-off-by: Adeel Ahmad Signed-off-by: Jan Kiszka Commit: 2dfb4f518291d81db71223ab277e66315657076f https://github.com/siemens/jailhouse/commit/2dfb4f518291d81db71223ab277e66315657076f Author: Adeel Ahmad Date: 2018-03-06 (Tue, 06 Mar 2018) Changed paths: M hypervisor/arch/arm/include/asm/sysregs.h M hypervisor/arch/arm64/include/asm/sysregs.h Log Message: --- arm/arm64: Simplify bit field extractions using GET_FIELD macro The bit field extractions are made more readable by the use of GET_FIELD macro, this also allows them to be mapped directly to processor manuals. This commit also includes a typo fix. Signed-off-by: Adeel Ahmad [Jan: kept "hsr" as parameter name on arm] Signed-off-by: Jan Kiszka Compare: https://github.com/siemens/jailhouse/compare/a85b0ebd1766...2dfb4f518291 -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to jailhouse-dev+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [PATCH] arm/arm64: Simplify bit field extractions using GET_FIELD macro
On 2018-03-06 20:20, Jan Kiszka wrote: > On 2018-03-06 18:43, Adeel Ahmad wrote: >> The bit field extractions are made more readable by the use >> of GET_FIELD macro, this also allows them to be mapped >> directly to processor manuals. This commit also >> includes a typo fix. >> >> Signed-off-by: Adeel Ahmad >> --- >> hypervisor/arch/arm/include/asm/sysregs.h | 10 -- >> hypervisor/arch/arm64/include/asm/sysregs.h | 10 -- >> 2 files changed, 8 insertions(+), 12 deletions(-) >> >> diff --git a/hypervisor/arch/arm/include/asm/sysregs.h >> b/hypervisor/arch/arm/include/asm/sysregs.h >> index 6c9a53c..fb6b503 100644 >> --- a/hypervisor/arch/arm/include/asm/sysregs.h >> +++ b/hypervisor/arch/arm/include/asm/sysregs.h >> @@ -107,13 +107,11 @@ >> #define ESR_EL2 SYSREG_32(4, c5, c2, 0) >> #define HSR ESR_EL2 /* AArch32 name */ >> /* exception class */ >> -#define HSR_EC_SHIFT 26 >> -#define HSR_EC(hsr)((hsr) >> HSR_EC_SHIFT & 0x3f) >> +#define HSR_EC(esr)GET_FIELD((esr), 31, 26) Almost copy & paste: "hsr" should remain hsr. It's esr on arm64 only. I'm fixing these up while merging, no need to resend. Jan >> /* instruction length */ >> -#define HSR_IL_SHIFT 25 >> -#define HSR_IL(hsr)((hsr) >> HSR_IL_SHIFT & 0x1) >> -/* Instruction specific */ >> -#define HSR_ISS(hsr) ((hsr) & BIT_MASK(24, 0)) >> +#define HSR_IL(esr)GET_FIELD((esr), 25, 25) >> +/* Instruction specific syndrome */ >> +#define HSR_ISS(esr) GET_FIELD((esr), 24, 0) >> /* Exception classes values */ >> #define HSR_EC_UNK 0x00 >> #define HSR_EC_WFI 0x01 >> diff --git a/hypervisor/arch/arm64/include/asm/sysregs.h >> b/hypervisor/arch/arm64/include/asm/sysregs.h >> index d3feee0..70c0d13 100644 >> --- a/hypervisor/arch/arm64/include/asm/sysregs.h >> +++ b/hypervisor/arch/arm64/include/asm/sysregs.h >> @@ -107,13 +107,11 @@ >> #define HCR_VM_BIT (1u << 0) >> >> /* exception class */ >> -#define ESR_EC_SHIFT26 >> -#define ESR_EC(hsr) ((hsr) >> ESR_EC_SHIFT & 0x3f) >> +#define ESR_EC(esr) GET_FIELD((esr), 31, 26) >> /* instruction length */ >> -#define ESR_IL_SHIFT25 >> -#define ESR_IL(hsr) ((hsr) >> ESR_IL_SHIFT & 0x1) >> -/* Instruction specific syndrom */ >> -#define ESR_ISS(esr)((esr) & BIT_MASK(24, 0)) >> +#define ESR_IL(esr) GET_FIELD((esr), 25, 25) >> +/* Instruction specific syndrome */ >> +#define ESR_ISS(esr)GET_FIELD((esr), 24, 0) >> /* Exception classes values */ >> #define ESR_EC_UNKNOWN 0x00 >> #define ESR_EC_WFx 0x01 >> > > Applied to next. > > Did you look around in other hypervisor files where shifting/masking > happens if this pattern applies there as well? > > Thanks, > Jan > -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to jailhouse-dev+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [PATCH] arm/arm64: Simplify bit field extractions using GET_FIELD macro
On 2018-03-06 18:43, Adeel Ahmad wrote: > The bit field extractions are made more readable by the use > of GET_FIELD macro, this also allows them to be mapped > directly to processor manuals. This commit also > includes a typo fix. > > Signed-off-by: Adeel Ahmad > --- > hypervisor/arch/arm/include/asm/sysregs.h | 10 -- > hypervisor/arch/arm64/include/asm/sysregs.h | 10 -- > 2 files changed, 8 insertions(+), 12 deletions(-) > > diff --git a/hypervisor/arch/arm/include/asm/sysregs.h > b/hypervisor/arch/arm/include/asm/sysregs.h > index 6c9a53c..fb6b503 100644 > --- a/hypervisor/arch/arm/include/asm/sysregs.h > +++ b/hypervisor/arch/arm/include/asm/sysregs.h > @@ -107,13 +107,11 @@ > #define ESR_EL2 SYSREG_32(4, c5, c2, 0) > #define HSR ESR_EL2 /* AArch32 name */ > /* exception class */ > -#define HSR_EC_SHIFT26 > -#define HSR_EC(hsr) ((hsr) >> HSR_EC_SHIFT & 0x3f) > +#define HSR_EC(esr) GET_FIELD((esr), 31, 26) > /* instruction length */ > -#define HSR_IL_SHIFT25 > -#define HSR_IL(hsr) ((hsr) >> HSR_IL_SHIFT & 0x1) > -/* Instruction specific */ > -#define HSR_ISS(hsr)((hsr) & BIT_MASK(24, 0)) > +#define HSR_IL(esr) GET_FIELD((esr), 25, 25) > +/* Instruction specific syndrome */ > +#define HSR_ISS(esr)GET_FIELD((esr), 24, 0) > /* Exception classes values */ > #define HSR_EC_UNK 0x00 > #define HSR_EC_WFI 0x01 > diff --git a/hypervisor/arch/arm64/include/asm/sysregs.h > b/hypervisor/arch/arm64/include/asm/sysregs.h > index d3feee0..70c0d13 100644 > --- a/hypervisor/arch/arm64/include/asm/sysregs.h > +++ b/hypervisor/arch/arm64/include/asm/sysregs.h > @@ -107,13 +107,11 @@ > #define HCR_VM_BIT (1u << 0) > > /* exception class */ > -#define ESR_EC_SHIFT 26 > -#define ESR_EC(hsr) ((hsr) >> ESR_EC_SHIFT & 0x3f) > +#define ESR_EC(esr) GET_FIELD((esr), 31, 26) > /* instruction length */ > -#define ESR_IL_SHIFT 25 > -#define ESR_IL(hsr) ((hsr) >> ESR_IL_SHIFT & 0x1) > -/* Instruction specific syndrom */ > -#define ESR_ISS(esr) ((esr) & BIT_MASK(24, 0)) > +#define ESR_IL(esr) GET_FIELD((esr), 25, 25) > +/* Instruction specific syndrome */ > +#define ESR_ISS(esr) GET_FIELD((esr), 24, 0) > /* Exception classes values */ > #define ESR_EC_UNKNOWN 0x00 > #define ESR_EC_WFx 0x01 > Applied to next. Did you look around in other hypervisor files where shifting/masking happens if this pattern applies there as well? Thanks, Jan -- Siemens AG, Corporate Technology, CT RDA IOT SES-DE Corporate Competence Center Embedded Linux -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to jailhouse-dev+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: [PATCH] Documentation: update required QEMU version to be >= 2.8
On 2018-03-06 18:30, Adeel Ahmad wrote: > The "x86 Demonstration in QEMU/KVM" section currently > lists QEMU version to be 2.7 or newer, as the > x-buggy-eim property was introduced in version 2.8, > this version won't work. > > Signed-off-by: Adeel Ahmad > --- > README.md | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/README.md b/README.md > index 6f5dac2..dedd35c 100644 > --- a/README.md > +++ b/README.md > @@ -247,7 +247,7 @@ x86 Demonstration in QEMU/KVM > > The included system configuration qemu-x86.c can be used to run Jailhouse in > QEMU/KVM virtual machine on x86 hosts (Intel and AMD are supported). > Currently > -it requires Linux 4.4 or newer on the host side. QEMU version 2.7 or newer is > +it requires Linux 4.4 or newer on the host side. QEMU version 2.8 or newer is > required. > > You also need a Linux guest image with a recent kernel (tested with >= 3.9) > and > Thanks, applied to next. Jan PS: I thinks your hotmail account is not only problematic for google. My company inbox remained empty as well. Maybe switch to some other account? -- Siemens AG, Corporate Technology, CT RDA IOT SES-DE Corporate Competence Center Embedded Linux -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to jailhouse-dev+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
shared memory application to run on non rootcell
Jan, we are tying to access( read & write) from shared memory region between root cell and non rootcell. I cant use ivshm-shared.bin file because I want to load another linux kernel on non rootcell. After booting into non rootcell, how can I write into shared memory region and trigger interrupt so that root cell can receive it. I am using minimal file system in non rootcell and I cant compile and create some application on non rootcell. Can I create ivshm-shared memory application instead of binary in rootcell. If yes, I can use this application to run on non rootcell to write into share memory region. please suggest me is there any way to achieve this. Regards, Anil -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to jailhouse-dev+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
need application executa
Jan, we are tying to access( read & write) from shared memory region between root cell and non rootcell. I cant use ivshm-shared.bin file because I want to load another linux kernel on non rootcell. After booting into non rootcell, how can I write into shared memory region and trigger interrupt so that root cell can receive it. I am using minimal file system in non rootcell and I cant compile and create some application on non rootcell. Can I create ivshm-shared memory application instead of binary in rootcell. If yes, I can use this application to run on non rootcell to write into share memory region. please suggest me is there any way to achieve this. Regards, Anil -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to jailhouse-dev+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[PATCH] Documentation: update required QEMU version to be >= 2.8
The "x86 Demonstration in QEMU/KVM" section currently lists QEMU version to be 2.7 or newer, as the x-buggy-eim property was introduced in version 2.8, this version won't work. Signed-off-by: Adeel Ahmad --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 6f5dac2..dedd35c 100644 --- a/README.md +++ b/README.md @@ -247,7 +247,7 @@ x86 Demonstration in QEMU/KVM The included system configuration qemu-x86.c can be used to run Jailhouse in QEMU/KVM virtual machine on x86 hosts (Intel and AMD are supported). Currently -it requires Linux 4.4 or newer on the host side. QEMU version 2.7 or newer is +it requires Linux 4.4 or newer on the host side. QEMU version 2.8 or newer is required. You also need a Linux guest image with a recent kernel (tested with >= 3.9) and -- 1.9.1 -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to jailhouse-dev+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
[PATCH] arm/arm64: Simplify bit field extractions using GET_FIELD macro
The bit field extractions are made more readable by the use of GET_FIELD macro, this also allows them to be mapped directly to processor manuals. This commit also includes a typo fix. Signed-off-by: Adeel Ahmad --- hypervisor/arch/arm/include/asm/sysregs.h | 10 -- hypervisor/arch/arm64/include/asm/sysregs.h | 10 -- 2 files changed, 8 insertions(+), 12 deletions(-) diff --git a/hypervisor/arch/arm/include/asm/sysregs.h b/hypervisor/arch/arm/include/asm/sysregs.h index 6c9a53c..fb6b503 100644 --- a/hypervisor/arch/arm/include/asm/sysregs.h +++ b/hypervisor/arch/arm/include/asm/sysregs.h @@ -107,13 +107,11 @@ #define ESR_EL2SYSREG_32(4, c5, c2, 0) #define HSRESR_EL2 /* AArch32 name */ /* exception class */ -#define HSR_EC_SHIFT 26 -#define HSR_EC(hsr) ((hsr) >> HSR_EC_SHIFT & 0x3f) +#define HSR_EC(esr) GET_FIELD((esr), 31, 26) /* instruction length */ -#define HSR_IL_SHIFT 25 -#define HSR_IL(hsr) ((hsr) >> HSR_IL_SHIFT & 0x1) -/* Instruction specific */ -#define HSR_ISS(hsr) ((hsr) & BIT_MASK(24, 0)) +#define HSR_IL(esr) GET_FIELD((esr), 25, 25) +/* Instruction specific syndrome */ +#define HSR_ISS(esr) GET_FIELD((esr), 24, 0) /* Exception classes values */ #define HSR_EC_UNK0x00 #define HSR_EC_WFI0x01 diff --git a/hypervisor/arch/arm64/include/asm/sysregs.h b/hypervisor/arch/arm64/include/asm/sysregs.h index d3feee0..70c0d13 100644 --- a/hypervisor/arch/arm64/include/asm/sysregs.h +++ b/hypervisor/arch/arm64/include/asm/sysregs.h @@ -107,13 +107,11 @@ #define HCR_VM_BIT (1u << 0) /* exception class */ -#define ESR_EC_SHIFT 26 -#define ESR_EC(hsr)((hsr) >> ESR_EC_SHIFT & 0x3f) +#define ESR_EC(esr)GET_FIELD((esr), 31, 26) /* instruction length */ -#define ESR_IL_SHIFT 25 -#define ESR_IL(hsr)((hsr) >> ESR_IL_SHIFT & 0x1) -/* Instruction specific syndrom */ -#define ESR_ISS(esr) ((esr) & BIT_MASK(24, 0)) +#define ESR_IL(esr)GET_FIELD((esr), 25, 25) +/* Instruction specific syndrome */ +#define ESR_ISS(esr) GET_FIELD((esr), 24, 0) /* Exception classes values */ #define ESR_EC_UNKNOWN 0x00 #define ESR_EC_WFx 0x01 -- 1.9.1 -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to jailhouse-dev+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
Re: Submitting a patch to the mailing list
> > Your messages got stuck in the spam filter of googlegroups - Google > seems to hate hotmail :). I've whitelisted you and confirmed the last > version of the patch. If anything is missing, please repost now. > > Jan > Hi Jan, I just submitted two patches to the mailing list, but they didn't show up. Could you please check if they got marked as spam again? Thanks, Adeel > -- > Siemens AG, Corporate Technology, CT RDA IOT SES-DE > Corporate Competence Center Embedded Linux -- You received this message because you are subscribed to the Google Groups "Jailhouse" group. To unsubscribe from this group and stop receiving emails from it, send an email to jailhouse-dev+unsubscr...@googlegroups.com. For more options, visit https://groups.google.com/d/optout.
