CC: kbuild-...@lists.01.org CC: Linux Memory Management List <linux...@kvack.org> TO: Tan Tee Min <tee.min....@intel.com> CC: Wong Vee Khee <vee.khee.w...@linux.intel.com>
tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master head: b74523885a715463203d4ccc3cf8c85952d3701a commit: f4da56529da602010979e8497d1f02eaf5df8883 [12103/14231] net: stmmac: Add support for external trigger timestamping :::::: branch date: 4 hours ago :::::: commit date: 7 days ago config: x86_64-randconfig-m001-20210421 (attached as .config) compiler: gcc-9 (Debian 9.3.0-22) 9.3.0 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <l...@intel.com> Reported-by: Dan Carpenter <dan.carpen...@oracle.com> smatch warnings: drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c:369 intel_crosststamp() warn: inconsistent returns '&priv->aux_ts_lock'. vim +369 drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c 341f67e424e572 Tan Tee Min 2021-03-23 274 341f67e424e572 Tan Tee Min 2021-03-23 275 static int intel_crosststamp(ktime_t *device, 341f67e424e572 Tan Tee Min 2021-03-23 276 struct system_counterval_t *system, 341f67e424e572 Tan Tee Min 2021-03-23 277 void *ctx) 341f67e424e572 Tan Tee Min 2021-03-23 278 { 341f67e424e572 Tan Tee Min 2021-03-23 279 struct intel_priv_data *intel_priv; 341f67e424e572 Tan Tee Min 2021-03-23 280 341f67e424e572 Tan Tee Min 2021-03-23 281 struct stmmac_priv *priv = (struct stmmac_priv *)ctx; 341f67e424e572 Tan Tee Min 2021-03-23 282 void __iomem *ptpaddr = priv->ptpaddr; 341f67e424e572 Tan Tee Min 2021-03-23 283 void __iomem *ioaddr = priv->hw->pcsr; 341f67e424e572 Tan Tee Min 2021-03-23 284 unsigned long flags; 341f67e424e572 Tan Tee Min 2021-03-23 285 u64 art_time = 0; 341f67e424e572 Tan Tee Min 2021-03-23 286 u64 ptp_time = 0; 341f67e424e572 Tan Tee Min 2021-03-23 287 u32 num_snapshot; 341f67e424e572 Tan Tee Min 2021-03-23 288 u32 gpio_value; 341f67e424e572 Tan Tee Min 2021-03-23 289 u32 acr_value; 341f67e424e572 Tan Tee Min 2021-03-23 290 int ret; 341f67e424e572 Tan Tee Min 2021-03-23 291 u32 v; 341f67e424e572 Tan Tee Min 2021-03-23 292 int i; 341f67e424e572 Tan Tee Min 2021-03-23 293 341f67e424e572 Tan Tee Min 2021-03-23 294 if (!boot_cpu_has(X86_FEATURE_ART)) 341f67e424e572 Tan Tee Min 2021-03-23 295 return -EOPNOTSUPP; 341f67e424e572 Tan Tee Min 2021-03-23 296 341f67e424e572 Tan Tee Min 2021-03-23 297 intel_priv = priv->plat->bsp_priv; 341f67e424e572 Tan Tee Min 2021-03-23 298 f4da56529da602 Tan Tee Min 2021-04-14 299 /* Both internal crosstimestamping and external triggered event f4da56529da602 Tan Tee Min 2021-04-14 300 * timestamping cannot be run concurrently. f4da56529da602 Tan Tee Min 2021-04-14 301 */ f4da56529da602 Tan Tee Min 2021-04-14 302 if (priv->plat->ext_snapshot_en) f4da56529da602 Tan Tee Min 2021-04-14 303 return -EBUSY; f4da56529da602 Tan Tee Min 2021-04-14 304 f4da56529da602 Tan Tee Min 2021-04-14 305 mutex_lock(&priv->aux_ts_lock); 341f67e424e572 Tan Tee Min 2021-03-23 306 /* Enable Internal snapshot trigger */ 341f67e424e572 Tan Tee Min 2021-03-23 307 acr_value = readl(ptpaddr + PTP_ACR); 341f67e424e572 Tan Tee Min 2021-03-23 308 acr_value &= ~PTP_ACR_MASK; 341f67e424e572 Tan Tee Min 2021-03-23 309 switch (priv->plat->int_snapshot_num) { 341f67e424e572 Tan Tee Min 2021-03-23 310 case AUX_SNAPSHOT0: 341f67e424e572 Tan Tee Min 2021-03-23 311 acr_value |= PTP_ACR_ATSEN0; 341f67e424e572 Tan Tee Min 2021-03-23 312 break; 341f67e424e572 Tan Tee Min 2021-03-23 313 case AUX_SNAPSHOT1: 341f67e424e572 Tan Tee Min 2021-03-23 314 acr_value |= PTP_ACR_ATSEN1; 341f67e424e572 Tan Tee Min 2021-03-23 315 break; 341f67e424e572 Tan Tee Min 2021-03-23 316 case AUX_SNAPSHOT2: 341f67e424e572 Tan Tee Min 2021-03-23 317 acr_value |= PTP_ACR_ATSEN2; 341f67e424e572 Tan Tee Min 2021-03-23 318 break; 341f67e424e572 Tan Tee Min 2021-03-23 319 case AUX_SNAPSHOT3: 341f67e424e572 Tan Tee Min 2021-03-23 320 acr_value |= PTP_ACR_ATSEN3; 341f67e424e572 Tan Tee Min 2021-03-23 321 break; 341f67e424e572 Tan Tee Min 2021-03-23 322 default: 341f67e424e572 Tan Tee Min 2021-03-23 323 return -EINVAL; 341f67e424e572 Tan Tee Min 2021-03-23 324 } 341f67e424e572 Tan Tee Min 2021-03-23 325 writel(acr_value, ptpaddr + PTP_ACR); 341f67e424e572 Tan Tee Min 2021-03-23 326 341f67e424e572 Tan Tee Min 2021-03-23 327 /* Clear FIFO */ 341f67e424e572 Tan Tee Min 2021-03-23 328 acr_value = readl(ptpaddr + PTP_ACR); 341f67e424e572 Tan Tee Min 2021-03-23 329 acr_value |= PTP_ACR_ATSFC; 341f67e424e572 Tan Tee Min 2021-03-23 330 writel(acr_value, ptpaddr + PTP_ACR); f4da56529da602 Tan Tee Min 2021-04-14 331 /* Release the mutex */ f4da56529da602 Tan Tee Min 2021-04-14 332 mutex_unlock(&priv->aux_ts_lock); 341f67e424e572 Tan Tee Min 2021-03-23 333 341f67e424e572 Tan Tee Min 2021-03-23 334 /* Trigger Internal snapshot signal 341f67e424e572 Tan Tee Min 2021-03-23 335 * Create a rising edge by just toggle the GPO1 to low 341f67e424e572 Tan Tee Min 2021-03-23 336 * and back to high. 341f67e424e572 Tan Tee Min 2021-03-23 337 */ 341f67e424e572 Tan Tee Min 2021-03-23 338 gpio_value = readl(ioaddr + GMAC_GPIO_STATUS); 341f67e424e572 Tan Tee Min 2021-03-23 339 gpio_value &= ~GMAC_GPO1; 341f67e424e572 Tan Tee Min 2021-03-23 340 writel(gpio_value, ioaddr + GMAC_GPIO_STATUS); 341f67e424e572 Tan Tee Min 2021-03-23 341 gpio_value |= GMAC_GPO1; 341f67e424e572 Tan Tee Min 2021-03-23 342 writel(gpio_value, ioaddr + GMAC_GPIO_STATUS); 341f67e424e572 Tan Tee Min 2021-03-23 343 341f67e424e572 Tan Tee Min 2021-03-23 344 /* Poll for time sync operation done */ 341f67e424e572 Tan Tee Min 2021-03-23 345 ret = readl_poll_timeout(priv->ioaddr + GMAC_INT_STATUS, v, 341f67e424e572 Tan Tee Min 2021-03-23 346 (v & GMAC_INT_TSIE), 100, 10000); 341f67e424e572 Tan Tee Min 2021-03-23 347 341f67e424e572 Tan Tee Min 2021-03-23 348 if (ret == -ETIMEDOUT) { 341f67e424e572 Tan Tee Min 2021-03-23 349 pr_err("%s: Wait for time sync operation timeout\n", __func__); 341f67e424e572 Tan Tee Min 2021-03-23 350 return ret; 341f67e424e572 Tan Tee Min 2021-03-23 351 } 341f67e424e572 Tan Tee Min 2021-03-23 352 341f67e424e572 Tan Tee Min 2021-03-23 353 num_snapshot = (readl(ioaddr + GMAC_TIMESTAMP_STATUS) & 341f67e424e572 Tan Tee Min 2021-03-23 354 GMAC_TIMESTAMP_ATSNS_MASK) >> 341f67e424e572 Tan Tee Min 2021-03-23 355 GMAC_TIMESTAMP_ATSNS_SHIFT; 341f67e424e572 Tan Tee Min 2021-03-23 356 341f67e424e572 Tan Tee Min 2021-03-23 357 /* Repeat until the timestamps are from the FIFO last segment */ 341f67e424e572 Tan Tee Min 2021-03-23 358 for (i = 0; i < num_snapshot; i++) { 341f67e424e572 Tan Tee Min 2021-03-23 359 spin_lock_irqsave(&priv->ptp_lock, flags); 341f67e424e572 Tan Tee Min 2021-03-23 360 stmmac_get_ptptime(priv, ptpaddr, &ptp_time); 341f67e424e572 Tan Tee Min 2021-03-23 361 *device = ns_to_ktime(ptp_time); 341f67e424e572 Tan Tee Min 2021-03-23 362 spin_unlock_irqrestore(&priv->ptp_lock, flags); 341f67e424e572 Tan Tee Min 2021-03-23 363 get_arttime(priv->mii, intel_priv->mdio_adhoc_addr, &art_time); 341f67e424e572 Tan Tee Min 2021-03-23 364 *system = convert_art_to_tsc(art_time); 341f67e424e572 Tan Tee Min 2021-03-23 365 } 341f67e424e572 Tan Tee Min 2021-03-23 366 1c137d4777b5b6 Wong Vee Khee 2021-03-30 367 system->cycles *= intel_priv->crossts_adj; 1c137d4777b5b6 Wong Vee Khee 2021-03-30 368 341f67e424e572 Tan Tee Min 2021-03-23 @369 return 0; 341f67e424e572 Tan Tee Min 2021-03-23 370 } 341f67e424e572 Tan Tee Min 2021-03-23 371 :::::: The code at line 369 was first introduced by commit :::::: 341f67e424e572bfc034daa534c6fa667533e6a4 net: stmmac: Add hardware supported cross-timestamp :::::: TO: Tan Tee Min <tee.min....@intel.com> :::::: CC: David S. Miller <da...@davemloft.net> --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-...@lists.01.org
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