[valgrind] [Bug 398545] Support for SHA instruction on Ryzen

2019-12-13 Thread Reini Urban
https://bugs.kde.org/show_bug.cgi?id=398545

--- Comment #5 from Reini Urban  ---
> How to add vex support for it? Sounds trivial.
> binutils/objdump can do it for a long time.

I started with that at https://github.com/rurban/valgrind
linux names it sha_ni, freebsd SHA1,SHA2, 
on Windows it's Family 3, cpu Model >= 92 on Intel and cpu Model >= 23 on amd.

But for adding the necessary logic stubs my 30 min self-intro into the code is
certainly not enough. There shouldn't be much logic needed I think. Similar to
the aesdec and crc insn, which do exist already. 
I haven't even found the location where hwcaps are set.

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[valgrind] [Bug 398545] Support for SHA instruction on Ryzen

2019-12-13 Thread Reini Urban
https://bugs.kde.org/show_bug.cgi?id=398545

Reini Urban  changed:

   What|Removed |Added

 CC||rur...@cpan.org

--- Comment #4 from Reini Urban  ---
These new SHA extensions are supported on amd since epyc, on intel since
Goldmont (2017), and on recent arm's and power8.

https://software.intel.com/en-us/articles/intel-sha-extensions

How to add vex support for it? Sounds trivial.
binutils/objdump can do it for a long time.

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