Re: How to measure the RAM read/write performance
I am not sure but what if you make the variable as a volatile? Hey i tried. But still is showing the same time for int volatile int. Thanks Sandeep On Tue, Feb 26, 2013 at 6:50 PM, ankur dwivedi ankurengg2...@gmail.comwrote: I am not sure but what if you make the variable as a volatile? On Tue, Feb 26, 2013 at 5:01 PM, sandeep kumar coolsandyfor...@gmail.comwrote: Hi All In performance benchmark tools, When we profile read/write timings mostly, those read/writes are done to cache only. I want to measure my DDR(RAM chip) performance. So i want to make sure, every read/write should happen to DDR RAM chip only. How can i achieve this...Any ideas/suggestions...? -- With regards, Sandeep Kumar Anantapalli, ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies -- Thanks Ankur Dwivedi -- With regards, Sandeep Kumar Anantapalli, ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Re: How to measure the RAM read/write performance
let' see what if you do read and write pattern, in certain order so that it will be invalidated by the L1/L2/L3 cache everytime? And how do you suggest we do that?? That is infact my question.. On Tue, Feb 26, 2013 at 9:05 PM, Mulyadi Santosa mulyadi.sant...@gmail.comwrote: On Tue, Feb 26, 2013 at 6:31 PM, sandeep kumar coolsandyfor...@gmail.com wrote: Hi All In performance benchmark tools, When we profile read/write timings mostly, those read/writes are done to cache only. I want to measure my DDR(RAM chip) performance. So i want to make sure, every read/write should happen to DDR RAM chip only. let' see what if you do read and write pattern, in certain order so that it will be invalidated by the L1/L2/L3 cache everytime? AFAIK, one thing for sure, reading data from sequentially and re-read them will make end up reading cache in the 2nd operation and so on. I think the most certain way to do it is to read data (or write) data bigger than total L1/L2/L3 cache. -- regards, Mulyadi Santosa Freelance Linux trainer and consultant blog: the-hydra.blogspot.com training: mulyaditraining.blogspot.com -- With regards, Sandeep Kumar Anantapalli, ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Re: How to measure the RAM read/write performance
volatile only say to the compiler to not put the variable in a register. Could i ask why does you want to mesure the speed of the RAM ? Is it to study the NUMA behavior of the machine? In development phase of the board, we are trying to measure RAM performance gain while changing type of the RAM. The standard benchmark tools are giving us the Cache performance only. So we want to try some method to measure RAM performance. On Wed, Feb 27, 2013 at 2:30 PM, Karaoui mohamed lamine mohar...@gmail.comwrote: 2013/2/27 sandeep kumar coolsandyfor...@gmail.com I am not sure but what if you make the variable as a volatile? Hey i tried. But still is showing the same time for int volatile int. volatile only say to the compiler to not put the variable in a register. Could i ask why does you want to mesure the speed of the RAM ? Is it to study the NUMA behavior of the machine? Thanks Sandeep On Tue, Feb 26, 2013 at 6:50 PM, ankur dwivedi ankurengg2...@gmail.comwrote: I am not sure but what if you make the variable as a volatile? On Tue, Feb 26, 2013 at 5:01 PM, sandeep kumar coolsandyfor...@gmail.com wrote: Hi All In performance benchmark tools, When we profile read/write timings mostly, those read/writes are done to cache only. I want to measure my DDR(RAM chip) performance. So i want to make sure, every read/write should happen to DDR RAM chip only. How can i achieve this...Any ideas/suggestions...? -- With regards, Sandeep Kumar Anantapalli, ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies -- Thanks Ankur Dwivedi -- With regards, Sandeep Kumar Anantapalli, ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies -- With regards, Sandeep Kumar Anantapalli, ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Kernel updating : export gpio not working ?
Hi everyone ! I am currently updating the kernel of my company and I have some problems about gpios so I am asking you some help ! :) I think I am in the good mailist because it is the first time I update a kernel and a board configuration ! :D The previous kernel used was 2.6.31.14 and I am trying to update it to last stable version 3.7.9. In the previous kernel for a home-made board (with a IMx27 and a ARM9), we used these methods to export gpios in sysfs (for example for Gpio OUT) : mxc_gpio_mode(gpio_number | GPIO_GPIO | GPIO_OUT); gpio_request(gpio_number, name_of_gpio); gpio_export(gpio_number, 0); gpio_direction_output(gpio_number, gpio_value); In the sysfs, the gpio exported was visible under name_of_gpio. Now, if I use the same methods, I can not get anything in sysfs except gpiochip0, gpiochip32 etc. I tried to use these functions in a module and I could export a gpio but under gpioXX and not name_of_gpio. Moreover, I tried to export a gpio using the sysfs interface. I succeeded to export it and set direction to out but when I try to set the value, it did not work and the value is always set to 0 (and this gpio was configured as OUT in the board). I make a diff about the gpio documentation and the old kernel used did not seem to have many differences with the new kernel ! There is only some methods added such as gpio_resquest_one and gpio_export_link. I tried them without good results. What am I doing wrong ? What am I missing to make it work ? Is there some other configurations to add in the board configuration ? Thank you for any help/explanation ! -- Mylène JOSSERAND ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Re: How to measure the RAM read/write performance
On Tue, Feb 26, 2013 at 5:01 PM, sandeep kumar coolsandyfor...@gmail.com wrote: Hi All In performance benchmark tools, When we profile read/write timings mostly, those read/writes are done to cache only. I want to measure my DDR(RAM chip) performance. So i want to make sure, every read/write should happen to DDR RAM chip only. Try below points: 1. I am not sure about snapdragon(is it Qualcomm?) but try CONFIG_CPU_DCACHE_DISABLE. 2. You are better off programming some DMA master to do large (and uncached) reads/writes to RAM and timing that. However simple uncached LDR/STR from the CPU may not be a great measure of RAM controller perf. You should always add arm mailing list and please mention the chip set details. cat /proc/cpuinfo is a great way How can i achieve this...Any ideas/suggestions...? -- With regards, Sandeep Kumar Anantapalli, ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Re: How to measure the RAM read/write performance
On Wed, Feb 27, 2013 at 6:16 PM, sandeep kumar coolsandyfor...@gmail.com wrote: Try below points: 1. I am not sure about snapdragon(is it Qualcomm?) but try CONFIG_CPU_DCACHE_DISABLE. I did that already, device is not booting. In our architecture cache is tightly coupled with CPU. Should be discussed with Qualcomm guys here as to the reason why it doesn't boot up. 2. You are better off programming some DMA master to do large (and uncached) reads/writes to RAM and timing that. DMA is not a standard way, i suppose, as it depends on what I/O peripheral we are doing the DMA. You are doing I/O to RAM so it should do what you want. CPU-DMA CONTROLLER-RAM You should always add arm mailing list and please mention the chip set details. cat /proc/cpuinfo is a great way Processor : ARMv7 Processor rev 2 (v7l) BogoMIPS: 163.38 Features: swp half thumb fastmult vfp edsp neon vfpv3 tls CPU implementer : 0x51 CPU architecture: 7 CPU variant : 0x1 CPU part: 0x00f CPU revision: 2 Thanks Sandeep On Wed, Feb 27, 2013 at 5:37 PM, anish singh anish198519851...@gmail.com wrote: On Tue, Feb 26, 2013 at 5:01 PM, sandeep kumar coolsandyfor...@gmail.com wrote: Hi All In performance benchmark tools, When we profile read/write timings mostly, those read/writes are done to cache only. I want to measure my DDR(RAM chip) performance. So i want to make sure, every read/write should happen to DDR RAM chip only. Try below points: 1. I am not sure about snapdragon(is it Qualcomm?) but try CONFIG_CPU_DCACHE_DISABLE. 2. You are better off programming some DMA master to do large (and uncached) reads/writes to RAM and timing that. However simple uncached LDR/STR from the CPU may not be a great measure of RAM controller perf. You should always add arm mailing list and please mention the chip set details. cat /proc/cpuinfo is a great way How can i achieve this...Any ideas/suggestions...? -- With regards, Sandeep Kumar Anantapalli, ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies -- With regards, Sandeep Kumar Anantapalli, ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
RE: How to measure the RAM read/write performance
From: coolsandyfor...@gmail.com Date: Tue, 26 Feb 2013 17:01:54 +0530 Subject: How to measure the RAM read/write performance To: kernelnewbies@kernelnewbies.org CC: dhyla...@gmail.com Hi All In performance benchmark tools, When we profile read/write timings mostly, those read/writes are done to cache only. I want to measure my DDR(RAM chip) performance. So i want to make sure, every read/write should happen to DDR RAM chip only. How can i achieve this...Any ideas/suggestions...? try to reserve a large region from bootloader(L4 in Qualcomm platform), let's say it is 10MB continuous physical memory. in kernel, map this region to an continuous virtual region, note that the pgprot should be uncachable since you want to test without cache. once you configed like this, you can read/write to this vitual region without data cache invovled. -- With regards, Sandeep Kumar Anantapalli, ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
RE: How to measure the RAM read/write performance
From: bu...@live.cn To: coolsandyfor...@gmail.com; kernelnewbies@kernelnewbies.org Subject: RE: How to measure the RAM read/write performance Date: Wed, 27 Feb 2013 22:33:15 +0800 CC: dhyla...@gmail.com From: coolsandyfor...@gmail.com Date: Tue, 26 Feb 2013 17:01:54 +0530 Subject: How to measure the RAM read/write performance To: kernelnewbies@kernelnewbies.org CC: dhyla...@gmail.com Hi All In performance benchmark tools, When we profile read/write timings mostly, those read/writes are done to cache only. I want to measure my DDR(RAM chip) performance. So i want to make sure, every read/write should happen to DDR RAM chip only. How can i achieve this...Any ideas/suggestions...? try to reserve a large region from bootloader(L4 in Qualcomm platform), let's say it is 10MB continuous physical memory. sorry, to be accurate, reserve physical memory is done by kernel cmdline, this cmdline parameter can be passed from L4 to kernel, or configed by kernel itself. the cmdline will be like below: mem=510M@0 test_region=2M@510M above example tells kernel you have totally 512MB physical memory, but kernel will only use the first 510MB, the latter 2MB memory is used by you. how to map and use this region depends on you. in kernel, map this region to an continuous virtual region, note that the pgprot should be uncachable since you want to test without cache. 1. use early_param to get the physical start address and size of test_region, or you can just ignore this step and hard code to 510M and 2M for test purpose only. 2. use ioremap_nocache() to map this region to a virtual region. note that this funtion may fail if you are asking a very large vitual memroy region. once you configed like this, you can read/write to this vitual region without data cache invovled. -- With regards, Sandeep Kumar Anantapalli, ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Re: Kernel updating : export gpio not working ?
Just to update you that I have found my problem ! In my config file, I did not notice that my own board and an other imx27 board was enabled ! So the gpios configured was the one from this board and not mine's (thanks debugfs !). That is why it did not act like I wanted. Otherwise, the gpios are still exported as gpioXX and not with name_of_gpio. The label name_of_gpio can be found in the debugfs but not printed in the sysfs. I don't know if there is a way to change that, I will search for it if I have time. Best regards, -- Mylène JOSSERAND Le 27/02/2013 11:51, Mylene Josserand a écrit : Hi everyone ! I am currently updating the kernel of my company and I have some problems about gpios so I am asking you some help ! :) I think I am in the good mailist because it is the first time I update a kernel and a board configuration ! :D The previous kernel used was 2.6.31.14 and I am trying to update it to last stable version 3.7.9. In the previous kernel for a home-made board (with a IMx27 and a ARM9), we used these methods to export gpios in sysfs (for example for Gpio OUT) : mxc_gpio_mode(gpio_number | GPIO_GPIO | GPIO_OUT); gpio_request(gpio_number, name_of_gpio); gpio_export(gpio_number, 0); gpio_direction_output(gpio_number, gpio_value); In the sysfs, the gpio exported was visible under name_of_gpio. Now, if I use the same methods, I can not get anything in sysfs except gpiochip0, gpiochip32 etc. I tried to use these functions in a module and I could export a gpio but under gpioXX and not name_of_gpio. Moreover, I tried to export a gpio using the sysfs interface. I succeeded to export it and set direction to out but when I try to set the value, it did not work and the value is always set to 0 (and this gpio was configured as OUT in the board). I make a diff about the gpio documentation and the old kernel used did not seem to have many differences with the new kernel ! There is only some methods added such as gpio_resquest_one and gpio_export_link. I tried them without good results. What am I doing wrong ? What am I missing to make it work ? Is there some other configurations to add in the board configuration ? Thank you for any help/explanation ! ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Re: How to measure the RAM read/write performance
On Wed, 27 Feb 2013 15:38:00 +0530, sandeep kumar said: In development phase of the board, we are trying to measure RAM performance gain while changing type of the RAM. The standard benchmark tools are giving us the Cache performance only. So we want to try some method to measure RAM performance. The fact that you can't measure the effect of RAM speed because the L1/2/3 cache masks the effect should tell you something :) If you are seeing a 98% hit rate or so, RAM speed will indeed not matter much. If you're seeing a poor cache hit ratio, you're most likely to get better performance not by changing the RAM, but changing the application to improve its cache usage. And of course, if the application's design is one that is resistant to improved cache hit ratios, it is important you measure RAM performance *with that application running*, not a benchmark. This is because if your application is managing to thrash the cache, the resulting RAM access patterns will be *highly* sensitive to actual program behavior, and any corner cases in the hardware may or may not be hit by the benchmark the same way the application does. pgpZ2odHm7mss.pgp Description: PGP signature ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Re: Kernel updating : export gpio not working ?
On Wed, Feb 27, 2013 at 10:19 PM, Mylene Josserand mylene.josser...@navocap.com wrote: Just to update you that I have found my problem ! In my config file, I did not notice that my own board and an other imx27 board was enabled ! So the gpios configured was the one from this board and not mine's (thanks debugfs !). That is why it did not act like I wanted. This is the kind of post that I like most some one has problem but he/she also still find a way to solve. Then post it back to kernelnewbies. Nice info to know. -- regards, Mulyadi Santosa Freelance Linux trainer and consultant blog: the-hydra.blogspot.com training: mulyaditraining.blogspot.com ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Re: How to measure the RAM read/write performance
1. use early_param to get the physical start address and size of test_region, or you can just ignore this step and hard code to 510M and 2M for test purpose only. 2. use ioremap_nocache() to map this region to a virtual region. note that this funtion may fail if you are asking a very large vitual memroy region. Sounds good, i am gonna try this and let you know.. :) On Wed, Feb 27, 2013 at 8:19 PM, buyitian bu...@live.cn wrote: From: bu...@live.cn To: coolsandyfor...@gmail.com; kernelnewbies@kernelnewbies.org Subject: RE: How to measure the RAM read/write performance Date: Wed, 27 Feb 2013 22:33:15 +0800 CC: dhyla...@gmail.com From: coolsandyfor...@gmail.com Date: Tue, 26 Feb 2013 17:01:54 +0530 Subject: How to measure the RAM read/write performance To: kernelnewbies@kernelnewbies.org CC: dhyla...@gmail.com Hi All In performance benchmark tools, When we profile read/write timings mostly, those read/writes are done to cache only. I want to measure my DDR(RAM chip) performance. So i want to make sure, every read/write should happen to DDR RAM chip only. How can i achieve this...Any ideas/suggestions...? try to reserve a large region from bootloader(L4 in Qualcomm platform), let's say it is 10MB continuous physical memory. sorry, to be accurate, reserve physical memory is done by kernel cmdline, this cmdline parameter can be passed from L4 to kernel, or configed by kernel itself. the cmdline will be like below: mem=510M@0 test_region=2M@510M above example tells kernel you have totally 512MB physical memory, but kernel will only use the first 510MB, the latter 2MB memory is used by you. how to map and use this region depends on you. in kernel, map this region to an continuous virtual region, note that the pgprot should be uncachable since you want to test without cache. 1. use early_param to get the physical start address and size of test_region, or you can just ignore this step and hard code to 510M and 2M for test purpose only. 2. use ioremap_nocache() to map this region to a virtual region. note that this funtion may fail if you are asking a very large vitual memroy region. once you configed like this, you can read/write to this vitual region without data cache invovled. -- With regards, Sandeep Kumar Anantapalli, ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies -- With regards, Sandeep Kumar Anantapalli, ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Re: How to measure the RAM read/write performance
1. use early_param to get the physical start address and size of
test_region, or you can just ignore this step and hard code to 510M and 2M
for test purpose only.
2. use ioremap_nocache() to map this region to a virtual region. note that
this funtion may fail if you are asking a very large vitual memroy region.
I did the following things,
1) Reserved 3MB memory through ATAGS
2) Wrote small driver to ioremap that memory in following way,
void *tcpm_base = ioremap_nocache(0x03B0, SZ_3MB);
27 if(tcpm_base!=NULL)
28 {
29 printk(Jiffies %x %ld\n\n\n\n, jiffies, jiffies);
30 for(i=0;iSZ_4KB;i++)
31 src = readl(tcpm_base+i);
32 printk(Jiffies %x %ld\n\n\n\n, jiffies, jiffies);
33 }
34 else
35 printk(unable to map 3MB\n);
3) I am getting the following error,
[1.876647] Unable to handle kernel paging request at virtual address
ea82c000
[1.880950] pgd = c0004000
[1.883636] [ea82c000] *pgd=49818811, *pte=, *ppte=
[1.889892] Internal error: Oops: 7 [#1] PREEMPT
[1.894500] Modules linked in:
[1.897521] CPU: 0Not tainted (3.0.31-g1080f34-dirty #106)
[1.903442] PC is at sand_misc_init+0x4c/0xac
[1.907775] LR is at sand_misc_init+0x3c/0xac
[1.912109] pc : [c0022ee0]lr : [c0022ed0]psr: 8013
[1.912139] sp : e982bf98 ip : fp :
[1.923553] r10: r9 : r8 :
[1.928771] r7 : r6 : c00461b4 r5 : ea828000 r4 :
[1.935272] r3 : 3fff r2 : 3ffd r1 : c07ea2cf r0 : 0063
[1.941802] Flags: Nzcv IRQs on FIQs on Mode SVC_32 ISA ARM Segment
kernel
[1.949096] Control: 10c57c7d Table: 00404059 DAC: 0015
[1.954803]
[1.954833] PC: 0xc0022e60:
[1.959075] 2e60 c09105f0 c0366554 c07ea27e c07ea296 e3a01000 e92d4010
e1a02001 eb0a9acd
[1.967224] 2e80 e59f3008 e5830008 e3a1 e8bd8010 c0dd8380 e92d4037
e3a04000 e3a0063b
[1.975402] 2ea0 e3a01901 e1a02004 e5cd4007 e5cd4006 eb00b9aa e2505000
0a19 e59f3070
[1.983551] 2ec0 e59f0070 e5931000 e5932000 eb18a072 e58d4000 e3033fff
ea07 e59d2000
[1.991699] 2ee0 e7952002 f57ff04f e6ef2072 e5cd2007 e59d2000 e2822001
e58d2000 e59d2000
[1.999877] 2f00 e1520003 daf4 e59f3024 e59f0024 e5931000 e5932000
e28dd00c e8bd4030
[2.008026] 2f20 ea18a05d e59f0010 e28dd00c e8bd4030 ea18a059 c08ea600
c07ea2cf c07ea2e2
[2.016174] 2f40 e59f3040 e3a01000 e92d4010 e59f0038 e5932000 eb0a845a
e59f3030 e350
[2.024353]
[2.024353] LR: 0xc0022e50:
[2.028594] 2e50 e3e00015 e8bd81fc c0dd8380 c07ea279 c09105f0 c0366554
c07ea27e c07ea296
[2.036773] 2e70 e3a01000 e92d4010 e1a02001 eb0a9acd e59f3008 e5830008
e3a1 e8bd8010
[2.044921] 2e90 c0dd8380 e92d4037 e3a04000 e3a0063b e3a01901 e1a02004
e5cd4007 e5cd4006
[2.053070] 2eb0 eb00b9aa e2505000 0a19 e59f3070 e59f0070 e5931000
e5932000 eb18a072
[2.061248] 2ed0 e58d4000 e3033fff ea07 e59d2000 e7952002 f57ff04f
e6ef2072 e5cd2007
[2.069396] 2ef0 e59d2000 e2822001 e58d2000 e59d2000 e1520003 daf4
e59f3024 e59f0024
[2.077575] 2f10 e5931000 e5932000 e28dd00c e8bd4030 ea18a05d e59f0010
e28dd00c e8bd4030
[2.085723] 2f30 ea18a059 c08ea600 c07ea2cf c07ea2e2 e59f3040 e3a01000
e92d4010 e59f0038
[2.093872]
[2.093902] SP: 0xe982bf18:
[2.098144] bf18 382e3120 30393536 00205d35 00d0 4fff 3b00
192d8000 ea82bfff
[2.106292] bf38 03b0 e982bf84 c00461b4 c0044dac
0063 c07ea2cf
[2.114440] bf58 3ffd 3fff ea828000 c00461b4
[2.122619] bf78 e982bf98 c0022ed0 c0022ee0
8013
[2.130767] bf98 3ffd a27e c0037b4c c0022e94 c003f3fc
e9814a80 00373231
[2.138946] bfb8 0236 c0037b4c c003818c
c00461b4 0013
[2.147094] bfd8 c0008374 c0008300
c00461b4 c00461b4
[2.155242] bff8 0001 e9817940
c08e8ef4
[2.163421]
[2.163421] R1: 0xc07ea24f:
[2.167663] a24c 65207265 726f7272 6f6c6220 25206b63 000a646c 706f6f6c
26006425 3e2d6f6c
[2.175842] a26c 635f6f6c 6d5f6c74 78657475 6f6f6c00 363c0070 6f6f6c3e
6d203a70 6c75646f
[2.183990] a28c 6f6c2065 64656461 363c000a 6f6f6c3e 6f203a70 6f207475
656d2066 79726f6d
[2.192138] a2ac 6162000a 6e696b63 69665f67 7300656c 6c657a69 74696d69
74756100 656c636f
[2.200317] a2cc 4a007261 6969 25207365 6c252078 0a0a0a64 6e75000a
656c6261 206f7420
[2.208465] a2ec 2070616d 0a424d33 656d7000 65725f6d 6e6f6967 333c0073
656d703e 7325286d
[2.216613] a30c 736b3a29 635f7465 74616572 6e615f65 64615f64 61662064
000a6c69 703e343c
[2.224792] a32c 3a6d656d 6d6f7320 69687465 6920676e 65762073 77207972
676e6f72 6f79202c
[2.232940] a34c 72612075
