Thank you Srinivas, that was in my mind. I will do that and let you guys
know.
Regards,
Sri.
On Fri, Dec 27, 2013 at 7:34 PM, srinivas bakki wrote:
> Suggest you to eliminate the problem on the FPGA first. Hook on a scope
> onto the address lines of the FPGA and check whether you get the required
> addresses when you access it. I think there's no reason to doubt ioremap.
>
>
> On Fri, Dec 27, 2013 at 12:22 PM, haresh langaraman wrote:
>
>> Is there any way to specify in power pc that we can make static physical
>> to virtual mapping which is similar to io_table_init in ARM?
>>
>> choose the virtual address and map to FPGA physical address using mapping
>> function similar to io_table_init? I am hoping that it has to be there
>> because your platform driver requires to access the board's registers using
>> it.
>>
>> have you tried using io_remap alone instead of io_remap_nocahe?
>>
>> or just to try
>>
>> write a user space application with mmap to this address and try to see
>> whether you are able to read scratch regs?
>>
>>
>>
>> On Fri, Dec 27, 2013 at 12:11 PM, Sri Ram Vemulpali <
>> sri.ram.gm...@gmail.com> wrote:
>>
>>> Haresh,
>>>
>>> iotable_init() is specific to ARM arch. I am using powerpc, seems there
>>> is no equivalent to that static function. Can you please give more input.
>>>
>>> Thanks,
>>> Sri.
>>>
>>>
>>> On Thu, Dec 26, 2013 at 9:01 PM, Sri Ram Vemulpali <
>>> sri.ram.gm...@gmail.com> wrote:
>>>
Thanks for reply Haresh. Will try and let u know.
Thanks,
Sri
On Thu, Dec 26, 2013 at 5:09 PM, haresh langaraman
wrote:
> Hi ram,
>
> Can you try to map the address using io_table_init table of kernel
> initialization code.
>
> Thanks,
> Haresh.
> On 27 Dec 2013 05:12, "Sri Ram Vemulpali"
> wrote:
>
>> Hi All,
>>
>> I am using custom board MPC8641d. It has all evaluation board devices
>> connected. Apart from that an external FPGA device connected through
>> localbus.
>>
>> The localbus is at address 0xF5005000 directly connected to
>> processor. The FPGA address in the processor realm is 0xF380. As per
>> spec FPGA target interface is CS3 (chip select 3). 32-bit peripheral
>> address bus as seen by FPGA is 0xF380. The global address of FPGA is
>> 0x0BFC.
>>
>>
>> I am implementing driver for FPGA. I am using ioremap() to map to
>> FPGA registers at location 0xF380. The virtual address returned by
>> ioremap() when used with write32(), read32() at memory locations shows no
>> response from device. FPGA has special scratch pad to which one can write
>> and read to validate the memory map is working. When I write and read I
>> see
>> no value.
>>
>> #define FCP_ADDRESS_START 0xF380
>> #define FCP_ADDRESS_END 0xF3808000
>> #define FCP_ADDRESS_RANGE (FCP_ADDRESS_END - FCP_ADDRESS_START)
>>
>> void *fcp_scratch_pad;
>> char buff[10];
>>
>> io_fcp_mem = ioremap_nocache( FCP_ADDRESS_START, FCP_ADDRESS_RANGE );
>>
>> if( ! io_fcp_mem ) {
>> return -ENODEV;
>> }
>>
>> printk( KERN_CRIT "ioremap virt mem:%p\n", io_fcp_mem );
>>
>> fcp_scratch_pad = ((char*)io_fcp_mem) + 224;
>>
>> printk( KERN_CRIT "scratch pad virt mem:%p\n",
>> fcp_scratch_pad );
>>
>> iowrite8_rep( fcp_scratch_pad, "Hello", 6 );
>>
>> ioread8_rep( fcp_scratch_pad, buff, 6 );
>>
>> printk( KERN_CRIT "value read from scratch_pad:%s\n", buff );
>>
>> return 0;
>>
>>
>> Attached is the device tree of the board.
>>
>> Can anyone please direct me or point where I am doing wrong. It seems
>> I am unable to access FPGA device memory. Thanks.
>>
>> --
>> Regards,
>> Sri.
>>
>> ___
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>>
>>
--
Regards,
Sri.
>>>
>>>
>>>
>>> --
>>> Regards,
>>> Sri.
>>>
>>
>>
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>> Kernelnewbies mailing list
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>>
>>
>
--
Regards,
Sri.
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