Re: Memory barrier
Hi, In my opinion it is not correct to say "make order on current CPU" in case of SMP. Actually, we cope with shared resource here - memory, and observes for that resource - CPUs. As soon as CPU is asked to make a barrier (with some sort of instruction) access to shared resource is ordered among all of observers. So, in case of SMP we have to protect shared resource with "hardware" memory barriers. In case of UP, memory is not shared, so, generally, we have to take care that memory access won't be optimized by compiler. P.S. Sorry for digging this thread. Best wishes Vladimir Murzin On 12/9/11, 卜弋天 wrote: > > Hi : > > if you write code as below: > > golbal int in1=0,int2=0; > > cpu1: cpu2: > > int1 = 1; b= int2; > smp_wmb() > int2 = 2; a = in1; > > cpu2 may get the result: b==2 & a==0 , which means although cpu1 set int1=1 > before int2=2, there is no garentee for cpu2 to perceive int1 before int2. > you must add smp_rmb() inside cpu2 to prevent this. > > two cpus must cooperate to acheive the sequence memory order. > > > > > >> Date: Fri, 9 Dec 2011 14:14:37 +0530 >> Subject: Re: Memory barrier >> From: trisha1ma...@gmail.com >> To: bu...@live.cn >> CC: kernelnewbies@kernelnewbies.org >> >> I will add more info here: >> smp_mb() >> Similar to mb(), but only guarantees ordering between cores/processors >> within an SMP system. All memory accesses before the smp_mb() will be >> visible to all cores within the SMP system before any accesses after >> the smp_mb(). >> smp_rmb() >> Like smp_mb(), but only guarantees ordering between read accesses. >> smp_wmb() >> Like smp_mb(), but only guarantees ordering between write accesses. >> >> So these made me total confuse . >> >> Thanks >> >> 2011/12/9 trisha yad : >> > Thanks, >> > >> > I got bit confuse with below statement: >> > This is from paper Memory access ordering Part 2 >> > SMP conditional barriers >> > The SMP conditional barriers are used to ensure a consistent view of >> > memory between different cores within a cache coherent SMP system. >> > When compiling a kernel without CONFIG_SMP, all SMP barriers are >> > converted into plain compiler barriers. >> > >> > 2011/12/9 卜弋天 : >> >> Hi : >> >> >> >> memory barriers can not make order on other cpus, only the current >> >> cpu's order will be promised. >> >> >> >> >> >> >> >>> Date: Fri, 9 Dec 2011 12:54:40 +0530 >> >>> Subject: Memory barrier >> >>> From: trisha1ma...@gmail.com >> >>> To: Kernelnewbies@kernelnewbies.org >> >> >> >>> >> >>> Hi All, >> >>> >> >>> I need small clarification on memory barrier. >> >>> #define smp_mb() mb() >> >>> #define smp_rmb() rmb() >> >>> #define smp_wmb() wmb() >> >>> In case of SMP: >> >>> is smp_mb() or smp_rmb() make order on current CPU or all cpu's >> >>> >> >>> Thanks >> >>> >> >>> ___ >> >>> Kernelnewbies mailing list >> >>> Kernelnewbies@kernelnewbies.org >> >>> http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies >> >> ___ >> Kernelnewbies mailing list >> Kernelnewbies@kernelnewbies.org >> http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies > ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Re: memory barrier in UP
Hi Subin On Tue, Dec 13, 2011 at 01:57, subin gangadharan wrote: > Hi Mulyadi, > > Thanks for the answer. You welcome...I just shared what I know :) > In that case (ALPHA), is compiler barrier sufficient enough to prevent > the re ordering done by the processor. > What I was thinking,compiler barrier is to instruct the compiler to > not do any re ordering. Again this is architecture problem. I am not sure about Alpha, since I only know about one compiler barrier that is "volatile". What I guess is that in Alpha, it could be something elsemaybe it is assembly instruction like "lock" or something. I remember there's an old Linuxjournal article that explains about it. So to avoid further misunderstandings that I might bring, please kindly read this article: http://www.linuxjournal.com/article/8212 Hope that helps... -- regards, Mulyadi Santosa Freelance Linux trainer and consultant blog: the-hydra.blogspot.com training: mulyaditraining.blogspot.com ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Re: memory barrier in UP
Hi Mulyadi, Thanks for the answer. On Mon, Dec 12, 2011 at 11:16 AM, Mulyadi Santosa wrote: > Hi... > > On Mon, Dec 12, 2011 at 01:11, subin gangadharan > wrote: >> Hi All, >> >> I am reading about the barrier from linux kernel development.In this >> books, he says >> "On SMP kernels they are defined only as usual memory barriers.where >> as on UP kernels they are >> defined only as a compiler barrier" >> >> Does this mean in UP, processor won't reorder the instructions ? > > In some arch like Alpha, loosely reordering even in UP could happen at > any time. But in x86 UP, IIRC there's only strict re-ordering, meaning > that every read is always fetching latest write etc. In that case (ALPHA), is compiler barrier sufficient enough to prevent the re ordering done by the processor. What I was thinking,compiler barrier is to instruct the compiler to not do any re ordering. Please correct me if I am wrong. > -- > regards, > > Mulyadi Santosa > Freelance Linux trainer and consultant > > blog: the-hydra.blogspot.com > training: mulyaditraining.blogspot.com -- With Regards Subin Gangadharan I am not afraid and I am also not afraid of being afraid. ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Re: memory barrier in UP
Hi... On Mon, Dec 12, 2011 at 01:11, subin gangadharan wrote: > Hi All, > > I am reading about the barrier from linux kernel development.In this > books, he says > "On SMP kernels they are defined only as usual memory barriers.where > as on UP kernels they are > defined only as a compiler barrier" > > Does this mean in UP, processor won't reorder the instructions ? In some arch like Alpha, loosely reordering even in UP could happen at any time. But in x86 UP, IIRC there's only strict re-ordering, meaning that every read is always fetching latest write etc. -- regards, Mulyadi Santosa Freelance Linux trainer and consultant blog: the-hydra.blogspot.com training: mulyaditraining.blogspot.com ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
memory barrier in UP
Hi All, I am reading about the barrier from linux kernel development.In this books, he says "On SMP kernels they are defined only as usual memory barriers.where as on UP kernels they are defined only as a compiler barrier" Does this mean in UP, processor won't reorder the instructions ? Could please give any idea on this. -- With Regards Subin Gangadharan I am not afraid and I am also not afraid of being afraid. ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
RE: Memory barrier
Hi : if you write code as below: golbal int in1=0,int2=0; cpu1: cpu2: int1 = 1; b= int2; smp_wmb() int2 = 2; a = in1; cpu2 may get the result: b==2 & a==0 , which means although cpu1 set int1=1 before int2=2, there is no garentee for cpu2 to perceive int1 before int2. you must add smp_rmb() inside cpu2 to prevent this. two cpus must cooperate to acheive the sequence memory order. > Date: Fri, 9 Dec 2011 14:14:37 +0530 > Subject: Re: Memory barrier > From: trisha1ma...@gmail.com > To: bu...@live.cn > CC: kernelnewbies@kernelnewbies.org > > I will add more info here: > smp_mb() > Similar to mb(), but only guarantees ordering between cores/processors > within an SMP system. All memory accesses before the smp_mb() will be > visible to all cores within the SMP system before any accesses after > the smp_mb(). > smp_rmb() > Like smp_mb(), but only guarantees ordering between read accesses. > smp_wmb() > Like smp_mb(), but only guarantees ordering between write accesses. > > So these made me total confuse . > > Thanks > > 2011/12/9 trisha yad : > > Thanks, > > > > I got bit confuse with below statement: > > This is from paper Memory access ordering Part 2 > > SMP conditional barriers > > The SMP conditional barriers are used to ensure a consistent view of > > memory between different cores within a cache coherent SMP system. > > When compiling a kernel without CONFIG_SMP, all SMP barriers are > > converted into plain compiler barriers. > > > > 2011/12/9 卜弋天 : > >> Hi : > >> > >> memory barriers can not make order on other cpus, only the current > >> cpu's order will be promised. > >> > >> > >> > >>> Date: Fri, 9 Dec 2011 12:54:40 +0530 > >>> Subject: Memory barrier > >>> From: trisha1ma...@gmail.com > >>> To: Kernelnewbies@kernelnewbies.org > >> > >>> > >>> Hi All, > >>> > >>> I need small clarification on memory barrier. > >>> #define smp_mb() mb() > >>> #define smp_rmb() rmb() > >>> #define smp_wmb() wmb() > >>> In case of SMP: > >>> is smp_mb() or smp_rmb() make order on current CPU or all cpu's > >>> > >>> Thanks > >>> > >>> ___ > >>> Kernelnewbies mailing list > >>> Kernelnewbies@kernelnewbies.org > >>> http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies > > ___ > Kernelnewbies mailing list > Kernelnewbies@kernelnewbies.org > http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Re: Memory barrier
I will add more info here: smp_mb() Similar to mb(), but only guarantees ordering between cores/processors within an SMP system. All memory accesses before the smp_mb() will be visible to all cores within the SMP system before any accesses after the smp_mb(). smp_rmb() Like smp_mb(), but only guarantees ordering between read accesses. smp_wmb() Like smp_mb(), but only guarantees ordering between write accesses. So these made me total confuse . Thanks 2011/12/9 trisha yad : > Thanks, > > I got bit confuse with below statement: > This is from paper Memory access ordering Part 2 > SMP conditional barriers > The SMP conditional barriers are used to ensure a consistent view of > memory between different cores within a cache coherent SMP system. > When compiling a kernel without CONFIG_SMP, all SMP barriers are > converted into plain compiler barriers. > > 2011/12/9 卜弋天 : >> Hi : >> >> memory barriers can not make order on other cpus, only the current >> cpu's order will be promised. >> >> >> >>> Date: Fri, 9 Dec 2011 12:54:40 +0530 >>> Subject: Memory barrier >>> From: trisha1ma...@gmail.com >>> To: Kernelnewbies@kernelnewbies.org >> >>> >>> Hi All, >>> >>> I need small clarification on memory barrier. >>> #define smp_mb()mb() >>> #define smp_rmb() rmb() >>> #define smp_wmb() wmb() >>> In case of SMP: >>> is smp_mb() or smp_rmb() make order on current CPU or all cpu's >>> >>> Thanks >>> >>> ___ >>> Kernelnewbies mailing list >>> Kernelnewbies@kernelnewbies.org >>> http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Re: Memory barrier
Thanks, I got bit confuse with below statement: This is from paper Memory access ordering Part 2 SMP conditional barriers The SMP conditional barriers are used to ensure a consistent view of memory between different cores within a cache coherent SMP system. When compiling a kernel without CONFIG_SMP, all SMP barriers are converted into plain compiler barriers. 2011/12/9 卜弋天 : > Hi : > > memory barriers can not make order on other cpus, only the current > cpu's order will be promised. > > > >> Date: Fri, 9 Dec 2011 12:54:40 +0530 >> Subject: Memory barrier >> From: trisha1ma...@gmail.com >> To: Kernelnewbies@kernelnewbies.org > >> >> Hi All, >> >> I need small clarification on memory barrier. >> #define smp_mb()mb() >> #define smp_rmb() rmb() >> #define smp_wmb() wmb() >> In case of SMP: >> is smp_mb() or smp_rmb() make order on current CPU or all cpu's >> >> Thanks >> >> ___ >> Kernelnewbies mailing list >> Kernelnewbies@kernelnewbies.org >> http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
RE: Memory barrier
Hi : memory barriers can not make order on other cpus, only the current cpu's order will be promised. > Date: Fri, 9 Dec 2011 12:54:40 +0530 > Subject: Memory barrier > From: trisha1ma...@gmail.com > To: Kernelnewbies@kernelnewbies.org > > Hi All, > > I need small clarification on memory barrier. > #define smp_mb()mb() > #define smp_rmb() rmb() > #define smp_wmb() wmb() > In case of SMP: > is smp_mb() or smp_rmb() make order on current CPU or all cpu's > > Thanks > > ___ > Kernelnewbies mailing list > Kernelnewbies@kernelnewbies.org > http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
Memory barrier
Hi All, I need small clarification on memory barrier. #define smp_mb() mb() #define smp_rmb() rmb() #define smp_wmb() wmb() In case of SMP: is smp_mb() or smp_rmb() make order on current CPU or all cpu's Thanks ___ Kernelnewbies mailing list Kernelnewbies@kernelnewbies.org http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
