Re: [Kicad-developers] [PATCH] Fix clang warnings

2014-06-02 Thread Lorenzo Marcantonio
On Tue, Jun 03, 2014 at 08:18:52AM +0200, Heiko Rosemann wrote:
> Probably the way to do this formally correct and without relying on
> implicit integer-boolean conversion would be the following:
> if( (ip = s1.Intersect( s_next )) != 0 )

Best of all MISRA-C recommends

if (0 != stuff())

because even in the == case, a mistyped = won't compile. Paranoid stuff,
of course (to avoid memory access errors they simply somewhat banned
pointers). However be careful in C++:

if (stuff())

triggers an implicit to-bool conversion where

if (0 != stuff())

uses an implicit to-int conversion (due to integral promotion)

And for to-bool implicit conversion there is a special rule. An you could
have defined an operator bool() but not an operator int(). Obviously it
depends on what stuff() returns exactly... Usual C++ nasty need-to-know
stuff. See http://en.cppreference.com/w/cpp/language/implicit_cast

-- 
Lorenzo Marcantonio
Logos Srl

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Re: [Kicad-developers] [PATCH] Fix clang warnings

2014-06-02 Thread Heiko Rosemann
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1

On 06/03/2014 04:49 AM, tiger12506 wrote:
> This is a guess (i'm not OP), but it's pretty common to shun
> assignment within an if condition. The second line probably just
> masks the warning from the compiler -- the check that triggers the
> warning probably isn't exhaustive enough to check within the
> parentheses for assignment.

Probably the way to do this formally correct and without relying on
implicit integer-boolean conversion would be the following:
if( (ip = s1.Intersect( s_next )) != 0 )

Heiko

> On 6/2/2014 6:32 PM, Tomasz Wlostowski wrote:
>> On 02.06.2014 19:52, Bernhard Stegmaier wrote:
>>> Hi,
>>> 
>>> building with clang (at least on OSX) and -Wall is really noisy
>>> so that you can hardly see what’s going wrong. So, I decided to
>>> fix the warnings… attached are 3 patches I prepared (against
>>> rev. 4911):
>>> 
>>> *** clang-warnings-1.diff: Everything that probably should be
>>> fixed:\
>> 
>> Hi Bernhard,
>> 
>> -if( ip = s1.Intersect( s_next ) ) +if(
>> (ip = s1.Intersect( s_next )) )
>> 
>> What upsets clang in the first line? I'm asking because I'm
>> unable to get Kicad to build with clang on Linux (wx 3.0) due to
>> compilation errors in wx...
>> 
>> Tom


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Re: [Kicad-developers] [PATCH] Fix clang warnings

2014-06-02 Thread Bernhard Stegmaier
Hi,

it warns because it is not clear whether (a) you really mean the assignment 
(and want to check if the result is zero) or (b) you just forgot one “=“ and 
you meant “ip == s1…”. The additional brackets are proposed in the compiler 
warning to silence the warning in case of (a).

Beside a lot of warnings I have switched off via compile switch both build for 
me.
On OSX, I have:
Apple LLVM version 5.1 (clang-503.0.40) (based on LLVM 3.4svn)


Regards,
Bernhard

On 03.06.2014, at 00:32, Tomasz Wlostowski  wrote:

> On 02.06.2014 19:52, Bernhard Stegmaier wrote:
>> Hi,
>> 
>> building with clang (at least on OSX) and -Wall is really noisy so that
>> you can hardly see what’s going wrong.
>> So, I decided to fix the warnings… attached are 3 patches I prepared
>> (against rev. 4911):
>> 
>> *** clang-warnings-1.diff:
>> Everything that probably should be fixed:\
> 
> Hi Bernhard,
> 
> -if( ip = s1.Intersect( s_next ) )
> +if( (ip = s1.Intersect( s_next )) )
> 
> What upsets clang in the first line? I'm asking because I'm unable to get 
> Kicad to build with clang on Linux (wx 3.0) due to compilation errors in wx...
> 
> Tom

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Re: [Kicad-developers] [PATCH] Fix clang warnings

2014-06-02 Thread tiger12506
This is a guess (i'm not OP), but it's pretty common to shun assignment 
within an if condition.
The second line probably just masks the warning from the compiler -- the 
check that triggers the warning probably isn't exhaustive enough to 
check within the parentheses for assignment.



On 6/2/2014 6:32 PM, Tomasz Wlostowski wrote:

On 02.06.2014 19:52, Bernhard Stegmaier wrote:

Hi,

building with clang (at least on OSX) and -Wall is really noisy so that
you can hardly see what’s going wrong.
So, I decided to fix the warnings… attached are 3 patches I prepared
(against rev. 4911):

*** clang-warnings-1.diff:
Everything that probably should be fixed:\


Hi Bernhard,

-if( ip = s1.Intersect( s_next ) )
+if( (ip = s1.Intersect( s_next )) )

What upsets clang in the first line? I'm asking because I'm unable to 
get Kicad to build with clang on Linux (wx 3.0) due to compilation 
errors in wx...


Tom

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Re: [Kicad-developers] [PATCH] Fix clang warnings

2014-06-02 Thread Tomasz Wlostowski

On 02.06.2014 19:52, Bernhard Stegmaier wrote:

Hi,

building with clang (at least on OSX) and -Wall is really noisy so that
you can hardly see what’s going wrong.
So, I decided to fix the warnings… attached are 3 patches I prepared
(against rev. 4911):

*** clang-warnings-1.diff:
Everything that probably should be fixed:\


Hi Bernhard,

-if( ip = s1.Intersect( s_next ) )
+if( (ip = s1.Intersect( s_next )) )

What upsets clang in the first line? I'm asking because I'm unable to 
get Kicad to build with clang on Linux (wx 3.0) due to compilation 
errors in wx...


Tom

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Re: [Kicad-developers] [PATCH] Fix clang warnings

2014-06-02 Thread Bernhard Stegmaier
Of course x >=0 … or x < 0… :)

Some of the unused variables really don’t seem to be used… e.g. in 
pcb_calculator classes, where I really guess no OSX dependencies and don’t see 
any #define around...


Regards,
Bernhard

On 02.06.2014, at 20:04, Lorenzo Marcantonio  wrote:

> On Mon, Jun 02, 2014 at 07:52:52PM +0200, Bernhard Stegmaier wrote:
>> Removes unneeded checks (e.g., a check “x > 0” for an "unsigned x” is pretty 
>> obsolete).
> 
> x >= 0, I hope :D
> 
> As for unused variable probably it's only a Mac thing (or clang has
> a better flow analyzer than g++), I don't see any with -O3 -Wall on
> linux
> 
> -- 
> Lorenzo Marcantonio
> Logos Srl
> 
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Re: [Kicad-developers] [PATCH] Fix clang warnings

2014-06-02 Thread Lorenzo Marcantonio
On Mon, Jun 02, 2014 at 07:52:52PM +0200, Bernhard Stegmaier wrote:
> Removes unneeded checks (e.g., a check “x > 0” for an "unsigned x” is pretty 
> obsolete).

x >= 0, I hope :D

As for unused variable probably it's only a Mac thing (or clang has
a better flow analyzer than g++), I don't see any with -O3 -Wall on
linux

-- 
Lorenzo Marcantonio
Logos Srl

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[Kicad-developers] [PATCH] Fix clang warnings

2014-06-02 Thread Bernhard Stegmaier
Hi,

building with clang (at least on OSX) and -Wall is really noisy so that you can 
hardly see what’s going wrong.
So, I decided to fix the warnings… attached are 3 patches I prepared (against 
rev. 4911):

*** clang-warnings-1.diff:
Everything that probably should be fixed:
* Disable “overloaded virtual” and many template warnings by means of compiler 
switch (maybe they should be checked somewhen, but most of the stuff seems to 
come from wxWidgets and other libraries)
* Mainly cosmetic stuff and some things with undefined behavior
* A real catch in view.cpp with a wrong “;”

*** clang-warnings-2.diff:
Removes every variable/function reported as unused. 
Might probably depend on my configuration, I don’t know whether they should be 
kept or not for whatever reason.

*** clang-warnings-3.diff:
Removes unneeded checks (e.g., a check “x > 0” for an "unsigned x” is pretty 
obsolete).

With those 3 patches it builds really nice and clean also with clang (like I 
have seen on linux with gcc).


Best regards,
Bernhard



clang-warnings-1.diff
Description: Binary data


clang-warnings-2.diff
Description: Binary data


clang-warnings-3.diff
Description: Binary data
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Re: [Kicad-developers] Jenkins halted?

2014-06-02 Thread Marco Ciampa
On Mon, Jun 02, 2014 at 11:04:21PM +1200, Blair Bonnett wrote:
> For anybody wanting to use GitHub, I also have a mirror at
> https://github.com/blairbonnett-mirrors/kicad which is updated every 10
> minutes. Henner Zeller used it to fork from for his contributions a couple
> of months back so I assume it is usable :).

Hello to all the list and many thanks for this mirror.

What about to write about these mirrors somewhere?

-- 


Marco Ciampa

"L'utopia sta all'orizzonte. Mi avvicino  di due passi, lei si allontana
di due  passi. Faccio dieci  passi e  l'orizzonte si allontana  di dieci
passi.  Per quanto cammini, non la raggiungerò  mai. A cosa serve
l'utopia? A questo: serve a camminare."  Eduardo Galeano

++
| Linux User  #78271 |
| FSFE fellow   #364 |
++


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Re: [Kicad-developers] [Kicad-lib-committers] Silk screens over pads and naming

2014-06-02 Thread Lorenzo Marcantonio
On Mon, Jun 02, 2014 at 10:32:18AM -0400, Jean-Paul Louis wrote:
> Guys,
> 
> I am reading all this thread, and I am amazed that people suggest a silk 
> shape that will HAVE TO BE REMOVED by the PCB fabricator.

The industry took a long time to discover this, too :D
And it isn't a full standard yet, too!

> This is adding cost to a PCB without any value added.

Without a separate fabrication layer I think could the best way to
achieve the assembly drawing. Otherwise silk+pads could be OK, too.
OTOH cost for silk is (usually) independant of how much ink you use...
I guess that for high volume production it would matter, but I have no
experience on that.

> The example shown by Lorenzo is a very good example. The yellow rectangle has 
> zero value AND an extra cost, while just two lines (shown in white) provide 
> the real value of locating the chip without hindering the manufacturing 
> process.
> On top to it, because it is just inside the guard area (outside rectangle), 
> it provide guidance for the 
> clearance between parts.

In fact the specs says that silk should be on the 'maximum material'
position. I don't remember if I drawn them that way. Anyway the idea is
that silk should be visible after assembly for inspection, this is the
*new* primary purpose of the silk. The *old* one, guidance for assembly,
is mostly obsolete (machines read fiducials, not silk screen)

Guidance for clearance would be actually done with the courtyard (dark
grey boxes). Rejected along the fabrication drawing, too... some CAD
system (the mentor ones, I guess, since they somewhat invented it)
actually do DRC on courtyard to avoid collision and such.

Sadly I have no money for PADS/Boardstation/Expedition whatever they
sell these days, so I don't know for sure (pcblibraries and the
footprint generator *are* by mentor, BTW)

-- 
Lorenzo Marcantonio
Logos Srl

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Re: [Kicad-developers] [Kicad-lib-committers] Silk screens over pads and naming

2014-06-02 Thread Jean-Paul Louis
Guys,

I am reading all this thread, and I am amazed that people suggest a silk shape 
that will HAVE TO BE REMOVED by the PCB fabricator.
This is adding cost to a PCB without any value added.

The example shown by Lorenzo is a very good example. The yellow rectangle has 
zero value AND an extra cost, while just two lines (shown in white) provide the 
real value of locating the chip without hindering the manufacturing process.
On top to it, because it is just inside the guard area (outside rectangle), it 
provide guidance for the 
clearance between parts.

Thank you, Lorenzo.

Jean-Paul
AC9GH


On Jun 2, 2014, at 5:54 AM, Lorenzo Marcantonio  
wrote:

> On Mon, Jun 02, 2014 at 09:57:47AM +0200, Paweł Dras wrote:
>> IMHO some rules according to silk should be specified in convention. For
>> example line width should be the same (perhaps with some exceptions) in
> 
> IPC says that, depending on the environment, line should be 4/5/6 mils
> or 0.1/0.12/0.15 mm (yes, it depends on the 'main' unit). So for
> a nominal metric design it would be 0.12mm. However our fabricators says
> that silk is 0.2mm minimum anyway, since we usually do 'true' silk
> screening (not inkjet). YMMV, depending on the process available.
> 
>> whole library, because then the PCB looks clean and more "professional".
>> With pads over the silk is the same situation, in many cases after silk
>> erasure by solder mask it don't looks good on final product.
> 
> By experience after erasure it sucks a lot! SOICs with silk erasures
> seems jumbles of dots.
> 
>> Another problem is to wide placed silk.
>> For example in attachment is how looks now silk for 1206 resistor and my
>> proposal for new one. IMHO the silk should be tight to the pad, because
>> then when we place few such resistors close to each other we don't get a
>> mess with silk.
> 
> The new one is more like in principle to the IPC one (see attachment).
> The main issue is that silk for chip components eats valuable courtyard
> space, especially when you need a wider pad for probing (this is not
> taken in account by IPC!). In fact on the 0603 pads we use you can quite
> easily mount a 0805... As usual it depends on your target density.
> 
> See other attachment to see how do i do these usually (even the SOT23s
> are oversized for mechanical resistance). However I packed things way
> more than that, this is a test board designed for hand assembly :P
> 
>> I have a question, can be ref and value placed as in my attachment or
>> should  be above and below resistor?
> 
> Value usually is not shown on silk; it's already difficult enough to
> place the refdes! By convention refdes is on the placement point for
> fabrication drawing and... wherever it fits on the silk. If there is
> place, obviously... sometimes you see block of components (usually small
> passives) bracketed on the silk with the list of the references, but
> that is manual tune-up of the layout of course.
> 
> -- 
> Lorenzo Marcantonio
> Logos Srl
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Re: [Kicad-developers] Jenkins halted?

2014-06-02 Thread Blair Bonnett
On 2 June 2014 22:35, jp charras  wrote:

> Le 02/06/2014 12:15, Povilas Kanapickas a écrit :
> > On 02/06/14 12:36, Povilas Kanapickas wrote:
> >> On 29/05/14 16:15, Nick Østergaard wrote:
> >>> Hello
> >>>
> >>> I am not sure who maintains the Jenkins build bot at
> >>> http://ci.kicad-pcb.org/, but I have noticed that is has stopped. I am
> >>> not sure who runs that, so I write to the list.
> >>>
> >>> Also the kicad-source-mirror on github has stopped updating. Is it the
> >>> same person that maintains those services?
> >>>
> >>
> >> Hi,
> >>
> >> I've had a hard drive failure and haven't fully recovered my working
> >> environment yet. I expect to fix the issue and start updating the mirror
> >> in the coming days. Sorry for the inconveniences :-)
> >>
> >> Cheers,
> >> Povilas
> >>
> >
> > I've just pushed some hundred of commits that have accumulated. The
> > mirror won't update each 10 minutes for now, that will be fixed in the
> > near future.
> >
> > Cheers,
> > Povilas
>
> Thanks, Povilas.
>
> It looks like your involvement is highly appreciated, especially for
> kicad-source-mirror on github.
>

For anybody wanting to use GitHub, I also have a mirror at
https://github.com/blairbonnett-mirrors/kicad which is updated every 10
minutes. Henner Zeller used it to fork from for his contributions a couple
of months back so I assume it is usable :).

Blair
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Re: [Kicad-developers] Jenkins halted?

2014-06-02 Thread jp charras
Le 02/06/2014 12:15, Povilas Kanapickas a écrit :
> On 02/06/14 12:36, Povilas Kanapickas wrote:
>> On 29/05/14 16:15, Nick Østergaard wrote:
>>> Hello
>>>
>>> I am not sure who maintains the Jenkins build bot at
>>> http://ci.kicad-pcb.org/, but I have noticed that is has stopped. I am
>>> not sure who runs that, so I write to the list.
>>>
>>> Also the kicad-source-mirror on github has stopped updating. Is it the
>>> same person that maintains those services?
>>>
>>
>> Hi,
>>
>> I've had a hard drive failure and haven't fully recovered my working
>> environment yet. I expect to fix the issue and start updating the mirror
>> in the coming days. Sorry for the inconveniences :-)
>>
>> Cheers,
>> Povilas
>>
> 
> I've just pushed some hundred of commits that have accumulated. The
> mirror won't update each 10 minutes for now, that will be fixed in the
> near future.
> 
> Cheers,
> Povilas

Thanks, Povilas.

It looks like your involvement is highly appreciated, especially for
kicad-source-mirror on github.

Jenkins build is also highly appreciated, because if something is wrong
after a commit, we know very fast there is an issue after this commit
(which happens sometimes, despites our tests).
I experienced that.


-- 
Jean-Pierre CHARRAS

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Re: [Kicad-developers] Jenkins halted?

2014-06-02 Thread Povilas Kanapickas

On 02/06/14 12:36, Povilas Kanapickas wrote:

On 29/05/14 16:15, Nick Østergaard wrote:

Hello

I am not sure who maintains the Jenkins build bot at
http://ci.kicad-pcb.org/, but I have noticed that is has stopped. I am
not sure who runs that, so I write to the list.

Also the kicad-source-mirror on github has stopped updating. Is it the
same person that maintains those services?



Hi,

I've had a hard drive failure and haven't fully recovered my working
environment yet. I expect to fix the issue and start updating the mirror
in the coming days. Sorry for the inconveniences :-)

Cheers,
Povilas



I've just pushed some hundred of commits that have accumulated. The 
mirror won't update each 10 minutes for now, that will be fixed in the 
near future.


Cheers,
Povilas



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Re: [Kicad-developers] Jenkins halted?

2014-06-02 Thread Povilas Kanapickas

On 29/05/14 16:15, Nick Østergaard wrote:

Hello

I am not sure who maintains the Jenkins build bot at
http://ci.kicad-pcb.org/, but I have noticed that is has stopped. I am
not sure who runs that, so I write to the list.

Also the kicad-source-mirror on github has stopped updating. Is it the
same person that maintains those services?



Hi,

I've had a hard drive failure and haven't fully recovered my working 
environment yet. I expect to fix the issue and start updating the mirror 
in the coming days. Sorry for the inconveniences :-)


Cheers,
Povilas



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