Re: [PATCH] KVM: disable halt_poll_ns as default for s390x

[Christian Borntraeger]

Am 18.09.2015 um 13:29 schrieb Paolo Bonzini:
> 
> 
> On 18/09/2015 12:54, Christian Borntraeger wrote:
>>> -/* halt polling only reduces halt latency by 5-7 us, 500us is enough */
>>> -static unsigned int halt_poll_ns = 50;
>>> +/* Architectures should define their poll value according to the halt 
>>> latency */
>>> +static unsigned int halt_poll_ns = KVM_HALT_POLL_NS_DEFAULT;
>>
>> Yes, I prefer this over disabling it via Kconfig. There are benchmarks which
>> benefit from polling on s390. Furthermore it seems that the latency
>> strongly depends on timing of the architecture so making it per arch is
>> probably the right thing to do.
> 
> Perhaps a #ifndef is better than replicating the 500us default in all
> architectures?  Or should the default be 0?

Any guidance from your side? All different proposals are certainly ok.
Are you going to take Davids patch or shall he respin?

Christian

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RE: [PATCH v2 00/15] KVM: arm64: GICv3 ITS emulation

[Pavel Fedin]

 Hello Andre and others!

 How are things going? I see the last message in thread something like 1 month 
old, then silence...
 Our project relies on this feature, any assistance needed?

Kind regards,
Pavel Fedin
Expert Engineer
Samsung Electronics Research center Russia


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Re: [PATCH] KVM: x86: fix bogus warning about reserved bits

[Borislav Petkov]

On Thu, Sep 24, 2015 at 11:23:08AM +0800, Xiao Guangrong wrote:
> >+static inline bool
> >+boot_cpu_is_amd(void)
> >+{
> >+WARN_ON_ONCE(!tdp_enabled);
> >+return shadow_x_mask != 0;
> 
> shadow_x_mask != 0 is Intel's CPU.
> 
> Borislav, could you please check shadow_x_mask == 0 instead and test it again?

That did the trick:

[   62.640392] kvm: zapping shadow pages for mmio generation wraparound
[   63.100301] cpuid(0).ebx = 68747541
[   63.193426] kvm [3748]: vcpu0 unhandled rdmsr: 0xc0010112
[   64.538294] kvm [3748]: vcpu0 unhandled rdmsr: 0xc0011021
[   64.866263] kvm [3748]: vcpu1 unhandled rdmsr: 0xc0011021
[   64.971972] kvm [3748]: vcpu2 unhandled rdmsr: 0xc0011021
[   65.070376] kvm [3748]: vcpu3 unhandled rdmsr: 0xc0011021
[   65.170625] kvm [3748]: vcpu4 unhandled rdmsr: 0xc0011021
[   65.272838] kvm [3748]: vcpu5 unhandled rdmsr: 0xc0011021
[   65.374288] kvm [3748]: vcpu6 unhandled rdmsr: 0xc0011021
[   65.474825] kvm [3748]: vcpu7 unhandled rdmsr: 0xc0011021

That's all I got in dmesg from booting the guest - no more mmio PF
warnings.

Thanks.

-- 
Regards/Gruss,
Boris.

ECO tip #101: Trim your mails when you reply.
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RE: [PATCH 1/3] arm/arm64: KVM: vgic: Check for !irqchip_in_kernel() when mapping resources

[Pavel Fedin]

 Hello!

> Until b26e5fdac43c ("arm/arm64: KVM: introduce per-VM ops"),
> kvm_vgic_map_resources() used to include a check on irqchip_in_kernel(),
> and vgic_v2_map_resources() still has it.

 I'm back from vacation and very glad to see myself being useful :)
 What's with the rest of that patch set? Does it need rebase or what ?
 By the way, after this is applied, we can drop useless check inside 
vgic_v2_map_resources(). 

Kind regards,
Pavel Fedin
Expert Engineer
Samsung Electronics Research center Russia


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Re: [PATCH v2] Fix AF_PACKET ABI breakage in 4.2

[David Woodhouse]

On Thu, 2015-09-24 at 12:55 +0300, Michael S. Tsirkin wrote:
> 
> I'm fine with this patch
> 
> Acked-by: Michael S. Tsirkin 

Thanks. In fact Dave has already merged it.

> but if you want to re-work it along the lines suggested
> by Greg, that's also fine with me.

If I'm going to define my own accessors, I'd probably just make them
use (__force __virtio16). But TBH none of the options seemed
particularly pretty to me. I can live with what we have.

-- 
David WoodhouseOpen Source Technology Centre
david.woodho...@intel.com  Intel Corporation



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[PATCH kvm-unit-tests] x86: Test watchpoints during emulation

[Nadav Amit]

From: Rami Burstein& Anrey Isakov 

This adds a test for data and port watchpoints during instruction emulation.

Signed-off-by: Rami Burstein 
Signed-off-by: Andrey Isakov 

---

This unit tests are based on old kvm-unit-tests version and are only delivered
for reference. They are certainly bloated in their current form.

---
 x86/debug.c | 374 
 1 file changed, 374 insertions(+)

diff --git a/x86/debug.c b/x86/debug.c
index 34e56fb..43a2777 100644
--- a/x86/debug.c
+++ b/x86/debug.c
@@ -11,10 +11,24 @@
 
 #include "libcflat.h"
 #include "desc.h"
+#include "vm.h"
+
+#define TESTDEV_IO_PORT0xe0
 
 static volatile unsigned long bp_addr[10], dr6[10];
 static volatile unsigned int n;
 static volatile unsigned long value;
+static volatile char st1[] = "abcdefghijklmnop";
+
+static void set_dr2(void *value)
+{
+   asm volatile("mov %0,%%dr2" : : "r" (value));
+}
+
+static void set_dr3(void *value)
+{
+   asm volatile("mov %0,%%dr3" : : "r" (value));
+}
 
 static unsigned long get_dr6(void)
 {
@@ -58,6 +72,360 @@ static void handle_bp(struct ex_regs *regs)
bp_addr[0] = regs->rip;
 }
 
+static void test_port_io_bp()
+{
+   unsigned char r = 0;
+   unsigned short port_in = 0;
+   unsigned int port_din = 0;
+
+   n = 0;
+   set_dr0((void*)TESTDEV_IO_PORT);
+   set_dr1((void*)TESTDEV_IO_PORT);
+   set_dr2((void*)TESTDEV_IO_PORT);
+   set_dr3((void*)TESTDEV_IO_PORT);
+   set_dr7(0x00020402);
+
+   // Set DE flag.
+   write_cr4(read_cr4() | 0x8);
+   asm volatile("movw %0, %%dx \n\t" "outsb \n\t"
+   : : "i"((short)TESTDEV_IO_PORT),"S"(st1));
+   asm volatile("inb %1, %0\n\t" : "=a"(r) : "i"((short)TESTDEV_IO_PORT));
+io_0:
+   report("em_IO out_in 1 byte bp through dr0",
+   n == 2 && bp_addr[n-1] == ((unsigned long)&_0) &&
+   dr6[n-1] == 0x4ff1);
+
+   set_dr7(0x00200408);
+   asm volatile("movw %0, %%dx \n\t" "outsb \n\t"
+   : : "i"((short)TESTDEV_IO_PORT), "S"(st1));
+   asm volatile("inb %1, %0\n\t" : "=a"(r)
+   : "i"((short)TESTDEV_IO_PORT));
+io_1:
+   report("em_IO out_in 1 byte bp through dr1",
+   n == 4 && bp_addr[n-1] == ((unsigned long)&_1) &&
+   dr6[n-1] == 0x4ff2);
+
+   set_dr7(0x02000420);
+   asm volatile("movw %0, %%dx \n\t" "outsb \n\t"
+   : : "i"((short)TESTDEV_IO_PORT), "S"(st1));
+   asm volatile("inb %1, %0\n\t" : "=a"(r)
+   : "i"((short)TESTDEV_IO_PORT));
+io_2:
+   report("em_IO out_in 1 byte bp through dr2",
+   n == 6 && bp_addr[n-1] == ((unsigned long)&_2) &&
+   dr6[n-1] == 0x4ff4);
+
+   set_dr7(0x2480);
+   asm volatile("movw %0, %%dx \n\t" "outsb \n\t"
+   : : "i"((short)TESTDEV_IO_PORT), "S"(st1));
+   asm volatile("inb %1, %0\n\t" : "=a"(r)
+   : "i"((short)TESTDEV_IO_PORT));
+io_3:
+   report("em_IO out_in 1 byte bp through dr3",
+   n == 8 && bp_addr[n-1] == ((unsigned long)&_3) &&
+   dr6[n-1] == 0x4ff8);
+
+   n=0;
+   set_dr7(0x6480);
+   asm volatile("movw %0, %%dx \n\t" "outsw \n\t"
+: : "i"((short)TESTDEV_IO_PORT), "S"(st1));
+   asm volatile("inw %1, %0\n\t" : "=r"(port_in)
+   : "i"((short)TESTDEV_IO_PORT));
+io_w:
+   report("em_IO out_in 2 byte bp through dr3",
+   n == 2 && bp_addr[n-1] == ((unsigned 
long)&_w) &&
+   dr6[n-1] == 0x4ff8);
+
+   set_dr7(0xe480);
+   asm volatile("movw %0, %%dx \n\t" "outsl \n\t"
+   : : "i"((short)TESTDEV_IO_PORT), "S"(st1));
+   asm volatile ("insl;" :"+D" (port_din)
+   : "i" ((short)TESTDEV_IO_PORT) : "memory");
+io_dw:
+   report("em_IO out_in 4 byte bp through dr3",
+   n == 4 && bp_addr[n-1] == ((unsigned long)&_dw)
+   && dr6[n-1] == 0x4ff8);
+}
+static void test_port_io_aligned_bp(){
+
+   unsigned char r = 0;
+   unsigned short port_in = 0;
+   unsigned int port_din = 0;
+
+   n = 0;
+   write_cr4(read_cr4() | 0x8);
+
+   set_dr7(0x00020402);
+   set_dr0((void*)(TESTDEV_IO_PORT ));
+   asm volatile("movw %0, %%dx \n\t" "outsb \n\t"
+   : : "i"((short)TESTDEV_IO_PORT),"S"(st1));
+   asm volatile("inb %1, %0\n\t" : "=a"(r)
+   : "i"((short)TESTDEV_IO_PORT));
+aio_0:
+   report("em_IO aligned out_in 1 byte bp through dr0",
+   n == 2 && 

Re: [PATCH v2] Fix AF_PACKET ABI breakage in 4.2

[Michael S. Tsirkin]

On Thu, Sep 24, 2015 at 09:25:45AM +0200, Greg Kurz wrote:
> On Wed, 23 Sep 2015 19:45:08 +0100
> David Woodhouse  wrote:
> 
> > Commit 7d82410950aa ("virtio: add explicit big-endian support to memory
> > accessors") accidentally changed the virtio_net header used by
> > AF_PACKET with PACKET_VNET_HDR from host-endian to big-endian.
> > 
> 
> Hi David,
> 
> Oops my bad... I obviously overlooked this one when adding cross-endian
> support.
> 
> > Since virtio_legacy_is_little_endian() is a very long identifier,
> > define a VIO_LE macro and use that throughout the code instead of the
> 
> VIO usually refers to virtual IO adapters for the PowerPC pSeries platform.
> 
> > hard-coded 'false' for little-endian.
> > 
> 
> What about introducing dedicated accessors as it is done in many other
> locations where we do virtio byteswap ? Something like:
> 
> static inline bool packet_is_little_endian(void)
> {
>   return virtio_legacy_is_little_endian();
> }
> 
> static inline u16 packet16_to_cpu(__virtio16 val)
> {
>   return __virtio16_to_cpu(packet_is_little_endian(), val);
> }
> 
> static inline __virtio16 cpu_to_packet16(u16 val)
> {
>   return __cpu_to_virtio16(packet_is_little_endian(), val);
> }
> 
> It results in prettier code IMHO. Have a look at drivers/net/tun.c or
> drivers/vhost/vhost.c.
> 
> > This restores the ABI to match 4.1 and earlier kernels, and makes my
> > test program work again.
> > 
> 
> BTW, there is still work to do if we want to support cross-endian legacy or
> virtio 1 on a big endian arch...
> 
> Cheers.
> 
> --
> Greg

It seems the API that we have is a confusing one.

virtio endian-ness is either native or little, depending on a flag, so
__virtio16_to_cpu seems to mean "either native to cpu or little to cpu
depending on flag".

It used to be like that, but not anymore.

This leads to all kind of bugs.

For example, I have only now realized vhost_is_little_endian isn't a
constant on LE hosts if cross-endian support is not compiled.

I think we need to fix it, but also think about a better API.


> > Signed-off-by: David Woodhouse 
> > ---
> > On Wed, 2015-09-23 at 11:09 -0700, David Miller wrote:
> > > > +#define VIO_LE virtio_legacy_is_little_endian()
> > > 
> > > When you define a shorthand macro, the defines to a function call,
> > > make the macro have parenthesis too.
> > 
> > In which case I suppose it also wants to be lower-case. Although
> > "function call" is a bit strong since it's effectively just a constant.
> > I'm still wondering if it'd be nicer just to use (__force u16) instead.
> > 
> > diff --git a/net/packet/af_packet.c b/net/packet/af_packet.c
> > index 7b8e39a..aa4b15c 100644
> > --- a/net/packet/af_packet.c
> > +++ b/net/packet/af_packet.c
> > @@ -230,6 +230,8 @@ struct packet_skb_cb {
> > } sa;
> >  };
> >  
> > +#define vio_le() virtio_legacy_is_little_endian()
> > +
> >  #define PACKET_SKB_CB(__skb)   ((struct packet_skb_cb *)((__skb)->cb))
> >  
> >  #define GET_PBDQC_FROM_RB(x)   ((struct tpacket_kbdq_core 
> > *)(&(x)->prb_bdqc))
> > @@ -2680,15 +2682,15 @@ static int packet_snd(struct socket *sock, struct 
> > msghdr *msg, size_t len)
> > goto out_unlock;
> >  
> > if ((vnet_hdr.flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) &&
> > -   (__virtio16_to_cpu(false, vnet_hdr.csum_start) +
> > -__virtio16_to_cpu(false, vnet_hdr.csum_offset) + 2 >
> > - __virtio16_to_cpu(false, vnet_hdr.hdr_len)))
> > -   vnet_hdr.hdr_len = __cpu_to_virtio16(false,
> > -__virtio16_to_cpu(false, vnet_hdr.csum_start) +
> > -   __virtio16_to_cpu(false, vnet_hdr.csum_offset) 
> > + 2);
> > +   (__virtio16_to_cpu(vio_le(), vnet_hdr.csum_start) +
> > +__virtio16_to_cpu(vio_le(), vnet_hdr.csum_offset) + 2 >
> > + __virtio16_to_cpu(vio_le(), vnet_hdr.hdr_len)))
> > +   vnet_hdr.hdr_len = __cpu_to_virtio16(vio_le(),
> > +__virtio16_to_cpu(vio_le(), 
> > vnet_hdr.csum_start) +
> > +   __virtio16_to_cpu(vio_le(), 
> > vnet_hdr.csum_offset) + 2);
> >  
> > err = -EINVAL;
> > -   if (__virtio16_to_cpu(false, vnet_hdr.hdr_len) > len)
> > +   if (__virtio16_to_cpu(vio_le(), vnet_hdr.hdr_len) > len)
> > goto out_unlock;
> >  
> > if (vnet_hdr.gso_type != VIRTIO_NET_HDR_GSO_NONE) {
> > @@ -2731,7 +2733,7 @@ static int packet_snd(struct socket *sock, struct 
> > msghdr *msg, size_t len)
> > hlen = LL_RESERVED_SPACE(dev);
> > tlen = dev->needed_tailroom;
> > skb = packet_alloc_skb(sk, hlen + tlen, hlen, len,
> > -  __virtio16_to_cpu(false, vnet_hdr.hdr_len),
> > +  __virtio16_to_cpu(vio_le(), vnet_hdr.hdr_len),
> >msg->msg_flags & 

Re: [PATCH v2] Fix AF_PACKET ABI breakage in 4.2

[Michael S. Tsirkin]

On Wed, Sep 23, 2015 at 07:45:08PM +0100, David Woodhouse wrote:
> Commit 7d82410950aa ("virtio: add explicit big-endian support to memory
> accessors") accidentally changed the virtio_net header used by
> AF_PACKET with PACKET_VNET_HDR from host-endian to big-endian.
> 
> Since virtio_legacy_is_little_endian() is a very long identifier,
> define a VIO_LE macro and use that throughout the code instead of the
> hard-coded 'false' for little-endian.
> 
> This restores the ABI to match 4.1 and earlier kernels, and makes my
> test program work again.
> 
> Signed-off-by: David Woodhouse 


I'm fine with this patch

Acked-by: Michael S. Tsirkin 

but if you want to re-work it along the lines suggested
by Greg, that's also fine with me.

> ---
> On Wed, 2015-09-23 at 11:09 -0700, David Miller wrote:
> > > +#define VIO_LE virtio_legacy_is_little_endian()
> > 
> > When you define a shorthand macro, the defines to a function call,
> > make the macro have parenthesis too.
> 
> In which case I suppose it also wants to be lower-case. Although
> "function call" is a bit strong since it's effectively just a constant.
> I'm still wondering if it'd be nicer just to use (__force u16) instead.
> 
> diff --git a/net/packet/af_packet.c b/net/packet/af_packet.c
> index 7b8e39a..aa4b15c 100644
> --- a/net/packet/af_packet.c
> +++ b/net/packet/af_packet.c
> @@ -230,6 +230,8 @@ struct packet_skb_cb {
>   } sa;
>  };
>  
> +#define vio_le() virtio_legacy_is_little_endian()
> +
>  #define PACKET_SKB_CB(__skb) ((struct packet_skb_cb *)((__skb)->cb))
>  
>  #define GET_PBDQC_FROM_RB(x) ((struct tpacket_kbdq_core *)(&(x)->prb_bdqc))
> @@ -2680,15 +2682,15 @@ static int packet_snd(struct socket *sock, struct 
> msghdr *msg, size_t len)
>   goto out_unlock;
>  
>   if ((vnet_hdr.flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) &&
> - (__virtio16_to_cpu(false, vnet_hdr.csum_start) +
> -  __virtio16_to_cpu(false, vnet_hdr.csum_offset) + 2 >
> -   __virtio16_to_cpu(false, vnet_hdr.hdr_len)))
> - vnet_hdr.hdr_len = __cpu_to_virtio16(false,
> -  __virtio16_to_cpu(false, vnet_hdr.csum_start) +
> - __virtio16_to_cpu(false, vnet_hdr.csum_offset) 
> + 2);
> + (__virtio16_to_cpu(vio_le(), vnet_hdr.csum_start) +
> +  __virtio16_to_cpu(vio_le(), vnet_hdr.csum_offset) + 2 >
> +   __virtio16_to_cpu(vio_le(), vnet_hdr.hdr_len)))
> + vnet_hdr.hdr_len = __cpu_to_virtio16(vio_le(),
> +  __virtio16_to_cpu(vio_le(), 
> vnet_hdr.csum_start) +
> + __virtio16_to_cpu(vio_le(), 
> vnet_hdr.csum_offset) + 2);
>  
>   err = -EINVAL;
> - if (__virtio16_to_cpu(false, vnet_hdr.hdr_len) > len)
> + if (__virtio16_to_cpu(vio_le(), vnet_hdr.hdr_len) > len)
>   goto out_unlock;
>  
>   if (vnet_hdr.gso_type != VIRTIO_NET_HDR_GSO_NONE) {
> @@ -2731,7 +2733,7 @@ static int packet_snd(struct socket *sock, struct 
> msghdr *msg, size_t len)
>   hlen = LL_RESERVED_SPACE(dev);
>   tlen = dev->needed_tailroom;
>   skb = packet_alloc_skb(sk, hlen + tlen, hlen, len,
> -__virtio16_to_cpu(false, vnet_hdr.hdr_len),
> +__virtio16_to_cpu(vio_le(), vnet_hdr.hdr_len),
>  msg->msg_flags & MSG_DONTWAIT, );
>   if (skb == NULL)
>   goto out_unlock;
> @@ -2778,8 +2780,8 @@ static int packet_snd(struct socket *sock, struct 
> msghdr *msg, size_t len)
>  
>   if (po->has_vnet_hdr) {
>   if (vnet_hdr.flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) {
> - u16 s = __virtio16_to_cpu(false, vnet_hdr.csum_start);
> - u16 o = __virtio16_to_cpu(false, vnet_hdr.csum_offset);
> + u16 s = __virtio16_to_cpu(vio_le(), 
> vnet_hdr.csum_start);
> + u16 o = __virtio16_to_cpu(vio_le(), 
> vnet_hdr.csum_offset);
>   if (!skb_partial_csum_set(skb, s, o)) {
>   err = -EINVAL;
>   goto out_free;
> @@ -2787,7 +2789,7 @@ static int packet_snd(struct socket *sock, struct 
> msghdr *msg, size_t len)
>   }
>  
>   skb_shinfo(skb)->gso_size =
> - __virtio16_to_cpu(false, vnet_hdr.gso_size);
> + __virtio16_to_cpu(vio_le(), vnet_hdr.gso_size);
>   skb_shinfo(skb)->gso_type = gso_type;
>  
>   /* Header must be checked, and gso_segs computed. */
> @@ -3161,9 +3163,9 @@ static int packet_recvmsg(struct socket *sock, struct 
> msghdr *msg, size_t len,
>  
>   /* This is a hint as to how much should be linear. */
>   vnet_hdr.hdr_len =
> -  

Re: [PATCH 2/2] KVM: x86: Guest watchpoints during emulation.

[Nadav Amit]

Looking at the patch again, there two points you may want to change, see
inline.

If you want, I’ll send a v2.

Nadav

Nadav Amit  wrote:

> From: Nadav Amit 
> 
> This adds support for guest data and I/O breakpoints during instruction
> emulation.
> 
> Watchpoints are examined during data and io interceptions: segmented_read,
> segmented_write, em_in, em_out, segmented_read_std and kvm_fast_pio_out.
> 
> When such a breakpoint is triggered, trap is reported by DB_VECTOR
> exception.
> 
> Signed-off-by: Andrey Isakov 
> Signed-off-by: Rami Burstein 
> Signed-off-by: Nadav Amit 
> ---
> arch/x86/include/asm/kvm_emulate.h |  3 ++
> arch/x86/kvm/emulate.c | 32 +
> arch/x86/kvm/x86.c | 74 +-
> 3 files changed, 92 insertions(+), 17 deletions(-)
> 
> diff --git a/arch/x86/include/asm/kvm_emulate.h 
> b/arch/x86/include/asm/kvm_emulate.h
> index e16466e..f6d5d6c 100644
> --- a/arch/x86/include/asm/kvm_emulate.h
> +++ b/arch/x86/include/asm/kvm_emulate.h
> @@ -211,6 +211,9 @@ struct x86_emulate_ops {
>   void (*get_cpuid)(struct x86_emulate_ctxt *ctxt,
> u32 *eax, u32 *ebx, u32 *ecx, u32 *edx);
>   void (*set_nmi_mask)(struct x86_emulate_ctxt *ctxt, bool masked);
> + bool (*check_watchpoint)(struct x86_emulate_ctxt *ctxt,
> +  unsigned long addr, unsigned int length,
> +  int type);
> };
> 
> typedef u32 __attribute__((vector_size(16))) sse128_t;
> diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
> index b372a75..4e91b7b 100644
> --- a/arch/x86/kvm/emulate.c
> +++ b/arch/x86/kvm/emulate.c
> @@ -24,6 +24,7 @@
> #include "kvm_cache_regs.h"
> #include 
> #include 
> +#include 
> #include 
> #include 
> 
> @@ -564,6 +565,17 @@ static int emulate_db(struct x86_emulate_ctxt *ctxt)
>   return emulate_exception(ctxt, DB_VECTOR, 0, false);
> }
> 
> +static void emulate_db_trap(struct x86_emulate_ctxt *ctxt)
> +{
> + /*
> +  * If a fault is later encountered, the exception information will be
> +  * overridden. Otherwise the trap would be handled after the emulation
> +  * is completed.
> +  */
> + (void)emulate_exception(ctxt, DB_VECTOR, 0, false);
> + ctxt->have_exception = true;
> +}
> +
> static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
> {
>   return emulate_exception(ctxt, GP_VECTOR, err, true);
> @@ -776,6 +788,10 @@ static int segmented_read_std(struct x86_emulate_ctxt 
> *ctxt,
>   rc = linearize(ctxt, addr, size, false, );
>   if (rc != X86EMUL_CONTINUE)
>   return rc;
> +
> + if (ctxt->ops->check_watchpoint(ctxt, linear, size, DR_RW_READ))
> + emulate_db_trap(ctxt);
> +
>   return ctxt->ops->read_std(ctxt, linear, data, size, >exception);
> }
> 
> @@ -1369,6 +1385,10 @@ static int segmented_read(struct x86_emulate_ctxt 
> *ctxt,
>   rc = linearize(ctxt, addr, size, false, );
>   if (rc != X86EMUL_CONTINUE)
>   return rc;
> +
> + if (ctxt->ops->check_watchpoint(ctxt, linear, size, DR_RW_READ))
> + emulate_db_trap(ctxt);
> +
>   return read_emulated(ctxt, linear, data, size);
> }
> 
> @@ -1383,6 +1403,10 @@ static int segmented_write(struct x86_emulate_ctxt 
> *ctxt,
>   rc = linearize(ctxt, addr, size, true, );
>   if (rc != X86EMUL_CONTINUE)
>   return rc;
> +
> + if (ctxt->ops->check_watchpoint(ctxt, linear, size, DR_RW_WRITE))
> + emulate_db_trap(ctxt);
> +
>   return ctxt->ops->write_emulated(ctxt, linear, data, size,
>>exception);
> }
> @@ -3729,11 +3753,19 @@ static int em_in(struct x86_emulate_ctxt *ctxt)
>>dst.val))
>   return X86EMUL_IO_NEEDED;
> 
> + if (ctxt->ops->check_watchpoint(ctxt, ctxt->src.val, ctxt->dst.bytes,
> + DR_RW_PORT))
> + emulate_db_trap(ctxt);
> +
>   return X86EMUL_CONTINUE;
> }
> 
> static int em_out(struct x86_emulate_ctxt *ctxt)
> {
> + if (ctxt->ops->check_watchpoint(ctxt, ctxt->dst.val, ctxt->src.bytes,
> + DR_RW_PORT))
> + emulate_db_trap(ctxt);
> +
>   ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
>   >src.val, 1);
>   /* Disable writeback. */
> diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
> index 3e4d032..ba75f76 100644
> --- a/arch/x86/kvm/x86.c
> +++ b/arch/x86/kvm/x86.c
> @@ -4831,6 +4831,55 @@ static void emulator_set_nmi_mask(struct 
> x86_emulate_ctxt *ctxt, bool masked)
>   kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
> }
> 
> +static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 len,
> + u32 dr7, unsigned 

Re: [PATCH v2 00/15] KVM: arm64: GICv3 ITS emulation

[Andre Przywara]

Hi Pavel,

On 24/09/15 12:18, Pavel Fedin wrote:
>  Hello Andre and others!
> 
>  How are things going? I see the last message in thread something like 1 
> month old, then silence...
>  Our project relies on this feature, any assistance needed?

I am about to make it work on top of Christoffer's latest arch timer
rework patches, which means I need to rewrite most of patch 1. Currently
that boots, but hangs as soon as I put some load on it. Finding the
reason for this is a bit tedious at the moment.
I have addressed the comments from the list on the other patches, so
ideally I can send a new revision as soon as I fixed that bug in the
first patch.

Cheers,
Andre.
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[PATCH 2/2] KVM: x86: Guest watchpoints during emulation.

[Nadav Amit]

From: Nadav Amit 

This adds support for guest data and I/O breakpoints during instruction
emulation.

Watchpoints are examined during data and io interceptions: segmented_read,
segmented_write, em_in, em_out, segmented_read_std and kvm_fast_pio_out.

When such a breakpoint is triggered, trap is reported by DB_VECTOR
exception.

Signed-off-by: Andrey Isakov 
Signed-off-by: Rami Burstein 
Signed-off-by: Nadav Amit 
---
 arch/x86/include/asm/kvm_emulate.h |  3 ++
 arch/x86/kvm/emulate.c | 32 +
 arch/x86/kvm/x86.c | 74 +-
 3 files changed, 92 insertions(+), 17 deletions(-)

diff --git a/arch/x86/include/asm/kvm_emulate.h 
b/arch/x86/include/asm/kvm_emulate.h
index e16466e..f6d5d6c 100644
--- a/arch/x86/include/asm/kvm_emulate.h
+++ b/arch/x86/include/asm/kvm_emulate.h
@@ -211,6 +211,9 @@ struct x86_emulate_ops {
void (*get_cpuid)(struct x86_emulate_ctxt *ctxt,
  u32 *eax, u32 *ebx, u32 *ecx, u32 *edx);
void (*set_nmi_mask)(struct x86_emulate_ctxt *ctxt, bool masked);
+   bool (*check_watchpoint)(struct x86_emulate_ctxt *ctxt,
+unsigned long addr, unsigned int length,
+int type);
 };
 
 typedef u32 __attribute__((vector_size(16))) sse128_t;
diff --git a/arch/x86/kvm/emulate.c b/arch/x86/kvm/emulate.c
index b372a75..4e91b7b 100644
--- a/arch/x86/kvm/emulate.c
+++ b/arch/x86/kvm/emulate.c
@@ -24,6 +24,7 @@
 #include "kvm_cache_regs.h"
 #include 
 #include 
+#include 
 #include 
 #include 
 
@@ -564,6 +565,17 @@ static int emulate_db(struct x86_emulate_ctxt *ctxt)
return emulate_exception(ctxt, DB_VECTOR, 0, false);
 }
 
+static void emulate_db_trap(struct x86_emulate_ctxt *ctxt)
+{
+   /*
+* If a fault is later encountered, the exception information will be
+* overridden. Otherwise the trap would be handled after the emulation
+* is completed.
+*/
+   (void)emulate_exception(ctxt, DB_VECTOR, 0, false);
+   ctxt->have_exception = true;
+}
+
 static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
 {
return emulate_exception(ctxt, GP_VECTOR, err, true);
@@ -776,6 +788,10 @@ static int segmented_read_std(struct x86_emulate_ctxt 
*ctxt,
rc = linearize(ctxt, addr, size, false, );
if (rc != X86EMUL_CONTINUE)
return rc;
+
+   if (ctxt->ops->check_watchpoint(ctxt, linear, size, DR_RW_READ))
+   emulate_db_trap(ctxt);
+
return ctxt->ops->read_std(ctxt, linear, data, size, >exception);
 }
 
@@ -1369,6 +1385,10 @@ static int segmented_read(struct x86_emulate_ctxt *ctxt,
rc = linearize(ctxt, addr, size, false, );
if (rc != X86EMUL_CONTINUE)
return rc;
+
+   if (ctxt->ops->check_watchpoint(ctxt, linear, size, DR_RW_READ))
+   emulate_db_trap(ctxt);
+
return read_emulated(ctxt, linear, data, size);
 }
 
@@ -1383,6 +1403,10 @@ static int segmented_write(struct x86_emulate_ctxt *ctxt,
rc = linearize(ctxt, addr, size, true, );
if (rc != X86EMUL_CONTINUE)
return rc;
+
+   if (ctxt->ops->check_watchpoint(ctxt, linear, size, DR_RW_WRITE))
+   emulate_db_trap(ctxt);
+
return ctxt->ops->write_emulated(ctxt, linear, data, size,
 >exception);
 }
@@ -3729,11 +3753,19 @@ static int em_in(struct x86_emulate_ctxt *ctxt)
 >dst.val))
return X86EMUL_IO_NEEDED;
 
+   if (ctxt->ops->check_watchpoint(ctxt, ctxt->src.val, ctxt->dst.bytes,
+   DR_RW_PORT))
+   emulate_db_trap(ctxt);
+
return X86EMUL_CONTINUE;
 }
 
 static int em_out(struct x86_emulate_ctxt *ctxt)
 {
+   if (ctxt->ops->check_watchpoint(ctxt, ctxt->dst.val, ctxt->src.bytes,
+   DR_RW_PORT))
+   emulate_db_trap(ctxt);
+
ctxt->ops->pio_out_emulated(ctxt, ctxt->src.bytes, ctxt->dst.val,
>src.val, 1);
/* Disable writeback. */
diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
index 3e4d032..ba75f76 100644
--- a/arch/x86/kvm/x86.c
+++ b/arch/x86/kvm/x86.c
@@ -4831,6 +4831,55 @@ static void emulator_set_nmi_mask(struct 
x86_emulate_ctxt *ctxt, bool masked)
kvm_x86_ops->set_nmi_mask(emul_to_vcpu(ctxt), masked);
 }
 
+static int kvm_vcpu_check_hw_bp(unsigned long addr, u32 type, u32 len,
+   u32 dr7, unsigned long *db)
+{
+   u32 dr6 = 0;
+   int i;
+   u32 enable, dr7_rw, dr7_len;
+   unsigned long align_db;
+
+   enable = dr7;
+   dr7_rw = dr7 >> 16;
+   dr7_len = dr7_rw >> 2;
+   for (i = 0; i < 4; i++, enable >>= 2, dr7_rw >>= 4, dr7_len >>= 4) {
+   if 

[PATCH 1/2] KVM: x86: Add DR flag definition for IO watchpoints

[Nadav Amit]

From: Rami Burstein 

Add DR_RW_PROT for I/O watchponts.

Signed-off-by: Andrey Isakov 
Signed-off-by: Rami Burstein 
Signed-off-by: Nadav Amit 
---
 arch/x86/include/uapi/asm/debugreg.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/include/uapi/asm/debugreg.h 
b/arch/x86/include/uapi/asm/debugreg.h
index 3c0874d..d815cd4 100644
--- a/arch/x86/include/uapi/asm/debugreg.h
+++ b/arch/x86/include/uapi/asm/debugreg.h
@@ -37,6 +37,7 @@
 
 #define DR_RW_EXECUTE (0x0)   /* Settings for the access types to trap on */
 #define DR_RW_WRITE (0x1)
+#define DR_RW_PORT (0x2)
 #define DR_RW_READ (0x3)
 
 #define DR_LEN_1 (0x0) /* Settings for data length to trap on */
-- 
2.1.4

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[PATCH] KVM: PPC: e500: Emulate TMCFG0 TMRN register

[Laurentiu Tudor]

Emulate TMCFG0 TMRN register exposing one HW thread per vcpu.

Signed-off-by: Mihai Caraman 
[laurentiu.tu...@freescale.com: rebased on latest kernel,
 use define instead of hardcoded value]
Signed-off-by: Laurentiu Tudor 
---
Needs this patch: https://patchwork.ozlabs.org/patch/521752/

 arch/powerpc/include/asm/disassemble.h |  5 +
 arch/powerpc/kvm/e500_emulate.c| 11 +++
 2 files changed, 16 insertions(+)

diff --git a/arch/powerpc/include/asm/disassemble.h 
b/arch/powerpc/include/asm/disassemble.h
index 6330a61..4852e84 100644
--- a/arch/powerpc/include/asm/disassemble.h
+++ b/arch/powerpc/include/asm/disassemble.h
@@ -42,6 +42,11 @@ static inline unsigned int get_dcrn(u32 inst)
return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0);
 }
 
+static inline unsigned int get_tmrn(u32 inst)
+{
+   return ((inst >> 16) & 0x1f) | ((inst >> 6) & 0x3e0);
+}
+
 static inline unsigned int get_rt(u32 inst)
 {
return (inst >> 21) & 0x1f;
diff --git a/arch/powerpc/kvm/e500_emulate.c b/arch/powerpc/kvm/e500_emulate.c
index ce7291c..44ac54b 100644
--- a/arch/powerpc/kvm/e500_emulate.c
+++ b/arch/powerpc/kvm/e500_emulate.c
@@ -15,6 +15,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "booke.h"
 #include "e500.h"
@@ -22,6 +23,7 @@
 #define XOP_DCBTLS  166
 #define XOP_MSGSND  206
 #define XOP_MSGCLR  238
+#define XOP_MFTMR   366
 #define XOP_TLBIVAX 786
 #define XOP_TLBSX   914
 #define XOP_TLBRE   946
@@ -165,6 +167,15 @@ int kvmppc_core_emulate_op_e500(struct kvm_run *run, 
struct kvm_vcpu *vcpu,
emulated = kvmppc_e500_emul_tlbivax(vcpu, ea);
break;
 
+   case XOP_MFTMR:
+   /* Expose one thread per vcpu */
+   if (get_tmrn(inst) == TMRN_TMCFG0)
+   kvmppc_set_gpr(vcpu, rt,
+  1 | (1 << 
TMRN_TMCFG0_NATHRD_SHIFT));
+   else
+   emulated = EMULATE_FAIL;
+   break;
+
case XOP_EHPRIV:
emulated = kvmppc_e500_emul_ehpriv(run, vcpu, inst,
   advance);
-- 
1.8.3.1
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[PATCH 0/2] KVM: x86: Emulated I/O and data breakpoints support

[Nadav Amit]

This patch-set adds data and I/O breakpoints support on emulated instructions
to KVM. The first patch just adds a missing definition and all the logic is in
the second one.

These patches were implemented as part of a university project, and then
cleaned and rebased on the latest KVM by me. I have some concerns about their
impact on performance, so it is possible to add a fast-patch for the case all
breakpoints are disabled. In addition, these patches do not handle watchpoints
that are set by the host debugger.

Nadav Amit (1):
  KVM: x86: Guest watchpoints during emulation.

Rami Burstein (1):
  KVM: x86: Add DR flag definition for IO watchpoints

 arch/x86/include/asm/kvm_emulate.h   |  3 ++
 arch/x86/include/uapi/asm/debugreg.h |  1 +
 arch/x86/kvm/emulate.c   | 32 
 arch/x86/kvm/x86.c   | 74 +++-
 4 files changed, 93 insertions(+), 17 deletions(-)

-- 
2.1.4

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[PATCH] KVM: nVMX: expose VPID capability to L1

[Wanpeng Li]

Expose VPID capability to L1.

Signed-off-by: Wanpeng Li 
---
 arch/x86/kvm/vmx.c | 22 +++---
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index f9219ad..866045c 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -442,7 +442,7 @@ struct nested_vmx {
u32 nested_vmx_true_entry_ctls_low;
u32 nested_vmx_misc_low;
u32 nested_vmx_misc_high;
-   u32 nested_vmx_ept_caps;
+   u64 nested_vmx_ept_vpid_caps;
 };
 
 #define POSTED_INTR_ON  0
@@ -2485,22 +2485,23 @@ static void nested_vmx_setup_ctls_msrs(struct vcpu_vmx 
*vmx)
SECONDARY_EXEC_WBINVD_EXITING |
SECONDARY_EXEC_XSAVES;
 
-   if (enable_ept) {
+   if (enable_ept | enable_vpid) {
/* nested EPT: emulate EPT also to L1 */
vmx->nested.nested_vmx_secondary_ctls_high |=
SECONDARY_EXEC_ENABLE_EPT;
-   vmx->nested.nested_vmx_ept_caps = VMX_EPT_PAGE_WALK_4_BIT |
+   vmx->nested.nested_vmx_ept_vpid_caps = VMX_EPT_PAGE_WALK_4_BIT |
 VMX_EPTP_WB_BIT | VMX_EPT_2MB_PAGE_BIT |
 VMX_EPT_INVEPT_BIT;
-   vmx->nested.nested_vmx_ept_caps &= vmx_capability.ept;
+   vmx->nested.nested_vmx_ept_vpid_caps &= vmx_capability.ept;
/*
 * For nested guests, we don't do anything specific
 * for single context invalidation. Hence, only advertise
 * support for global context invalidation.
 */
-   vmx->nested.nested_vmx_ept_caps |= VMX_EPT_EXTENT_GLOBAL_BIT;
+   vmx->nested.nested_vmx_ept_vpid_caps |= 
VMX_EPT_EXTENT_GLOBAL_BIT;
+   vmx->nested.nested_vmx_ept_vpid_caps |= (unsigned 
long)vmx_capability.vpid << 32;
} else
-   vmx->nested.nested_vmx_ept_caps = 0;
+   vmx->nested.nested_vmx_ept_vpid_caps = 0;
 
if (enable_unrestricted_guest)
vmx->nested.nested_vmx_secondary_ctls_high |=
@@ -2616,8 +2617,7 @@ static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 
msr_index, u64 *pdata)
vmx->nested.nested_vmx_secondary_ctls_high);
break;
case MSR_IA32_VMX_EPT_VPID_CAP:
-   /* Currently, no nested vpid support */
-   *pdata = vmx->nested.nested_vmx_ept_caps;
+   *pdata = vmx->nested.nested_vmx_ept_vpid_caps;
break;
default:
return 1;
@@ -7152,7 +7152,7 @@ static int handle_invept(struct kvm_vcpu *vcpu)
 
if (!(vmx->nested.nested_vmx_secondary_ctls_high &
  SECONDARY_EXEC_ENABLE_EPT) ||
-   !(vmx->nested.nested_vmx_ept_caps & VMX_EPT_INVEPT_BIT)) {
+   !(vmx->nested.nested_vmx_ept_vpid_caps & VMX_EPT_INVEPT_BIT)) {
kvm_queue_exception(vcpu, UD_VECTOR);
return 1;
}
@@ -7168,7 +7168,7 @@ static int handle_invept(struct kvm_vcpu *vcpu)
vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
 
-   types = (vmx->nested.nested_vmx_ept_caps >> VMX_EPT_EXTENT_SHIFT) & 6;
+   types = (vmx->nested.nested_vmx_ept_vpid_caps >> VMX_EPT_EXTENT_SHIFT) 
& 6;
 
if (!(types & (1UL << type))) {
nested_vmx_failValid(vcpu,
@@ -8772,7 +8772,7 @@ static void nested_ept_init_mmu_context(struct kvm_vcpu 
*vcpu)
 {
WARN_ON(mmu_is_nested(vcpu));
kvm_init_shadow_ept_mmu(vcpu,
-   to_vmx(vcpu)->nested.nested_vmx_ept_caps &
+   to_vmx(vcpu)->nested.nested_vmx_ept_vpid_caps &
VMX_EPT_EXECUTE_ONLY_BIT);
vcpu->arch.mmu.set_cr3   = vmx_set_cr3;
vcpu->arch.mmu.get_cr3   = nested_ept_get_cr3;
-- 
1.9.1

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Re: [PATCH v2] Fix AF_PACKET ABI breakage in 4.2

[Greg Kurz]

On Wed, 23 Sep 2015 19:45:08 +0100
David Woodhouse  wrote:

> Commit 7d82410950aa ("virtio: add explicit big-endian support to memory
> accessors") accidentally changed the virtio_net header used by
> AF_PACKET with PACKET_VNET_HDR from host-endian to big-endian.
> 

Hi David,

Oops my bad... I obviously overlooked this one when adding cross-endian
support.

> Since virtio_legacy_is_little_endian() is a very long identifier,
> define a VIO_LE macro and use that throughout the code instead of the

VIO usually refers to virtual IO adapters for the PowerPC pSeries platform.

> hard-coded 'false' for little-endian.
> 

What about introducing dedicated accessors as it is done in many other
locations where we do virtio byteswap ? Something like:

static inline bool packet_is_little_endian(void)
{
return virtio_legacy_is_little_endian();
}

static inline u16 packet16_to_cpu(__virtio16 val)
{
return __virtio16_to_cpu(packet_is_little_endian(), val);
}

static inline __virtio16 cpu_to_packet16(u16 val)
{
return __cpu_to_virtio16(packet_is_little_endian(), val);
}

It results in prettier code IMHO. Have a look at drivers/net/tun.c or
drivers/vhost/vhost.c.

> This restores the ABI to match 4.1 and earlier kernels, and makes my
> test program work again.
> 

BTW, there is still work to do if we want to support cross-endian legacy or
virtio 1 on a big endian arch...

Cheers.

--
Greg

> Signed-off-by: David Woodhouse 
> ---
> On Wed, 2015-09-23 at 11:09 -0700, David Miller wrote:
> > > +#define VIO_LE virtio_legacy_is_little_endian()
> > 
> > When you define a shorthand macro, the defines to a function call,
> > make the macro have parenthesis too.
> 
> In which case I suppose it also wants to be lower-case. Although
> "function call" is a bit strong since it's effectively just a constant.
> I'm still wondering if it'd be nicer just to use (__force u16) instead.
> 
> diff --git a/net/packet/af_packet.c b/net/packet/af_packet.c
> index 7b8e39a..aa4b15c 100644
> --- a/net/packet/af_packet.c
> +++ b/net/packet/af_packet.c
> @@ -230,6 +230,8 @@ struct packet_skb_cb {
>   } sa;
>  };
>  
> +#define vio_le() virtio_legacy_is_little_endian()
> +
>  #define PACKET_SKB_CB(__skb) ((struct packet_skb_cb *)((__skb)->cb))
>  
>  #define GET_PBDQC_FROM_RB(x) ((struct tpacket_kbdq_core *)(&(x)->prb_bdqc))
> @@ -2680,15 +2682,15 @@ static int packet_snd(struct socket *sock, struct 
> msghdr *msg, size_t len)
>   goto out_unlock;
>  
>   if ((vnet_hdr.flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) &&
> - (__virtio16_to_cpu(false, vnet_hdr.csum_start) +
> -  __virtio16_to_cpu(false, vnet_hdr.csum_offset) + 2 >
> -   __virtio16_to_cpu(false, vnet_hdr.hdr_len)))
> - vnet_hdr.hdr_len = __cpu_to_virtio16(false,
> -  __virtio16_to_cpu(false, vnet_hdr.csum_start) +
> - __virtio16_to_cpu(false, vnet_hdr.csum_offset) 
> + 2);
> + (__virtio16_to_cpu(vio_le(), vnet_hdr.csum_start) +
> +  __virtio16_to_cpu(vio_le(), vnet_hdr.csum_offset) + 2 >
> +   __virtio16_to_cpu(vio_le(), vnet_hdr.hdr_len)))
> + vnet_hdr.hdr_len = __cpu_to_virtio16(vio_le(),
> +  __virtio16_to_cpu(vio_le(), 
> vnet_hdr.csum_start) +
> + __virtio16_to_cpu(vio_le(), 
> vnet_hdr.csum_offset) + 2);
>  
>   err = -EINVAL;
> - if (__virtio16_to_cpu(false, vnet_hdr.hdr_len) > len)
> + if (__virtio16_to_cpu(vio_le(), vnet_hdr.hdr_len) > len)
>   goto out_unlock;
>  
>   if (vnet_hdr.gso_type != VIRTIO_NET_HDR_GSO_NONE) {
> @@ -2731,7 +2733,7 @@ static int packet_snd(struct socket *sock, struct 
> msghdr *msg, size_t len)
>   hlen = LL_RESERVED_SPACE(dev);
>   tlen = dev->needed_tailroom;
>   skb = packet_alloc_skb(sk, hlen + tlen, hlen, len,
> -__virtio16_to_cpu(false, vnet_hdr.hdr_len),
> +__virtio16_to_cpu(vio_le(), vnet_hdr.hdr_len),
>  msg->msg_flags & MSG_DONTWAIT, );
>   if (skb == NULL)
>   goto out_unlock;
> @@ -2778,8 +2780,8 @@ static int packet_snd(struct socket *sock, struct 
> msghdr *msg, size_t len)
>  
>   if (po->has_vnet_hdr) {
>   if (vnet_hdr.flags & VIRTIO_NET_HDR_F_NEEDS_CSUM) {
> - u16 s = __virtio16_to_cpu(false, vnet_hdr.csum_start);
> - u16 o = __virtio16_to_cpu(false, vnet_hdr.csum_offset);
> + u16 s = __virtio16_to_cpu(vio_le(), 
> vnet_hdr.csum_start);
> + u16 o = __virtio16_to_cpu(vio_le(), 
> vnet_hdr.csum_offset);
>   if (!skb_partial_csum_set(skb, s, o)) {
>   err = -EINVAL;
> 

Re: Migration fail randomly

[Sander Klein]

On 2015-09-16 08:45, Sander Klein wrote:

On 2015-09-15 15:38, Paolo Bonzini wrote:

On 15/09/2015 15:36, Sander Klein wrote:

On 2015-09-15 15:24, Paolo Bonzini wrote:


What kernel runs in the host?


The host is the standard Debian Jessie kernel, 3.16.7-ckt11-1+deb8u3.


Please try a more recent kernel (3.19 or newer).



Will do, I just pulled 4.1.6 from Debian Backports. It does take some
time before the problem might pop up so I will be back in a couple of
days/weeks.


I could reproduce it again. All my KVM hosts are running 4.1.6, but the 
migration still sometimes fails.


The VM must be running for a day or 2 to be able to trigger it. It does 
not seem to happen to all VM's, some VM's seem to be more vulnerable to 
this than others.


I'm not sure of the problem is in kernel or in userspace. Since no error 
is given at all.


Regards,

Sander
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RE: [PATCH v3 5/5] KVM: arm64: Implement vGICv3 CPU interface access

[Pavel Fedin]

 Hello!

> The only thing that is pure 64-bit is the MRS/MSR _instruction_ in
> Aarch64, which always takes a x register.
> So can you model the register size according to the spec and allow
> 32-bit accesses from userland?

 I would like to complete the rework and respin v4, but this is, i guess, the 
only major issue left.
Additionally, it impacts the API. So...
 In order to allow 32-bit accesses we would have to drop using ARM64_SYS_REG() 
for building
attribute ID and introduce something own, like KVM_DEV_ARM_VGIC_REG(). It will 
have different bits
layout (actually it will be missing 'arch' and 'size' field, and instead i will 
use
KVM_DEV_ARM_VGIC_64BIT flag for length specification, the same as for 
redistributor.
 Will this be OK ?

Kind regards,
Pavel Fedin
Expert Engineer
Samsung Electronics Research center Russia


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[RFC PATCH v3] os-android: Add support to android platform

[Houcheng Lin]

Hi,

The v3 patch fix ident error and add error checking on
ptsname_r() function. This patch is based on version:
007e620a7576e4ce2ea6955541e87d8ae8ed32ae.

---

Building QEMU on android reqiures android NDK r10 cross-compilation
toolchain with following changes:

- install qemu dependent libraries
- upgrade bionic libc
- add mssing includes, scsi/sg.h, in toolchain
- make a symbolic link x86_64-linux-android-pkg-config that links
  to host's pkg-config.

Then, configure and build static linked qemu by commands:
  $ export SYSROOT="/opt/android-toolchain64/sysroot"
  $ PKG_CONFIG_LIBDIR=/opt/android-toolchain64/sysroot/usr/lib/pkgconfig \
./configure \
--cross-prefix=x86_64-linux-android- --enable-kvm \
--enable-trace-backend=nop --disable-fdt --target-list=x86_64-softmmu \
--disable-spice --disable-vhost-net --disable-libiscsi \
--audio-drv-list="" --disable-gtk --disable-gnutls \
--disable-libnfs --disable-glusterfs --disable-libssh2 \
--disable-seccomp --disable-usb-redir --disable-libusb \
--disable-guest-agent --static
  $ make -j4

For dynamic build, you can skip the "static" option during configure, copy
dependent so files into android and add "." into LD_LIBRARY_PATH.

How to prepare your cross-compilation toolcahin
---

1. Download NDK r10, install toolchain from NDK and build the following 
libraries and install in your toolchain sysroot:
libiconv-1.14
gettext-0.19
libffi-3.0.12
glib-2.34.3
libpng-1.2.52
pixman-0.30

2. Download AOSP and apply this patch I made to support posix lockf()
https://android-review.googlesource.com/#/c/172150/

3. Build bionic C and update your toolchain's libc.a and libc.so.

4. Copy kernel header file, scsi/sg.h into toolchain's 
sysroot/usr/includes/scsi/

5. Update these header files in your toolchain to prevent compilation warning,
   includes:
unistd.h for lockf() and related define
sys/uio.h for pread() and pwrite()
signal.h for sigtimedwait()

Signed-off-by: Houcheng Lin 
---
 configure   | 18 --
 default-configs/pci.mak |  2 +-
 hw/i386/kvm/pci-assign.c|  1 -
 include/qemu/osdep.h|  7 +++
 include/sysemu/os-android.h | 12 
 kvm-all.c   |  4 
 tests/Makefile  |  2 ++
 util/oslib-posix.c  | 12 
 util/qemu-openpty.c | 20 +++-
 9 files changed, 69 insertions(+), 9 deletions(-)
 create mode 100644 include/sysemu/os-android.h

diff --git a/configure b/configure
index d7c24cd..12e3402 100755
--- a/configure
+++ b/configure
@@ -567,7 +567,6 @@ fi
 
 # host *BSD for user mode
 HOST_VARIANT_DIR=""
-
 case $targetos in
 CYGWIN*)
   mingw32="yes"
@@ -693,9 +692,20 @@ Haiku)
   vhost_net="yes"
   vhost_scsi="yes"
   QEMU_INCLUDES="-I\$(SRC_PATH)/linux-headers -I$(pwd)/linux-headers 
$QEMU_INCLUDES"
+  case $cross_prefix in
+*android*)
+  android="yes"
+;;
+*)
+;;
+  esac
 ;;
 esac
 
+if [ "$android" = "yes" ] ; then
+  LIBS="-lglib-2.0 -lgthread-2.0 -lz -lpixman-1 -lintl -liconv -lc $LIBS"
+  libs_qga="-lglib-2.0 -lgthread-2.0 -lz -lpixman-1 -lintl -liconv -lc"
+fi
 if [ "$bsd" = "yes" ] ; then
   if [ "$darwin" != "yes" ] ; then
 bsd_user="yes"
@@ -3791,7 +3801,7 @@ elif compile_prog "" "$pthread_lib -lrt" ; then
 fi
 
 if test "$darwin" != "yes" -a "$mingw32" != "yes" -a "$solaris" != yes -a \
-"$aix" != "yes" -a "$haiku" != "yes" ; then
+"$aix" != "yes" -a "$haiku" != "yes" -a "$android" != "yes" ; then
 libs_softmmu="-lutil $libs_softmmu"
 fi
 
@@ -4737,6 +4747,10 @@ if test "$linux" = "yes" ; then
   echo "CONFIG_LINUX=y" >> $config_host_mak
 fi
 
+if test "$android" = "yes" ; then
+  echo "CONFIG_ANDROID=y" >> $config_host_mak
+fi
+
 if test "$darwin" = "yes" ; then
   echo "CONFIG_DARWIN=y" >> $config_host_mak
 fi
diff --git a/default-configs/pci.mak b/default-configs/pci.mak
index 7e10903..e76dd41 100644
--- a/default-configs/pci.mak
+++ b/default-configs/pci.mak
@@ -35,5 +35,5 @@ CONFIG_SDHCI=y
 CONFIG_EDU=y
 CONFIG_VGA=y
 CONFIG_VGA_PCI=y
-CONFIG_IVSHMEM=$(CONFIG_KVM)
+CONFIG_IVSHMEM=$(call land,$(call lnot,$(CONFIG_ANDROID)),$(CONFIG_KVM))
 CONFIG_ROCKER=y
diff --git a/hw/i386/kvm/pci-assign.c b/hw/i386/kvm/pci-assign.c
index b1beaa6..44beee3 100644
--- a/hw/i386/kvm/pci-assign.c
+++ b/hw/i386/kvm/pci-assign.c
@@ -22,7 +22,6 @@
  */
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h
index ab3c876..f5be51c 100644
--- a/include/qemu/osdep.h
+++ b/include/qemu/osdep.h
@@ -59,6 +59,10 @@
 #define WEXITSTATUS(x) (x)
 #endif
 
+#ifdef CONFIG_ANDROID
+#include "sysemu/os-android.h"
+#endif
+
 #ifdef _WIN32
 #include "sysemu/os-win32.h"
 #endif
@@ -284,4 +288,7 @@ 

[PATCH] KVM: PPC: e6500: support powers of 2K TLB1 sizes

[Laurentiu Tudor]

Book-E MMUv2 present in e6500 cores supports
powers of 2K page sizes while older MMUv1 cores
support only powers of 4K page sizes, or in other
words the LSB of TSIZE on MMUv1 is always 0.
Thus, on MMUv2 we must not strip the LSB.

Signed-off-by: Mihai Caraman 
[laurentiu.tu...@freescale.com: addressed review
 feedback, split in distinct patch]
Signed-off-by: Laurentiu Tudor 
---
 arch/powerpc/kvm/e500_mmu_host.c | 28 +---
 1 file changed, 21 insertions(+), 7 deletions(-)

diff --git a/arch/powerpc/kvm/e500_mmu_host.c b/arch/powerpc/kvm/e500_mmu_host.c
index 4d33e19..12d5c67 100644
--- a/arch/powerpc/kvm/e500_mmu_host.c
+++ b/arch/powerpc/kvm/e500_mmu_host.c
@@ -371,6 +371,7 @@ static inline int kvmppc_e500_shadow_map(struct 
kvmppc_vcpu_e500 *vcpu_e500,
 
unsigned long start, end;
unsigned long slot_start, slot_end;
+   int tsize_inc;
 
pfnmap = 1;
 
@@ -392,10 +393,20 @@ static inline int kvmppc_e500_shadow_map(struct 
kvmppc_vcpu_e500 *vcpu_e500,
MAS1_TSIZE_SHIFT;
 
/*
-* e500 doesn't implement the lowest tsize bit,
-* or 1K pages.
+* MMUv1 doesn't implement the lowest tsize bit,
+* or translations smaller than 4K.
 */
-   tsize = max(BOOK3E_PAGESZ_4K, tsize & ~1);
+   if (!has_feature(_e500->vcpu, VCPU_FTR_MMU_V2))
+   tsize &= ~1;
+   tsize = max(BOOK3E_PAGESZ_4K, tsize);
+
+   /*
+* Calculate TSIZE increment. MMUv2 supports
+* power of 2K translations while MMUv1 is limited
+* to power of 4K sizes.
+*/
+   tsize_inc = has_feature(_e500->vcpu,
+   VCPU_FTR_MMU_V2) ? 1 : 2;
 
/*
 * Now find the largest tsize (up to what the guest
@@ -404,7 +415,8 @@ static inline int kvmppc_e500_shadow_map(struct 
kvmppc_vcpu_e500 *vcpu_e500,
 * aligned.
 */
 
-   for (; tsize > BOOK3E_PAGESZ_4K; tsize -= 2) {
+   for (; tsize > BOOK3E_PAGESZ_4K;
+tsize -= tsize_inc) {
unsigned long gfn_start, gfn_end;
tsize_pages = 1 << (tsize - 2);
 
@@ -437,10 +449,12 @@ static inline int kvmppc_e500_shadow_map(struct 
kvmppc_vcpu_e500 *vcpu_e500,
tsize = min(__ilog2(psize) - 10, tsize);
 
/*
-* e500 doesn't implement the lowest tsize bit,
-* or 1K pages.
+* MMUv1 doesn't implement the lowest tsize bit,
+* or translations smaller than 4K.
 */
-   tsize = max(BOOK3E_PAGESZ_4K, tsize & ~1);
+   if (!has_feature(_e500->vcpu, VCPU_FTR_MMU_V2))
+   tsize &= ~1;
+   tsize = max(BOOK3E_PAGESZ_4K, tsize);
}
 
up_read(>mm->mmap_sem);
-- 
1.8.3.1
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[PATCH 2/2] KVM: PPC: e6500: TLB emulation for IND entries

[Laurentiu Tudor]

Handle indirect entries (IND) in TLB emulation code.
Translation size of IND entries differs from the size
of referred Page Tables (Linux guests now use IND
of 2MB for 4KB PTs) and this requires careful tweaking
of the existing logic.

TLB search emulation requires additional search in
HW TLB0 (since entries might be directly added by HTW)
and found entries should be presented to the guest with
RPN changed from PFN to GFN. There might be more GFNs
pointing to the same PFN so the only way to get the
corresponding GFN is to search it in guest's PTE.
If the IND entry for the corresponding PT is not available
just invalidate guest's ea and report a tlbsx miss.
This patch only implements the invalidation and lets a
TODO note for searching HW TLB0.

Signed-off-by: Mihai Caraman 
[laurentiu.tu...@freescale.com: addressed review feedback,
 refactoring, cleanup & other fixes]
Signed-off-by: Laurentiu Tudor 
---
 arch/powerpc/include/asm/mmu-book3e.h |  2 +
 arch/powerpc/kvm/e500.h   | 93 +--
 arch/powerpc/kvm/e500_mmu.c   | 92 ++
 arch/powerpc/kvm/e500_mmu_host.c  | 30 ++-
 arch/powerpc/kvm/e500mc.c | 45 +++--
 5 files changed, 222 insertions(+), 40 deletions(-)

diff --git a/arch/powerpc/include/asm/mmu-book3e.h 
b/arch/powerpc/include/asm/mmu-book3e.h
index 9dbad3c..c8a1518 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -61,6 +61,7 @@
 #define MAS1_IPROT 0x4000
 #define MAS1_TID(x)(((x) << 16) & 0x3FFF)
 #define MAS1_IND   0x2000
+#define MAS1_IND_SHIFT 13
 #define MAS1_TS0x1000
 #define MAS1_TSIZE_MASK0x0f80
 #define MAS1_TSIZE_SHIFT   7
@@ -97,6 +98,7 @@
 #define MAS4_TLBSEL_MASK   MAS0_TLBSEL_MASK
 #define MAS4_TLBSELD(x)MAS0_TLBSEL(x)
 #define MAS4_INDD  0x8000  /* Default IND */
+#define MAS4_INDD_SHIFT15
 #define MAS4_TSIZED(x) MAS1_TSIZE(x)
 #define MAS4_X0D   0x0040
 #define MAS4_X1D   0x0020
diff --git a/arch/powerpc/kvm/e500.h b/arch/powerpc/kvm/e500.h
index 72920be..16f70eb 100644
--- a/arch/powerpc/kvm/e500.h
+++ b/arch/powerpc/kvm/e500.h
@@ -149,6 +149,22 @@ unsigned int kvmppc_e500_get_sid(struct kvmppc_vcpu_e500 
*vcpu_e500,
 unsigned int pr, int avoid_recursion);
 #endif
 
+static inline bool has_feature(const struct kvm_vcpu *vcpu,
+  enum vcpu_ftr ftr)
+{
+   bool has_ftr;
+
+   switch (ftr) {
+   case VCPU_FTR_MMU_V2:
+   has_ftr = ((vcpu->arch.mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V2);
+   break;
+
+   default:
+   return false;
+   }
+   return has_ftr;
+}
+
 /* TLB helper functions */
 static inline unsigned int
 get_tlb_size(const struct kvm_book3e_206_tlb_entry *tlbe)
@@ -208,6 +224,16 @@ get_tlb_tsize(const struct kvm_book3e_206_tlb_entry *tlbe)
return (tlbe->mas1 & MAS1_TSIZE_MASK) >> MAS1_TSIZE_SHIFT;
 }
 
+static inline unsigned int
+get_tlb_ind(const struct kvm_vcpu *vcpu,
+   const struct kvm_book3e_206_tlb_entry *tlbe)
+{
+   if (has_feature(vcpu, VCPU_FTR_MMU_V2))
+   return (tlbe->mas1 & MAS1_IND) >> MAS1_IND_SHIFT;
+
+   return 0;
+}
+
 static inline unsigned int get_cur_pid(struct kvm_vcpu *vcpu)
 {
return vcpu->arch.pid & 0xff;
@@ -233,6 +259,30 @@ static inline unsigned int get_cur_sas(const struct 
kvm_vcpu *vcpu)
return vcpu->arch.shared->mas6 & 0x1;
 }
 
+static inline unsigned int get_cur_ind(const struct kvm_vcpu *vcpu)
+{
+   if (has_feature(vcpu, VCPU_FTR_MMU_V2))
+   return (vcpu->arch.shared->mas1 & MAS1_IND) >> MAS1_IND_SHIFT;
+
+   return 0;
+}
+
+static inline unsigned int get_cur_indd(const struct kvm_vcpu *vcpu)
+{
+   if (has_feature(vcpu, VCPU_FTR_MMU_V2))
+   return (vcpu->arch.shared->mas4 & MAS4_INDD) >> MAS4_INDD_SHIFT;
+
+   return 0;
+}
+
+static inline unsigned int get_cur_sind(const struct kvm_vcpu *vcpu)
+{
+   if (has_feature(vcpu, VCPU_FTR_MMU_V2))
+   return (vcpu->arch.shared->mas6 & MAS6_SIND) >> MAS6_SIND_SHIFT;
+
+   return 0;
+}
+
 static inline unsigned int get_tlb_tlbsel(const struct kvm_vcpu *vcpu)
 {
/*
@@ -287,6 +337,34 @@ void kvmppc_e500_tlbil_one(struct kvmppc_vcpu_e500 
*vcpu_e500,
 void kvmppc_e500_tlbil_all(struct kvmppc_vcpu_e500 *vcpu_e500);
 
 #ifdef CONFIG_KVM_BOOKE_HV
+/*
+ * On e6500 cores with hw page table walk support the HW might
+ * populate TLB0 by its own, following a page table walk.
+ * Below functions ensure that the hw added tlb0 entries
+ * are also pruned when the guest invalidates the tlb.
+ * Note that as a consequence of the HWPTW, the shadow tlb could
+ 

[PATCH 0/2] KVM Book3E support for Hardware Page Tablewalk enabled guests

[Laurentiu Tudor]

This is a revival of LRAT & HWPTW support that Mike
submitted some time ago [1].
Patches are rebased and (most [2]) feedback addressed.
Also, fixed some issues i noticed plus some cleanup.

[1]  https://patchwork.ozlabs.org/patch/366892/
 https://patchwork.ozlabs.org/patch/366895/
 https://patchwork.ozlabs.org/patch/366893/
 https://patchwork.ozlabs.org/patch/366894/

[2] Comments not addressed
[Alex] "Don't we have to keep the page locked so it doesn't get swapped away?"
 * when will the page be unlocked?
 * Alex, can you please elaborate more on this? Where would the unlock happen if
   we keep it locked here?
[Scott] "use local_paca->tcd for tlb1 as well (except on 32-bit)"
 * i guess this needs a distinct patch, no?
[Scott] "A-008139"
 * distinct patch adding the erratum workaround
   in __write_host_tlbe(), e500_mmu_host.c

Detailed changes per patch from RFC:

[1/4] powerpc/booke64: Add LRAT next and max entries to tlb_core_data structure
[2/4] KVM: PPC: Book3E: Handle LRAT error exception
 - use tcd_ptr pointing to common tcd instead of local paca tcd
 - drop lrat_size() as it only had 2 uses
 - squashed these 2 patches as they address the same topic (lrat support):
 - mmap_sem was left locked on an exit path
 - wrapped new tcd struct members with #ifdef CONFIG_KVM_BOOKE_HV
 - dropped inline in c files (Alex)
 - changed lrat_next() implementation (Alex, Scott)
 - s/WARN/WARN_ONCE (Alex, Scott)
 - dropped write_host_lrate() unused lrat_entry param (Scott)
 - use get_paca() instead of local_paca (Scott)
[3/4] KVM: PPC: e500: TLB emulation for IND entries
[4/4] KVM: PPC: e500mc: Advertise E.PT to support HTW guests
 - squashed these too as they address the same topic (add HPTW support)
 - rebased & merged with e6500 single threaded vcpu support
 - commented inval_*_on_host() (Scott)
 - split generic MMUv2 support in a distinct patch (Scott)
 - s/tlbilx 3/tlbilxva/ (Scott)
 - code style (Scott)
 - dropped inval_tlb_on_host() and called kvmppc_e500_tlbil_lpid() or
   kvmppc_e500_tlbil_pid() directly (Scott)
 - for better naming and consistency:
s/kvmppc_e500_tlbil_lpid/kvmppc_e500_tlbil_lpid_on_host
s/kvmppc_e500_tlbil_pid/kvmppc_e500_tlbil_pid_on_host
s/inval_ea_on_host/kvmppc_e500_tlbil_ea_on_host
 - use MAS4_TLBSELD instead of open-coding
 - reworded some comments
 - TSIZE of a page table of an IND entry may be <4K so don't limit it


Mihai Caraman (2):
  KVM: PPC: e6500: Handle LRAT error exception
  KVM: PPC: e6500: TLB emulation for IND entries

 arch/powerpc/include/asm/kvm_host.h   |   1 +
 arch/powerpc/include/asm/kvm_ppc.h|   2 +
 arch/powerpc/include/asm/mmu-book3e.h |  14 
 arch/powerpc/include/asm/reg_booke.h  |  14 
 arch/powerpc/kernel/asm-offsets.c |   1 +
 arch/powerpc/kvm/booke.c  |  41 ++
 arch/powerpc/kvm/bookehv_interrupts.S |   9 ++-
 arch/powerpc/kvm/e500.h   |  93 +++
 arch/powerpc/kvm/e500_mmu.c   |  92 ++-
 arch/powerpc/kvm/e500_mmu_host.c  | 136 +-
 arch/powerpc/kvm/e500mc.c |  49 +++-
 arch/powerpc/mm/fsl_booke_mmu.c   |  10 +++
 12 files changed, 421 insertions(+), 41 deletions(-)

-- 
1.8.3.1
---

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[PATCH 1/2] KVM: PPC: e6500: Handle LRAT error exception

[Laurentiu Tudor]

Handle LRAT error exception with support for
lrat mapping and invalidation.

Signed-off-by: Mihai Caraman 
[laurentiu.tu...@freescale.com: addressed review feedback,
 refactoring, cleanup & other fixes]
Signed-off-by: Laurentiu Tudor 
---
 arch/powerpc/include/asm/kvm_host.h   |   1 +
 arch/powerpc/include/asm/kvm_ppc.h|   2 +
 arch/powerpc/include/asm/mmu-book3e.h |  12 
 arch/powerpc/include/asm/reg_booke.h  |  14 +
 arch/powerpc/kernel/asm-offsets.c |   1 +
 arch/powerpc/kvm/booke.c  |  41 +
 arch/powerpc/kvm/bookehv_interrupts.S |   9 ++-
 arch/powerpc/kvm/e500_mmu_host.c  | 106 ++
 arch/powerpc/kvm/e500mc.c |   4 ++
 arch/powerpc/mm/fsl_booke_mmu.c   |  10 
 10 files changed, 199 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/include/asm/kvm_host.h 
b/arch/powerpc/include/asm/kvm_host.h
index e187b6a..b207a32 100644
--- a/arch/powerpc/include/asm/kvm_host.h
+++ b/arch/powerpc/include/asm/kvm_host.h
@@ -444,6 +444,7 @@ struct kvm_vcpu_arch {
u32 eplc;
u32 epsc;
u32 oldpir;
+   u64 fault_lper;
 #endif
 
 #if defined(CONFIG_BOOKE)
diff --git a/arch/powerpc/include/asm/kvm_ppc.h 
b/arch/powerpc/include/asm/kvm_ppc.h
index c6ef05b..ac3574f 100644
--- a/arch/powerpc/include/asm/kvm_ppc.h
+++ b/arch/powerpc/include/asm/kvm_ppc.h
@@ -117,6 +117,8 @@ extern void kvmppc_mmu_itlb_miss(struct kvm_vcpu *vcpu);
 extern int kvmppc_xlate(struct kvm_vcpu *vcpu, ulong eaddr,
enum xlate_instdata xlid, enum xlate_readwrite xlrw,
struct kvmppc_pte *pte);
+extern void kvmppc_lrat_map(struct kvm_vcpu *vcpu, gfn_t gfn);
+extern void kvmppc_lrat_invalidate(struct kvm_vcpu *vcpu);
 
 extern struct kvm_vcpu *kvmppc_core_vcpu_create(struct kvm *kvm,
 unsigned int id);
diff --git a/arch/powerpc/include/asm/mmu-book3e.h 
b/arch/powerpc/include/asm/mmu-book3e.h
index cd4f04a..9dbad3c 100644
--- a/arch/powerpc/include/asm/mmu-book3e.h
+++ b/arch/powerpc/include/asm/mmu-book3e.h
@@ -40,6 +40,8 @@
 
 /* MAS registers bit definitions */
 
+#define MAS0_ATSEL 0x8000
+#define MAS0_ATSEL_SHIFT   31
 #define MAS0_TLBSEL_MASK   0x3000
 #define MAS0_TLBSEL_SHIFT  28
 #define MAS0_TLBSEL(x) (((x) << MAS0_TLBSEL_SHIFT) & MAS0_TLBSEL_MASK)
@@ -55,6 +57,7 @@
 #define MAS0_WQ_CLR_RSRV   0x2000
 
 #define MAS1_VALID 0x8000
+#define MAS1_VALID_SHIFT   31
 #define MAS1_IPROT 0x4000
 #define MAS1_TID(x)(((x) << 16) & 0x3FFF)
 #define MAS1_IND   0x2000
@@ -220,6 +223,12 @@
 #define TLBILX_T_CLASS26
 #define TLBILX_T_CLASS37
 
+/* LRATCFG bits */
+#define LRATCFG_ASSOC  0xFF00
+#define LRATCFG_LASIZE 0x00FE
+#define LRATCFG_LPID   0x2000
+#define LRATCFG_NENTRY 0x0FFF
+
 #ifndef __ASSEMBLY__
 #include 
 
@@ -297,6 +306,9 @@ struct tlb_core_data {
 
/* For software way selection, as on Freescale TLB1 */
u8 esel_next, esel_max, esel_first;
+#ifdef CONFIG_KVM_BOOKE_HV
+   u8 lrat_next, lrat_max;
+#endif
 };
 
 #ifdef CONFIG_PPC64
diff --git a/arch/powerpc/include/asm/reg_booke.h 
b/arch/powerpc/include/asm/reg_booke.h
index 2fef74b..265f5ec 100644
--- a/arch/powerpc/include/asm/reg_booke.h
+++ b/arch/powerpc/include/asm/reg_booke.h
@@ -55,6 +55,8 @@
 
 /* Special Purpose Registers (SPRNs)*/
 #define SPRN_DECAR 0x036   /* Decrementer Auto Reload Register */
+#define SPRN_LPER  0x038   /* Logical Page Exception Register */
+#define SPRN_LPERU 0x039   /* Logical Page Exception Register Upper */
 #define SPRN_IVPR  0x03F   /* Interrupt Vector Prefix Register */
 #define SPRN_USPRG00x100   /* User Special Purpose Register General 0 */
 #define SPRN_SPRG3R0x103   /* Special Purpose Register General 3 Read */
@@ -76,6 +78,7 @@
 #define SPRN_DVC2  0x13F   /* Data Value Compare Register 2 */
 #define SPRN_LPID  0x152   /* Logical Partition ID */
 #define SPRN_MAS8  0x155   /* MMU Assist Register 8 */
+#define SPRN_LRATCFG   0x156   /* LRAT Configuration Register */
 #define SPRN_TLB0PS0x158   /* TLB 0 Page Size Register */
 #define SPRN_TLB1PS0x159   /* TLB 1 Page Size Register */
 #define SPRN_MAS5_MAS6 0x15c   /* MMU Assist Register 5 || 6 */
@@ -371,6 +374,9 @@
 #define ESR_ILK0x0010  /* Instr. Cache Locking */
 #define ESR_PUO0x0004  /* Unimplemented Operation 
exception */
 #define ESR_BO 0x0002  /* Byte Ordering */
+#define ESR_DATA   0x0400  /* Page Table Data Access */
+#define ESR_TLBI   0x0200  /* Page Table TLB Ineligible */
+#define ESR_PT 0x0100  /* Page Table Translation */
 #define 

Re: [PATCH 1/1] target-i386: get/put MSR_TSC_AUX across reset and migration

[Eduardo Habkost]

On Wed, Sep 23, 2015 at 09:47:43AM +0200, Paolo Bonzini wrote:
> 
> 
> On 23/09/2015 08:27, Amit Shah wrote:
> > There's one report of migration breaking due to missing MSR_TSC_AUX
> > save/restore.  Fix this by adding a new subsection that saves the state
> > of this MSR.
> > 
> > https://bugzilla.redhat.com/show_bug.cgi?id=1261797
> 
> It turns out that the MSR is already saved/restored into the migration
> stream!  However, the commit that introduced RDTSCP support (commit
> 1b05007, "target-i386: add RDTSCP support", 2009-09-19) was written for
> TCG, and we ended up forgetting to fish the value out of KVM and send it
> back in.
> 
> The KVM bits are okay.  Eduardo, can you undo the machine.c hunk or
> should Amit send v2?

I can remove the machine.c hunk manually when applying. Thanks!

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[PATCH 15/19] KVM: PPC: e500: fix handling local_sid_lookup result

[Andrzej Hajda]

The function can return negative value.

The problem has been detected using proposed semantic patch
scripts/coccinelle/tests/assign_signed_to_unsigned.cocci [1].

[1]: http://permalink.gmane.org/gmane.linux.kernel/2046107

Signed-off-by: Andrzej Hajda 
---
Hi,

To avoid problems with too many mail recipients I have sent whole
patchset only to LKML. Anyway patches have no dependencies.

Regards
Andrzej
---
 arch/powerpc/kvm/e500.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/kvm/e500.c b/arch/powerpc/kvm/e500.c
index b29ce75..32fdab5 100644
--- a/arch/powerpc/kvm/e500.c
+++ b/arch/powerpc/kvm/e500.c
@@ -237,7 +237,8 @@ void kvmppc_e500_tlbil_one(struct kvmppc_vcpu_e500 
*vcpu_e500,
struct kvm_book3e_206_tlb_entry *gtlbe)
 {
struct vcpu_id_table *idt = vcpu_e500->idt;
-   unsigned int pr, tid, ts, pid;
+   unsigned int pr, tid, ts;
+   int pid;
u32 val, eaddr;
unsigned long flags;
 
-- 
1.9.1

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[PATCH 15/19] KVM: PPC: e500: fix handling local_sid_lookup result

[Andrzej Hajda]

The function can return negative value.

The problem has been detected using proposed semantic patch
scripts/coccinelle/tests/assign_signed_to_unsigned.cocci [1].

[1]: http://permalink.gmane.org/gmane.linux.kernel/2046107

Signed-off-by: Andrzej Hajda 
---
Hi,

To avoid problems with too many mail recipients I have sent whole
patchset only to LKML. Anyway patches have no dependencies.

Regards
Andrzej
---
 arch/powerpc/kvm/e500.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/kvm/e500.c b/arch/powerpc/kvm/e500.c
index b29ce75..32fdab5 100644
--- a/arch/powerpc/kvm/e500.c
+++ b/arch/powerpc/kvm/e500.c
@@ -237,7 +237,8 @@ void kvmppc_e500_tlbil_one(struct kvmppc_vcpu_e500 
*vcpu_e500,
struct kvm_book3e_206_tlb_entry *gtlbe)
 {
struct vcpu_id_table *idt = vcpu_e500->idt;
-   unsigned int pr, tid, ts, pid;
+   unsigned int pr, tid, ts;
+   int pid;
u32 val, eaddr;
unsigned long flags;
 
-- 
1.9.1

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Re: [PATCH 1/1] target-i386: get/put MSR_TSC_AUX across reset and migration

[Eduardo Habkost]

On Wed, Sep 23, 2015 at 11:57:33AM +0530, Amit Shah wrote:
> There's one report of migration breaking due to missing MSR_TSC_AUX
> save/restore.  Fix this by adding a new subsection that saves the state
> of this MSR.
> 
> https://bugzilla.redhat.com/show_bug.cgi?id=1261797
> 
> Reported-by: Xiaoqing Wei 
> Signed-off-by: Amit Shah 
> CC: Paolo Bonzini 
> CC: Juan Quintela 
> CC: "Dr. David Alan Gilbert" 
> CC: Marcelo Tosatti 
> CC: Richard Henderson 
> CC: Eduardo Habkost 
> ---
>  target-i386/kvm.c | 14 ++
>  target-i386/machine.c | 20 
>  2 files changed, 34 insertions(+)

For the target-i386/kvm.c hunk:
Reviewed-by: Eduardo Habkost 

Applied to x86 tree without the machine.c hunk. Thanks!

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Re: [PATCH] KVM: nVMX: emulate the INVVPID instruction

[Bandan Das]

Paolo Bonzini  writes:
...
>> @@ -7189,7 +7189,28 @@ static int handle_invept(struct kvm_vcpu *vcpu)
>>  
>>  static int handle_invvpid(struct kvm_vcpu *vcpu)
>>  {
>> -kvm_queue_exception(vcpu, UD_VECTOR);
>> +u32 vmx_instruction_info;
>> +unsigned long type;
>> +
>> +if (!nested_vmx_check_permission(vcpu))
>> +return 1;
>> +
>> +vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
>> +type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
>> +
>> +switch (type) {
>> +case VMX_VPID_EXTENT_INDIVIDUAL_ADDR:
>> +case VMX_VPID_EXTENT_SINGLE_CONTEXT:
>> +case VMX_VPID_EXTENT_ALL_CONTEXT:
>> +vmx_flush_tlb(vcpu);
>> +nested_vmx_succeed(vcpu);
>> +break;
>> +default:
>> +nested_vmx_failInvalid(vcpu);
>> +break;
>> +}
>> +
>> +skip_emulated_instruction(vcpu);
>>  return 1;
>>  }
>>  
>> 
>
> This is not enough.  You need to add a VPID argument to
> vpid_sync_vcpu_single, and inline vmx_flush_tlb in handle_invvpid so
> that it can use the new VPID argument of vpid_sync_vcpu_single.
>
> Note that the "all context" variant can be mapped to
> vpid_sync_vcpu_single with vpid02 as the argument (a nice side effect of
> your vpid02 design).
>
> However, I have applied the patch to kvm/queue.  Please send the changes
> separately, and I will squash them in the existing VPID patch.

Please don't do this. It's making it really difficult to review these
patches individually :( Why not let them get some review time before
applying them all together ?


> Paolo
> --
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Re: [PATCH 1/2] KVM: introduce __vmx_flush_tlb to handle specific vpid

[Bandan Das]

Wanpeng Li  writes:

> Introduce __vmx_flush_tlb() to handle specific vpid.
>
> Signed-off-by: Wanpeng Li 
> ---
>  arch/x86/kvm/vmx.c | 21 +
>  1 file changed, 13 insertions(+), 8 deletions(-)
>
> diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
> index 794c529..7188c5e 100644
> --- a/arch/x86/kvm/vmx.c
> +++ b/arch/x86/kvm/vmx.c
> @@ -1343,13 +1343,13 @@ static void loaded_vmcs_clear(struct loaded_vmcs 
> *loaded_vmcs)
>__loaded_vmcs_clear, loaded_vmcs, 1);
>  }
>  
> -static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
> +static inline void vpid_sync_vcpu_single(int vpid)
>  {
> - if (vmx->vpid == 0)
> + if (vpid == 0)
>   return;
>  
>   if (cpu_has_vmx_invvpid_single())
> - __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
> + __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
>  }
>  
>  static inline void vpid_sync_vcpu_global(void)
> @@ -1358,10 +1358,10 @@ static inline void vpid_sync_vcpu_global(void)
>   __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
>  }
>  
> -static inline void vpid_sync_context(struct vcpu_vmx *vmx)
> +static inline void vpid_sync_context(int vpid)
>  {
>   if (cpu_has_vmx_invvpid_single())
> - vpid_sync_vcpu_single(vmx);
> + vpid_sync_vcpu_single(vpid);
>   else
>   vpid_sync_vcpu_global();
>  }

Not sure myself what's the right thing to do but this may be undesirable
in a nested environment. Assuming the processor supports global invalidation
only, this seems like a easy way for the nested guest to invalidate *all*
mappings - even the L1 specific mappings.


> @@ -3450,9 +3450,9 @@ static void exit_lmode(struct kvm_vcpu *vcpu)
>  
>  #endif
>  
> -static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
> +static inline void __vmx_flush_tlb(struct kvm_vcpu *vcpu, int vpid)
>  {
> - vpid_sync_context(to_vmx(vcpu));
> + vpid_sync_context(vpid);
>   if (enable_ept) {
>   if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
>   return;
> @@ -3460,6 +3460,11 @@ static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
>   }
>  }
>  
> +static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
> +{
> + __vmx_flush_tlb(vcpu, to_vmx(vcpu)->vpid);
> +}
> +
>  static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
>  {
>   ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
> @@ -4795,7 +4800,7 @@ static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool 
> init_event)
>   vmx_fpu_activate(vcpu);
>   update_exception_bitmap(vcpu);
>  
> - vpid_sync_context(vmx);
> + vpid_sync_context(vmx->vpid);
>  }
>  
>  /*
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Re: [PATCH] KVM: PPC: e6500: support powers of 2K TLB1 sizes

[Scott Wood]

On Thu, 2015-09-24 at 15:57 +0300, Laurentiu Tudor wrote:
> Book-E MMUv2 present in e6500 cores supports
> powers of 2K page sizes while older MMUv1 cores
> support only powers of 4K page sizes, or in other
> words the LSB of TSIZE on MMUv1 is always 0.
> Thus, on MMUv2 we must not strip the LSB.

We can get better TLB utilization by not stripping it, but why "must not" 
which makes it sound like a bugfix rather than an optimization?

> Signed-off-by: Mihai Caraman 
> [laurentiu.tu...@freescale.com: addressed review
>  feedback, split in distinct patch]
> Signed-off-by: Laurentiu Tudor 
> ---
>  arch/powerpc/kvm/e500_mmu_host.c | 28 +---
>  1 file changed, 21 insertions(+), 7 deletions(-)
> 
> diff --git a/arch/powerpc/kvm/e500_mmu_host.c 
> b/arch/powerpc/kvm/e500_mmu_host.c
> index 4d33e19..12d5c67 100644
> --- a/arch/powerpc/kvm/e500_mmu_host.c
> +++ b/arch/powerpc/kvm/e500_mmu_host.c
> @@ -371,6 +371,7 @@ static inline int kvmppc_e500_shadow_map(struct 
> kvmppc_vcpu_e500 *vcpu_e500,
>  
>   unsigned long start, end;
>   unsigned long slot_start, slot_end;
> + int tsize_inc;
>  
>   pfnmap = 1;
>  
> @@ -392,10 +393,20 @@ static inline int kvmppc_e500_shadow_map(struct 
> kvmppc_vcpu_e500 *vcpu_e500,
>   MAS1_TSIZE_SHIFT;
>  
>   /*
> -  * e500 doesn't implement the lowest tsize bit,
> -  * or 1K pages.
> +  * MMUv1 doesn't implement the lowest tsize bit,
> +  * or translations smaller than 4K.
>*/
> - tsize = max(BOOK3E_PAGESZ_4K, tsize & ~1);
> + if (!has_feature(_e500->vcpu, VCPU_FTR_MMU_V2))
> + tsize &= ~1;
> + tsize = max(BOOK3E_PAGESZ_4K, tsize);
> +
> + /*
> +  * Calculate TSIZE increment. MMUv2 supports
> +  * power of 2K translations while MMUv1 is limited
> +  * to power of 4K sizes.
> +  */
> + tsize_inc = has_feature(_e500->vcpu,
> + VCPU_FTR_MMU_V2) ? 1 : 2;

If you calculate tsize_inc first, then the previous if-statement can become 
"tsize &= ~(tsize_inc - 1);".

>  
>   /*
>* Now find the largest tsize (up to what the guest
> @@ -404,7 +415,8 @@ static inline int kvmppc_e500_shadow_map(struct 
> kvmppc_vcpu_e500 *vcpu_e500,
>* aligned.
>*/
>  
> - for (; tsize > BOOK3E_PAGESZ_4K; tsize -= 2) {
> + for (; tsize > BOOK3E_PAGESZ_4K;
> +  tsize -= tsize_inc) {
>   unsigned long gfn_start, gfn_end;
>   tsize_pages = 1 << (tsize - 2);
>  
> @@ -437,10 +449,12 @@ static inline int kvmppc_e500_shadow_map(struct 
> kvmppc_vcpu_e500 *vcpu_e500,
>   tsize = min(__ilog2(psize) - 10, tsize);
>  
>   /*
> -  * e500 doesn't implement the lowest tsize bit,
> -  * or 1K pages.
> +  * MMUv1 doesn't implement the lowest tsize bit,
> +  * or translations smaller than 4K.
>*/

This comment makes it sound like MMUv2 might support translations smaller 
than 4K.

-Scott

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[PATCH v3 02/20] KVM: ARM64: Define PMU data structure for each vcpu

[Shannon Zhao]

Here we plan to support virtual PMU for guest by full software
emulation, so define some basic structs and functions preparing for
futher steps. Define struct kvm_pmc for performance monitor counter and
struct kvm_pmu for performance monitor unit for each vcpu. According to
ARMv8 spec, the PMU contains at most 32(ARMV8_MAX_COUNTERS) counters.

Since this only supports ARM64 (or PMUv3), add a separate config symbol
for it.

Signed-off-by: Shannon Zhao 
---
 arch/arm64/include/asm/kvm_host.h |  2 ++
 arch/arm64/kvm/Kconfig|  8 
 include/kvm/arm_pmu.h | 40 +++
 3 files changed, 50 insertions(+)
 create mode 100644 include/kvm/arm_pmu.h

diff --git a/arch/arm64/include/asm/kvm_host.h 
b/arch/arm64/include/asm/kvm_host.h
index 415938d..6a246a3 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -42,6 +42,7 @@
 
 #include 
 #include 
+#include 
 
 #define KVM_VCPU_MAX_FEATURES 3
 
@@ -135,6 +136,7 @@ struct kvm_vcpu_arch {
/* VGIC state */
struct vgic_cpu vgic_cpu;
struct arch_timer_cpu timer_cpu;
+   struct kvm_pmu pmu;
 
/*
 * Anything that is not used directly from assembly code goes
diff --git a/arch/arm64/kvm/Kconfig b/arch/arm64/kvm/Kconfig
index bfffe8f..3c7c58d 100644
--- a/arch/arm64/kvm/Kconfig
+++ b/arch/arm64/kvm/Kconfig
@@ -31,6 +31,7 @@ config KVM
select KVM_VFIO
select HAVE_KVM_EVENTFD
select HAVE_KVM_IRQFD
+   select KVM_ARM_PMU
---help---
  Support hosting virtualized guest machines.
 
@@ -52,4 +53,11 @@ config KVM_ARM_MAX_VCPUS
  large, so only choose a reasonable number that you expect to
  actually use.
 
+config KVM_ARM_PMU
+   bool
+   depends on KVM_ARM_HOST
+   ---help---
+ Adds support for a virtual Performance Monitoring Unit (PMU) in
+ virtual machines.
+
 endif # VIRTUALIZATION
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
new file mode 100644
index 000..bb0cd21
--- /dev/null
+++ b/include/kvm/arm_pmu.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2015 Linaro Ltd.
+ * Author: Shannon Zhao 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+#ifndef __ASM_ARM_KVM_PMU_H
+#define __ASM_ARM_KVM_PMU_H
+
+#include 
+#include 
+
+struct kvm_pmc {
+   u8 idx;/* index into the pmu->pmc array */
+   struct perf_event *perf_event;
+   struct kvm_vcpu *vcpu;
+};
+
+struct kvm_pmu {
+#ifdef CONFIG_KVM_ARM_PMU
+   /* PMU IRQ Number per VCPU */
+   int irq_num;
+   /* IRQ pending flag */
+   bool irq_pending;
+   struct kvm_pmc pmc[ARMV8_MAX_COUNTERS];
+#endif
+};
+
+#endif
-- 
2.1.4

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[PATCH v3 00/20] KVM: ARM64: Add guest PMU support

[Shannon Zhao]

This patchset adds guest PMU support for KVM on ARM64. It takes
trap-and-emulate approach. When guest wants to monitor one event, it
will be trapped by KVM and KVM will call perf_event API to create a perf
event and call relevant perf_event APIs to get the count value of event.

Use perf to test this patchset in guest. When using "perf list", it
shows the list of the hardware events and hardware cache events perf
supports. Then use "perf stat -e EVENT" to monitor some event. For
example, use "perf stat -e cycles" to count cpu cycles and
"perf stat -e cache-misses" to count cache misses.

Below are the outputs of "perf stat -r 5 sleep 5" when running in host
and guest.

Host:
 Performance counter stats for 'sleep 5' (5 runs):

  0.551428  task-clock (msec) #0.000 CPUs utilized  
  ( +-  0.91% )
 1  context-switches  #0.002 M/sec
 0  cpu-migrations#0.000 K/sec
48  page-faults   #0.088 M/sec  
  ( +-  1.05% )
   1150265  cycles#2.086 GHz
  ( +-  0.92% )
 stalled-cycles-frontend
 stalled-cycles-backend
526398  instructions  #0.46  insns per cycle
  ( +-  0.89% )
 branches
  9485  branch-misses #   17.201 M/sec  
  ( +-  2.35% )

   5.000831616 seconds time elapsed 
 ( +-  0.00% )

Guest:
 Performance counter stats for 'sleep 5' (5 runs):

  0.730868  task-clock (msec) #0.000 CPUs utilized  
  ( +-  1.13% )
 1  context-switches  #0.001 M/sec
 0  cpu-migrations#0.000 K/sec
48  page-faults   #0.065 M/sec  
  ( +-  0.42% )
   1642982  cycles#2.248 GHz
  ( +-  1.04% )
 stalled-cycles-frontend
 stalled-cycles-backend
637964  instructions  #0.39  insns per cycle
  ( +-  0.65% )
 branches
 10377  branch-misses #   14.198 M/sec  
  ( +-  1.09% )

   5.001289068 seconds time elapsed 
 ( +-  0.00% )

This patchset can be fetched from [1] and the relevant QEMU version for
test can be fetched from [2].

Thanks,
Shannon

[1] https://git.linaro.org/people/shannon.zhao/linux-mainline.git  
KVM_ARM64_PMU_v3
[2] https://git.linaro.org/people/shannon.zhao/qemu.git  PMU_v2

Changes since v2->v3:
* Directly use perf raw event type to create perf_event in KVM
* Add a helper vcpu_sysreg_write
* remove unrelated header file

Changes since v1->v2:
* Use switch...case for registers access handler instead of adding
  alone handler for each register
* Try to use the sys_regs to store the register value instead of adding
  new variables in struct kvm_pmc
* Fix the handle of cp15 regs
* Create a new kvm device vPMU, then userspace could choose whether to
  create PMU
* Fix the handle of PMU overflow interrupt

Shannon Zhao (20):
  ARM64: Move PMU register related defines to asm/pmu.h
  KVM: ARM64: Define PMU data structure for each vcpu
  KVM: ARM64: Add offset defines for PMU registers
  KVM: ARM64: Add reset and access handlers for PMCR_EL0 register
  KVM: ARM64: Add reset and access handlers for PMSELR register
  KVM: ARM64: Add reset and access handlers for PMCEID0 and PMCEID1
register
  KVM: ARM64: PMU: Add perf event map and introduce perf event creating
function
  KVM: ARM64: Add reset and access handlers for PMXEVTYPER register
  KVM: ARM64: Add reset and access handlers for PMXEVCNTR register
  KVM: ARM64: Add reset and access handlers for PMCCNTR register
  KVM: ARM64: Add reset and access handlers for PMCNTENSET and
PMCNTENCLR register
  KVM: ARM64: Add reset and access handlers for PMINTENSET and
PMINTENCLR register
  KVM: ARM64: Add reset and access handlers for PMOVSSET and PMOVSCLR
register
  KVM: ARM64: Add reset and access handlers for PMUSERENR register
  KVM: ARM64: Add reset and access handlers for PMSWINC register
  KVM: ARM64: Add access handlers for PMEVCNTRn and PMEVTYPERn register
  KVM: ARM64: Add PMU overflow interrupt routing
  KVM: ARM64: Reset PMU state when resetting vcpu
  KVM: ARM64: Free perf event of PMU when destroying vcpu
  KVM: ARM64: Add a new kvm ARM PMU device

 Documentation/virtual/kvm/devices/arm-pmu.txt |  15 +
 arch/arm/kvm/arm.c|   5 +
 arch/arm64/include/asm/kvm_asm.h  |  59 +++-
 arch/arm64/include/asm/kvm_host.h |   2 +
 arch/arm64/include/asm/pmu.h  |  47 +++
 arch/arm64/include/uapi/asm/kvm.h |   3 +
 arch/arm64/kernel/perf_event.c|  35 --
 arch/arm64/kvm/Kconfig 

[PATCH v3 01/20] ARM64: Move PMU register related defines to asm/pmu.h

[Shannon Zhao]

To use the ARMv8 PMU related register defines from the KVM code,
we move the relevant definitions to asm/pmu.h header file.

Signed-off-by: Anup Patel 
Signed-off-by: Shannon Zhao 
---
 arch/arm64/include/asm/pmu.h   | 45 ++
 arch/arm64/kernel/perf_event.c | 35 
 2 files changed, 45 insertions(+), 35 deletions(-)

diff --git a/arch/arm64/include/asm/pmu.h b/arch/arm64/include/asm/pmu.h
index b7710a5..b9f394a 100644
--- a/arch/arm64/include/asm/pmu.h
+++ b/arch/arm64/include/asm/pmu.h
@@ -19,6 +19,51 @@
 #ifndef __ASM_PMU_H
 #define __ASM_PMU_H
 
+#define ARMV8_MAX_COUNTERS  32
+#define ARMV8_COUNTER_MASK  (ARMV8_MAX_COUNTERS - 1)
+
+/*
+ * Per-CPU PMCR: config reg
+ */
+#define ARMV8_PMCR_E   (1 << 0) /* Enable all counters */
+#define ARMV8_PMCR_P   (1 << 1) /* Reset all counters */
+#define ARMV8_PMCR_C   (1 << 2) /* Cycle counter reset */
+#define ARMV8_PMCR_D   (1 << 3) /* CCNT counts every 64th cpu cycle */
+#define ARMV8_PMCR_X   (1 << 4) /* Export to ETM */
+#define ARMV8_PMCR_DP  (1 << 5) /* Disable CCNT if non-invasive debug*/
+#defineARMV8_PMCR_N_SHIFT  11   /* Number of counters 
supported */
+#defineARMV8_PMCR_N_MASK   0x1f
+#defineARMV8_PMCR_MASK 0x3f /* Mask for writable bits */
+
+/*
+ * PMCNTEN: counters enable reg
+ */
+#defineARMV8_CNTEN_MASK0x  /* Mask for writable 
bits */
+
+/*
+ * PMINTEN: counters interrupt enable reg
+ */
+#defineARMV8_INTEN_MASK0x  /* Mask for writable 
bits */
+
+/*
+ * PMOVSR: counters overflow flag status reg
+ */
+#defineARMV8_OVSR_MASK 0x  /* Mask for writable 
bits */
+#defineARMV8_OVERFLOWED_MASK   ARMV8_OVSR_MASK
+
+/*
+ * PMXEVTYPER: Event selection reg
+ */
+#defineARMV8_EVTYPE_MASK   0xc80003ff  /* Mask for writable 
bits */
+#defineARMV8_EVTYPE_EVENT  0x3ff   /* Mask for EVENT bits 
*/
+
+/*
+ * Event filters for PMUv3
+ */
+#defineARMV8_EXCLUDE_EL1   (1 << 31)
+#defineARMV8_EXCLUDE_EL0   (1 << 30)
+#defineARMV8_INCLUDE_EL2   (1 << 27)
+
 #ifdef CONFIG_HW_PERF_EVENTS
 
 /* The events for a given PMU register set. */
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index f9a74d4..534e8ad 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -741,9 +741,6 @@ static const unsigned 
armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 #defineARMV8_IDX_COUNTER0  1
 #defineARMV8_IDX_COUNTER_LAST  (ARMV8_IDX_CYCLE_COUNTER + 
cpu_pmu->num_events - 1)
 
-#defineARMV8_MAX_COUNTERS  32
-#defineARMV8_COUNTER_MASK  (ARMV8_MAX_COUNTERS - 1)
-
 /*
  * ARMv8 low level PMU access
  */
@@ -754,38 +751,6 @@ static const unsigned 
armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
 #defineARMV8_IDX_TO_COUNTER(x) \
(((x) - ARMV8_IDX_COUNTER0) & ARMV8_COUNTER_MASK)
 
-/*
- * Per-CPU PMCR: config reg
- */
-#define ARMV8_PMCR_E   (1 << 0) /* Enable all counters */
-#define ARMV8_PMCR_P   (1 << 1) /* Reset all counters */
-#define ARMV8_PMCR_C   (1 << 2) /* Cycle counter reset */
-#define ARMV8_PMCR_D   (1 << 3) /* CCNT counts every 64th cpu cycle */
-#define ARMV8_PMCR_X   (1 << 4) /* Export to ETM */
-#define ARMV8_PMCR_DP  (1 << 5) /* Disable CCNT if non-invasive debug*/
-#defineARMV8_PMCR_N_SHIFT  11   /* Number of counters 
supported */
-#defineARMV8_PMCR_N_MASK   0x1f
-#defineARMV8_PMCR_MASK 0x3f /* Mask for writable bits */
-
-/*
- * PMOVSR: counters overflow flag status reg
- */
-#defineARMV8_OVSR_MASK 0x  /* Mask for writable 
bits */
-#defineARMV8_OVERFLOWED_MASK   ARMV8_OVSR_MASK
-
-/*
- * PMXEVTYPER: Event selection reg
- */
-#defineARMV8_EVTYPE_MASK   0xc80003ff  /* Mask for writable 
bits */
-#defineARMV8_EVTYPE_EVENT  0x3ff   /* Mask for EVENT bits 
*/
-
-/*
- * Event filters for PMUv3
- */
-#defineARMV8_EXCLUDE_EL1   (1 << 31)
-#defineARMV8_EXCLUDE_EL0   (1 << 30)
-#defineARMV8_INCLUDE_EL2   (1 << 27)
-
 static inline u32 armv8pmu_pmcr_read(void)
 {
u32 val;
-- 
2.1.4

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[PATCH v3 07/20] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function

[Shannon Zhao]

When we use tools like perf on host, perf passes the event type and the
id of this event type category to kernel, then kernel will map them to
hardware event number and write this number to PMU PMEVTYPER_EL0
register. When getting the event number in KVM, directly use raw event
type to create a perf_event for it.

Signed-off-by: Shannon Zhao 
---
 arch/arm64/include/asm/pmu.h |   2 +
 arch/arm64/kvm/Makefile  |   1 +
 include/kvm/arm_pmu.h|  13 
 virt/kvm/arm/pmu.c   | 154 +++
 4 files changed, 170 insertions(+)
 create mode 100644 virt/kvm/arm/pmu.c

diff --git a/arch/arm64/include/asm/pmu.h b/arch/arm64/include/asm/pmu.h
index b9f394a..2c025f2 100644
--- a/arch/arm64/include/asm/pmu.h
+++ b/arch/arm64/include/asm/pmu.h
@@ -31,6 +31,8 @@
 #define ARMV8_PMCR_D   (1 << 3) /* CCNT counts every 64th cpu cycle */
 #define ARMV8_PMCR_X   (1 << 4) /* Export to ETM */
 #define ARMV8_PMCR_DP  (1 << 5) /* Disable CCNT if non-invasive debug*/
+/* Determines which PMCCNTR_EL0 bit generates an overflow */
+#define ARMV8_PMCR_LC  (1 << 6)
 #defineARMV8_PMCR_N_SHIFT  11   /* Number of counters 
supported */
 #defineARMV8_PMCR_N_MASK   0x1f
 #defineARMV8_PMCR_MASK 0x3f /* Mask for writable bits */
diff --git a/arch/arm64/kvm/Makefile b/arch/arm64/kvm/Makefile
index 1949fe5..18d56d8 100644
--- a/arch/arm64/kvm/Makefile
+++ b/arch/arm64/kvm/Makefile
@@ -27,3 +27,4 @@ kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic-v3.o
 kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/vgic-v3-emul.o
 kvm-$(CONFIG_KVM_ARM_HOST) += vgic-v3-switch.o
 kvm-$(CONFIG_KVM_ARM_HOST) += $(KVM)/arm/arch_timer.o
+kvm-$(CONFIG_KVM_ARM_PMU) += $(KVM)/arm/pmu.o
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index bb0cd21..b48cdc6 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -37,4 +37,17 @@ struct kvm_pmu {
 #endif
 };
 
+#ifdef CONFIG_KVM_ARM_PMU
+unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx);
+void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data,
+   u32 select_idx);
+#else
+unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx)
+{
+   return 0;
+}
+void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data,
+   u32 select_idx) {}
+#endif
+
 #endif
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
new file mode 100644
index 000..002ec79
--- /dev/null
+++ b/virt/kvm/arm/pmu.c
@@ -0,0 +1,154 @@
+/*
+ * Copyright (C) 2015 Linaro Ltd.
+ * Author: Shannon Zhao 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+static void kvm_pmu_set_evttyper(struct kvm_vcpu *vcpu, u32 idx, u32 val)
+{
+   if (!vcpu_mode_is_32bit(vcpu))
+   vcpu_sys_reg(vcpu, PMEVTYPER0_EL0 + idx) = val;
+   else
+   vcpu_cp15(vcpu, c14_PMEVTYPER0 + idx) = val;
+}
+
+static unsigned long kvm_pmu_get_evttyper(struct kvm_vcpu *vcpu, u32 idx)
+{
+   if (!vcpu_mode_is_32bit(vcpu))
+   return vcpu_sys_reg(vcpu, PMEVTYPER0_EL0 + idx)
+  & ARMV8_EVTYPE_EVENT;
+   else
+   return vcpu_cp15(vcpu, c14_PMEVTYPER0 + idx)
+  & ARMV8_EVTYPE_EVENT;
+}
+
+/**
+ * kvm_pmu_stop_counter - stop PMU counter for the selected counter
+ * @vcpu: The vcpu pointer
+ * @select_idx: The counter index
+ *
+ * If this counter has been configured to monitor some event, disable and
+ * release it.
+ */
+static void kvm_pmu_stop_counter(struct kvm_vcpu *vcpu, u32 select_idx)
+{
+   struct kvm_pmu *pmu = >arch.pmu;
+   struct kvm_pmc *pmc = >pmc[select_idx];
+
+   if (pmc->perf_event) {
+   perf_event_disable(pmc->perf_event);
+   perf_event_release_kernel(pmc->perf_event);
+   pmc->perf_event = NULL;
+   }
+   kvm_pmu_set_evttyper(vcpu, select_idx, ARMV8_EVTYPE_EVENT);
+}
+
+/**
+ * kvm_pmu_get_counter_value - get PMU counter value
+ * @vcpu: The vcpu pointer
+ * @select_idx: The counter index
+ */
+unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx)
+{
+   u64 enabled, running;
+   struct kvm_pmu *pmu = >arch.pmu;
+   struct kvm_pmc *pmc = 

[PATCH v3 10/20] KVM: ARM64: Add reset and access handlers for PMCCNTR register

[Shannon Zhao]

Since the reset value of PMCCNTR is UNKNOWN, use reset_unknown for its
reset handler. Add a new case to emulate reading to PMCCNTR register.

Signed-off-by: Shannon Zhao 
---
 arch/arm64/kvm/sys_regs.c | 17 +++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index e7f6058..c38c2de 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -518,6 +518,12 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
}
} else {
switch (r->reg) {
+   case PMCCNTR_EL0: {
+   val = kvm_pmu_get_counter_value(vcpu,
+   ARMV8_MAX_COUNTERS - 1);
+   *vcpu_reg(vcpu, p->Rt) = val;
+   break;
+   }
case PMXEVCNTR_EL0: {
val = kvm_pmu_get_counter_value(vcpu,
vcpu_sys_reg(vcpu, PMSELR_EL0));
@@ -748,7 +754,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
  access_pmu_regs, reset_pmceid, PMCEID1_EL0 },
/* PMCCNTR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),
- trap_raz_wi },
+ access_pmu_regs, reset_unknown, PMCCNTR_EL0 },
/* PMXEVTYPER_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001),
  access_pmu_regs, reset_unknown, PMXEVTYPER_EL0 },
@@ -997,6 +1003,12 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu,
}
} else {
switch (r->reg) {
+   case c9_PMCCNTR: {
+   val = kvm_pmu_get_counter_value(vcpu,
+   ARMV8_MAX_COUNTERS - 1);
+   *vcpu_reg(vcpu, p->Rt) = val;
+   break;
+   }
case c9_PMXEVCNTR: {
val = kvm_pmu_get_counter_value(vcpu,
vcpu_cp15(vcpu, c9_PMSELR));
@@ -1051,7 +1063,8 @@ static const struct sys_reg_desc cp15_regs[] = {
  reset_pmceid, c9_PMCEID0 },
{ Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmu_cp15_regs,
  reset_pmceid, c9_PMCEID1 },
-   { Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
+   { Op1( 0), CRn( 9), CRm(13), Op2( 0), access_pmu_cp15_regs,
+ reset_unknown_cp15, c9_PMCCNTR },
{ Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_cp15_regs,
  reset_unknown_cp15, c9_PMXEVTYPER },
{ Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_cp15_regs,
-- 
2.1.4

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[PATCH v3 06/20] KVM: ARM64: Add reset and access handlers for PMCEID0 and PMCEID1 register

[Shannon Zhao]

Add reset handler which gets host value of PMCEID0 or PMCEID1. Since
write action to PMCEID0 or PMCEID1 is ignored, add a new case for this.

Signed-off-by: Shannon Zhao 
---
 arch/arm64/kvm/sys_regs.c | 29 +
 1 file changed, 25 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index f73aea9..d49657a 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -466,6 +466,19 @@ static void reset_pmcr(struct kvm_vcpu *vcpu, const struct 
sys_reg_desc *r)
vcpu_sysreg_write(vcpu, r, val);
 }
 
+static void reset_pmceid(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
+{
+   u64 pmceid;
+
+   if (r->reg == PMCEID0_EL0 || r->reg == c9_PMCEID0)
+   asm volatile("mrs %0, pmceid0_el0\n" : "=r" (pmceid));
+   else
+   /* PMCEID1_EL0 or c9_PMCEID1 */
+   asm volatile("mrs %0, pmceid1_el0\n" : "=r" (pmceid));
+
+   vcpu_sysreg_write(vcpu, r, pmceid);
+}
+
 /* PMU registers accessor. */
 static bool access_pmu_regs(struct kvm_vcpu *vcpu,
const struct sys_reg_params *p,
@@ -483,6 +496,9 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
vcpu_sys_reg(vcpu, r->reg) = val;
break;
}
+   case PMCEID0_EL0:
+   case PMCEID1_EL0:
+   return ignore_write(vcpu, p);
default:
vcpu_sys_reg(vcpu, r->reg) = *vcpu_reg(vcpu, p->Rt);
break;
@@ -703,10 +719,10 @@ static const struct sys_reg_desc sys_reg_descs[] = {
  access_pmu_regs, reset_unknown, PMSELR_EL0 },
/* PMCEID0_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
- trap_raz_wi },
+ access_pmu_regs, reset_pmceid, PMCEID0_EL0 },
/* PMCEID1_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b111),
- trap_raz_wi },
+ access_pmu_regs, reset_pmceid, PMCEID1_EL0 },
/* PMCCNTR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000),
  trap_raz_wi },
@@ -936,6 +952,9 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu,
vcpu_cp15(vcpu, r->reg) = val;
break;
}
+   case c9_PMCEID0:
+   case c9_PMCEID1:
+   return ignore_write(vcpu, p);
default:
vcpu_cp15(vcpu, r->reg) = *vcpu_reg(vcpu, p->Rt);
break;
@@ -982,8 +1001,10 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmu_cp15_regs,
  reset_unknown_cp15, c9_PMSELR },
-   { Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi },
-   { Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi },
+   { Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmu_cp15_regs,
+ reset_pmceid, c9_PMCEID0 },
+   { Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmu_cp15_regs,
+ reset_pmceid, c9_PMCEID1 },
{ Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(13), Op2( 1), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(13), Op2( 2), trap_raz_wi },
-- 
2.1.4

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[PATCH v3 14/20] KVM: ARM64: Add reset and access handlers for PMUSERENR register

[Shannon Zhao]

The reset value of PMUSERENR_EL0 is UNKNOWN, use reset_unknown. While
the reset value of PMUSERENR is zero, use reset_val_cp15 with zero for
its reset handler.

Add a helper for CP15 registers reset to specified value.

Signed-off-by: Shannon Zhao 
---
 arch/arm64/kvm/sys_regs.c | 5 +++--
 arch/arm64/kvm/sys_regs.h | 8 
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 6f76dc8..749e1e2 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -805,7 +805,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
  access_pmu_regs, reset_unknown, PMXEVCNTR_EL0 },
/* PMUSERENR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000),
- trap_raz_wi },
+ access_pmu_regs, reset_unknown, PMUSERENR_EL0 },
/* PMOVSSET_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011),
  access_pmu_regs, reset_unknown, PMOVSSET_EL0 },
@@ -1156,7 +1156,8 @@ static const struct sys_reg_desc cp15_regs[] = {
  reset_unknown_cp15, c9_PMXEVTYPER },
{ Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_cp15_regs,
  reset_unknown_cp15, c9_PMXEVCNTR },
-   { Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi },
+   { Op1( 0), CRn( 9), CRm(14), Op2( 0), access_pmu_cp15_regs,
+ reset_val_cp15,  c9_PMUSERENR, 0 },
{ Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pmu_cp15_regs,
  reset_unknown_cp15, c9_PMINTENSET },
{ Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pmu_cp15_regs,
diff --git a/arch/arm64/kvm/sys_regs.h b/arch/arm64/kvm/sys_regs.h
index 8afeff7..aba997d 100644
--- a/arch/arm64/kvm/sys_regs.h
+++ b/arch/arm64/kvm/sys_regs.h
@@ -125,6 +125,14 @@ static inline void reset_val(struct kvm_vcpu *vcpu, const 
struct sys_reg_desc *r
vcpu_sys_reg(vcpu, r->reg) = r->val;
 }
 
+static inline void reset_val_cp15(struct kvm_vcpu *vcpu,
+ const struct sys_reg_desc *r)
+{
+   BUG_ON(!r->reg);
+   BUG_ON(r->reg >= NR_SYS_REGS);
+   vcpu_cp15(vcpu, r->reg) = r->val;
+}
+
 static inline int cmp_sys_reg(const struct sys_reg_desc *i1,
  const struct sys_reg_desc *i2)
 {
-- 
2.1.4

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[PATCH v3 13/20] KVM: ARM64: Add reset and access handlers for PMOVSSET and PMOVSCLR register

[Shannon Zhao]

Since the reset value of PMOVSSET and PMOVSCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a new case to emulate writing
PMOVSSET or PMOVSCLR register.

Signed-off-by: Shannon Zhao 
---
 arch/arm64/kvm/sys_regs.c | 33 ++---
 1 file changed, 30 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index e52325c..6f76dc8 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -531,6 +531,18 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
break;
}
+   case PMOVSSET_EL0: {
+   val = *vcpu_reg(vcpu, p->Rt);
+   vcpu_sys_reg(vcpu, r->reg) |= val;
+   vcpu_sys_reg(vcpu, PMOVSCLR_EL0) |= val;
+   break;
+   }
+   case PMOVSCLR_EL0: {
+   val = *vcpu_reg(vcpu, p->Rt);
+   vcpu_sys_reg(vcpu, r->reg) &= ~val;
+   vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~val;
+   break;
+   }
case PMCR_EL0: {
/* Only update writeable bits of PMCR */
val = vcpu_sys_reg(vcpu, r->reg);
@@ -769,7 +781,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
  access_pmu_regs, reset_unknown, PMCNTENCLR_EL0 },
/* PMOVSCLR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011),
- trap_raz_wi },
+ access_pmu_regs, reset_unknown, PMOVSCLR_EL0 },
/* PMSWINC_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100),
  trap_raz_wi },
@@ -796,7 +808,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
  trap_raz_wi },
/* PMOVSSET_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b011),
- trap_raz_wi },
+ access_pmu_regs, reset_unknown, PMOVSSET_EL0 },
 
/* TPIDR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b), Op2(0b010),
@@ -1046,6 +1058,18 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu,
vcpu_cp15(vcpu, c9_PMINTENSET) &= ~val;
break;
}
+   case c9_PMOVSSET: {
+   val = *vcpu_reg(vcpu, p->Rt);
+   vcpu_cp15(vcpu, r->reg) |= val;
+   vcpu_cp15(vcpu, c9_PMOVSCLR) |= val;
+   break;
+   }
+   case c9_PMOVSCLR: {
+   val = *vcpu_reg(vcpu, p->Rt);
+   vcpu_cp15(vcpu, r->reg) &= ~val;
+   vcpu_cp15(vcpu, c9_PMOVSSET) &= ~val;
+   break;
+   }
case c9_PMCR: {
/* Only update writeable bits of PMCR */
val = vcpu_cp15(vcpu, r->reg);
@@ -1118,7 +1142,8 @@ static const struct sys_reg_desc cp15_regs[] = {
  reset_unknown_cp15, c9_PMCNTENSET },
{ Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmu_cp15_regs,
  reset_unknown_cp15, c9_PMCNTENCLR },
-   { Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
+   { Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmu_cp15_regs,
+ reset_unknown_cp15, c9_PMOVSCLR },
{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmu_cp15_regs,
  reset_unknown_cp15, c9_PMSELR },
{ Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmu_cp15_regs,
@@ -1136,6 +1161,8 @@ static const struct sys_reg_desc cp15_regs[] = {
  reset_unknown_cp15, c9_PMINTENSET },
{ Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pmu_cp15_regs,
  reset_unknown_cp15, c9_PMINTENCLR },
+   { Op1( 0), CRn( 9), CRm(14), Op2( 3), access_pmu_cp15_regs,
+ reset_unknown_cp15, c9_PMOVSSET },
 
{ Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
{ Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
-- 
2.1.4

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[PATCH v3 11/20] KVM: ARM64: Add reset and access handlers for PMCNTENSET and PMCNTENCLR register

[Shannon Zhao]

Since the reset value of PMCNTENSET and PMCNTENCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a new case to emulate writing
PMCNTENSET or PMCNTENCLR register.

When writing to PMCNTENSET, call perf_event_enable to enable the perf
event. When writing to PMCNTENCLR, call perf_event_disable to disable
the perf event.

Signed-off-by: Shannon Zhao 
---
 arch/arm64/kvm/sys_regs.c | 46 +
 include/kvm/arm_pmu.h |  4 
 virt/kvm/arm/pmu.c| 48 +++
 3 files changed, 94 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index c38c2de..98da5a2 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -501,6 +501,24 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
   val);
break;
}
+   case PMCNTENSET_EL0: {
+   val = *vcpu_reg(vcpu, p->Rt);
+   kvm_pmu_enable_counter(vcpu, val);
+   /*Value 1 of PMCNTENSET_EL0 and PMCNTENCLR_EL0 means
+* corresponding counter enabled */
+   vcpu_sys_reg(vcpu, r->reg) |= val;
+   vcpu_sys_reg(vcpu, PMCNTENCLR_EL0) |= val;
+   break;
+   }
+   case PMCNTENCLR_EL0: {
+   val = *vcpu_reg(vcpu, p->Rt);
+   kvm_pmu_disable_counter(vcpu, val);
+   /*Value 0 of PMCNTENSET_EL0 and PMCNTENCLR_EL0 means
+* corresponding counter disabled */
+   vcpu_sys_reg(vcpu, r->reg) &= ~val;
+   vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
+   break;
+   }
case PMCR_EL0: {
/* Only update writeable bits of PMCR */
val = vcpu_sys_reg(vcpu, r->reg);
@@ -733,10 +751,10 @@ static const struct sys_reg_desc sys_reg_descs[] = {
  access_pmu_regs, reset_pmcr, PMCR_EL0, },
/* PMCNTENSET_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001),
- trap_raz_wi },
+ access_pmu_regs, reset_unknown, PMCNTENSET_EL0 },
/* PMCNTENCLR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b010),
- trap_raz_wi },
+ access_pmu_regs, reset_unknown, PMCNTENCLR_EL0 },
/* PMOVSCLR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b011),
  trap_raz_wi },
@@ -986,6 +1004,24 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu,
   val);
break;
}
+   case c9_PMCNTENSET: {
+   val = *vcpu_reg(vcpu, p->Rt);
+   kvm_pmu_enable_counter(vcpu, val);
+   /*Value 1 of PMCNTENSET_EL0 and PMCNTENCLR_EL0 means
+* corresponding counter enabled */
+   vcpu_cp15(vcpu, r->reg) |= val;
+   vcpu_cp15(vcpu, c9_PMCNTENCLR) |= val;
+   break;
+   }
+   case c9_PMCNTENCLR: {
+   val = *vcpu_reg(vcpu, p->Rt);
+   kvm_pmu_disable_counter(vcpu, val);
+   /*Value 0 of PMCNTENSET_EL0 and PMCNTENCLR_EL0 means
+* corresponding counter disabled */
+   vcpu_cp15(vcpu, r->reg) &= ~val;
+   vcpu_cp15(vcpu, c9_PMCNTENSET) &= ~val;
+   break;
+   }
case c9_PMCR: {
/* Only update writeable bits of PMCR */
val = vcpu_cp15(vcpu, r->reg);
@@ -1054,8 +1090,10 @@ static const struct sys_reg_desc cp15_regs[] = {
/* PMU */
{ Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmu_cp15_regs,
  reset_pmcr, c9_PMCR },
-   { Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi },
-   { Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
+   { Op1( 0), CRn( 9), CRm(12), Op2( 1), access_pmu_cp15_regs,
+ reset_unknown_cp15, c9_PMCNTENSET },
+   { Op1( 0), CRn( 9), CRm(12), Op2( 2), access_pmu_cp15_regs,
+ reset_unknown_cp15, c9_PMCNTENCLR },
{ Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmu_cp15_regs,
  reset_unknown_cp15, c9_PMSELR },
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index b48cdc6..9b4ee5e 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -39,6 +39,8 @@ struct kvm_pmu {
 
 #ifdef CONFIG_KVM_ARM_PMU
 unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx);
+void kvm_pmu_disable_counter(struct kvm_vcpu 

Re: [PATCH] KVM: PPC: e500: Emulate TMCFG0 TMRN register

[Scott Wood]

On Thu, 2015-09-24 at 09:56 +0300, Laurentiu Tudor wrote:
> Emulate TMCFG0 TMRN register exposing one HW thread per vcpu.
> 
> Signed-off-by: Mihai Caraman 
> [laurentiu.tu...@freescale.com: rebased on latest kernel,
>  use define instead of hardcoded value]
> Signed-off-by: Laurentiu Tudor 
> ---
> Needs this patch: https://patchwork.ozlabs.org/patch/521752/
> 
>  arch/powerpc/include/asm/disassemble.h |  5 +
>  arch/powerpc/kvm/e500_emulate.c| 11 +++
>  2 files changed, 16 insertions(+)

KVM patches should be sent to k...@vger.kernel.org in addition to kvm-
p...@vger.kernel.org.

> @@ -165,6 +167,15 @@ int kvmppc_core_emulate_op_e500(struct kvm_run *run, 
> struct kvm_vcpu *vcpu,
>   emulated = kvmppc_e500_emul_tlbivax(vcpu, ea);
>   break;
>  
> + case XOP_MFTMR:
> + /* Expose one thread per vcpu */
> + if (get_tmrn(inst) == TMRN_TMCFG0)
> + kvmppc_set_gpr(vcpu, rt,
> +1 | (1 << 
> TMRN_TMCFG0_NATHRD_SHIFT));
> + else
> + emulated = EMULATE_FAIL;
> + break;

Line length.  Please move the implementation into its own function like all 
the others.

-Scott

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[PATCH v3 04/20] KVM: ARM64: Add reset and access handlers for PMCR_EL0 register

[Shannon Zhao]

Add reset handler which gets host value of PMCR_EL0 and make writable
bits architecturally UNKNOWN. Add a common access handler for PMU
registers which emulates writing and reading register and add emulation
for PMCR.

Signed-off-by: Shannon Zhao 
---
 arch/arm64/kvm/sys_regs.c | 81 +--
 1 file changed, 79 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index b41607d..60c0842 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -33,6 +33,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include 
 
@@ -446,6 +447,53 @@ static void reset_mpidr(struct kvm_vcpu *vcpu, const 
struct sys_reg_desc *r)
vcpu_sys_reg(vcpu, MPIDR_EL1) = (1ULL << 31) | mpidr;
 }
 
+static void vcpu_sysreg_write(struct kvm_vcpu *vcpu,
+ const struct sys_reg_desc *r, u64 val)
+{
+   if (!vcpu_mode_is_32bit(vcpu))
+   vcpu_sys_reg(vcpu, r->reg) = val;
+   else
+   vcpu_cp15(vcpu, r->reg) = lower_32_bits(val);
+}
+
+static void reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
+{
+   u64 pmcr, val;
+
+   asm volatile("mrs %0, pmcr_el0\n" : "=r" (pmcr));
+   /* Writable bits of PMCR_EL0 (ARMV8_PMCR_MASK) is reset to UNKNOWN*/
+   val = (pmcr & ~ARMV8_PMCR_MASK) | (ARMV8_PMCR_MASK & 0xdecafbad);
+   vcpu_sysreg_write(vcpu, r, val);
+}
+
+/* PMU registers accessor. */
+static bool access_pmu_regs(struct kvm_vcpu *vcpu,
+   const struct sys_reg_params *p,
+   const struct sys_reg_desc *r)
+{
+   unsigned long val;
+
+   if (p->is_write) {
+   switch (r->reg) {
+   case PMCR_EL0: {
+   /* Only update writeable bits of PMCR */
+   val = vcpu_sys_reg(vcpu, r->reg);
+   val &= ~ARMV8_PMCR_MASK;
+   val |= *vcpu_reg(vcpu, p->Rt) & ARMV8_PMCR_MASK;
+   vcpu_sys_reg(vcpu, r->reg) = val;
+   break;
+   }
+   default:
+   vcpu_sys_reg(vcpu, r->reg) = *vcpu_reg(vcpu, p->Rt);
+   break;
+   }
+   } else {
+   *vcpu_reg(vcpu, p->Rt) = vcpu_sys_reg(vcpu, r->reg);
+   }
+
+   return true;
+}
+
 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \
/* DBGBVRn_EL1 */   \
@@ -637,7 +685,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
 
/* PMCR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b000),
- trap_raz_wi },
+ access_pmu_regs, reset_pmcr, PMCR_EL0, },
/* PMCNTENSET_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b001),
  trap_raz_wi },
@@ -871,6 +919,34 @@ static const struct sys_reg_desc cp14_64_regs[] = {
{ Op1( 0), CRm( 2), .access = trap_raz_wi },
 };
 
+/* PMU CP15 registers accessor. */
+static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu,
+const struct sys_reg_params *p,
+const struct sys_reg_desc *r)
+{
+   unsigned long val;
+
+   if (p->is_write) {
+   switch (r->reg) {
+   case c9_PMCR: {
+   /* Only update writeable bits of PMCR */
+   val = vcpu_cp15(vcpu, r->reg);
+   val &= ~ARMV8_PMCR_MASK;
+   val |= *vcpu_reg(vcpu, p->Rt) & ARMV8_PMCR_MASK;
+   vcpu_cp15(vcpu, r->reg) = val;
+   break;
+   }
+   default:
+   vcpu_cp15(vcpu, r->reg) = *vcpu_reg(vcpu, p->Rt);
+   break;
+   }
+   } else {
+   *vcpu_reg(vcpu, p->Rt) = vcpu_cp15(vcpu, r->reg);
+   }
+
+   return true;
+}
+
 /*
  * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
  * depending on the way they are accessed (as a 32bit or a 64bit
@@ -899,7 +975,8 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
 
/* PMU */
-   { Op1( 0), CRn( 9), CRm(12), Op2( 0), trap_raz_wi },
+   { Op1( 0), CRn( 9), CRm(12), Op2( 0), access_pmu_cp15_regs,
+ reset_pmcr, c9_PMCR },
{ Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
-- 
2.1.4

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[PATCH v3 03/20] KVM: ARM64: Add offset defines for PMU registers

[Shannon Zhao]

We are about to trap and emulate acccesses to each PMU register
individually. This adds the context offsets for the AArch64 PMU
registers and their AArch32 counterparts.

Signed-off-by: Shannon Zhao 
---
 arch/arm64/include/asm/kvm_asm.h | 59 +++-
 1 file changed, 52 insertions(+), 7 deletions(-)

diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h
index 67fa0de..0a4dfcc 100644
--- a/arch/arm64/include/asm/kvm_asm.h
+++ b/arch/arm64/include/asm/kvm_asm.h
@@ -48,14 +48,36 @@
 #define MDSCR_EL1  22  /* Monitor Debug System Control Register */
 #define MDCCINT_EL123  /* Monitor Debug Comms Channel Interrupt Enable 
Reg */
 
+/* Performance Monitors Registers */
+#define PMCR_EL0   24  /* Control Register */
+#define PMOVSSET_EL0   25  /* Overflow Flag Status Set Register */
+#define PMOVSCLR_EL0   26  /* Overflow Flag Status Clear Register */
+#define PMSELR_EL0 27  /* Event Counter Selection Register */
+#define PMCEID0_EL028  /* Common Event Identification Register 0 */
+#define PMCEID1_EL029  /* Common Event Identification Register 1 */
+#define PMEVCNTR0_EL0  30  /* Event Counter Register (0-30) */
+#define PMEVCNTR30_EL0 60
+#define PMCCNTR_EL061  /* Cycle Counter Register */
+#define PMEVTYPER0_EL0 62  /* Event Type Register (0-30) */
+#define PMEVTYPER30_EL092
+#define PMCCFILTR_EL0  93  /* Cycle Count Filter Register */
+#define PMXEVCNTR_EL0  94  /* Selected Event Count Register */
+#define PMXEVTYPER_EL0 95  /* Selected Event Type Register */
+#define PMCNTENSET_EL0 96  /* Count Enable Set Register */
+#define PMCNTENCLR_EL0 97  /* Count Enable Clear Register */
+#define PMINTENSET_EL1 98  /* Interrupt Enable Set Register */
+#define PMINTENCLR_EL1 99  /* Interrupt Enable Clear Register */
+#define PMUSERENR_EL0  100 /* User Enable Register */
+#define PMSWINC_EL0101 /* Software Increment Register */
+
 /* 32bit specific registers. Keep them at the end of the range */
-#defineDACR32_EL2  24  /* Domain Access Control Register */
-#defineIFSR32_EL2  25  /* Instruction Fault Status Register */
-#defineFPEXC32_EL2 26  /* Floating-Point Exception Control 
Register */
-#defineDBGVCR32_EL227  /* Debug Vector Catch Register */
-#defineTEECR32_EL1 28  /* ThumbEE Configuration Register */
-#defineTEEHBR32_EL129  /* ThumbEE Handler Base Register */
-#defineNR_SYS_REGS 30
+#defineDACR32_EL2  102 /* Domain Access Control Register */
+#defineIFSR32_EL2  103 /* Instruction Fault Status Register */
+#defineFPEXC32_EL2 104 /* Floating-Point Exception Control 
Register */
+#defineDBGVCR32_EL2105 /* Debug Vector Catch Register */
+#defineTEECR32_EL1 106 /* ThumbEE Configuration Register */
+#defineTEEHBR32_EL1107 /* ThumbEE Handler Base Register */
+#defineNR_SYS_REGS 108
 
 /* 32bit mapping */
 #define c0_MPIDR   (MPIDR_EL1 * 2) /* MultiProcessor ID Register */
@@ -77,6 +99,24 @@
 #define c6_IFAR(c6_DFAR + 1)   /* Instruction Fault Address 
Register */
 #define c7_PAR (PAR_EL1 * 2)   /* Physical Address Register */
 #define c7_PAR_high(c7_PAR + 1)/* PAR top 32 bits */
+
+/* Performance Monitors*/
+#define c9_PMCR(PMCR_EL0 * 2)
+#define c9_PMOVSSET(PMOVSSET_EL0 * 2)
+#define c9_PMOVSCLR(PMOVSCLR_EL0 * 2)
+#define c9_PMCCNTR (PMCCNTR_EL0 * 2)
+#define c9_PMSELR  (PMSELR_EL0 * 2)
+#define c9_PMCEID0 (PMCEID0_EL0 * 2)
+#define c9_PMCEID1 (PMCEID1_EL0 * 2)
+#define c9_PMXEVCNTR   (PMXEVCNTR_EL0 * 2)
+#define c9_PMXEVTYPER  (PMXEVTYPER_EL0 * 2)
+#define c9_PMCNTENSET  (PMCNTENSET_EL0 * 2)
+#define c9_PMCNTENCLR  (PMCNTENCLR_EL0 * 2)
+#define c9_PMINTENSET  (PMINTENSET_EL1 * 2)
+#define c9_PMINTENCLR  (PMINTENCLR_EL1 * 2)
+#define c9_PMUSERENR   (PMUSERENR_EL0 * 2)
+#define c9_PMSWINC (PMSWINC_EL0 * 2)
+
 #define c10_PRRR   (MAIR_EL1 * 2)  /* Primary Region Remap Register */
 #define c10_NMRR   (c10_PRRR + 1)  /* Normal Memory Remap Register */
 #define c12_VBAR   (VBAR_EL1 * 2)  /* Vector Base Address Register */
@@ -88,6 +128,11 @@
 #define c10_AMAIR1 (c10_AMAIR0 + 1)/* Aux Memory Attr Indirection Reg */
 #define c14_CNTKCTL(CNTKCTL_EL1 * 2) /* Timer Control Register (PL1) */
 
+/* Performance Monitors*/
+#define c14_PMEVCNTR0  (PMEVCNTR0_EL0 * 2)
+#define c14_PMEVTYPER0 (PMEVTYPER0_EL0 * 2)
+#define c14_PMCCFILTR  (PMCCFILTR_EL0 * 2)
+
 #define cp14_DBGDSCRext(MDSCR_EL1 * 2)
 #define cp14_DBGBCR0   (DBGBCR0_EL1 * 2)
 #define cp14_DBGBVR0   (DBGBVR0_EL1 * 2)
-- 
2.1.4

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More 

[PATCH v3 05/20] KVM: ARM64: Add reset and access handlers for PMSELR register

[Shannon Zhao]

Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for
its reset handler. As it doesn't need to deal with the acsessing action
specially, it uses default case to emulate writing and reading PMSELR
register.

Add a helper for CP15 registers reset to UNKNOWN.

Signed-off-by: Shannon Zhao 
---
 arch/arm64/kvm/sys_regs.c | 5 +++--
 arch/arm64/kvm/sys_regs.h | 8 
 2 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 60c0842..f73aea9 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -700,7 +700,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
  trap_raz_wi },
/* PMSELR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
- trap_raz_wi },
+ access_pmu_regs, reset_unknown, PMSELR_EL0 },
/* PMCEID0_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b110),
  trap_raz_wi },
@@ -980,7 +980,8 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn( 9), CRm(12), Op2( 1), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 2), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 3), trap_raz_wi },
-   { Op1( 0), CRn( 9), CRm(12), Op2( 5), trap_raz_wi },
+   { Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmu_cp15_regs,
+ reset_unknown_cp15, c9_PMSELR },
{ Op1( 0), CRn( 9), CRm(12), Op2( 6), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(12), Op2( 7), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
diff --git a/arch/arm64/kvm/sys_regs.h b/arch/arm64/kvm/sys_regs.h
index eaa324e..8afeff7 100644
--- a/arch/arm64/kvm/sys_regs.h
+++ b/arch/arm64/kvm/sys_regs.h
@@ -110,6 +110,14 @@ static inline void reset_unknown(struct kvm_vcpu *vcpu,
vcpu_sys_reg(vcpu, r->reg) = 0x1de7ec7edbadc0deULL;
 }
 
+static inline void reset_unknown_cp15(struct kvm_vcpu *vcpu,
+ const struct sys_reg_desc *r)
+{
+   BUG_ON(!r->reg);
+   BUG_ON(r->reg >= NR_COPRO_REGS);
+   vcpu_cp15(vcpu, r->reg) = 0xdecafbad;
+}
+
 static inline void reset_val(struct kvm_vcpu *vcpu, const struct sys_reg_desc 
*r)
 {
BUG_ON(!r->reg);
-- 
2.1.4

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[PATCH v3 09/20] KVM: ARM64: Add reset and access handlers for PMXEVCNTR register

[Shannon Zhao]

Since the reset value of PMXEVCNTR is UNKNOWN, use reset_unknown for
its reset handler. Add access handler which emulates writing and reading
PMXEVCNTR register. When reading PMXEVCNTR, call perf_event_read_value
to get the count value of the perf event.

Signed-off-by: Shannon Zhao 
---
 arch/arm64/kvm/sys_regs.c | 41 +
 1 file changed, 37 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 605972e..e7f6058 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -488,6 +488,12 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
 
if (p->is_write) {
switch (r->reg) {
+   case PMXEVCNTR_EL0: {
+   val = PMEVCNTR0_EL0 + vcpu_sys_reg(vcpu, PMSELR_EL0);
+   vcpu_sys_reg(vcpu, val) =
+ *vcpu_reg(vcpu, p->Rt) & 0xUL;
+   break;
+   }
case PMXEVTYPER_EL0: {
val = vcpu_sys_reg(vcpu, PMSELR_EL0);
kvm_pmu_set_counter_event_type(vcpu,
@@ -511,7 +517,17 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
break;
}
} else {
-   *vcpu_reg(vcpu, p->Rt) = vcpu_sys_reg(vcpu, r->reg);
+   switch (r->reg) {
+   case PMXEVCNTR_EL0: {
+   val = kvm_pmu_get_counter_value(vcpu,
+   vcpu_sys_reg(vcpu, PMSELR_EL0));
+   *vcpu_reg(vcpu, p->Rt) = val;
+   break;
+   }
+   default:
+   *vcpu_reg(vcpu, p->Rt) = vcpu_sys_reg(vcpu, r->reg);
+   break;
+   }
}
 
return true;
@@ -738,7 +754,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
  access_pmu_regs, reset_unknown, PMXEVTYPER_EL0 },
/* PMXEVCNTR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
- trap_raz_wi },
+ access_pmu_regs, reset_unknown, PMXEVCNTR_EL0 },
/* PMUSERENR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1110), Op2(0b000),
  trap_raz_wi },
@@ -951,6 +967,12 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu,
 
if (p->is_write) {
switch (r->reg) {
+   case c9_PMXEVCNTR: {
+   val = c14_PMEVCNTR0 + vcpu_cp15(vcpu, c9_PMSELR);
+   vcpu_cp15(vcpu, val) =
+ *vcpu_reg(vcpu, p->Rt) & 0xUL;
+   break;
+   }
case c9_PMXEVTYPER: {
val = vcpu_cp15(vcpu, c9_PMSELR);
kvm_pmu_set_counter_event_type(vcpu,
@@ -974,7 +996,17 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu,
break;
}
} else {
-   *vcpu_reg(vcpu, p->Rt) = vcpu_cp15(vcpu, r->reg);
+   switch (r->reg) {
+   case c9_PMXEVCNTR: {
+   val = kvm_pmu_get_counter_value(vcpu,
+   vcpu_cp15(vcpu, c9_PMSELR));
+   *vcpu_reg(vcpu, p->Rt) = val;
+   break;
+   }
+   default:
+   *vcpu_reg(vcpu, p->Rt) = vcpu_cp15(vcpu, r->reg);
+   break;
+   }
}
 
return true;
@@ -1022,7 +1054,8 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_cp15_regs,
  reset_unknown_cp15, c9_PMXEVTYPER },
-   { Op1( 0), CRn( 9), CRm(13), Op2( 2), trap_raz_wi },
+   { Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_cp15_regs,
+ reset_unknown_cp15, c9_PMXEVCNTR },
{ Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(14), Op2( 1), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(14), Op2( 2), trap_raz_wi },
-- 
2.1.4

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[PATCH v3 08/20] KVM: ARM64: Add reset and access handlers for PMXEVTYPER register

[Shannon Zhao]

Since the reset value of PMXEVTYPER is UNKNOWN, use reset_unknown or
reset_unknown_cp15 for its reset handler. Add access handler which
emulates writing and reading PMXEVTYPER register. When writing to
PMXEVTYPER, call kvm_pmu_set_counter_event_type to create a perf_event
for the selected event type.

Signed-off-by: Shannon Zhao 
---
 arch/arm64/kvm/sys_regs.c | 19 +--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index d49657a..605972e 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -488,6 +488,13 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
 
if (p->is_write) {
switch (r->reg) {
+   case PMXEVTYPER_EL0: {
+   val = vcpu_sys_reg(vcpu, PMSELR_EL0);
+   kvm_pmu_set_counter_event_type(vcpu,
+  *vcpu_reg(vcpu, p->Rt),
+  val);
+   break;
+   }
case PMCR_EL0: {
/* Only update writeable bits of PMCR */
val = vcpu_sys_reg(vcpu, r->reg);
@@ -728,7 +735,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
  trap_raz_wi },
/* PMXEVTYPER_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001),
- trap_raz_wi },
+ access_pmu_regs, reset_unknown, PMXEVTYPER_EL0 },
/* PMXEVCNTR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b010),
  trap_raz_wi },
@@ -944,6 +951,13 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu,
 
if (p->is_write) {
switch (r->reg) {
+   case c9_PMXEVTYPER: {
+   val = vcpu_cp15(vcpu, c9_PMSELR);
+   kvm_pmu_set_counter_event_type(vcpu,
+  *vcpu_reg(vcpu, p->Rt),
+  val);
+   break;
+   }
case c9_PMCR: {
/* Only update writeable bits of PMCR */
val = vcpu_cp15(vcpu, r->reg);
@@ -1006,7 +1020,8 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn( 9), CRm(12), Op2( 7), access_pmu_cp15_regs,
  reset_pmceid, c9_PMCEID1 },
{ Op1( 0), CRn( 9), CRm(13), Op2( 0), trap_raz_wi },
-   { Op1( 0), CRn( 9), CRm(13), Op2( 1), trap_raz_wi },
+   { Op1( 0), CRn( 9), CRm(13), Op2( 1), access_pmu_cp15_regs,
+ reset_unknown_cp15, c9_PMXEVTYPER },
{ Op1( 0), CRn( 9), CRm(13), Op2( 2), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi },
{ Op1( 0), CRn( 9), CRm(14), Op2( 1), trap_raz_wi },
-- 
2.1.4

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[PATCH v3 12/20] KVM: ARM64: Add reset and access handlers for PMINTENSET and PMINTENCLR register

[Shannon Zhao]

Since the reset value of PMINTENSET and PMINTENCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a new case to emulate writing
PMINTENSET or PMINTENCLR register.

Signed-off-by: Shannon Zhao 
---
 arch/arm64/kvm/sys_regs.c | 34 ++
 1 file changed, 30 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 98da5a2..e52325c 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -519,6 +519,18 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
break;
}
+   case PMINTENSET_EL1: {
+   val = *vcpu_reg(vcpu, p->Rt);
+   vcpu_sys_reg(vcpu, r->reg) |= val;
+   vcpu_sys_reg(vcpu, PMINTENCLR_EL1) |= val;
+   break;
+   }
+   case PMINTENCLR_EL1: {
+   val = *vcpu_reg(vcpu, p->Rt);
+   vcpu_sys_reg(vcpu, r->reg) &= ~val;
+   vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
+   break;
+   }
case PMCR_EL0: {
/* Only update writeable bits of PMCR */
val = vcpu_sys_reg(vcpu, r->reg);
@@ -708,10 +720,10 @@ static const struct sys_reg_desc sys_reg_descs[] = {
 
/* PMINTENSET_EL1 */
{ Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b001),
- trap_raz_wi },
+ access_pmu_regs, reset_unknown, PMINTENSET_EL1 },
/* PMINTENCLR_EL1 */
{ Op0(0b11), Op1(0b000), CRn(0b1001), CRm(0b1110), Op2(0b010),
- trap_raz_wi },
+ access_pmu_regs, reset_unknown, PMINTENCLR_EL1 },
 
/* MAIR_EL1 */
{ Op0(0b11), Op1(0b000), CRn(0b1010), CRm(0b0010), Op2(0b000),
@@ -1022,6 +1034,18 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu,
vcpu_cp15(vcpu, c9_PMCNTENSET) &= ~val;
break;
}
+   case c9_PMINTENSET: {
+   val = *vcpu_reg(vcpu, p->Rt);
+   vcpu_cp15(vcpu, r->reg) |= val;
+   vcpu_cp15(vcpu, c9_PMINTENCLR) |= val;
+   break;
+   }
+   case c9_PMINTENCLR: {
+   val = *vcpu_reg(vcpu, p->Rt);
+   vcpu_cp15(vcpu, r->reg) &= ~val;
+   vcpu_cp15(vcpu, c9_PMINTENSET) &= ~val;
+   break;
+   }
case c9_PMCR: {
/* Only update writeable bits of PMCR */
val = vcpu_cp15(vcpu, r->reg);
@@ -1108,8 +1132,10 @@ static const struct sys_reg_desc cp15_regs[] = {
{ Op1( 0), CRn( 9), CRm(13), Op2( 2), access_pmu_cp15_regs,
  reset_unknown_cp15, c9_PMXEVCNTR },
{ Op1( 0), CRn( 9), CRm(14), Op2( 0), trap_raz_wi },
-   { Op1( 0), CRn( 9), CRm(14), Op2( 1), trap_raz_wi },
-   { Op1( 0), CRn( 9), CRm(14), Op2( 2), trap_raz_wi },
+   { Op1( 0), CRn( 9), CRm(14), Op2( 1), access_pmu_cp15_regs,
+ reset_unknown_cp15, c9_PMINTENSET },
+   { Op1( 0), CRn( 9), CRm(14), Op2( 2), access_pmu_cp15_regs,
+ reset_unknown_cp15, c9_PMINTENCLR },
 
{ Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, c10_PRRR },
{ Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, c10_NMRR },
-- 
2.1.4

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[PATCH v3 20/20] KVM: ARM64: Add a new kvm ARM PMU device

[Shannon Zhao]

Add a new kvm device type KVM_DEV_TYPE_ARM_PMU_V3 for ARM PMU. Implement
the kvm_device_ops for it.

Signed-off-by: Shannon Zhao 
---
 Documentation/virtual/kvm/devices/arm-pmu.txt | 15 +
 arch/arm64/include/uapi/asm/kvm.h |  3 +
 include/linux/kvm_host.h  |  1 +
 include/uapi/linux/kvm.h  |  2 +
 virt/kvm/arm/pmu.c| 88 +++
 virt/kvm/kvm_main.c   |  4 ++
 6 files changed, 113 insertions(+)
 create mode 100644 Documentation/virtual/kvm/devices/arm-pmu.txt

diff --git a/Documentation/virtual/kvm/devices/arm-pmu.txt 
b/Documentation/virtual/kvm/devices/arm-pmu.txt
new file mode 100644
index 000..49481c4
--- /dev/null
+++ b/Documentation/virtual/kvm/devices/arm-pmu.txt
@@ -0,0 +1,15 @@
+ARM Virtual Performance Monitor Unit (vPMU)
+===
+
+Device types supported:
+  KVM_DEV_TYPE_ARM_PMU_V3 ARM Performance Monitor Unit v3
+
+Instantiate one PMU instance for per VCPU through this API.
+
+Groups:
+  KVM_DEV_ARM_PMU_GRP_IRQ
+  Attributes:
+A value describing the interrupt number of PMU overflow interrupt.
+
+  Errors:
+-EINVAL: Value set is out of the expected range
diff --git a/arch/arm64/include/uapi/asm/kvm.h 
b/arch/arm64/include/uapi/asm/kvm.h
index 0cd7b59..1309a93 100644
--- a/arch/arm64/include/uapi/asm/kvm.h
+++ b/arch/arm64/include/uapi/asm/kvm.h
@@ -204,6 +204,9 @@ struct kvm_arch_memory_slot {
 #define KVM_DEV_ARM_VGIC_GRP_CTRL  4
 #define   KVM_DEV_ARM_VGIC_CTRL_INIT   0
 
+/* Device Control API: ARM PMU */
+#define KVM_DEV_ARM_PMU_GRP_IRQ0
+
 /* KVM_IRQ_LINE irq field index values */
 #define KVM_ARM_IRQ_TYPE_SHIFT 24
 #define KVM_ARM_IRQ_TYPE_MASK  0xff
diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h
index 1bef9e2..f6be696 100644
--- a/include/linux/kvm_host.h
+++ b/include/linux/kvm_host.h
@@ -1122,6 +1122,7 @@ extern struct kvm_device_ops kvm_mpic_ops;
 extern struct kvm_device_ops kvm_xics_ops;
 extern struct kvm_device_ops kvm_arm_vgic_v2_ops;
 extern struct kvm_device_ops kvm_arm_vgic_v3_ops;
+extern struct kvm_device_ops kvm_arm_pmu_ops;
 
 #ifdef CONFIG_HAVE_KVM_CPU_RELAX_INTERCEPT
 
diff --git a/include/uapi/linux/kvm.h b/include/uapi/linux/kvm.h
index a9256f0..f41e6b6 100644
--- a/include/uapi/linux/kvm.h
+++ b/include/uapi/linux/kvm.h
@@ -1025,6 +1025,8 @@ enum kvm_device_type {
 #define KVM_DEV_TYPE_FLIC  KVM_DEV_TYPE_FLIC
KVM_DEV_TYPE_ARM_VGIC_V3,
 #define KVM_DEV_TYPE_ARM_VGIC_V3   KVM_DEV_TYPE_ARM_VGIC_V3
+   KVM_DEV_TYPE_ARM_PMU_V3,
+#defineKVM_DEV_TYPE_ARM_PMU_V3 KVM_DEV_TYPE_ARM_PMU_V3
KVM_DEV_TYPE_MAX,
 };
 
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index 00ef0b4..0aa4bc1 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -19,6 +19,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -324,3 +325,90 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, 
u32 data,
}
pmc->perf_event = event;
 }
+
+static int kvm_arm_pmu_set_irq(struct kvm *kvm, int irq)
+{
+   int j;
+   struct kvm_vcpu *vcpu;
+
+   kvm_for_each_vcpu(j, vcpu, kvm) {
+   struct kvm_pmu *pmu = >arch.pmu;
+
+   kvm_debug("Set kvm ARM PMU irq: %d\n", irq);
+   pmu->irq_num = irq;
+   }
+
+   return 0;
+}
+
+static int kvm_arm_pmu_create(struct kvm_device *dev, u32 type)
+{
+   int i, j;
+   struct kvm_vcpu *vcpu;
+   struct kvm *kvm = dev->kvm;
+
+   kvm_for_each_vcpu(j, vcpu, kvm) {
+   struct kvm_pmu *pmu = >arch.pmu;
+
+   memset(pmu, 0, sizeof(*pmu));
+   for (i = 0; i < ARMV8_MAX_COUNTERS; i++) {
+   pmu->pmc[i].idx = i;
+   pmu->pmc[i].vcpu = vcpu;
+   }
+   pmu->irq_num = -1;
+   }
+
+   return 0;
+}
+
+static void kvm_arm_pmu_destroy(struct kvm_device *dev)
+{
+   kfree(dev);
+}
+
+static int kvm_arm_pmu_set_attr(struct kvm_device *dev,
+   struct kvm_device_attr *attr)
+{
+   switch (attr->group) {
+   case KVM_DEV_ARM_PMU_GRP_IRQ: {
+   int __user *uaddr = (int __user *)(long)attr->addr;
+   int reg;
+
+   if (get_user(reg, uaddr))
+   return -EFAULT;
+
+   if (reg < VGIC_NR_SGIS || reg > dev->kvm->arch.vgic.nr_irqs)
+   return -EINVAL;
+
+   return kvm_arm_pmu_set_irq(dev->kvm, reg);
+   }
+   }
+
+   return -ENXIO;
+}
+
+static int kvm_arm_pmu_get_attr(struct kvm_device *dev,
+   struct kvm_device_attr *attr)
+{
+   return 0;
+}
+
+static int kvm_arm_pmu_has_attr(struct kvm_device *dev,
+   struct kvm_device_attr *attr)
+{
+   

[PATCH v3 15/20] KVM: ARM64: Add reset and access handlers for PMSWINC register

[Shannon Zhao]

Add access handler which emulates writing and reading PMSWINC
register and add support for creating software increment event.

Signed-off-by: Shannon Zhao 
---
 arch/arm64/kvm/sys_regs.c | 18 +-
 include/kvm/arm_pmu.h |  2 ++
 virt/kvm/arm/pmu.c| 33 +
 3 files changed, 52 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 749e1e2..dd790c7 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -543,6 +543,11 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~val;
break;
}
+   case PMSWINC_EL0: {
+   val = *vcpu_reg(vcpu, p->Rt);
+   kvm_pmu_software_increment(vcpu, val);
+   break;
+   }
case PMCR_EL0: {
/* Only update writeable bits of PMCR */
val = vcpu_sys_reg(vcpu, r->reg);
@@ -572,6 +577,8 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
*vcpu_reg(vcpu, p->Rt) = val;
break;
}
+   case PMSWINC_EL0:
+   return read_zero(vcpu, p);
default:
*vcpu_reg(vcpu, p->Rt) = vcpu_sys_reg(vcpu, r->reg);
break;
@@ -784,7 +791,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
  access_pmu_regs, reset_unknown, PMOVSCLR_EL0 },
/* PMSWINC_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b100),
- trap_raz_wi },
+ access_pmu_regs, reset_unknown, PMSWINC_EL0 },
/* PMSELR_EL0 */
{ Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1100), Op2(0b101),
  access_pmu_regs, reset_unknown, PMSELR_EL0 },
@@ -1070,6 +1077,11 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu,
vcpu_cp15(vcpu, c9_PMOVSSET) &= ~val;
break;
}
+   case c9_PMSWINC: {
+   val = *vcpu_reg(vcpu, p->Rt);
+   kvm_pmu_software_increment(vcpu, val);
+   break;
+   }
case c9_PMCR: {
/* Only update writeable bits of PMCR */
val = vcpu_cp15(vcpu, r->reg);
@@ -1099,6 +,8 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu,
*vcpu_reg(vcpu, p->Rt) = val;
break;
}
+   case c9_PMSWINC:
+   return read_zero(vcpu, p);
default:
*vcpu_reg(vcpu, p->Rt) = vcpu_cp15(vcpu, r->reg);
break;
@@ -1144,6 +1158,8 @@ static const struct sys_reg_desc cp15_regs[] = {
  reset_unknown_cp15, c9_PMCNTENCLR },
{ Op1( 0), CRn( 9), CRm(12), Op2( 3), access_pmu_cp15_regs,
  reset_unknown_cp15, c9_PMOVSCLR },
+   { Op1( 0), CRn( 9), CRm(12), Op2( 4), access_pmu_cp15_regs,
+ reset_unknown_cp15, c9_PMSWINC },
{ Op1( 0), CRn( 9), CRm(12), Op2( 5), access_pmu_cp15_regs,
  reset_unknown_cp15, c9_PMSELR },
{ Op1( 0), CRn( 9), CRm(12), Op2( 6), access_pmu_cp15_regs,
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index 9b4ee5e..9293133 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -41,6 +41,7 @@ struct kvm_pmu {
 unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx);
 void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val);
 void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u32 val);
+void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u32 val);
 void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data,
u32 select_idx);
 #else
@@ -50,6 +51,7 @@ unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu 
*vcpu, u32 select_idx)
 }
 void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val) {}
 void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u32 val) {}
+void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u32 val) {}
 void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data,
u32 select_idx) {}
 #endif
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index 46145d1..18637c9 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -134,6 +134,35 @@ void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 
val)
 }
 
 /**
+ * kvm_pmu_software_increment - do software increment
+ * @vcpu: The vcpu pointer
+ * @val: the value guest writes to PMSWINC register
+ */
+void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u32 val)
+{
+   int i;
+   u32 type, enable;
+
+   for (i = 0; i < 32; i++) {
+   if ((val >> i) & 0x1) {
+   

[PATCH v3 19/20] KVM: ARM64: Free perf event of PMU when destroying vcpu

[Shannon Zhao]

When KVM frees VCPU, it needs to free the perf_event of PMU.

Signed-off-by: Shannon Zhao 
---
 arch/arm/kvm/arm.c|  1 +
 include/kvm/arm_pmu.h |  2 ++
 virt/kvm/arm/pmu.c| 21 +
 3 files changed, 24 insertions(+)

diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index 3fca263..4d24498 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -259,6 +259,7 @@ void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
kvm_mmu_free_memory_caches(vcpu);
kvm_timer_vcpu_terminate(vcpu);
kvm_vgic_vcpu_destroy(vcpu);
+   kvm_pmu_vcpu_destroy(vcpu);
kmem_cache_free(kvm_vcpu_cache, vcpu);
 }
 
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index 8dacfd3..a32e630 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -39,6 +39,7 @@ struct kvm_pmu {
 
 #ifdef CONFIG_KVM_ARM_PMU
 void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu);
+void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu);
 void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu);
 unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx);
 void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val);
@@ -48,6 +49,7 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, 
u32 data,
u32 select_idx);
 #else
 void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu) {}
+void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu) {}
 void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu) {}
 unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx)
 {
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index faa2b76..00ef0b4 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -81,6 +81,27 @@ void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu)
 }
 
 /**
+ * kvm_pmu_vcpu_destroy - free perf event of PMU for cpu
+ * @vcpu: The vcpu pointer
+ *
+ */
+void kvm_pmu_vcpu_destroy(struct kvm_vcpu *vcpu)
+{
+   int i;
+   struct kvm_pmu *pmu = >arch.pmu;
+
+   for (i = 0; i < ARMV8_MAX_COUNTERS; i++) {
+   struct kvm_pmc *pmc = >pmc[i];
+
+   if (pmc->perf_event) {
+   perf_event_disable(pmc->perf_event);
+   perf_event_release_kernel(pmc->perf_event);
+   pmc->perf_event = NULL;
+   }
+   }
+}
+
+/**
  * kvm_pmu_sync_hwstate - sync pmu state for cpu
  * @vcpu: The vcpu pointer
  *
-- 
2.1.4

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[PATCH v3 16/20] KVM: ARM64: Add access handlers for PMEVCNTRn and PMEVTYPERn register

[Shannon Zhao]

Add access handler which emulates writing and reading PMEVCNTRn and
PMEVTYPERn.

Signed-off-by: Shannon Zhao 
---
 arch/arm64/kvm/sys_regs.c | 164 ++
 1 file changed, 164 insertions(+)

diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index dd790c7..0c785fc 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@ -603,6 +603,20 @@ static bool access_pmu_regs(struct kvm_vcpu *vcpu,
{ Op0(0b10), Op1(0b000), CRn(0b), CRm((n)), Op2(0b111), \
  trap_wcr, reset_wcr, n, 0,  get_wcr, set_wcr }
 
+/* Macro to expand the PMEVCNTRn_EL0 register */
+#define PMU_PMEVCNTR_EL0(n)\
+   /* PMEVCNTRn_EL0 */ \
+   { Op0(0b11), Op1(0b011), CRn(0b1110),   \
+ CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
+ access_pmu_regs, reset_unknown, (PMEVCNTR0_EL0 + n), }
+
+/* Macro to expand the PMEVTYPERn_EL0 register */
+#define PMU_PMEVTYPER_EL0(n)   \
+   /* PMEVTYPERn_EL0 */\
+   { Op0(0b11), Op1(0b011), CRn(0b1110),   \
+ CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
+ access_pmu_regs, reset_unknown, (PMEVTYPER0_EL0 + n), }
+
 /*
  * Architected system registers.
  * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
@@ -824,6 +838,74 @@ static const struct sys_reg_desc sys_reg_descs[] = {
{ Op0(0b11), Op1(0b011), CRn(0b1101), CRm(0b), Op2(0b011),
  NULL, reset_unknown, TPIDRRO_EL0 },
 
+   /* PMEVCNTRn_EL0 */
+   PMU_PMEVCNTR_EL0(0),
+   PMU_PMEVCNTR_EL0(1),
+   PMU_PMEVCNTR_EL0(2),
+   PMU_PMEVCNTR_EL0(3),
+   PMU_PMEVCNTR_EL0(4),
+   PMU_PMEVCNTR_EL0(5),
+   PMU_PMEVCNTR_EL0(6),
+   PMU_PMEVCNTR_EL0(7),
+   PMU_PMEVCNTR_EL0(8),
+   PMU_PMEVCNTR_EL0(9),
+   PMU_PMEVCNTR_EL0(10),
+   PMU_PMEVCNTR_EL0(11),
+   PMU_PMEVCNTR_EL0(12),
+   PMU_PMEVCNTR_EL0(13),
+   PMU_PMEVCNTR_EL0(14),
+   PMU_PMEVCNTR_EL0(15),
+   PMU_PMEVCNTR_EL0(16),
+   PMU_PMEVCNTR_EL0(17),
+   PMU_PMEVCNTR_EL0(18),
+   PMU_PMEVCNTR_EL0(19),
+   PMU_PMEVCNTR_EL0(20),
+   PMU_PMEVCNTR_EL0(21),
+   PMU_PMEVCNTR_EL0(22),
+   PMU_PMEVCNTR_EL0(23),
+   PMU_PMEVCNTR_EL0(24),
+   PMU_PMEVCNTR_EL0(25),
+   PMU_PMEVCNTR_EL0(26),
+   PMU_PMEVCNTR_EL0(27),
+   PMU_PMEVCNTR_EL0(28),
+   PMU_PMEVCNTR_EL0(29),
+   PMU_PMEVCNTR_EL0(30),
+   /* PMEVTYPERn_EL0 */
+   PMU_PMEVTYPER_EL0(0),
+   PMU_PMEVTYPER_EL0(1),
+   PMU_PMEVTYPER_EL0(2),
+   PMU_PMEVTYPER_EL0(3),
+   PMU_PMEVTYPER_EL0(4),
+   PMU_PMEVTYPER_EL0(5),
+   PMU_PMEVTYPER_EL0(6),
+   PMU_PMEVTYPER_EL0(7),
+   PMU_PMEVTYPER_EL0(8),
+   PMU_PMEVTYPER_EL0(9),
+   PMU_PMEVTYPER_EL0(10),
+   PMU_PMEVTYPER_EL0(11),
+   PMU_PMEVTYPER_EL0(12),
+   PMU_PMEVTYPER_EL0(13),
+   PMU_PMEVTYPER_EL0(14),
+   PMU_PMEVTYPER_EL0(15),
+   PMU_PMEVTYPER_EL0(16),
+   PMU_PMEVTYPER_EL0(17),
+   PMU_PMEVTYPER_EL0(18),
+   PMU_PMEVTYPER_EL0(19),
+   PMU_PMEVTYPER_EL0(20),
+   PMU_PMEVTYPER_EL0(21),
+   PMU_PMEVTYPER_EL0(22),
+   PMU_PMEVTYPER_EL0(23),
+   PMU_PMEVTYPER_EL0(24),
+   PMU_PMEVTYPER_EL0(25),
+   PMU_PMEVTYPER_EL0(26),
+   PMU_PMEVTYPER_EL0(27),
+   PMU_PMEVTYPER_EL0(28),
+   PMU_PMEVTYPER_EL0(29),
+   PMU_PMEVTYPER_EL0(30),
+   /* PMCCFILTR_EL0 */
+   { Op0(0b11), Op1(0b011), CRn(0b1110), CRm(0b), Op2(0b111),
+ access_pmu_regs, reset_unknown, PMCCFILTR_EL0, },
+
/* DACR32_EL2 */
{ Op0(0b11), Op1(0b100), CRn(0b0011), CRm(0b), Op2(0b000),
  NULL, reset_unknown, DACR32_EL2 },
@@ -1122,6 +1204,20 @@ static bool access_pmu_cp15_regs(struct kvm_vcpu *vcpu,
return true;
 }
 
+/* Macro to expand the PMEVCNTRn register */
+#define PMU_PMEVCNTR(n)
\
+   /* PMEVCNTRn */ \
+   { Op1(0), CRn(0b1110),  \
+ CRm((0b1000 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
+ access_pmu_cp15_regs, reset_unknown_cp15, (c14_PMEVCNTR0 + n), }
+
+/* Macro to expand the PMEVTYPERn register */
+#define PMU_PMEVTYPER(n)   \
+   /* PMEVTYPERn */\
+   { Op1(0), CRn(0b1110),  \
+ CRm((0b1100 | (((n) >> 3) & 0x3))), Op2(((n) & 0x7)), \
+ access_pmu_cp15_regs, reset_unknown_cp15, (c14_PMEVTYPER0 + n), }
+
 /*
  * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
 

[PATCH v3 17/20] KVM: ARM64: Add PMU overflow interrupt routing

[Shannon Zhao]

When calling perf_event_create_kernel_counter to create perf_event,
assign a overflow handler. Then when perf event overflows, set
irq_pending and call kvm_vcpu_kick() to sync the interrupt.

Signed-off-by: Shannon Zhao 
---
 arch/arm/kvm/arm.c|  4 
 include/kvm/arm_pmu.h |  2 ++
 virt/kvm/arm/pmu.c| 54 ++-
 3 files changed, 59 insertions(+), 1 deletion(-)

diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
index ce404a5..3fca263 100644
--- a/arch/arm/kvm/arm.c
+++ b/arch/arm/kvm/arm.c
@@ -28,6 +28,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #define CREATE_TRACE_POINTS
 #include "trace.h"
@@ -554,6 +555,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct 
kvm_run *run)
kvm_vgic_sync_hwstate(vcpu);
preempt_enable();
kvm_timer_sync_hwstate(vcpu);
+   kvm_pmu_sync_hwstate(vcpu);
continue;
}
 
@@ -604,6 +606,8 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct 
kvm_run *run)
 
kvm_timer_sync_hwstate(vcpu);
 
+   kvm_pmu_sync_hwstate(vcpu);
+
ret = handle_exit(vcpu, run, ret);
}
 
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index 9293133..953c400 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -38,6 +38,7 @@ struct kvm_pmu {
 };
 
 #ifdef CONFIG_KVM_ARM_PMU
+void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu);
 unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx);
 void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val);
 void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u32 val);
@@ -45,6 +46,7 @@ void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u32 
val);
 void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data,
u32 select_idx);
 #else
+void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu) {}
 unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx)
 {
return 0;
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index 18637c9..ca7e849 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -21,6 +21,7 @@
 #include 
 #include 
 #include 
+#include 
 
 static void kvm_pmu_set_evttyper(struct kvm_vcpu *vcpu, u32 idx, u32 val)
 {
@@ -62,6 +63,56 @@ static void kvm_pmu_stop_counter(struct kvm_vcpu *vcpu, u32 
select_idx)
 }
 
 /**
+ * kvm_pmu_sync_hwstate - sync pmu state for cpu
+ * @vcpu: The vcpu pointer
+ *
+ * Inject virtual PMU IRQ if IRQ is pending for this cpu.
+ */
+void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu)
+{
+   struct kvm_pmu *pmu = >arch.pmu;
+
+   if (pmu->irq_pending && (pmu->irq_num != -1)) {
+   kvm_vgic_inject_irq(vcpu->kvm, vcpu->vcpu_id, pmu->irq_num, 1);
+   pmu->irq_pending = false;
+   }
+}
+
+/**
+ * When perf event overflows, set irq_pending and call kvm_vcpu_kick() to 
inject
+ * the interrupt.
+ */
+static void kvm_pmu_perf_overflow(struct perf_event *perf_event,
+ struct perf_sample_data *data,
+ struct pt_regs *regs)
+{
+   struct kvm_pmc *pmc = perf_event->overflow_handler_context;
+   struct kvm_vcpu *vcpu = pmc->vcpu;
+   struct kvm_pmu *pmu = >arch.pmu;
+   int idx = pmc->idx;
+
+   if (!vcpu_mode_is_32bit(vcpu)) {
+   if ((vcpu_sys_reg(vcpu, PMINTENSET_EL1) >> idx) & 0x1) {
+   __set_bit(idx,
+   (unsigned long *)_sys_reg(vcpu, PMOVSSET_EL0));
+   __set_bit(idx,
+   (unsigned long *)_sys_reg(vcpu, PMOVSCLR_EL0));
+   pmu->irq_pending = true;
+   kvm_vcpu_kick(vcpu);
+   }
+   } else {
+   if ((vcpu_cp15(vcpu, c9_PMINTENSET) >> idx) & 0x1) {
+   __set_bit(idx,
+   (unsigned long *)_cp15(vcpu, c9_PMOVSSET));
+   __set_bit(idx,
+   (unsigned long *)_cp15(vcpu, c9_PMOVSCLR));
+   pmu->irq_pending = true;
+   kvm_vcpu_kick(vcpu);
+   }
+   }
+}
+
+/**
  * kvm_pmu_get_counter_value - get PMU counter value
  * @vcpu: The vcpu pointer
  * @select_idx: The counter index
@@ -225,7 +276,8 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, 
u32 data,
/* The initial sample period (overflow count) of an event. */
attr.sample_period = (-counter) & (((u64)1 << overflow_bit) - 1);
 
-   event = perf_event_create_kernel_counter(, -1, current, NULL, pmc);
+   event = perf_event_create_kernel_counter(, -1, current,
+kvm_pmu_perf_overflow, pmc);
if (IS_ERR(event)) {
printk_once("kvm: pmu event creation failed %ld\n",
  

[PATCH v3 18/20] KVM: ARM64: Reset PMU state when resetting vcpu

[Shannon Zhao]

Signed-off-by: Shannon Zhao 
---
 arch/arm64/kvm/reset.c |  3 +++
 include/kvm/arm_pmu.h  |  2 ++
 virt/kvm/arm/pmu.c | 18 ++
 3 files changed, 23 insertions(+)

diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c
index 91cf535..4da7f6c 100644
--- a/arch/arm64/kvm/reset.c
+++ b/arch/arm64/kvm/reset.c
@@ -120,6 +120,9 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
/* Reset system registers */
kvm_reset_sys_regs(vcpu);
 
+   /* Reset PMU */
+   kvm_pmu_vcpu_reset(vcpu);
+
/* Reset timer */
return kvm_timer_vcpu_reset(vcpu, cpu_vtimer_irq);
 }
diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
index 953c400..8dacfd3 100644
--- a/include/kvm/arm_pmu.h
+++ b/include/kvm/arm_pmu.h
@@ -38,6 +38,7 @@ struct kvm_pmu {
 };
 
 #ifdef CONFIG_KVM_ARM_PMU
+void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu);
 void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu);
 unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx);
 void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u32 val);
@@ -46,6 +47,7 @@ void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u32 
val);
 void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u32 data,
u32 select_idx);
 #else
+void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu) {}
 void kvm_pmu_sync_hwstate(struct kvm_vcpu *vcpu) {}
 unsigned long kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u32 select_idx)
 {
diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
index ca7e849..faa2b76 100644
--- a/virt/kvm/arm/pmu.c
+++ b/virt/kvm/arm/pmu.c
@@ -63,6 +63,24 @@ static void kvm_pmu_stop_counter(struct kvm_vcpu *vcpu, u32 
select_idx)
 }
 
 /**
+ * kvm_pmu_vcpu_reset - reset pmu state for cpu
+ * @vcpu: The vcpu pointer
+ *
+ */
+void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu)
+{
+   int i;
+   struct kvm_pmu *pmu = >arch.pmu;
+
+   for (i = 0; i < ARMV8_MAX_COUNTERS; i++) {
+   kvm_pmu_stop_counter(vcpu, i);
+   pmu->pmc[i].idx = i;
+   pmu->pmc[i].vcpu = vcpu;
+   }
+   pmu->irq_pending = false;
+}
+
+/**
  * kvm_pmu_sync_hwstate - sync pmu state for cpu
  * @vcpu: The vcpu pointer
  *
-- 
2.1.4

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Re: [PATCH] powerpc/e6500: add TMCFG0 register definition

[Scott Wood]

On Wed, 2015-09-23 at 18:06 +0300, Laurentiu Tudor wrote:
> The register is not currently used in the base kernel
> but will be in a forthcoming kvm patch.
> 
> Signed-off-by: Laurentiu Tudor 
> ---
>  arch/powerpc/include/asm/reg_booke.h | 6 ++
>  1 file changed, 6 insertions(+)

Acked-by: Scott Wood 

-Scott

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Re: [PATCH 15/19] KVM: PPC: e500: fix handling local_sid_lookup result

[Scott Wood]

On Thu, 2015-09-24 at 16:00 +0200, Andrzej Hajda wrote:
> The function can return negative value.
> 
> The problem has been detected using proposed semantic patch
> scripts/coccinelle/tests/assign_signed_to_unsigned.cocci [1].
> 
> [1]: http://permalink.gmane.org/gmane.linux.kernel/2046107
> 
> Signed-off-by: Andrzej Hajda 
> ---
> Hi,
> 
> To avoid problems with too many mail recipients I have sent whole
> patchset only to LKML. Anyway patches have no dependencies.
> 
> Regards
> Andrzej
> ---
>  arch/powerpc/kvm/e500.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)

Acked-by: Scott Wood 

-Scott

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Re: [PATCH 15/19] KVM: PPC: e500: fix handling local_sid_lookup result

[Scott Wood]

On Thu, 2015-09-24 at 16:00 +0200, Andrzej Hajda wrote:
> The function can return negative value.
> 
> The problem has been detected using proposed semantic patch
> scripts/coccinelle/tests/assign_signed_to_unsigned.cocci [1].
> 
> [1]: http://permalink.gmane.org/gmane.linux.kernel/2046107
> 
> Signed-off-by: Andrzej Hajda 
> ---
> Hi,
> 
> To avoid problems with too many mail recipients I have sent whole
> patchset only to LKML. Anyway patches have no dependencies.
> 
> Regards
> Andrzej
> ---
>  arch/powerpc/kvm/e500.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)

Acked-by: Scott Wood 

-Scott

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RE: [PATCH v9 00/18] Add VT-d Posted-Interrupts support - including prerequisite series

[Wu, Feng]

Hi Paolo,

Thanks for your review on this series! I'd like to confirm this series (plus
the patch fixing the compilation error) is okay to you and I don't need to
do extra things for it, right?

Thanks,
Feng

> -Original Message-
> From: Wu, Feng
> Sent: Friday, September 18, 2015 10:30 PM
> To: pbonz...@redhat.com; alex.william...@redhat.com; j...@8bytes.org;
> mtosa...@redhat.com
> Cc: eric.au...@linaro.org; kvm@vger.kernel.org;
> io...@lists.linux-foundation.org; linux-ker...@vger.kernel.org; Wu, Feng
> Subject: [PATCH v9 00/18] Add VT-d Posted-Interrupts support - including
> prerequisite series
> 
> VT-d Posted-Interrupts is an enhancement to CPU side Posted-Interrupt.
> With VT-d Posted-Interrupts enabled, external interrupts from
> direct-assigned devices can be delivered to guests without VMM
> intervention when guest is running in non-root mode.
> 
> You can find the VT-d Posted-Interrtups Spec. in the following URL:
> http://www.intel.com/content/www/us/en/intelligent-systems/intel-technolog
> y/vt-directed-io-spec.html
> 
> v9:
> - Include the whole series:
> [01/18]: irq bypasser manager
> [02/18] - [06/18]: Common non-architecture part for VT-d PI and ARM side
> forwarded irq
> [07/18] - [18/18]: VT-d PI part
> 
> v8:
> refer to the changelog in each patch
> 
> v7:
> * Define two weak irq bypass callbacks:
>   - kvm_arch_irq_bypass_start()
>   - kvm_arch_irq_bypass_stop()
> * Remove the x86 dummy implementation of the above two functions.
> * Print some useful information instead of WARN_ON() when the
>   irq bypass consumer unregistration fails.
> * Fix an issue when calling pi_pre_block and pi_post_block.
> 
> v6:
> * Rebase on 4.2.0-rc6
> * Rebase on https://lkml.org/lkml/2015/8/6/526 and
> http://www.gossamer-threads.com/lists/linux/kernel/2235623
> * Make the add_consumer and del_consumer callbacks static
> * Remove pointless INIT_LIST_HEAD to 'vdev->ctx[vector].producer.node)'
> * Use dev_info instead of WARN_ON() when irq_bypass_register_producer fails
> * Remove optional dummy callbacks for irq producer
> 
> v4:
> * For lowest-priority interrupt, only support single-CPU destination
> interrupts at the current stage, more common lowest priority support
> will be added later.
> * Accoring to Marcelo's suggestion, when vCPU is blocked, we handle
> the posted-interrupts in the HLT emulation path.
> * Some small changes (coding style, typo, add some code comments)
> 
> v3:
> * Adjust the Posted-interrupts Descriptor updating logic when vCPU is
>   preempted or blocked.
> * KVM_DEV_VFIO_DEVICE_POSTING_IRQ -->
> KVM_DEV_VFIO_DEVICE_POST_IRQ
> * __KVM_HAVE_ARCH_KVM_VFIO_POSTING -->
> __KVM_HAVE_ARCH_KVM_VFIO_POST
> * Add KVM_DEV_VFIO_DEVICE_UNPOST_IRQ attribute for VFIO irq, which
>   can be used to change back to remapping mode.
> * Fix typo
> 
> v2:
> * Use VFIO framework to enable this feature, the VFIO part of this series is
>   base on Eric's patch "[PATCH v3 0/8] KVM-VFIO IRQ forward control"
> * Rebase this patchset on
> git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git,
>   then revise some irq logic based on the new hierarchy irqdomain patches
> provided
>   by Jiang Liu 
> 
> 
> *** BLURB HERE ***
> 
> Alex Williamson (1):
>   virt: IRQ bypass manager
> 
> Eric Auger (4):
>   KVM: arm/arm64: select IRQ_BYPASS_MANAGER
>   KVM: create kvm_irqfd.h
>   KVM: introduce kvm_arch functions for IRQ bypass
>   KVM: eventfd: add irq bypass consumer management
> 
> Feng Wu (13):
>   KVM: x86: select IRQ_BYPASS_MANAGER
>   KVM: Extend struct pi_desc for VT-d Posted-Interrupts
>   KVM: Add some helper functions for Posted-Interrupts
>   KVM: Define a new interface kvm_intr_is_single_vcpu()
>   KVM: Make struct kvm_irq_routing_table accessible
>   KVM: make kvm_set_msi_irq() public
>   vfio: Register/unregister irq_bypass_producer
>   KVM: x86: Update IRTE for posted-interrupts
>   KVM: Implement IRQ bypass consumer callbacks for x86
>   KVM: Add an arch specific hooks in 'struct kvm_kernel_irqfd'
>   KVM: Update Posted-Interrupts Descriptor when vCPU is preempted
>   KVM: Update Posted-Interrupts Descriptor when vCPU is blocked
>   iommu/vt-d: Add a command line parameter for VT-d posted-interrupts
> 
>  Documentation/kernel-parameters.txt   |   1 +
>  Documentation/virtual/kvm/locking.txt |  12 ++
>  MAINTAINERS   |   7 +
>  arch/arm/kvm/Kconfig  |   2 +
>  arch/arm/kvm/Makefile |   1 +
>  arch/arm64/kvm/Kconfig|   2 +
>  arch/arm64/kvm/Makefile   |   1 +
>  arch/x86/include/asm/kvm_host.h   |  24 +++
>  arch/x86/kvm/Kconfig  |   3 +
>  arch/x86/kvm/Makefile |   3 +
>  arch/x86/kvm/irq_comm.c   |  32 ++-
>  arch/x86/kvm/lapic.c  |  59 ++
>  arch/x86/kvm/lapic.h  |   2 +
>  arch/x86/kvm/trace.h  |  33 
>  arch/x86/kvm/vmx.c| 361
> 

Re: [PATCH 1/2] KVM: introduce __vmx_flush_tlb to handle specific vpid

[Wanpeng Li]

On 9/25/15 12:12 AM, Bandan Das wrote:

Wanpeng Li  writes:


Introduce __vmx_flush_tlb() to handle specific vpid.

Signed-off-by: Wanpeng Li 
---
  arch/x86/kvm/vmx.c | 21 +
  1 file changed, 13 insertions(+), 8 deletions(-)

diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 794c529..7188c5e 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -1343,13 +1343,13 @@ static void loaded_vmcs_clear(struct loaded_vmcs 
*loaded_vmcs)
 __loaded_vmcs_clear, loaded_vmcs, 1);
  }
  
-static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)

+static inline void vpid_sync_vcpu_single(int vpid)
  {
-   if (vmx->vpid == 0)
+   if (vpid == 0)
return;
  
  	if (cpu_has_vmx_invvpid_single())

-   __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
+   __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vpid, 0);
  }
  
  static inline void vpid_sync_vcpu_global(void)

@@ -1358,10 +1358,10 @@ static inline void vpid_sync_vcpu_global(void)
__invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
  }
  
-static inline void vpid_sync_context(struct vcpu_vmx *vmx)

+static inline void vpid_sync_context(int vpid)
  {
if (cpu_has_vmx_invvpid_single())
-   vpid_sync_vcpu_single(vmx);
+   vpid_sync_vcpu_single(vpid);
else
vpid_sync_vcpu_global();
  }

Not sure myself what's the right thing to do but this may be undesirable
in a nested environment. Assuming the processor supports global invalidation
only, this seems like a easy way for the nested guest to invalidate *all*
mappings - even the L1 specific mappings.


Indeed, however, there's no easy way to handle the w/o single 
invalidation case, we can improve it if you have any idea, otherwise, it 
can be left to further optimization. :-)


Regards,
Wanpeng Li
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Re: [PATCH 1/2] KVM: PPC: e6500: Handle LRAT error exception

[Scott Wood]

On Thu, 2015-09-24 at 16:11 +0300, Laurentiu Tudor wrote:
> diff --git a/arch/powerpc/kvm/bookehv_interrupts.S 
> b/arch/powerpc/kvm/bookehv_interrupts.S
> index 81bd8a07..1e9fa2a 100644
> --- a/arch/powerpc/kvm/bookehv_interrupts.S
> +++ b/arch/powerpc/kvm/bookehv_interrupts.S
> @@ -62,6 +62,7 @@
>  #define NEED_EMU 0x0001 /* emulation -- save nv regs */
>  #define NEED_DEAR0x0002 /* save faulting DEAR */
>  #define NEED_ESR 0x0004 /* save faulting ESR */
> +#define NEED_LPER0x0008 /* save faulting LPER */
>  
>  /*
>   * On entry:
> @@ -159,6 +160,12 @@
>   PPC_STL r9, VCPU_FAULT_DEAR(r4)
>   .endif
>  
> + /* Only supported on 64-bit cores for now */
> + .if \flags & NEED_LPER
> + mfspr   r7, SPRN_LPER
> + std r7, VCPU_FAULT_LPER(r4)
> + .endif

What's the harm in using PPC_STL anyway?


>  /*
>   * For input register values, see 
> arch/powerpc/include/asm/kvm_booke_hv_asm.h
> diff --git a/arch/powerpc/kvm/e500_mmu_host.c 
> b/arch/powerpc/kvm/e500_mmu_host.c
> index 12d5c67..99ad88a 100644
> --- a/arch/powerpc/kvm/e500_mmu_host.c
> +++ b/arch/powerpc/kvm/e500_mmu_host.c
> @@ -96,6 +96,112 @@ static inline void __write_host_tlbe(struct 
> kvm_book3e_206_tlb_entry *stlbe,
> stlbe->mas2, stlbe->mas7_3);
>  }
>  
> +#if defined(CONFIG_64BIT) && defined(CONFIG_KVM_BOOKE_HV)
> +static int lrat_next(void)
> +{

Will anything break by removing the CONFIG_64BIT condition, even if we don't 
have a 32-bit target that uses this?

> +void kvmppc_lrat_map(struct kvm_vcpu *vcpu, gfn_t gfn)
> +{
> + struct kvm_memory_slot *slot;
> + unsigned long pfn;
> + unsigned long hva;
> + struct vm_area_struct *vma;
> + unsigned long psize;
> + int tsize;
> + unsigned long tsize_pages;
> +
> + slot = gfn_to_memslot(vcpu->kvm, gfn);
> + if (!slot) {
> + pr_err_ratelimited("%s: couldn't find memslot for gfn %lx!\n",
> +__func__, (long)gfn);
> + return;
> + }
> +
> + hva = slot->userspace_addr;

What if the faulting address is somewhere in the middle of the slot?  
Shouldn't you use gfn_to_hva_memslot() like kvmppc_e500_shadow_map()?  In 
fact there's probably a lot of logic that should be shared between these two 
functions.

> + down_read(>mm->mmap_sem);
> + vma = find_vma(current->mm, hva);
> + if (vma && (hva >= vma->vm_start)) {
> + psize = vma_kernel_pagesize(vma);

What if it's VM_PFNMAP?

> + } else {
> + pr_err_ratelimited("%s: couldn't find virtual memory address 
> for gfn 
> %lx!\n",
> +__func__, (long)gfn);
> + up_read(>mm->mmap_sem);
> + return;
> + }
> + up_read(>mm->mmap_sem);
> +
> + pfn = gfn_to_pfn_memslot(slot, gfn);
> + if (is_error_noslot_pfn(pfn)) {
> + pr_err_ratelimited("%s: couldn't get real page for gfn %lx!\n",
> +__func__, (long)gfn);
> + return;
> + }
> +
> + tsize = __ilog2(psize) - 10;
> + tsize_pages = 1 << (tsize + 10 - PAGE_SHIFT);

1UL << ...

kvmppc_e500_shadow_map needs the same fix.

> + gfn &= ~(tsize_pages - 1);
> + pfn &= ~(tsize_pages - 1);
> +
> + write_host_lrate(tsize, gfn, pfn, vcpu->kvm->arch.lpid, true);
> +
> + kvm_release_pfn_clean(pfn);
> +}
> +
> +void kvmppc_lrat_invalidate(struct kvm_vcpu *vcpu)
> +{
> + uint32_t mas0, mas1 = 0;
> + int esel;
> + unsigned long flags;
> +
> + local_irq_save(flags);
> +
> + /* LRAT does not have a dedicated instruction for invalidation */
> + for (esel = 0; esel < get_paca()->tcd_ptr->lrat_max; esel++) {
> + mas0 = MAS0_ATSEL | MAS0_ESEL(esel);
> + mtspr(SPRN_MAS0, mas0);
> + asm volatile("isync; tlbre" : : : "memory");
> + mas1 = mfspr(SPRN_MAS1) & ~MAS1_VALID;
> + mtspr(SPRN_MAS1, mas1);
> + asm volatile("isync; tlbwe" : : : "memory");
> + }
> + /* Must clear mas8 for other host tlbwe's */
> + mtspr(SPRN_MAS8, 0);
> + isync();
> +
> + local_irq_restore(flags);
> +}
> +#endif /* CONFIG_64BIT && CONFIG_KVM_BOOKE_HV */
> +
>  /*
>   * Acquire a mas0 with victim hint, as if we just took a TLB miss.
>   *
> diff --git a/arch/powerpc/kvm/e500mc.c b/arch/powerpc/kvm/e500mc.c
> index cda695d..5856f8f 100644
> --- a/arch/powerpc/kvm/e500mc.c
> +++ b/arch/powerpc/kvm/e500mc.c
> @@ -99,6 +99,10 @@ void kvmppc_e500_tlbil_all(struct kvmppc_vcpu_e500 
> *vcpu_e500)
>   asm volatile("tlbilxlpid");
>   mtspr(SPRN_MAS5, 0);
>   local_irq_restore(flags);
> +
> +#ifdef PPC64
> + kvmppc_lrat_invalidate(_e500->vcpu);
> +#endif

Don't you mean CONFIG_PPC64 (or CONFIG_64BIT to be consistent)?

>  }
>  
>  void kvmppc_set_pid(struct kvm_vcpu *vcpu, u32 pid)
> diff --git a/arch/powerpc/mm/fsl_booke_mmu.c 
>