PDPTEs are used only if CR0.PG=CR4.PAE=1.
In that situation, their format depends the value of IA32_EFER.LMA.
If IA32_EFER.LMA=0, bit 63 is reserved and must be 0 in any PDPTE that is
marked present. The execute-disable setting of a page is determined only by
the PDE and PTE.
If IA32_EFER.LMA=1, bit 63 is used for the execute-disable in PML4 entries,
PDPTEs, PDEs, and PTEs (assuming IA32_EFER.NXE=1).
- Gil
-----Original Message-----
From: Dong, Eddie
Sent: Monday, March 30, 2009 5:51 PM
To: Neiger, Gil
Cc: Avi Kivity; kvm@vger.kernel.org; Dong, Eddie
Subject: FW: Use rsvd_bits_mask in load_pdptrs for cleanup and considing EXB bit
Avi Kivity wrote:
> Dong, Eddie wrote:
>> @@ -2199,6 +2194,9 @@ void reset_rsvds_bits_mask(struct kvm_vcpu
>> *vcpu, int level) context->rsvd_bits_mask[1][0] = 0;
>> break;
>> case PT32E_ROOT_LEVEL:
>> + context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
>> + rsvd_bits(maxphyaddr, 62) |
>> + rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
>> context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
>> rsvd_bits(maxphyaddr, 62); /* PDE */
>> context->rsvd_bits_mask[0][0] = exb_bit_rsvd
>
> Are you sure that PDPTEs support NX? They don't support R/W and U/S,
> so it seems likely that NX is reserved as well even when EFER.NXE is
> enabled.
Gil:
Here is the original mail in KVM mailinglist. If you would be able to
help, that is great.
thx, eddie--
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