Re: [PATCH] seabios/pci: enable 64 bit bar on seabios

2012-11-05 Thread Gerd Hoffmann 
  Hi,

 I just want to enable 64 bit bars for KVM usage, seabios 1.7.0 is
 used in current qemu-kvm, which not handle 64 bit bars yet. I cloned
 seabios code from kernel.org(seems no 64 bit bars supporting), but I
 was not taking notice of the tree on http://git.qemu.org/, yes it has
 already done 64 bit bars handling. So you may ignore this patch.
 
 Btw, when will the latest seabios(especially 64 bits bars) be
 involved qemu-kvm?

qemu 1.2.0 has it (seabios 1.7.1, a git snapshot very close to it to be
exact), and qemu-kvm 1.2.0 should have it too.

cheers,
  Gerd
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RE: [PATCH] seabios/pci: enable 64 bit bar on seabios

2012-11-05 Thread Hao, Xudong 
 -Original Message-
 From: Gerd Hoffmann [mailto:kra...@redhat.com]
 Sent: Monday, November 05, 2012 5:08 PM
 To: Hao, Xudong
 Cc: ke...@koconnor.net; seab...@seabios.org; kvm@vger.kernel.org;
 a...@redhat.com
 Subject: Re: [PATCH] seabios/pci: enable 64 bit bar on seabios
 
   Hi,
 
  I just want to enable 64 bit bars for KVM usage, seabios 1.7.0 is
  used in current qemu-kvm, which not handle 64 bit bars yet. I cloned
  seabios code from kernel.org(seems no 64 bit bars supporting), but I
  was not taking notice of the tree on http://git.qemu.org/, yes it has
  already done 64 bit bars handling. So you may ignore this patch.
 
  Btw, when will the latest seabios(especially 64 bits bars) be
  involved qemu-kvm?
 
 qemu 1.2.0 has it (seabios 1.7.1, a git snapshot very close to it to be
 exact), and qemu-kvm 1.2.0 should have it too.
 

Got it, thanks.

-Xudong
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RE: [PATCH] seabios/pci: enable 64 bit bar on seabios

2012-11-04 Thread Hao, Xudong 

 -Original Message-
 From: Gerd Hoffmann [mailto:kra...@redhat.com]
 Sent: Friday, November 02, 2012 5:00 PM
 To: Hao, Xudong
 Cc: ke...@koconnor.net; seab...@seabios.org; kvm@vger.kernel.org;
 a...@redhat.com
 Subject: Re: [PATCH] seabios/pci: enable 64 bit bar on seabios
 
 On 11/02/12 06:42, Xudong Hao wrote:
  64 bit bar sizing and MMIO allocation. The 64 bit window is placed above 
  high
  memory, top down from the end of guest physical address space.
 
 What problem you are trying to fix?  The existing code should handle
 64bit bars just fine.  By default they are placed below 4G though for
 compatibility reasons (make old 32bit guests happy).  When running out
 of address space seabios will try map them above 4G though to make room
 below 4G.
 

I just want to enable 64 bit bars for KVM usage, seabios 1.7.0 is used in 
current qemu-kvm, which not handle 64 bit bars yet.
I cloned seabios code from kernel.org(seems no 64 bit bars supporting), but I 
was not taking notice of the tree on http://git.qemu.org/, yes it has already 
done 64 bit bars handling. So you may ignore this patch.

Btw, when will the latest seabios(especially 64 bits bars) be involved qemu-kvm?

 Mapping your 64bit PCI bars above 4G unconditionally (for testing or
 other reasons) can simply be done this way:
 
 --- a/src/pciinit.c
 +++ b/src/pciinit.c
 @@ -599,7 +599,7 @@ static void pci_bios_map_devices(struct pci_bus
 *busses)
  {
  pcimem_start = RamSize;
 
 -if (pci_bios_init_root_regions(busses)) {
 +if (1 /* pci_bios_init_root_regions(busses) */) {
  struct pci_region r64_mem, r64_pref;
  r64_mem.list = NULL;
  r64_pref.list = NULL;
 
 We might want add a config option for this.
 
 cheers,
   Gerd

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Re: [PATCH] seabios/pci: enable 64 bit bar on seabios

2012-11-02 Thread Gerd Hoffmann 
On 11/02/12 06:42, Xudong Hao wrote:
 64 bit bar sizing and MMIO allocation. The 64 bit window is placed above high
 memory, top down from the end of guest physical address space.

What problem you are trying to fix?  The existing code should handle
64bit bars just fine.  By default they are placed below 4G though for
compatibility reasons (make old 32bit guests happy).  When running out
of address space seabios will try map them above 4G though to make room
below 4G.

Mapping your 64bit PCI bars above 4G unconditionally (for testing or
other reasons) can simply be done this way:

--- a/src/pciinit.c
+++ b/src/pciinit.c
@@ -599,7 +599,7 @@ static void pci_bios_map_devices(struct pci_bus *busses)
 {
 pcimem_start = RamSize;

-if (pci_bios_init_root_regions(busses)) {
+if (1 /* pci_bios_init_root_regions(busses) */) {
 struct pci_region r64_mem, r64_pref;
 r64_mem.list = NULL;
 r64_pref.list = NULL;

We might want add a config option for this.

cheers,
  Gerd

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Re: [PATCH] seabios/pci: enable 64 bit bar on seabios

2012-11-02 Thread Kevin O'Connor 
On Fri, Nov 02, 2012 at 01:42:08PM +0800, Xudong Hao wrote:
 64 bit bar sizing and MMIO allocation. The 64 bit window is placed above high
 memory, top down from the end of guest physical address space.

Your patch seems to be against an old version of SeaBIOS.  The latest
SeaBIOS already supports 64bit pci bars.

-Kevin
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[PATCH] seabios/pci: enable 64 bit bar on seabios

2012-11-01 Thread Xudong Hao 
64 bit bar sizing and MMIO allocation. The 64 bit window is placed above high
memory, top down from the end of guest physical address space.

Signed-off-by: Xudong Hao xudong@intel.com
---
 src/mtrr.c|   24 +-
 src/pci.h |2 +-
 src/pciinit.c |   99 ++--
 src/util.h|1 +
 4 files changed, 85 insertions(+), 41 deletions(-)

diff --git a/src/mtrr.c b/src/mtrr.c
index 0548043..05264c4 100644
--- a/src/mtrr.c
+++ b/src/mtrr.c
@@ -31,12 +31,26 @@
 #define MTRR_MEMTYPE_WP 5
 #define MTRR_MEMTYPE_WB 6
 
+int cpu_phys_addr(void)
+{
+u32 eax, ebx, ecx, edx;
+int phys_bits = 36;
+cpuid(0x8000u, eax, ebx, ecx, edx);
+
+if (eax = 0x8008) {
+/* Get physical bits from leaf 0x8008 (if available) */
+cpuid(0x8008u, eax, ebx, ecx, edx);
+phys_bits = eax  0xff;
+}
+return phys_bits;
+}
+
 void mtrr_setup(void)
 {
 if (!CONFIG_MTRR_INIT || CONFIG_COREBOOT || usingXen())
 return;
 
-u32 eax, ebx, ecx, edx, cpuid_features;
+u32 eax, ebx, ecx, cpuid_features;
 cpuid(1, eax, ebx, ecx, cpuid_features);
 if (!(cpuid_features  CPUID_MTRR))
 return;
@@ -81,13 +95,7 @@ void mtrr_setup(void)
 }
 
 // Set variable MTRRs
-int phys_bits = 36;
-cpuid(0x8000u, eax, ebx, ecx, edx);
-if (eax = 0x8008) {
-/* Get physical bits from leaf 0x8008 (if available) */
-cpuid(0x8008u, eax, ebx, ecx, edx);
-phys_bits = eax  0xff;
-}
+int phys_bits = cpu_phys_addr();
 u64 phys_mask = ((1ull  phys_bits) - 1);
 for (i=0; ivcnt; i++) {
 wrmsr_smp(MTRRphysBase_MSR(i), 0);
diff --git a/src/pci.h b/src/pci.h
index a2a5a4c..0fa2ae8 100644
--- a/src/pci.h
+++ b/src/pci.h
@@ -53,7 +53,7 @@ struct pci_device {
 u8 secondary_bus;
 struct {
 u32 addr;
-u32 size;
+u64 size;
 int is64;
 } bars[PCI_NUM_REGIONS];
 
diff --git a/src/pciinit.c b/src/pciinit.c
index 7d83368..a3a92ae 100644
--- a/src/pciinit.c
+++ b/src/pciinit.c
@@ -22,6 +22,7 @@ enum pci_region_type {
 PCI_REGION_TYPE_IO,
 PCI_REGION_TYPE_MEM,
 PCI_REGION_TYPE_PREFMEM,
+PCI_REGION_TYPE_MEM_64,
 PCI_REGION_TYPE_COUNT,
 };
 
@@ -29,35 +30,40 @@ static const char *region_type_name[] = {
 [ PCI_REGION_TYPE_IO ]  = io,
 [ PCI_REGION_TYPE_MEM ] = mem,
 [ PCI_REGION_TYPE_PREFMEM ] = prefmem,
+[ PCI_REGION_TYPE_MEM_64 ]  = mem64,
 };
 
 struct pci_bus {
 struct {
 /* pci region stats */
-u32 count[32 - PCI_MEM_INDEX_SHIFT];
-u32 sum, max;
+u32 count[64 - PCI_MEM_INDEX_SHIFT];
+u64 sum, max;
 /* seconday bus region sizes */
 u32 size;
 /* pci region assignments */
-u32 bases[32 - PCI_MEM_INDEX_SHIFT];
-u32 base;
+u64 bases[64 - PCI_MEM_INDEX_SHIFT];
+u64 base;
 } r[PCI_REGION_TYPE_COUNT];
 struct pci_device *bus_dev;
 };
 
-static int pci_size_to_index(u32 size, enum pci_region_type type)
+static u64 pci_size_to_index(u64 size, enum pci_region_type type)
 {
-int index = __fls(size);
+u64 index;
 int shift = (type == PCI_REGION_TYPE_IO) ?
 PCI_IO_INDEX_SHIFT : PCI_MEM_INDEX_SHIFT;
 
+if (((u32)(size  32)  ~0) == 0)
+index = (u64)__fls((u32)size);
+else
+index = (u64)__fls((u32)(size  32)) + 32;
 if (index  shift)
 index = shift;
 index -= shift;
 return index;
 }
 
-static u32 pci_index_to_size(int index, enum pci_region_type type)
+static u64 pci_index_to_size(u64 index, enum pci_region_type type)
 {
 int shift = (type == PCI_REGION_TYPE_IO) ?
 PCI_IO_INDEX_SHIFT : PCI_MEM_INDEX_SHIFT;
@@ -69,6 +75,8 @@ static enum pci_region_type pci_addr_to_type(u32 addr)
 {
 if (addr  PCI_BASE_ADDRESS_SPACE_IO)
 return PCI_REGION_TYPE_IO;
+if (addr  PCI_BASE_ADDRESS_MEM_TYPE_64)
+return PCI_REGION_TYPE_MEM_64;
 if (addr  PCI_BASE_ADDRESS_MEM_PREFETCH)
 return PCI_REGION_TYPE_PREFMEM;
 return PCI_REGION_TYPE_MEM;
@@ -330,7 +338,7 @@ static u32 pci_size_roundup(u32 size)
 }
 
 static void
-pci_bios_get_bar(struct pci_device *pci, int bar, u32 *val, u32 *size)
+pci_bios_get_bar(struct pci_device *pci, int bar, u32 *val, u64 *size)
 {
 u32 ofs = pci_bar(pci, bar);
 u16 bdf = pci-bdf;
@@ -352,9 +360,9 @@ pci_bios_get_bar(struct pci_device *pci, int bar, u32 *val, 
u32 *size)
 *size = (~(*val  mask)) + 1;
 }
 
-static void pci_bios_bus_reserve(struct pci_bus *bus, int type, u32 size)
+static void pci_bios_bus_reserve(struct pci_bus *bus, int type, u64 size)
 {
-u32 index;
+u64 index;
 
 index = pci_size_to_index(size, type);
 size = pci_index_to_size(index, type);
@@ -378,17 +386,27 @@ static void pci_bios_check_devices(struct pci_bus *busses)
 struct pci_bus *bus = busses[pci_bdf_to_bus(pci-bdf)];