Re: [PATCH 5/5] kvm: expose MSI capability to guest
On Monday 24 November 2008 19:50:35 Sheng Yang wrote:
> Signed-off-by: Sheng Yang <[EMAIL PROTECTED]>
Oh, hold this one for a moment...
I don't want to deal with compatible problem of deliver msi_msg, so I would
send out gsi->msi mapping patch and update the userspace patch.
--
regards
Yang, Sheng
> ---
> qemu/hw/device-assignment.c | 90
> +++--- qemu/hw/device-assignment.h |
> 2 +
> 2 files changed, 85 insertions(+), 7 deletions(-)
>
> diff --git a/qemu/hw/device-assignment.c b/qemu/hw/device-assignment.c
> index d3105bc..67bd6b3 100644
> --- a/qemu/hw/device-assignment.c
> +++ b/qemu/hw/device-assignment.c
> @@ -262,7 +262,8 @@ static void assigned_dev_pci_write_config(PCIDevice *d,
> uint32_t address, }
>
> if ((address >= 0x10 && address <= 0x24) || address == 0x34 ||
> -address == 0x3c || address == 0x3d) {
> +address == 0x3c || address == 0x3d ||
> +pci_access_cap_config(d, address, len)) {
> /* used for update-mappings (BAR emulation) */
> pci_default_write_config(d, address, val, len);
> return;
> @@ -296,7 +297,8 @@ static uint32_t assigned_dev_pci_read_config(PCIDevice
> *d, uint32_t address, AssignedDevice *pci_dev = container_of(d,
> AssignedDevice, dev);
>
> if ((address >= 0x10 && address <= 0x24) || address == 0x34 ||
> -address == 0x3c || address == 0x3d) {
> +address == 0x3c || address == 0x3d ||
> +pci_access_cap_config(d, address, len)) {
> val = pci_default_read_config(d, address, len);
> DEBUG("(%x.%x): address=%04x val=0x%08x len=%d\n",
>(d->devfn >> 3) & 0x1F, (d->devfn & 0x7), address, val,
> len); @@ -325,11 +327,13 @@ do_log:
> DEBUG("(%x.%x): address=%04x val=0x%08x len=%d\n",
>(d->devfn >> 3) & 0x1F, (d->devfn & 0x7), address, val, len);
>
> -/* kill the special capabilities */
> -if (address == 4 && len == 4)
> -val &= ~0x10;
> -else if (address == 6)
> -val &= ~0x10;
> +if (!pci_dev->cap.available) {
> +/* kill the special capabilities */
> +if (address == 4 && len == 4)
> +val &= ~0x10;
> +else if (address == 6)
> +val &= ~0x10;
> +}
>
> return val;
> }
> @@ -537,6 +541,73 @@ void assigned_dev_update_irq(PCIDevice *d)
> }
> }
>
> +#ifdef KVM_CAP_DEVICE_MSI
> +static void assigned_dev_enable_msi(PCIDevice *pci_dev)
> +{
> +int r;
> +struct kvm_assigned_irq assigned_irq_data;
> +AssignedDevice *assigned_dev = container_of(pci_dev, AssignedDevice,
> dev); +
> +memset(&assigned_irq_data, 0, sizeof assigned_irq_data);
> +assigned_irq_data.assigned_dev_id =
> +calc_assigned_dev_id(assigned_dev->h_busnr,
> +(uint8_t)assigned_dev->h_devfn);
> +assigned_irq_data.guest_msi.addr_lo = *(uint32_t *)
> +(pci_dev->cap.config + 4);
> +assigned_irq_data.guest_msi.data = *(uint16_t *)
> +(pci_dev->cap.config + 8);
> +assigned_irq_data.flags |= KVM_DEV_IRQ_ASSIGN_ENABLE_MSI;
> +r = kvm_assign_irq(kvm_context, &assigned_irq_data);
> +if (r < 0) {
> +perror("assigned_dev_enable_msi");
> +assigned_dev->cap.enabled &= ~ASSIGNED_DEVICE_MSI_ENABLED;
> +/* Fail to enable MSI, enable INTx instead */
> +assigned_dev_update_irq(pci_dev);
> +}
> +}
> +#endif
> +
> +void assigned_device_pci_cap_write_config(PCIDevice *pci_dev, uint32_t
> address, + uint32_t val, int len)
> +{
> +AssignedDevice *assigned_dev = container_of(pci_dev, AssignedDevice,
> dev); +uint32_t pos = pci_dev->cap.start;
> +uint8_t target_byte, target_position;
> +
> +pci_default_cap_write_config(pci_dev, address, val, len);
> +#ifdef KVM_CAP_DEVICE_MSI
> +/* Check if guest want to enable MSI */
> +if (assigned_dev->cap.available & ASSIGNED_DEVICE_CAP_MSI) {
> +target_position = pos + 2;
> +if (address <= target_position && address + len > target_position)
> { +target_byte = (uint8_t)(val >> (target_position - address));
> +if (target_byte == 1) {
> +assigned_dev->cap.enabled |= ASSIGNED_DEVICE_MSI_ENABLED;
> +assigned_dev_enable_msi(pci_dev);
> +if (!assigned_dev->cap.enabled &
> ASSIGNED_DEVICE_MSI_ENABLED) +
> pci_dev->cap.config[target_position - pos] = 0; +}
> +}
> +pos += PCI_CAPABILITY_CONFIG_MSI_LENGTH;
> +}
> +#endif
> +return;
> +}
> +
> +void assigned_device_pci_cap_init(PCIDevice *pci_dev)
> +{
> +AssignedDevice *dev = container_of(pci_dev, AssignedDevice, dev);
> +
> +#ifdef KVM_CAP_DEVICE_MSI
> +/* Expose MSI capability
> + * MSI capability is the 1st capability in cap.config */
> +if (dev->cap.available & ASSIGNED_DEVICE_CAP_MSI) {
> +pci_dev->cap.config[0] = 0x5;
> +pci_de
[PATCH 5/5] kvm: expose MSI capability to guest
Signed-off-by: Sheng Yang <[EMAIL PROTECTED]>
---
qemu/hw/device-assignment.c | 90 +++---
qemu/hw/device-assignment.h |2 +
2 files changed, 85 insertions(+), 7 deletions(-)
diff --git a/qemu/hw/device-assignment.c b/qemu/hw/device-assignment.c
index d3105bc..67bd6b3 100644
--- a/qemu/hw/device-assignment.c
+++ b/qemu/hw/device-assignment.c
@@ -262,7 +262,8 @@ static void assigned_dev_pci_write_config(PCIDevice *d,
uint32_t address,
}
if ((address >= 0x10 && address <= 0x24) || address == 0x34 ||
-address == 0x3c || address == 0x3d) {
+address == 0x3c || address == 0x3d ||
+pci_access_cap_config(d, address, len)) {
/* used for update-mappings (BAR emulation) */
pci_default_write_config(d, address, val, len);
return;
@@ -296,7 +297,8 @@ static uint32_t assigned_dev_pci_read_config(PCIDevice *d,
uint32_t address,
AssignedDevice *pci_dev = container_of(d, AssignedDevice, dev);
if ((address >= 0x10 && address <= 0x24) || address == 0x34 ||
-address == 0x3c || address == 0x3d) {
+address == 0x3c || address == 0x3d ||
+pci_access_cap_config(d, address, len)) {
val = pci_default_read_config(d, address, len);
DEBUG("(%x.%x): address=%04x val=0x%08x len=%d\n",
(d->devfn >> 3) & 0x1F, (d->devfn & 0x7), address, val, len);
@@ -325,11 +327,13 @@ do_log:
DEBUG("(%x.%x): address=%04x val=0x%08x len=%d\n",
(d->devfn >> 3) & 0x1F, (d->devfn & 0x7), address, val, len);
-/* kill the special capabilities */
-if (address == 4 && len == 4)
-val &= ~0x10;
-else if (address == 6)
-val &= ~0x10;
+if (!pci_dev->cap.available) {
+/* kill the special capabilities */
+if (address == 4 && len == 4)
+val &= ~0x10;
+else if (address == 6)
+val &= ~0x10;
+}
return val;
}
@@ -537,6 +541,73 @@ void assigned_dev_update_irq(PCIDevice *d)
}
}
+#ifdef KVM_CAP_DEVICE_MSI
+static void assigned_dev_enable_msi(PCIDevice *pci_dev)
+{
+int r;
+struct kvm_assigned_irq assigned_irq_data;
+AssignedDevice *assigned_dev = container_of(pci_dev, AssignedDevice, dev);
+
+memset(&assigned_irq_data, 0, sizeof assigned_irq_data);
+assigned_irq_data.assigned_dev_id =
+calc_assigned_dev_id(assigned_dev->h_busnr,
+(uint8_t)assigned_dev->h_devfn);
+assigned_irq_data.guest_msi.addr_lo = *(uint32_t *)
+(pci_dev->cap.config + 4);
+assigned_irq_data.guest_msi.data = *(uint16_t *)
+(pci_dev->cap.config + 8);
+assigned_irq_data.flags |= KVM_DEV_IRQ_ASSIGN_ENABLE_MSI;
+r = kvm_assign_irq(kvm_context, &assigned_irq_data);
+if (r < 0) {
+perror("assigned_dev_enable_msi");
+assigned_dev->cap.enabled &= ~ASSIGNED_DEVICE_MSI_ENABLED;
+/* Fail to enable MSI, enable INTx instead */
+assigned_dev_update_irq(pci_dev);
+}
+}
+#endif
+
+void assigned_device_pci_cap_write_config(PCIDevice *pci_dev, uint32_t address,
+ uint32_t val, int len)
+{
+AssignedDevice *assigned_dev = container_of(pci_dev, AssignedDevice, dev);
+uint32_t pos = pci_dev->cap.start;
+uint8_t target_byte, target_position;
+
+pci_default_cap_write_config(pci_dev, address, val, len);
+#ifdef KVM_CAP_DEVICE_MSI
+/* Check if guest want to enable MSI */
+if (assigned_dev->cap.available & ASSIGNED_DEVICE_CAP_MSI) {
+target_position = pos + 2;
+if (address <= target_position && address + len > target_position) {
+target_byte = (uint8_t)(val >> (target_position - address));
+if (target_byte == 1) {
+assigned_dev->cap.enabled |= ASSIGNED_DEVICE_MSI_ENABLED;
+assigned_dev_enable_msi(pci_dev);
+if (!assigned_dev->cap.enabled & ASSIGNED_DEVICE_MSI_ENABLED)
+pci_dev->cap.config[target_position - pos] = 0;
+}
+}
+pos += PCI_CAPABILITY_CONFIG_MSI_LENGTH;
+}
+#endif
+return;
+}
+
+void assigned_device_pci_cap_init(PCIDevice *pci_dev)
+{
+AssignedDevice *dev = container_of(pci_dev, AssignedDevice, dev);
+
+#ifdef KVM_CAP_DEVICE_MSI
+/* Expose MSI capability
+ * MSI capability is the 1st capability in cap.config */
+if (dev->cap.available & ASSIGNED_DEVICE_CAP_MSI) {
+pci_dev->cap.config[0] = 0x5;
+pci_dev->cap.length += PCI_CAPABILITY_CONFIG_MSI_LENGTH;
+}
+#endif
+}
+
struct PCIDevice *init_assigned_device(AssignedDevInfo *adev, PCIBus *bus)
{
int r;
@@ -580,6 +651,11 @@ struct PCIDevice *init_assigned_device(AssignedDevInfo
*adev, PCIBus *bus)
dev->h_busnr = adev->bus;
dev->h_devfn = PCI_DEVFN(adev->dev, adev->func);
+if (dev->cap.available)
+pci_enable_capability_support(pci_dev, 0, NULL,
+
