RE: [PATCH v9 2/3] x86, apicv: add virtual x2apic support

2013-01-13 Thread Zhang, Yang Z 
Gleb Natapov wrote on 2013-01-12:
> On Fri, Jan 11, 2013 at 07:36:44AM +, Zhang, Yang Z wrote:
>> Gleb Natapov wrote on 2013-01-10:
>>> On Thu, Jan 10, 2013 at 12:22:51PM +, Zhang, Yang Z wrote:
 Gleb Natapov wrote on 2013-01-10:
> On Thu, Jan 10, 2013 at 11:54:21AM +, Zhang, Yang Z wrote:
 The right logic should be:
 When register virtualization enabled, read all apic msr(except apic id
> reg
>>> and
>>> tmcct which have the hook) not cause vmexit and only write TPR not
>>> cause vmexit.
 When vid enabled, write to TPR, EOI and SELF IPI not cause vmexit.
 It's better to put the patch of envirtualize x2apic mode as first 
 patch.
 
>>> There is no point whatsoever to enable virtualize x2apic without
>>> allowing at least one non intercepted access to x2apic MSR range and
>>> this is what your patch is doing when run on cpu without vid capability.
>> No, at least read/write TPR will not cause vmexit if virtualize x2apic 
>> mode
> is
> enabled.
> For that you need to disable 808H MSR intercept, which your patch does
> not
>>> do.
 I want to do this in next patch.
 
>>> Then don't. There is no point in the patch that enables virtualize
>>> x2apic and does not allow at least one non-intercepted MSR access.
>> As I said, read/write TPR will not cause vmexit if virtual x2apic is set.
>> 
> From my reading of the spec you need to disable 808H intercept for that.
> Is this not the case?
After thinking, since Linux doesn't use TPR, there is no point to do this. No 
real guest will benefit from this.

>> I am not sure whether I understand your comments right in previous
>> discussion, here is my thinking: 1. enable virtualize x2apic mode if
>> guest is really using x2apic and clear TPR in msr read  and write
>> bitmap. This will benefit reading TPR. 2. If APIC registers
>> virtualization is enabled, clear all bit in rang
> 0x800-0x8ff(except apic id reg and tmcct).
> Clear all read bits in the range.
> 
>> 3. If vid is enabled, clear EOI and SELF IPI in msr write map.
>> 
> Looks OK.
> 
>> One concern you mentioned is that vid enabled and virtualize x2apic is
>>> disabled
> but guest still use x2apic. In this case, we still use MSR bitmap to
> intercept x2apic. This means the vEOI update will never happen. But we
> still can benefit from interrupt window.
>> 
> What interrupt windows? Without virtualized x2apic TPR/EOI
> virtualization will not happen and we rely on that in the code.
 Yes, but we can eliminate vmexit of interrupt window. Interrupt still can
>>> delivery to guest without vmexit when guest enables interrupt if vid
>>> is enabled. See SDM vol 3, 29.2.2.
 
>>> What does it matter that you eliminated vmexit of interrupt window if
>>> you broke everything else? The vid patch assumes that apic emulation
>>> either entirely happens in a software when vid is disabled or in a CPU
>>> if vid is enabled. Mixed mode will not work (apic->isr_count = 1 trick
>>> will break things for instance). And it is not worth it to complicate
>>> the code to make it work.
>> Yes, you are right. It too complicated.
>> Another question? Why not to hide x2apic capability to guest when vid is
> supported and virtual x2apic mode is not supported? It should be more
> reasonable than disable vid when virtual x2apic mode is unavailable.
>> 
> Because I think there will be no such HW. If such HW expected to be
> common then we can go this route.
> 
> --
>   Gleb.
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Best regards,
Yang


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RE: [PATCH v9 2/3] x86, apicv: add virtual x2apic support

2013-01-13 Thread Zhang, Yang Z 
Gleb Natapov wrote on 2013-01-12:
> On Fri, Jan 11, 2013 at 07:36:44AM +, Zhang, Yang Z wrote:
>> Gleb Natapov wrote on 2013-01-10:
>>> On Thu, Jan 10, 2013 at 12:22:51PM +, Zhang, Yang Z wrote:
 Gleb Natapov wrote on 2013-01-10:
> On Thu, Jan 10, 2013 at 11:54:21AM +, Zhang, Yang Z wrote:
 The right logic should be:
 When register virtualization enabled, read all apic msr(except apic id
> reg
>>> and
>>> tmcct which have the hook) not cause vmexit and only write TPR not
>>> cause vmexit.
 When vid enabled, write to TPR, EOI and SELF IPI not cause vmexit.
 It's better to put the patch of envirtualize x2apic mode as first 
 patch.
 
>>> There is no point whatsoever to enable virtualize x2apic without
>>> allowing at least one non intercepted access to x2apic MSR range and
>>> this is what your patch is doing when run on cpu without vid capability.
>> No, at least read/write TPR will not cause vmexit if virtualize x2apic 
>> mode
> is
> enabled.
> For that you need to disable 808H MSR intercept, which your patch does
> not
>>> do.
 I want to do this in next patch.
 
>>> Then don't. There is no point in the patch that enables virtualize
>>> x2apic and does not allow at least one non-intercepted MSR access.
>> As I said, read/write TPR will not cause vmexit if virtual x2apic is set.
>> 
> From my reading of the spec you need to disable 808H intercept for that.
> Is this not the case?
> 
>> I am not sure whether I understand your comments right in previous
>> discussion, here is my thinking: 1. enable virtualize x2apic mode if
>> guest is really using x2apic and clear TPR in msr read  and write
>> bitmap. This will benefit reading TPR. 2. If APIC registers
>> virtualization is enabled, clear all bit in rang
> 0x800-0x8ff(except apic id reg and tmcct).
> Clear all read bits in the range.
> 
>> 3. If vid is enabled, clear EOI and SELF IPI in msr write map.
>> 
> Looks OK.
> 
>> One concern you mentioned is that vid enabled and virtualize x2apic is
>>> disabled
> but guest still use x2apic. In this case, we still use MSR bitmap to
> intercept x2apic. This means the vEOI update will never happen. But we
> still can benefit from interrupt window.
>> 
> What interrupt windows? Without virtualized x2apic TPR/EOI
> virtualization will not happen and we rely on that in the code.
 Yes, but we can eliminate vmexit of interrupt window. Interrupt still can
>>> delivery to guest without vmexit when guest enables interrupt if vid
>>> is enabled. See SDM vol 3, 29.2.2.
 
>>> What does it matter that you eliminated vmexit of interrupt window if
>>> you broke everything else? The vid patch assumes that apic emulation
>>> either entirely happens in a software when vid is disabled or in a CPU
>>> if vid is enabled. Mixed mode will not work (apic->isr_count = 1 trick
>>> will break things for instance). And it is not worth it to complicate
>>> the code to make it work.
>> Yes, you are right. It too complicated.
>> Another question? Why not to hide x2apic capability to guest when vid is
> supported and virtual x2apic mode is not supported? It should be more
> reasonable than disable vid when virtual x2apic mode is unavailable.
>> 
> Because I think there will be no such HW. If such HW expected to be
> common then we can go this route.
Yes. No HW will support vid without supporting virtual x2apic mode. So we just 
ignore this case.

Best regards,
Yang


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Re: [PATCH v9 2/3] x86, apicv: add virtual x2apic support

2013-01-11 Thread Gleb Natapov 
On Fri, Jan 11, 2013 at 07:36:44AM +, Zhang, Yang Z wrote:
> Gleb Natapov wrote on 2013-01-10:
> > On Thu, Jan 10, 2013 at 12:22:51PM +, Zhang, Yang Z wrote:
> >> Gleb Natapov wrote on 2013-01-10:
> >>> On Thu, Jan 10, 2013 at 11:54:21AM +, Zhang, Yang Z wrote:
> >> The right logic should be:
> >> When register virtualization enabled, read all apic msr(except apic id 
> >> reg
> > and
> > tmcct which have the hook) not cause vmexit and only write TPR not cause
> > vmexit.
> >> When vid enabled, write to TPR, EOI and SELF IPI not cause vmexit.
> >> It's better to put the patch of envirtualize x2apic mode as first 
> >> patch.
> >> 
> > There is no point whatsoever to enable virtualize x2apic without
> > allowing at least one non intercepted access to x2apic MSR range and
> > this is what your patch is doing when run on cpu without vid capability.
>  No, at least read/write TPR will not cause vmexit if virtualize x2apic 
>  mode is
> >>> enabled.
> >>> For that you need to disable 808H MSR intercept, which your patch does not
> > do.
> >> I want to do this in next patch.
> >> 
> > Then don't. There is no point in the patch that enables virtualize
> > x2apic and does not allow at least one non-intercepted MSR access.
> As I said, read/write TPR will not cause vmexit if virtual x2apic is set.
> 
>From my reading of the spec you need to disable 808H intercept for that.
Is this not the case?

>  I am not sure whether I understand your comments right in previous
>  discussion, here is my thinking: 1. enable virtualize x2apic mode if
>  guest is really using x2apic and clear TPR in msr read  and write
>  bitmap. This will benefit reading TPR. 2. If APIC registers
>  virtualization is enabled, clear all bit in rang
> >>> 0x800-0x8ff(except apic id reg and tmcct).
> >>> Clear all read bits in the range.
> >>> 
>  3. If vid is enabled, clear EOI and SELF IPI in msr write map.
>  
> >>> Looks OK.
> >>> 
>  One concern you mentioned is that vid enabled and virtualize x2apic is
> > disabled
> >>> but guest still use x2apic. In this case, we still use MSR bitmap to
> >>> intercept x2apic. This means the vEOI update will never happen. But we
> >>> still can benefit from interrupt window.
>  
> >>> What interrupt windows? Without virtualized x2apic TPR/EOI
> >>> virtualization will not happen and we rely on that in the code.
> >> Yes, but we can eliminate vmexit of interrupt window. Interrupt still can
> > delivery to guest without vmexit when guest enables interrupt if vid is 
> > enabled.
> > See SDM vol 3, 29.2.2.
> >> 
> > What does it matter that you eliminated vmexit of interrupt window if
> > you broke everything else? The vid patch assumes that apic emulation
> > either entirely happens in a software when vid is disabled or in a CPU
> > if vid is enabled. Mixed mode will not work (apic->isr_count = 1 trick
> > will break things for instance). And it is not worth it to complicate
> > the code to make it work.
> Yes, you are right. It too complicated.
> Another question? Why not to hide x2apic capability to guest when vid is 
> supported and virtual x2apic mode is not supported? It should be more 
> reasonable than disable vid when virtual x2apic mode is unavailable.
> 
Because I think there will be no such HW. If such HW expected to be
common then we can go this route.

--
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Re: [PATCH v9 2/3] x86, apicv: add virtual x2apic support

2013-01-11 Thread Gleb Natapov 
On Fri, Jan 11, 2013 at 02:37:15AM +, Zhang, Yang Z wrote:
> Gleb Natapov wrote on 2013-01-10:
> > On Thu, Jan 10, 2013 at 08:32:06AM +, Zhang, Yang Z wrote:
> >> Gleb Natapov wrote on 2013-01-10:
> >>> On Thu, Jan 10, 2013 at 03:26:07PM +0800, Yang Zhang wrote:
>  From: Yang Zhang 
>  
>  basically to benefit from apicv, we need to enable virtualized x2apic 
>  mode.
>  Currently, we only enable it when guest is really using x2apic.
>  
>  Also, clear MSR bitmap for corresponding x2apic MSRs when guest enabled
> >>> x2apic:
>  0x800 - 0x8ff: no read intercept for apicv register virtualization,
>  except APIC ID and TMCCT.
>  APIC ID and TMCCT: need software's assistance to get right value.
>  TPR,EOI,SELF-IPI: no write intercept for virtual interrupt delivery.
>  Signed-off-by: Kevin Tian 
>  Signed-off-by: Yang Zhang 
>  ---
>   arch/x86/include/asm/kvm_host.h |2 + arch/x86/include/asm/vmx.h
> |1 + arch/x86/kvm/lapic.c|5 +-
> arch/x86/kvm/svm.c  |6 + arch/x86/kvm/vmx.c |  194
> +-- 5 files
> > changed, 200
>   insertions(+), 8 deletions(-)
>  diff --git a/arch/x86/include/asm/kvm_host.h
>  b/arch/x86/include/asm/kvm_host.h index c431b33..572a562 100644 ---
>  a/arch/x86/include/asm/kvm_host.h +++
>  b/arch/x86/include/asm/kvm_host.h @@ -697,6 +697,8 @@ struct
>  kvm_x86_ops {
>   void (*enable_nmi_window)(struct kvm_vcpu *vcpu);
>   void (*enable_irq_window)(struct kvm_vcpu *vcpu);
>   void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, 
>  int irr);
>  +void (*enable_virtual_x2apic_mode)(struct kvm_vcpu *vcpu);
>  +void (*disable_virtual_x2apic_mode)(struct kvm_vcpu *vcpu);
> >>> Make one callback with enable/disable parameter. And do not forget SVM.
> >>> 
>   int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
>   int (*get_tdp_level)(void);
>   u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool
> > is_mmio);
>  diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
>  index 44c3f7e..0a54df0 100644
>  --- a/arch/x86/include/asm/vmx.h
>  +++ b/arch/x86/include/asm/vmx.h
>  @@ -139,6 +139,7 @@
>   #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x0001 #define
>   SECONDARY_EXEC_ENABLE_EPT   0x0002 #define
>   SECONDARY_EXEC_RDTSCP   0x0008 +#define
>   SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE   0x0010 #define
>   SECONDARY_EXEC_ENABLE_VPID  0x0020 #define
>   SECONDARY_EXEC_WBINVD_EXITING   0x0040 #define
>   SECONDARY_EXEC_UNRESTRICTED_GUEST   0x0080
>  diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
>  index 0664c13..ec38906 100644
>  --- a/arch/x86/kvm/lapic.c
>  +++ b/arch/x86/kvm/lapic.c
>  @@ -1328,7 +1328,10 @@ void kvm_lapic_set_base(struct kvm_vcpu
> > *vcpu,
> >>> u64 value)
>   u32 id = kvm_apic_id(apic);
>   u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
>   kvm_apic_set_ldr(apic, ldr);
>  -}
>  +kvm_x86_ops->enable_virtual_x2apic_mode(vcpu);
>  +} else
>  +kvm_x86_ops->disable_virtual_x2apic_mode(vcpu);
>  +
> >>> You just broke SVM.
>   apic->base_address = apic->vcpu->arch.apic_base &
>    MSR_IA32_APICBASE_BASE;
>  diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
>  index d29d3cd..0b82cb1 100644
>  --- a/arch/x86/kvm/svm.c
>  +++ b/arch/x86/kvm/svm.c
>  @@ -3571,6 +3571,11 @@ static void update_cr8_intercept(struct
> > kvm_vcpu
> >>> *vcpu, int tpr, int irr)
>   set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
>   }
>  +static void svm_enable_virtual_x2apic_mode(struct kvm_vcpu *vcpu)
>  +{
>  +return;
>  +}
>  +
>   static int svm_nmi_allowed(struct kvm_vcpu *vcpu) { struct vcpu_svm
>   *svm = to_svm(vcpu); @@ -4290,6 +4295,7 @@ static struct kvm_x86_ops
>   svm_x86_ops = { .enable_nmi_window = enable_nmi_window,
>   .enable_irq_window = enable_irq_window, 
>  .update_cr8_intercept =
>   update_cr8_intercept,
>  +.enable_virtual_x2apic_mode = svm_enable_virtual_x2apic_mode,
>  
>   .set_tss_addr = svm_set_tss_addr,
>   .get_tdp_level = get_npt_level,
>  diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
>  index 688f43f..b203ce7 100644
>  --- a/arch/x86/kvm/vmx.c
>  +++ b/arch/x86/kvm/vmx.c
>  @@ -433,6 +433,8 @@ struct vcpu_vmx {
>  
>   bool rdtscp_enabled;
>  +bool virtual_x2apic_enabled;
>  +
> >

RE: [PATCH v9 2/3] x86, apicv: add virtual x2apic support

2013-01-10 Thread Zhang, Yang Z 
Gleb Natapov wrote on 2013-01-10:
> On Thu, Jan 10, 2013 at 12:22:51PM +, Zhang, Yang Z wrote:
>> Gleb Natapov wrote on 2013-01-10:
>>> On Thu, Jan 10, 2013 at 11:54:21AM +, Zhang, Yang Z wrote:
>> The right logic should be:
>> When register virtualization enabled, read all apic msr(except apic id 
>> reg
> and
> tmcct which have the hook) not cause vmexit and only write TPR not cause
> vmexit.
>> When vid enabled, write to TPR, EOI and SELF IPI not cause vmexit.
>> It's better to put the patch of envirtualize x2apic mode as first patch.
>> 
> There is no point whatsoever to enable virtualize x2apic without
> allowing at least one non intercepted access to x2apic MSR range and
> this is what your patch is doing when run on cpu without vid capability.
 No, at least read/write TPR will not cause vmexit if virtualize x2apic 
 mode is
>>> enabled.
>>> For that you need to disable 808H MSR intercept, which your patch does not
> do.
>> I want to do this in next patch.
>> 
> Then don't. There is no point in the patch that enables virtualize
> x2apic and does not allow at least one non-intercepted MSR access.
As I said, read/write TPR will not cause vmexit if virtual x2apic is set.

 I am not sure whether I understand your comments right in previous
 discussion, here is my thinking: 1. enable virtualize x2apic mode if
 guest is really using x2apic and clear TPR in msr read  and write
 bitmap. This will benefit reading TPR. 2. If APIC registers
 virtualization is enabled, clear all bit in rang
>>> 0x800-0x8ff(except apic id reg and tmcct).
>>> Clear all read bits in the range.
>>> 
 3. If vid is enabled, clear EOI and SELF IPI in msr write map.
 
>>> Looks OK.
>>> 
 One concern you mentioned is that vid enabled and virtualize x2apic is
> disabled
>>> but guest still use x2apic. In this case, we still use MSR bitmap to
>>> intercept x2apic. This means the vEOI update will never happen. But we
>>> still can benefit from interrupt window.
 
>>> What interrupt windows? Without virtualized x2apic TPR/EOI
>>> virtualization will not happen and we rely on that in the code.
>> Yes, but we can eliminate vmexit of interrupt window. Interrupt still can
> delivery to guest without vmexit when guest enables interrupt if vid is 
> enabled.
> See SDM vol 3, 29.2.2.
>> 
> What does it matter that you eliminated vmexit of interrupt window if
> you broke everything else? The vid patch assumes that apic emulation
> either entirely happens in a software when vid is disabled or in a CPU
> if vid is enabled. Mixed mode will not work (apic->isr_count = 1 trick
> will break things for instance). And it is not worth it to complicate
> the code to make it work.
Yes, you are right. It too complicated.
Another question? Why not to hide x2apic capability to guest when vid is 
supported and virtual x2apic mode is not supported? It should be more 
reasonable than disable vid when virtual x2apic mode is unavailable.

Best regards,
Yang


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RE: [PATCH v9 2/3] x86, apicv: add virtual x2apic support

2013-01-10 Thread Zhang, Yang Z 
Gleb Natapov wrote on 2013-01-10:
> On Thu, Jan 10, 2013 at 08:32:06AM +, Zhang, Yang Z wrote:
>> Gleb Natapov wrote on 2013-01-10:
>>> On Thu, Jan 10, 2013 at 03:26:07PM +0800, Yang Zhang wrote:
 From: Yang Zhang 
 
 basically to benefit from apicv, we need to enable virtualized x2apic mode.
 Currently, we only enable it when guest is really using x2apic.
 
 Also, clear MSR bitmap for corresponding x2apic MSRs when guest enabled
>>> x2apic:
 0x800 - 0x8ff: no read intercept for apicv register virtualization,
   except APIC ID and TMCCT.
 APIC ID and TMCCT: need software's assistance to get right value.
 TPR,EOI,SELF-IPI: no write intercept for virtual interrupt delivery.
 Signed-off-by: Kevin Tian 
 Signed-off-by: Yang Zhang 
 ---
  arch/x86/include/asm/kvm_host.h |2 + arch/x86/include/asm/vmx.h
|1 + arch/x86/kvm/lapic.c|5 +-
arch/x86/kvm/svm.c  |6 + arch/x86/kvm/vmx.c |  194
+-- 5 files
> changed, 200
  insertions(+), 8 deletions(-)
 diff --git a/arch/x86/include/asm/kvm_host.h
 b/arch/x86/include/asm/kvm_host.h index c431b33..572a562 100644 ---
 a/arch/x86/include/asm/kvm_host.h +++
 b/arch/x86/include/asm/kvm_host.h @@ -697,6 +697,8 @@ struct
 kvm_x86_ops {
void (*enable_nmi_window)(struct kvm_vcpu *vcpu);
void (*enable_irq_window)(struct kvm_vcpu *vcpu);
void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr);
 +  void (*enable_virtual_x2apic_mode)(struct kvm_vcpu *vcpu);
 +  void (*disable_virtual_x2apic_mode)(struct kvm_vcpu *vcpu);
>>> Make one callback with enable/disable parameter. And do not forget SVM.
>>> 
int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
int (*get_tdp_level)(void);
u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool
> is_mmio);
 diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
 index 44c3f7e..0a54df0 100644
 --- a/arch/x86/include/asm/vmx.h
 +++ b/arch/x86/include/asm/vmx.h
 @@ -139,6 +139,7 @@
  #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x0001 #define
  SECONDARY_EXEC_ENABLE_EPT   0x0002 #define
  SECONDARY_EXEC_RDTSCP 0x0008 +#define
  SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE   0x0010 #define
  SECONDARY_EXEC_ENABLE_VPID  0x0020 #define
  SECONDARY_EXEC_WBINVD_EXITING 0x0040 #define
  SECONDARY_EXEC_UNRESTRICTED_GUEST 0x0080
 diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
 index 0664c13..ec38906 100644
 --- a/arch/x86/kvm/lapic.c
 +++ b/arch/x86/kvm/lapic.c
 @@ -1328,7 +1328,10 @@ void kvm_lapic_set_base(struct kvm_vcpu
> *vcpu,
>>> u64 value)
u32 id = kvm_apic_id(apic);
u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
kvm_apic_set_ldr(apic, ldr);
 -  }
 +  kvm_x86_ops->enable_virtual_x2apic_mode(vcpu);
 +  } else
 +  kvm_x86_ops->disable_virtual_x2apic_mode(vcpu);
 +
>>> You just broke SVM.
apic->base_address = apic->vcpu->arch.apic_base &
 MSR_IA32_APICBASE_BASE;
 diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
 index d29d3cd..0b82cb1 100644
 --- a/arch/x86/kvm/svm.c
 +++ b/arch/x86/kvm/svm.c
 @@ -3571,6 +3571,11 @@ static void update_cr8_intercept(struct
> kvm_vcpu
>>> *vcpu, int tpr, int irr)
set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
  }
 +static void svm_enable_virtual_x2apic_mode(struct kvm_vcpu *vcpu)
 +{
 +  return;
 +}
 +
  static int svm_nmi_allowed(struct kvm_vcpu *vcpu) {   struct vcpu_svm
  *svm = to_svm(vcpu); @@ -4290,6 +4295,7 @@ static struct kvm_x86_ops
  svm_x86_ops = {   .enable_nmi_window = enable_nmi_window,
.enable_irq_window = enable_irq_window, .update_cr8_intercept =
  update_cr8_intercept,
 +  .enable_virtual_x2apic_mode = svm_enable_virtual_x2apic_mode,
 
.set_tss_addr = svm_set_tss_addr,
.get_tdp_level = get_npt_level,
 diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
 index 688f43f..b203ce7 100644
 --- a/arch/x86/kvm/vmx.c
 +++ b/arch/x86/kvm/vmx.c
 @@ -433,6 +433,8 @@ struct vcpu_vmx {
 
bool rdtscp_enabled;
 +  bool virtual_x2apic_enabled;
 +
/* Support for a guest hypervisor (nested VMX) */
struct nested_vmx nested;
  };
 @@ -767,12 +769,23 @@ static inline bool
>>> cpu_has_vmx_virtualize_apic_accesses(void)
SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
  }
 +static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
 +{
 +  return vmcs_config.cpu_based_2nd_exec_ctrl &
 +  SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
 +}

Re: [PATCH v9 2/3] x86, apicv: add virtual x2apic support

2013-01-10 Thread Gleb Natapov 
On Thu, Jan 10, 2013 at 12:22:51PM +, Zhang, Yang Z wrote:
> Gleb Natapov wrote on 2013-01-10:
> > On Thu, Jan 10, 2013 at 11:54:21AM +, Zhang, Yang Z wrote:
>  The right logic should be:
>  When register virtualization enabled, read all apic msr(except apic id 
>  reg and
> >>> tmcct which have the hook) not cause vmexit and only write TPR not cause
> >>> vmexit.
>  When vid enabled, write to TPR, EOI and SELF IPI not cause vmexit.
>  It's better to put the patch of envirtualize x2apic mode as first patch.
>  
> >>> There is no point whatsoever to enable virtualize x2apic without
> >>> allowing at least one non intercepted access to x2apic MSR range and
> >>> this is what your patch is doing when run on cpu without vid capability.
> >> No, at least read/write TPR will not cause vmexit if virtualize x2apic 
> >> mode is
> > enabled.
> > For that you need to disable 808H MSR intercept, which your patch does not 
> > do.
> I want to do this in next patch.
>  
Then don't. There is no point in the patch that enables virtualize
x2apic and does not allow at least one non-intercepted MSR access.

> >> I am not sure whether I understand your comments right in previous
> >> discussion, here is my thinking: 1. enable virtualize x2apic mode if
> >> guest is really using x2apic and clear TPR in msr read  and write
> >> bitmap. This will benefit reading TPR. 2. If APIC registers
> >> virtualization is enabled, clear all bit in rang
> > 0x800-0x8ff(except apic id reg and tmcct).
> > Clear all read bits in the range.
> > 
> >> 3. If vid is enabled, clear EOI and SELF IPI in msr write map.
> >> 
> > Looks OK.
> > 
> >> One concern you mentioned is that vid enabled and virtualize x2apic is 
> >> disabled
> > but guest still use x2apic. In this case, we still use MSR bitmap to 
> > intercept x2apic.
> > This means the vEOI update will never happen. But we still can benefit from
> > interrupt window.
> >> 
> > What interrupt windows? Without virtualized x2apic TPR/EOI
> > virtualization will not happen and we rely on that in the code.
> Yes, but we can eliminate vmexit of interrupt window. Interrupt still can 
> delivery to guest without vmexit when guest enables interrupt if vid is 
> enabled. See SDM vol 3, 29.2.2.
> 
What does it matter that you eliminated vmexit of interrupt window if
you broke everything else? The vid patch assumes that apic emulation
either entirely happens in a software when vid is disabled or in a CPU
if vid is enabled. Mixed mode will not work (apic->isr_count = 1 trick
will break things for instance). And it is not worth it to complicate
the code to make it work.

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RE: [PATCH v9 2/3] x86, apicv: add virtual x2apic support

2013-01-10 Thread Zhang, Yang Z 
Gleb Natapov wrote on 2013-01-10:
> On Thu, Jan 10, 2013 at 11:54:21AM +, Zhang, Yang Z wrote:
 The right logic should be:
 When register virtualization enabled, read all apic msr(except apic id reg 
 and
>>> tmcct which have the hook) not cause vmexit and only write TPR not cause
>>> vmexit.
 When vid enabled, write to TPR, EOI and SELF IPI not cause vmexit.
 It's better to put the patch of envirtualize x2apic mode as first patch.
 
>>> There is no point whatsoever to enable virtualize x2apic without
>>> allowing at least one non intercepted access to x2apic MSR range and
>>> this is what your patch is doing when run on cpu without vid capability.
>> No, at least read/write TPR will not cause vmexit if virtualize x2apic mode 
>> is
> enabled.
> For that you need to disable 808H MSR intercept, which your patch does not do.
I want to do this in next patch.
 
>> I am not sure whether I understand your comments right in previous
>> discussion, here is my thinking: 1. enable virtualize x2apic mode if
>> guest is really using x2apic and clear TPR in msr read  and write
>> bitmap. This will benefit reading TPR. 2. If APIC registers
>> virtualization is enabled, clear all bit in rang
> 0x800-0x8ff(except apic id reg and tmcct).
> Clear all read bits in the range.
> 
>> 3. If vid is enabled, clear EOI and SELF IPI in msr write map.
>> 
> Looks OK.
> 
>> One concern you mentioned is that vid enabled and virtualize x2apic is 
>> disabled
> but guest still use x2apic. In this case, we still use MSR bitmap to 
> intercept x2apic.
> This means the vEOI update will never happen. But we still can benefit from
> interrupt window.
>> 
> What interrupt windows? Without virtualized x2apic TPR/EOI
> virtualization will not happen and we rely on that in the code.
Yes, but we can eliminate vmexit of interrupt window. Interrupt still can 
delivery to guest without vmexit when guest enables interrupt if vid is 
enabled. See SDM vol 3, 29.2.2.

Best regards,
Yang


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Re: [PATCH v9 2/3] x86, apicv: add virtual x2apic support

2013-01-10 Thread Gleb Natapov 
On Thu, Jan 10, 2013 at 11:54:21AM +, Zhang, Yang Z wrote:
> >> The right logic should be:
> >> When register virtualization enabled, read all apic msr(except apic id reg 
> >> and
> > tmcct which have the hook) not cause vmexit and only write TPR not cause
> > vmexit.
> >> When vid enabled, write to TPR, EOI and SELF IPI not cause vmexit.
> >> It's better to put the patch of envirtualize x2apic mode as first patch.
> >> 
> > There is no point whatsoever to enable virtualize x2apic without
> > allowing at least one non intercepted access to x2apic MSR range and
> > this is what your patch is doing when run on cpu without vid capability.
> No, at least read/write TPR will not cause vmexit if virtualize x2apic mode 
> is enabled.
For that you need to disable 808H MSR intercept, which your patch does not do.

> I am not sure whether I understand your comments right in previous 
> discussion, here is my thinking:
> 1. enable virtualize x2apic mode if guest is really using x2apic and clear 
> TPR in msr read  and write bitmap. This will benefit reading TPR.
> 2. If APIC registers virtualization is enabled, clear all bit in rang 
> 0x800-0x8ff(except apic id reg and tmcct).
Clear all read bits in the range.

> 3. If vid is enabled, clear EOI and SELF IPI in msr write map.
> 
Looks OK.

> One concern you mentioned is that vid enabled and virtualize x2apic is 
> disabled but guest still use x2apic. In this case, we still use MSR bitmap to 
> intercept x2apic. This means the vEOI update will never happen. But we still 
> can benefit from interrupt window.
> 
What interrupt windows? Without virtualized x2apic TPR/EOI
virtualization will not happen and we rely on that in the code.

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RE: [PATCH v9 2/3] x86, apicv: add virtual x2apic support

2013-01-10 Thread Zhang, Yang Z 
Gleb Natapov wrote on 2013-01-10:
> On Thu, Jan 10, 2013 at 08:32:06AM +, Zhang, Yang Z wrote:
>> Gleb Natapov wrote on 2013-01-10:
>>> On Thu, Jan 10, 2013 at 03:26:07PM +0800, Yang Zhang wrote:
 From: Yang Zhang 
 
 basically to benefit from apicv, we need to enable virtualized x2apic mode.
 Currently, we only enable it when guest is really using x2apic.
 
 Also, clear MSR bitmap for corresponding x2apic MSRs when guest enabled
>>> x2apic:
 0x800 - 0x8ff: no read intercept for apicv register virtualization,
   except APIC ID and TMCCT.
 APIC ID and TMCCT: need software's assistance to get right value.
 TPR,EOI,SELF-IPI: no write intercept for virtual interrupt delivery.
 Signed-off-by: Kevin Tian 
 Signed-off-by: Yang Zhang 
 ---
  arch/x86/include/asm/kvm_host.h |2 + arch/x86/include/asm/vmx.h
|1 + arch/x86/kvm/lapic.c|5 +-
arch/x86/kvm/svm.c  |6 + arch/x86/kvm/vmx.c |  194
+-- 5 files
> changed, 200
  insertions(+), 8 deletions(-)
 diff --git a/arch/x86/include/asm/kvm_host.h
 b/arch/x86/include/asm/kvm_host.h index c431b33..572a562 100644 ---
 a/arch/x86/include/asm/kvm_host.h +++
 b/arch/x86/include/asm/kvm_host.h @@ -697,6 +697,8 @@ struct
 kvm_x86_ops {
void (*enable_nmi_window)(struct kvm_vcpu *vcpu);
void (*enable_irq_window)(struct kvm_vcpu *vcpu);
void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr);
 +  void (*enable_virtual_x2apic_mode)(struct kvm_vcpu *vcpu);
 +  void (*disable_virtual_x2apic_mode)(struct kvm_vcpu *vcpu);
>>> Make one callback with enable/disable parameter. And do not forget SVM.
>>> 
int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
int (*get_tdp_level)(void);
u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool
> is_mmio);
 diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
 index 44c3f7e..0a54df0 100644
 --- a/arch/x86/include/asm/vmx.h
 +++ b/arch/x86/include/asm/vmx.h
 @@ -139,6 +139,7 @@
  #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x0001 #define
  SECONDARY_EXEC_ENABLE_EPT   0x0002 #define
  SECONDARY_EXEC_RDTSCP 0x0008 +#define
  SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE   0x0010 #define
  SECONDARY_EXEC_ENABLE_VPID  0x0020 #define
  SECONDARY_EXEC_WBINVD_EXITING 0x0040 #define
  SECONDARY_EXEC_UNRESTRICTED_GUEST 0x0080
 diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
 index 0664c13..ec38906 100644
 --- a/arch/x86/kvm/lapic.c
 +++ b/arch/x86/kvm/lapic.c
 @@ -1328,7 +1328,10 @@ void kvm_lapic_set_base(struct kvm_vcpu
> *vcpu,
>>> u64 value)
u32 id = kvm_apic_id(apic);
u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
kvm_apic_set_ldr(apic, ldr);
 -  }
 +  kvm_x86_ops->enable_virtual_x2apic_mode(vcpu);
 +  } else
 +  kvm_x86_ops->disable_virtual_x2apic_mode(vcpu);
 +
>>> You just broke SVM.
apic->base_address = apic->vcpu->arch.apic_base &
 MSR_IA32_APICBASE_BASE;
 diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
 index d29d3cd..0b82cb1 100644
 --- a/arch/x86/kvm/svm.c
 +++ b/arch/x86/kvm/svm.c
 @@ -3571,6 +3571,11 @@ static void update_cr8_intercept(struct
> kvm_vcpu
>>> *vcpu, int tpr, int irr)
set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
  }
 +static void svm_enable_virtual_x2apic_mode(struct kvm_vcpu *vcpu)
 +{
 +  return;
 +}
 +
  static int svm_nmi_allowed(struct kvm_vcpu *vcpu) {   struct vcpu_svm
  *svm = to_svm(vcpu); @@ -4290,6 +4295,7 @@ static struct kvm_x86_ops
  svm_x86_ops = {   .enable_nmi_window = enable_nmi_window,
.enable_irq_window = enable_irq_window, .update_cr8_intercept =
  update_cr8_intercept,
 +  .enable_virtual_x2apic_mode = svm_enable_virtual_x2apic_mode,
 
.set_tss_addr = svm_set_tss_addr,
.get_tdp_level = get_npt_level,
 diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
 index 688f43f..b203ce7 100644
 --- a/arch/x86/kvm/vmx.c
 +++ b/arch/x86/kvm/vmx.c
 @@ -433,6 +433,8 @@ struct vcpu_vmx {
 
bool rdtscp_enabled;
 +  bool virtual_x2apic_enabled;
 +
/* Support for a guest hypervisor (nested VMX) */
struct nested_vmx nested;
  };
 @@ -767,12 +769,23 @@ static inline bool
>>> cpu_has_vmx_virtualize_apic_accesses(void)
SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
  }
 +static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
 +{
 +  return vmcs_config.cpu_based_2nd_exec_ctrl &
 +  SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
 +}

Re: [PATCH v9 2/3] x86, apicv: add virtual x2apic support

2013-01-10 Thread Gleb Natapov 
On Thu, Jan 10, 2013 at 08:31:51AM +, Zhang, Yang Z wrote:
> Gleb Natapov wrote on 2013-01-10:
> > On Thu, Jan 10, 2013 at 03:26:07PM +0800, Yang Zhang wrote:
> >> +static void vmx_enable_virtual_x2apic_mode(struct kvm_vcpu *vcpu)
> >> +{
> >> +  u32 exec_control;
> >> +  int msr;
> >> +  struct vcpu_vmx *vmx = to_vmx(vcpu);
> >> +
> >> +  if (!cpu_has_vmx_virtualize_x2apic_mode())
> >> +  return;
> >> +
> >> +  exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
> >> +  /* virtualize x2apic mode relies on tpr shadow */
> >> +  if (!(exec_control & CPU_BASED_TPR_SHADOW))
> >> +  return;
> >> +
> >> +  exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
> >> +  exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
> >> +  exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
> >> +  vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
> >> +  vmx->virtual_x2apic_enabled = true;
> >> +
> >> +  if (!cpu_has_vmx_virtual_intr_delivery())
> >> +  return;
> >> +
> >> +  for (msr = 0x800; msr <= 0x8ff; msr++)
> >> +  vmx_intercept_for_msr_read(msr, false, false);
> >> +
> >> +  /* APIC ID */
> >> +  vmx_intercept_for_msr_read(0x802, false, true);
> > Why are you enabling apic id read intercept?
> Current code to read apic id in x2apic mode has some hacks:
> 
> if (apic_x2apic_mode(apic))
>val = kvm_apic_id(apic);
> else
>val = kvm_apic_id(apic) << 24;
> 
> static inline int kvm_apic_id(struct kvm_lapic *apic)
> {
> return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
> }
> 
> According SPEC, in x2apic mode, the whole id reg is used, but in KVM, it only 
> use the highest eight bits.
> 
Correct. Put the comment above apic id intercept that we do that since
in x2apic mode apic id is not correctly reflected in apic page.

> >> +  /* TMCCT */
> >> +  vmx_intercept_for_msr_read(0x839, false, true);
> >> +  /* TPR */
> >> +  vmx_intercept_for_msr_write(0x808, false, false);
> >> +  /* EOI */
> >> +  vmx_intercept_for_msr_write(0x80b, false, false);
> >> +  /* SELF-IPI */
> >> +  vmx_intercept_for_msr_write(0x83f, false, false);
> >> +
> >> +}
> >> +
> > 
> > --
> > Gleb.
> 
> 
> Best regards,
> Yang
> 

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Re: [PATCH v9 2/3] x86, apicv: add virtual x2apic support

2013-01-10 Thread Gleb Natapov 
On Thu, Jan 10, 2013 at 08:32:06AM +, Zhang, Yang Z wrote:
> Gleb Natapov wrote on 2013-01-10:
> > On Thu, Jan 10, 2013 at 03:26:07PM +0800, Yang Zhang wrote:
> >> From: Yang Zhang 
> >> 
> >> basically to benefit from apicv, we need to enable virtualized x2apic mode.
> >> Currently, we only enable it when guest is really using x2apic.
> >> 
> >> Also, clear MSR bitmap for corresponding x2apic MSRs when guest enabled
> > x2apic:
> >> 0x800 - 0x8ff: no read intercept for apicv register virtualization,
> >>   except APIC ID and TMCCT.
> >> APIC ID and TMCCT: need software's assistance to get right value.
> >> TPR,EOI,SELF-IPI: no write intercept for virtual interrupt delivery.
> >> Signed-off-by: Kevin Tian 
> >> Signed-off-by: Yang Zhang 
> >> ---
> >>  arch/x86/include/asm/kvm_host.h |2 + arch/x86/include/asm/vmx.h   
> >>|1 + arch/x86/kvm/lapic.c|5 +-
> >>  arch/x86/kvm/svm.c  |6 + arch/x86/kvm/vmx.c   
> >>|  194 +-- 5 files changed, 200
> >>  insertions(+), 8 deletions(-)
> >> diff --git a/arch/x86/include/asm/kvm_host.h
> >> b/arch/x86/include/asm/kvm_host.h index c431b33..572a562 100644 ---
> >> a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h
> >> @@ -697,6 +697,8 @@ struct kvm_x86_ops {
> >>void (*enable_nmi_window)(struct kvm_vcpu *vcpu);
> >>void (*enable_irq_window)(struct kvm_vcpu *vcpu);
> >>void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr);
> >> +  void (*enable_virtual_x2apic_mode)(struct kvm_vcpu *vcpu);
> >> +  void (*disable_virtual_x2apic_mode)(struct kvm_vcpu *vcpu);
> > Make one callback with enable/disable parameter. And do not forget SVM.
> > 
> >>int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
> >>int (*get_tdp_level)(void);
> >>u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio);
> >> diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
> >> index 44c3f7e..0a54df0 100644
> >> --- a/arch/x86/include/asm/vmx.h
> >> +++ b/arch/x86/include/asm/vmx.h
> >> @@ -139,6 +139,7 @@
> >>  #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x0001 #define
> >>  SECONDARY_EXEC_ENABLE_EPT   0x0002 #define
> >>  SECONDARY_EXEC_RDTSCP 0x0008 +#define
> >>  SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE   0x0010 #define
> >>  SECONDARY_EXEC_ENABLE_VPID  0x0020 #define
> >>  SECONDARY_EXEC_WBINVD_EXITING 0x0040 #define
> >>  SECONDARY_EXEC_UNRESTRICTED_GUEST 0x0080
> >> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
> >> index 0664c13..ec38906 100644
> >> --- a/arch/x86/kvm/lapic.c
> >> +++ b/arch/x86/kvm/lapic.c
> >> @@ -1328,7 +1328,10 @@ void kvm_lapic_set_base(struct kvm_vcpu *vcpu,
> > u64 value)
> >>u32 id = kvm_apic_id(apic);
> >>u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
> >>kvm_apic_set_ldr(apic, ldr);
> >> -  }
> >> +  kvm_x86_ops->enable_virtual_x2apic_mode(vcpu);
> >> +  } else
> >> +  kvm_x86_ops->disable_virtual_x2apic_mode(vcpu);
> >> +
> > You just broke SVM.
> >>apic->base_address = apic->vcpu->arch.apic_base &
> >> MSR_IA32_APICBASE_BASE;
> >> diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
> >> index d29d3cd..0b82cb1 100644
> >> --- a/arch/x86/kvm/svm.c
> >> +++ b/arch/x86/kvm/svm.c
> >> @@ -3571,6 +3571,11 @@ static void update_cr8_intercept(struct kvm_vcpu
> > *vcpu, int tpr, int irr)
> >>set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
> >>  }
> >> +static void svm_enable_virtual_x2apic_mode(struct kvm_vcpu *vcpu)
> >> +{
> >> +  return;
> >> +}
> >> +
> >>  static int svm_nmi_allowed(struct kvm_vcpu *vcpu) {   struct vcpu_svm
> >>  *svm = to_svm(vcpu); @@ -4290,6 +4295,7 @@ static struct kvm_x86_ops
> >>  svm_x86_ops = {   .enable_nmi_window = enable_nmi_window,
> >>.enable_irq_window = enable_irq_window, .update_cr8_intercept =
> >>  update_cr8_intercept,
> >> +  .enable_virtual_x2apic_mode = svm_enable_virtual_x2apic_mode,
> >> 
> >>.set_tss_addr = svm_set_tss_addr,
> >>.get_tdp_level = get_npt_level,
> >> diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
> >> index 688f43f..b203ce7 100644
> >> --- a/arch/x86/kvm/vmx.c
> >> +++ b/arch/x86/kvm/vmx.c
> >> @@ -433,6 +433,8 @@ struct vcpu_vmx {
> >> 
> >>bool rdtscp_enabled;
> >> +  bool virtual_x2apic_enabled;
> >> +
> >>/* Support for a guest hypervisor (nested VMX) */
> >>struct nested_vmx nested;
> >>  };
> >> @@ -767,12 +769,23 @@ static inline bool
> > cpu_has_vmx_virtualize_apic_accesses(void)
> >>SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
> >>  }
> >> +static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
> >> +{
> >> +  return vmcs_config.cpu_based_2nd_exec_ctrl &
> >> +  SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
> >> +}
> >> +
> >>  static inline bool cpu_h

RE: [PATCH v9 2/3] x86, apicv: add virtual x2apic support

2013-01-10 Thread Zhang, Yang Z 
Gleb Natapov wrote on 2013-01-10:
> On Thu, Jan 10, 2013 at 03:26:07PM +0800, Yang Zhang wrote:
>> From: Yang Zhang 
>> 
>> basically to benefit from apicv, we need to enable virtualized x2apic mode.
>> Currently, we only enable it when guest is really using x2apic.
>> 
>> Also, clear MSR bitmap for corresponding x2apic MSRs when guest enabled
> x2apic:
>> 0x800 - 0x8ff: no read intercept for apicv register virtualization,
>> except APIC ID and TMCCT.
>> APIC ID and TMCCT: need software's assistance to get right value.
>> TPR,EOI,SELF-IPI: no write intercept for virtual interrupt delivery.
>> Signed-off-by: Kevin Tian 
>> Signed-off-by: Yang Zhang 
>> ---
>>  arch/x86/include/asm/kvm_host.h |2 + arch/x86/include/asm/vmx.h   
>>|1 + arch/x86/kvm/lapic.c|5 +-
>>  arch/x86/kvm/svm.c  |6 + arch/x86/kvm/vmx.c   
>>|  194 +-- 5 files changed, 200
>>  insertions(+), 8 deletions(-)
>> diff --git a/arch/x86/include/asm/kvm_host.h
>> b/arch/x86/include/asm/kvm_host.h index c431b33..572a562 100644 ---
>> a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h
>> @@ -697,6 +697,8 @@ struct kvm_x86_ops {
>>  void (*enable_nmi_window)(struct kvm_vcpu *vcpu);
>>  void (*enable_irq_window)(struct kvm_vcpu *vcpu);
>>  void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr);
>> +void (*enable_virtual_x2apic_mode)(struct kvm_vcpu *vcpu);
>> +void (*disable_virtual_x2apic_mode)(struct kvm_vcpu *vcpu);
> Make one callback with enable/disable parameter. And do not forget SVM.
> 
>>  int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
>>  int (*get_tdp_level)(void);
>>  u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio);
>> diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
>> index 44c3f7e..0a54df0 100644
>> --- a/arch/x86/include/asm/vmx.h
>> +++ b/arch/x86/include/asm/vmx.h
>> @@ -139,6 +139,7 @@
>>  #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x0001 #define
>>  SECONDARY_EXEC_ENABLE_EPT   0x0002 #define
>>  SECONDARY_EXEC_RDTSCP   0x0008 +#define
>>  SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE   0x0010 #define
>>  SECONDARY_EXEC_ENABLE_VPID  0x0020 #define
>>  SECONDARY_EXEC_WBINVD_EXITING   0x0040 #define
>>  SECONDARY_EXEC_UNRESTRICTED_GUEST   0x0080
>> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
>> index 0664c13..ec38906 100644
>> --- a/arch/x86/kvm/lapic.c
>> +++ b/arch/x86/kvm/lapic.c
>> @@ -1328,7 +1328,10 @@ void kvm_lapic_set_base(struct kvm_vcpu *vcpu,
> u64 value)
>>  u32 id = kvm_apic_id(apic);
>>  u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
>>  kvm_apic_set_ldr(apic, ldr);
>> -}
>> +kvm_x86_ops->enable_virtual_x2apic_mode(vcpu);
>> +} else
>> +kvm_x86_ops->disable_virtual_x2apic_mode(vcpu);
>> +
> You just broke SVM.
>>  apic->base_address = apic->vcpu->arch.apic_base &
>>   MSR_IA32_APICBASE_BASE;
>> diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
>> index d29d3cd..0b82cb1 100644
>> --- a/arch/x86/kvm/svm.c
>> +++ b/arch/x86/kvm/svm.c
>> @@ -3571,6 +3571,11 @@ static void update_cr8_intercept(struct kvm_vcpu
> *vcpu, int tpr, int irr)
>>  set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
>>  }
>> +static void svm_enable_virtual_x2apic_mode(struct kvm_vcpu *vcpu)
>> +{
>> +return;
>> +}
>> +
>>  static int svm_nmi_allowed(struct kvm_vcpu *vcpu) { struct vcpu_svm
>>  *svm = to_svm(vcpu); @@ -4290,6 +4295,7 @@ static struct kvm_x86_ops
>>  svm_x86_ops = { .enable_nmi_window = enable_nmi_window,
>>  .enable_irq_window = enable_irq_window, .update_cr8_intercept =
>>  update_cr8_intercept,
>> +.enable_virtual_x2apic_mode = svm_enable_virtual_x2apic_mode,
>> 
>>  .set_tss_addr = svm_set_tss_addr,
>>  .get_tdp_level = get_npt_level,
>> diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
>> index 688f43f..b203ce7 100644
>> --- a/arch/x86/kvm/vmx.c
>> +++ b/arch/x86/kvm/vmx.c
>> @@ -433,6 +433,8 @@ struct vcpu_vmx {
>> 
>>  bool rdtscp_enabled;
>> +bool virtual_x2apic_enabled;
>> +
>>  /* Support for a guest hypervisor (nested VMX) */
>>  struct nested_vmx nested;
>>  };
>> @@ -767,12 +769,23 @@ static inline bool
> cpu_has_vmx_virtualize_apic_accesses(void)
>>  SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
>>  }
>> +static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
>> +{
>> +return vmcs_config.cpu_based_2nd_exec_ctrl &
>> +SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
>> +}
>> +
>>  static inline bool cpu_has_vmx_apic_register_virt(void)
>>  {
>>  return vmcs_config.cpu_based_2nd_exec_ctrl &
>>  SECONDARY_EXEC_APIC_REGISTER_VIRT;
>>  }
>> +static inline bool cpu_has_vmx_virtual_intr_delivery(void)
>> +{

RE: [PATCH v9 2/3] x86, apicv: add virtual x2apic support

2013-01-10 Thread Zhang, Yang Z 
Gleb Natapov wrote on 2013-01-10:
> On Thu, Jan 10, 2013 at 03:26:07PM +0800, Yang Zhang wrote:
>> +static void vmx_enable_virtual_x2apic_mode(struct kvm_vcpu *vcpu)
>> +{
>> +u32 exec_control;
>> +int msr;
>> +struct vcpu_vmx *vmx = to_vmx(vcpu);
>> +
>> +if (!cpu_has_vmx_virtualize_x2apic_mode())
>> +return;
>> +
>> +exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
>> +/* virtualize x2apic mode relies on tpr shadow */
>> +if (!(exec_control & CPU_BASED_TPR_SHADOW))
>> +return;
>> +
>> +exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
>> +exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
>> +exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
>> +vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
>> +vmx->virtual_x2apic_enabled = true;
>> +
>> +if (!cpu_has_vmx_virtual_intr_delivery())
>> +return;
>> +
>> +for (msr = 0x800; msr <= 0x8ff; msr++)
>> +vmx_intercept_for_msr_read(msr, false, false);
>> +
>> +/* APIC ID */
>> +vmx_intercept_for_msr_read(0x802, false, true);
> Why are you enabling apic id read intercept?
Current code to read apic id in x2apic mode has some hacks:

if (apic_x2apic_mode(apic))
   val = kvm_apic_id(apic);
else
   val = kvm_apic_id(apic) << 24;

static inline int kvm_apic_id(struct kvm_lapic *apic)
{
return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
}

According SPEC, in x2apic mode, the whole id reg is used, but in KVM, it only 
use the highest eight bits.

>> +/* TMCCT */
>> +vmx_intercept_for_msr_read(0x839, false, true);
>> +/* TPR */
>> +vmx_intercept_for_msr_write(0x808, false, false);
>> +/* EOI */
>> +vmx_intercept_for_msr_write(0x80b, false, false);
>> +/* SELF-IPI */
>> +vmx_intercept_for_msr_write(0x83f, false, false);
>> +
>> +}
>> +
> 
> --
>   Gleb.


Best regards,
Yang


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Re: [PATCH v9 2/3] x86, apicv: add virtual x2apic support

2013-01-10 Thread Gleb Natapov 
On Thu, Jan 10, 2013 at 03:26:07PM +0800, Yang Zhang wrote:
> +static void vmx_enable_virtual_x2apic_mode(struct kvm_vcpu *vcpu)
> +{
> + u32 exec_control;
> + int msr;
> + struct vcpu_vmx *vmx = to_vmx(vcpu);
> +
> + if (!cpu_has_vmx_virtualize_x2apic_mode())
> + return;
> +
> + exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
> + /* virtualize x2apic mode relies on tpr shadow */
> + if (!(exec_control & CPU_BASED_TPR_SHADOW))
> + return;
> +
> + exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
> + exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
> + exec_control |= SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
> + vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
> + vmx->virtual_x2apic_enabled = true;
> +
> + if (!cpu_has_vmx_virtual_intr_delivery())
> + return;
> +
> + for (msr = 0x800; msr <= 0x8ff; msr++)
> + vmx_intercept_for_msr_read(msr, false, false);
> +
> + /* APIC ID */
> + vmx_intercept_for_msr_read(0x802, false, true);
Why are you enabling apic id read intercept?

> + /* TMCCT */
> + vmx_intercept_for_msr_read(0x839, false, true);
> + /* TPR */
> + vmx_intercept_for_msr_write(0x808, false, false);
> + /* EOI */
> + vmx_intercept_for_msr_write(0x80b, false, false);
> + /* SELF-IPI */
> + vmx_intercept_for_msr_write(0x83f, false, false);
> +
> +}
> +

--
Gleb.
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Re: [PATCH v9 2/3] x86, apicv: add virtual x2apic support

2013-01-09 Thread Gleb Natapov 
On Thu, Jan 10, 2013 at 03:26:07PM +0800, Yang Zhang wrote:
> From: Yang Zhang 
> 
> basically to benefit from apicv, we need to enable virtualized x2apic mode.
> Currently, we only enable it when guest is really using x2apic.
> 
> Also, clear MSR bitmap for corresponding x2apic MSRs when guest enabled 
> x2apic:
> 0x800 - 0x8ff: no read intercept for apicv register virtualization,
>  except APIC ID and TMCCT.
> APIC ID and TMCCT: need software's assistance to get right value.
> TPR,EOI,SELF-IPI: no write intercept for virtual interrupt delivery.
> 
> Signed-off-by: Kevin Tian 
> Signed-off-by: Yang Zhang 
> ---
>  arch/x86/include/asm/kvm_host.h |2 +
>  arch/x86/include/asm/vmx.h  |1 +
>  arch/x86/kvm/lapic.c|5 +-
>  arch/x86/kvm/svm.c  |6 +
>  arch/x86/kvm/vmx.c  |  194 
> +--
>  5 files changed, 200 insertions(+), 8 deletions(-)
> 
> diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
> index c431b33..572a562 100644
> --- a/arch/x86/include/asm/kvm_host.h
> +++ b/arch/x86/include/asm/kvm_host.h
> @@ -697,6 +697,8 @@ struct kvm_x86_ops {
>   void (*enable_nmi_window)(struct kvm_vcpu *vcpu);
>   void (*enable_irq_window)(struct kvm_vcpu *vcpu);
>   void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr);
> + void (*enable_virtual_x2apic_mode)(struct kvm_vcpu *vcpu);
> + void (*disable_virtual_x2apic_mode)(struct kvm_vcpu *vcpu);
Make one callback with enable/disable parameter. And do not forget SVM.


>   int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
>   int (*get_tdp_level)(void);
>   u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio);
> diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
> index 44c3f7e..0a54df0 100644
> --- a/arch/x86/include/asm/vmx.h
> +++ b/arch/x86/include/asm/vmx.h
> @@ -139,6 +139,7 @@
>  #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x0001
>  #define SECONDARY_EXEC_ENABLE_EPT   0x0002
>  #define SECONDARY_EXEC_RDTSCP0x0008
> +#define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE   0x0010
>  #define SECONDARY_EXEC_ENABLE_VPID  0x0020
>  #define SECONDARY_EXEC_WBINVD_EXITING0x0040
>  #define SECONDARY_EXEC_UNRESTRICTED_GUEST0x0080
> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
> index 0664c13..ec38906 100644
> --- a/arch/x86/kvm/lapic.c
> +++ b/arch/x86/kvm/lapic.c
> @@ -1328,7 +1328,10 @@ void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 
> value)
>   u32 id = kvm_apic_id(apic);
>   u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
>   kvm_apic_set_ldr(apic, ldr);
> - }
> + kvm_x86_ops->enable_virtual_x2apic_mode(vcpu);
> + } else
> + kvm_x86_ops->disable_virtual_x2apic_mode(vcpu);
> +
You just broke SVM.

>   apic->base_address = apic->vcpu->arch.apic_base &
>MSR_IA32_APICBASE_BASE;
>  
> diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
> index d29d3cd..0b82cb1 100644
> --- a/arch/x86/kvm/svm.c
> +++ b/arch/x86/kvm/svm.c
> @@ -3571,6 +3571,11 @@ static void update_cr8_intercept(struct kvm_vcpu 
> *vcpu, int tpr, int irr)
>   set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
>  }
>  
> +static void svm_enable_virtual_x2apic_mode(struct kvm_vcpu *vcpu)
> +{
> + return;
> +}
> +
>  static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
>  {
>   struct vcpu_svm *svm = to_svm(vcpu);
> @@ -4290,6 +4295,7 @@ static struct kvm_x86_ops svm_x86_ops = {
>   .enable_nmi_window = enable_nmi_window,
>   .enable_irq_window = enable_irq_window,
>   .update_cr8_intercept = update_cr8_intercept,
> + .enable_virtual_x2apic_mode = svm_enable_virtual_x2apic_mode,
>  
>   .set_tss_addr = svm_set_tss_addr,
>   .get_tdp_level = get_npt_level,
> diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
> index 688f43f..b203ce7 100644
> --- a/arch/x86/kvm/vmx.c
> +++ b/arch/x86/kvm/vmx.c
> @@ -433,6 +433,8 @@ struct vcpu_vmx {
>  
>   bool rdtscp_enabled;
>  
> + bool virtual_x2apic_enabled;
> +
>   /* Support for a guest hypervisor (nested VMX) */
>   struct nested_vmx nested;
>  };
> @@ -767,12 +769,23 @@ static inline bool 
> cpu_has_vmx_virtualize_apic_accesses(void)
>   SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
>  }
>  
> +static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
> +{
> + return vmcs_config.cpu_based_2nd_exec_ctrl &
> + SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
> +}
> +
>  static inline bool cpu_has_vmx_apic_register_virt(void)
>  {
>   return vmcs_config.cpu_based_2nd_exec_ctrl &
>   SECONDARY_EXEC_APIC_REGISTER_VIRT;
>  }
>  
> +static inline bool cpu_has_vmx_virtual_intr_delivery(void)
> +{
> + return false;
> +}
> +
>  static inline bool cpu_has_vmx_flexpr

[PATCH v9 2/3] x86, apicv: add virtual x2apic support

2013-01-09 Thread Yang Zhang 
From: Yang Zhang 

basically to benefit from apicv, we need to enable virtualized x2apic mode.
Currently, we only enable it when guest is really using x2apic.

Also, clear MSR bitmap for corresponding x2apic MSRs when guest enabled x2apic:
0x800 - 0x8ff: no read intercept for apicv register virtualization,
   except APIC ID and TMCCT.
APIC ID and TMCCT: need software's assistance to get right value.
TPR,EOI,SELF-IPI: no write intercept for virtual interrupt delivery.

Signed-off-by: Kevin Tian 
Signed-off-by: Yang Zhang 
---
 arch/x86/include/asm/kvm_host.h |2 +
 arch/x86/include/asm/vmx.h  |1 +
 arch/x86/kvm/lapic.c|5 +-
 arch/x86/kvm/svm.c  |6 +
 arch/x86/kvm/vmx.c  |  194 +--
 5 files changed, 200 insertions(+), 8 deletions(-)

diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h
index c431b33..572a562 100644
--- a/arch/x86/include/asm/kvm_host.h
+++ b/arch/x86/include/asm/kvm_host.h
@@ -697,6 +697,8 @@ struct kvm_x86_ops {
void (*enable_nmi_window)(struct kvm_vcpu *vcpu);
void (*enable_irq_window)(struct kvm_vcpu *vcpu);
void (*update_cr8_intercept)(struct kvm_vcpu *vcpu, int tpr, int irr);
+   void (*enable_virtual_x2apic_mode)(struct kvm_vcpu *vcpu);
+   void (*disable_virtual_x2apic_mode)(struct kvm_vcpu *vcpu);
int (*set_tss_addr)(struct kvm *kvm, unsigned int addr);
int (*get_tdp_level)(void);
u64 (*get_mt_mask)(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio);
diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
index 44c3f7e..0a54df0 100644
--- a/arch/x86/include/asm/vmx.h
+++ b/arch/x86/include/asm/vmx.h
@@ -139,6 +139,7 @@
 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x0001
 #define SECONDARY_EXEC_ENABLE_EPT   0x0002
 #define SECONDARY_EXEC_RDTSCP  0x0008
+#define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE   0x0010
 #define SECONDARY_EXEC_ENABLE_VPID  0x0020
 #define SECONDARY_EXEC_WBINVD_EXITING  0x0040
 #define SECONDARY_EXEC_UNRESTRICTED_GUEST  0x0080
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 0664c13..ec38906 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -1328,7 +1328,10 @@ void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
u32 id = kvm_apic_id(apic);
u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
kvm_apic_set_ldr(apic, ldr);
-   }
+   kvm_x86_ops->enable_virtual_x2apic_mode(vcpu);
+   } else
+   kvm_x86_ops->disable_virtual_x2apic_mode(vcpu);
+
apic->base_address = apic->vcpu->arch.apic_base &
 MSR_IA32_APICBASE_BASE;
 
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index d29d3cd..0b82cb1 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -3571,6 +3571,11 @@ static void update_cr8_intercept(struct kvm_vcpu *vcpu, 
int tpr, int irr)
set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
 }
 
+static void svm_enable_virtual_x2apic_mode(struct kvm_vcpu *vcpu)
+{
+   return;
+}
+
 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
 {
struct vcpu_svm *svm = to_svm(vcpu);
@@ -4290,6 +4295,7 @@ static struct kvm_x86_ops svm_x86_ops = {
.enable_nmi_window = enable_nmi_window,
.enable_irq_window = enable_irq_window,
.update_cr8_intercept = update_cr8_intercept,
+   .enable_virtual_x2apic_mode = svm_enable_virtual_x2apic_mode,
 
.set_tss_addr = svm_set_tss_addr,
.get_tdp_level = get_npt_level,
diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
index 688f43f..b203ce7 100644
--- a/arch/x86/kvm/vmx.c
+++ b/arch/x86/kvm/vmx.c
@@ -433,6 +433,8 @@ struct vcpu_vmx {
 
bool rdtscp_enabled;
 
+   bool virtual_x2apic_enabled;
+
/* Support for a guest hypervisor (nested VMX) */
struct nested_vmx nested;
 };
@@ -767,12 +769,23 @@ static inline bool 
cpu_has_vmx_virtualize_apic_accesses(void)
SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 }
 
+static inline bool cpu_has_vmx_virtualize_x2apic_mode(void)
+{
+   return vmcs_config.cpu_based_2nd_exec_ctrl &
+   SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
+}
+
 static inline bool cpu_has_vmx_apic_register_virt(void)
 {
return vmcs_config.cpu_based_2nd_exec_ctrl &
SECONDARY_EXEC_APIC_REGISTER_VIRT;
 }
 
+static inline bool cpu_has_vmx_virtual_intr_delivery(void)
+{
+   return false;
+}
+
 static inline bool cpu_has_vmx_flexpriority(void)
 {
return cpu_has_vmx_tpr_shadow() &&
@@ -2544,6 +2557,7 @@ static __init int setup_vmcs_config(struct vmcs_config 
*vmcs_conf)
if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
min2 = 0;
opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
+   SEC