[Qemu-devel][PATCH 03/12] KVM/MIPS: Add save/restore state APIs for saving/restoring KVM guests.

[Sanjay Lal]

---
 hw/gt64xxx.c | 317 +++
 1 file changed, 317 insertions(+)

diff --git a/hw/gt64xxx.c b/hw/gt64xxx.c
index 977a2c5..3583ca8 100644
--- a/hw/gt64xxx.c
+++ b/hw/gt64xxx.c
@@ -31,6 +31,8 @@
 
 //#define DEBUG
 
+#define GT64XXX_VM_VERSION1
+
 #ifdef DEBUG
 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, 
##__VA_ARGS__)
 #else
@@ -1092,6 +1094,317 @@ static void gt64120_reset(void *opaque)
 gt64120_pci_mapping(s);
 }
 
+static void gt64xxx_save(QEMUFile *f, void *opaque)
+{
+GT64120State *s = opaque;
+
+/* CPU Configuration */
+qemu_put_be32s(f, &s->regs[GT_CPU]);
+qemu_put_be32s(f, &s->regs[GT_MULTI]);
+
+/* CPU Address decode */
+qemu_put_be32s(f, &s->regs[GT_SCS10LD]);
+qemu_put_be32s(f, &s->regs[GT_SCS10HD]);
+qemu_put_be32s(f, &s->regs[GT_SCS32LD]);
+qemu_put_be32s(f, &s->regs[GT_SCS32HD]);
+qemu_put_be32s(f, &s->regs[GT_CS20LD]);
+qemu_put_be32s(f, &s->regs[GT_CS20HD]);
+qemu_put_be32s(f, &s->regs[GT_CS3BOOTLD]);
+qemu_put_be32s(f, &s->regs[GT_CS3BOOTHD]);
+
+qemu_put_be32s(f, &s->regs[GT_PCI0IOLD]);
+qemu_put_be32s(f, &s->regs[GT_PCI0IOHD]);
+qemu_put_be32s(f, &s->regs[GT_PCI0M0LD]);
+qemu_put_be32s(f, &s->regs[GT_PCI0M0HD]);
+qemu_put_be32s(f, &s->regs[GT_ISD]);
+qemu_put_be32s(f, &s->regs[GT_PCI0M1LD]);
+qemu_put_be32s(f, &s->regs[GT_PCI0M1HD]);
+qemu_put_be32s(f, &s->regs[GT_PCI1IOLD]);
+qemu_put_be32s(f, &s->regs[GT_PCI1IOHD]);
+qemu_put_be32s(f, &s->regs[GT_PCI1M0LD]);
+qemu_put_be32s(f, &s->regs[GT_PCI1M0HD]);
+qemu_put_be32s(f, &s->regs[GT_PCI1M1LD]);
+qemu_put_be32s(f, &s->regs[GT_PCI1M1HD]);
+
+qemu_put_be32s(f, &s->regs[GT_SCS10AR]);
+qemu_put_be32s(f, &s->regs[GT_SCS32AR]);
+qemu_put_be32s(f, &s->regs[GT_CS20R]);
+qemu_put_be32s(f, &s->regs[GT_CS3BOOTR]);
+
+qemu_put_be32s(f, &s->regs[GT_PCI0IOREMAP]);
+qemu_put_be32s(f, &s->regs[GT_PCI0M0REMAP]);
+qemu_put_be32s(f, &s->regs[GT_PCI0M1REMAP]);
+qemu_put_be32s(f, &s->regs[GT_PCI1IOREMAP]);
+qemu_put_be32s(f, &s->regs[GT_PCI1M0REMAP]);
+qemu_put_be32s(f, &s->regs[GT_PCI1M1REMAP]);
+
+/* CPU Error Report */
+qemu_put_be32s(f, &s->regs[GT_CPUERR_ADDRLO]);
+qemu_put_be32s(f, &s->regs[GT_CPUERR_ADDRHI]);
+qemu_put_be32s(f, &s->regs[GT_CPUERR_DATALO]);
+qemu_put_be32s(f, &s->regs[GT_CPUERR_DATAHI]);
+qemu_put_be32s(f, &s->regs[GT_CPUERR_PARITY]);
+
+/* CPU Sync Barrier */
+qemu_put_be32s(f, &s->regs[GT_PCI0SYNC]);
+qemu_put_be32s(f, &s->regs[GT_PCI1SYNC]);
+
+/* SDRAM and Device Address Decode */
+qemu_put_be32s(f, &s->regs[GT_SCS0LD]);
+qemu_put_be32s(f, &s->regs[GT_SCS0HD]);
+qemu_put_be32s(f, &s->regs[GT_SCS1LD]);
+qemu_put_be32s(f, &s->regs[GT_SCS1HD]);
+qemu_put_be32s(f, &s->regs[GT_SCS2LD]);
+qemu_put_be32s(f, &s->regs[GT_SCS2HD]);
+qemu_put_be32s(f, &s->regs[GT_SCS3LD]);
+qemu_put_be32s(f, &s->regs[GT_SCS3HD]);
+qemu_put_be32s(f, &s->regs[GT_CS0LD]);
+qemu_put_be32s(f, &s->regs[GT_CS0HD]);
+qemu_put_be32s(f, &s->regs[GT_CS1LD]);
+qemu_put_be32s(f, &s->regs[GT_CS1HD]);
+qemu_put_be32s(f, &s->regs[GT_CS2LD]);
+qemu_put_be32s(f, &s->regs[GT_CS2HD]);
+qemu_put_be32s(f, &s->regs[GT_CS3LD]);
+qemu_put_be32s(f, &s->regs[GT_CS3HD]);
+qemu_put_be32s(f, &s->regs[GT_BOOTLD]);
+qemu_put_be32s(f, &s->regs[GT_BOOTHD]);
+qemu_put_be32s(f, &s->regs[GT_ADERR]);
+
+/* SDRAM Configuration */
+qemu_put_be32s(f, &s->regs[GT_SDRAM_CFG]);
+qemu_put_be32s(f, &s->regs[GT_SDRAM_OPMODE]);
+qemu_put_be32s(f, &s->regs[GT_SDRAM_BM]);
+qemu_put_be32s(f, &s->regs[GT_SDRAM_ADDRDECODE]);
+
+/* SDRAM Parameters */
+qemu_put_be32s(f, &s->regs[GT_SDRAM_B0]);
+qemu_put_be32s(f, &s->regs[GT_SDRAM_B1]);
+qemu_put_be32s(f, &s->regs[GT_SDRAM_B2]);
+qemu_put_be32s(f, &s->regs[GT_SDRAM_B3]);
+
+/* ECC */
+qemu_put_be32s(f, &s->regs[GT_ECC_ERRDATALO]);
+qemu_put_be32s(f, &s->regs[GT_ECC_ERRDATAHI]);
+qemu_put_be32s(f, &s->regs[GT_ECC_MEM]);
+qemu_put_be32s(f, &s->regs[GT_ECC_CALC]);
+qemu_put_be32s(f, &s->regs[GT_ECC_ERRADDR]);
+
+/* Device Parameters */
+qemu_put_be32s(f, &s->regs[GT_DEV_B0]);
+qemu_put_be32s(f, &s->regs[GT_DEV_B1]);
+qemu_put_be32s(f, &s->regs[GT_DEV_B2]);
+qemu_put_be32s(f, &s->regs[GT_DEV_B3]);
+qemu_put_be32s(f, &s->regs[GT_DEV_BOOT]);
+
+/* DMA registers are all zeroed at reset */
+
+/* Timer/Counter */
+qemu_put_be32s(f, &s->regs[GT_TC0]);
+qemu_put_be32s(f, &s->regs[GT_TC1]);
+qemu_put_be32s(f, &s->regs[GT_TC2]);
+qemu_put_be32s(f, &s->regs[GT_TC3]);
+qemu_put_be32s(f, &s->regs[GT_TC_CONTROL]);
+
+/* PCI Internal */
+qemu_put_be32s(f, &s->regs[GT_PCI0_CMD]);
+qemu_put_be32s(f, &s->regs[GT_PCI0_CMD]);
+qemu_put_be32s(f, &s->regs[GT_PCI0_TOR]);
+qemu_put_be32s(f, &s->regs[GT_PCI0_BS_SCS10])

Re: [Qemu-devel] [PATCH 03/12] KVM/MIPS: Add save/restore state APIs for saving/restoring KVM guests.

[Sanjay Lal]

On Mar 2, 2013, at 7:27 AM, Peter Maydell wrote:

> 2013/3/2 Sanjay Lal :
>> +static void gt64xxx_save(QEMUFile *f, void *opaque)
>> +{
>> +GT64120State *s = opaque;
>> +
>> +/* CPU Configuration */
>> +qemu_put_be32s(f, &s->regs[GT_CPU]);
>> +qemu_put_be32s(f, &s->regs[GT_MULTI]);
> 
> 
> Definitely no new save/load functions like this in new code,
> please. Use a VMState struct.
> 
> thanks
> -- PMM
> 

Will do for v2 of the patch set.

Regards
Sanjay


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Re: [Qemu-devel] [PATCH 03/12] KVM/MIPS: Add save/restore state APIs for saving/restoring KVM guests.

[Peter Maydell]

2013/3/2 Sanjay Lal :
> +static void gt64xxx_save(QEMUFile *f, void *opaque)
> +{
> +GT64120State *s = opaque;
> +
> +/* CPU Configuration */
> +qemu_put_be32s(f, &s->regs[GT_CPU]);
> +qemu_put_be32s(f, &s->regs[GT_MULTI]);


Definitely no new save/load functions like this in new code,
please. Use a VMState struct.

thanks
-- PMM
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