Re: [SeaBIOS] [PATCH] Make MTRR region 0xc0000-0x100000 be cached.

[Avi Kivity]

On 01/01/2010 08:23 PM, Kevin O'Connor wrote:

The current MTRR code in SeaBIOS uses uncached ram for
0xc-0x10.  This seems overly pessimistic as "write protect"
should be sufficient.  (Note, a WP mtrr does not prevent writes - it
is a caching strategy for memory that can be read-only.)

I'm not sure how much KVM really uses the MTRRs, but if it does honor
them this should make bootup a bit faster as it will allow caching of
the SeaBIOS code.

This change also clears all the variable mtrrs, and makes sure all the
mtrrs are set before they are enabled.

   


kvm ignores the MTRRs, unless device assignment is enabled, in which 
case it honours them.


--
I have a truly marvellous patch that fixes the bug which this
signature is too narrow to contain.

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[SeaBIOS] [PATCH] Make MTRR region 0xc0000-0x100000 be cached.

[Kevin O'Connor]

The current MTRR code in SeaBIOS uses uncached ram for
0xc-0x10.  This seems overly pessimistic as "write protect"
should be sufficient.  (Note, a WP mtrr does not prevent writes - it
is a caching strategy for memory that can be read-only.)

I'm not sure how much KVM really uses the MTRRs, but if it does honor
them this should make bootup a bit faster as it will allow caching of
the SeaBIOS code.

This change also clears all the variable mtrrs, and makes sure all the
mtrrs are set before they are enabled.

-Kevin



diff --git a/src/mtrr.c b/src/mtrr.c
index 7d1df09..ed239c8 100644
--- a/src/mtrr.c
+++ b/src/mtrr.c
@@ -44,42 +44,42 @@ void mtrr_setup(void)
 
 dprintf(3, "init mtrr\n");
 
-int i, vcnt, fix, wc;
-u32 mtrr_cap;
-union {
-u8 valb[8];
-u64 val;
-} u;
-
-mtrr_cap = rdmsr(MSR_MTRRcap);
-vcnt = mtrr_cap & 0xff;
-fix = mtrr_cap & 0x100;
-wc = mtrr_cap & 0x400;
+u32 mtrr_cap = rdmsr(MSR_MTRRcap);
+int vcnt = mtrr_cap & 0xff;
+int fix = mtrr_cap & 0x100;
 if (!vcnt || !fix)
return;
 
-// Fixed MTRRs
+// Disable MTRRs
+wrmsr_smp(MSR_MTRRdefType, 0);
+
+// Set fixed MTRRs
+union u64b {
+u8 valb[8];
+u64 val;
+} u;
 u.val = 0;
-for (i = 0; i < 8; ++i)
+int i;
+for (i = 0; i < 8; i++)
 if (RamSize >= 65536 * (i + 1))
 u.valb[i] = MTRR_MEMTYPE_WB;
 wrmsr_smp(MSR_MTRRfix64K_0, u.val);
 u.val = 0;
-for (i = 0; i < 8; ++i)
-if (RamSize >= 65536 * 8 + 16384 * (i + 1))
+for (i = 0; i < 8; i++)
+if (RamSize >= 0x8 + 16384 * (i + 1))
 u.valb[i] = MTRR_MEMTYPE_WB;
 wrmsr_smp(MSR_MTRRfix16K_8, u.val);
-wrmsr_smp(MSR_MTRRfix16K_A, 0);
-wrmsr_smp(MSR_MTRRfix4K_C, 0);
-wrmsr_smp(MSR_MTRRfix4K_C8000, 0);
-wrmsr_smp(MSR_MTRRfix4K_D, 0);
-wrmsr_smp(MSR_MTRRfix4K_D8000, 0);
-wrmsr_smp(MSR_MTRRfix4K_E, 0);
-wrmsr_smp(MSR_MTRRfix4K_E8000, 0);
-wrmsr_smp(MSR_MTRRfix4K_F, 0);
-wrmsr_smp(MSR_MTRRfix4K_F8000, 0);
+wrmsr_smp(MSR_MTRRfix16K_A, 0);   // 0xA-0xC is uncached
+int j;
+for (j = 0; j < 8; j++) {
+u.val = 0;
+for (i = 0; i < 8; i++)
+if (RamSize >= 0xC + j * 0x8000 + 4096 * (i + 1))
+u.valb[i] = MTRR_MEMTYPE_WP;
+wrmsr_smp(MSR_MTRRfix4K_C + j, u.val);
+}
 
-// Variable MTRRs
+// Set variable MTRRs
 int phys_bits = 36;
 cpuid(0x8000u, &eax, &ebx, &ecx, &edx);
 if (eax >= 0x8008) {
@@ -88,6 +88,10 @@ void mtrr_setup(void)
 phys_bits = eax & 0xff;
 }
 u64 phys_mask = ((1ull << phys_bits) - 1);
+for (i=0; ihttp://vger.kernel.org/majordomo-info.html