[PATCH 0/6] kvm/powerpc: Add emulation for MPC85xx in KVM mode
This patch set enable another KVM PowerPC platform E500. Like the 440 core, the MMU and a few other bits are not currently emulated in Qemu itself, so right now it's only functional in conjunction with KVM. The emulation of MPC85xx boards (which use E500 as its core) can be run on any MPC85xx hosts. The code has been tested on MPC8544DS and MPC8572DS. Patch 1: enable the MPIC for MPC85xx platform Patch 2: add emulation of freescale PCI controller for MPC85xx platform Patch 3: add IRQ support for E500 core Patch 4: extern one function for MPC85xx code use Patch 5: add MPC85xx board emulation Patch 6: flat device tree of MPC85xx -- To unsubscribe from this list: send the line unsubscribe kvm-ppc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/6] kvm/powerpc: Enable MPIC for MPC85xx platform
This patch add MPIC support for MPC85xx platform.
MPIC and OpenPIC have very similar design.
So a lot of code can be reused.
Since no other TCG and KVM platforms uses OpenPIC for now,
the modification makes the code only support MPIC.
Signed-off-by: Liu Yu yu@freescale.com
---
hw/openpic.c | 383 +++---
hw/openpic.h | 19 +++
hw/ppc_mac.h | 14 +--
3 files changed, 388 insertions(+), 28 deletions(-)
create mode 100644 hw/openpic.h
diff --git a/hw/openpic.c b/hw/openpic.c
index b8da4d7..2b4b9d3 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -35,6 +35,7 @@
#include hw.h
#include ppc_mac.h
#include pci.h
+#include openpic.h
//#define DEBUG_OPENPIC
@@ -45,7 +46,7 @@
#endif
#define ERROR(fmr, args...) do { printf(ERROR: fmr , ##args); } while (0)
-#define USE_MPCxxx /* Intel model is broken, for now */
+#define USE_MPC85xx /* Intel model and mac99 are broken, for now */
#if defined (USE_INTEL_GW80314)
/* Intel GW80314 I/O Companion chip */
@@ -84,15 +85,6 @@ enum {
#define OPENPIC_LITTLE_ENDIAN 1
#define OPENPIC_BIG_ENDIAN0
-#else
-#error Please select which OpenPic implementation is to be emulated
-#endif
-
-#if (OPENPIC_BIG_ENDIAN !TARGET_WORDS_BIGENDIAN) || \
-(OPENPIC_LITTLE_ENDIAN TARGET_WORDS_BIGENDIAN)
-#define OPENPIC_SWAP
-#endif
-
/* Interrupt definitions */
#define IRQ_FE (EXT_IRQ) /* Internal functional IRQ */
#define IRQ_ERR(EXT_IRQ + 1) /* Error IRQ */
@@ -105,6 +97,61 @@ enum {
#define IRQ_MBX0 (IRQ_DBL0 + MAX_DBL) /* First mailbox IRQ */
#endif
+#elif defined(USE_MPC85xx)
+
+#define MPIC_MAP_SIZE 0x4
+
+#define MAX_CPU 1
+#define MAX_EXT12
+#define MAX_INT64
+#define MAX_DBL 0
+#define MAX_MBX 0
+#define MAX_TMR 4
+#define MAX_MSG 4
+#define MAX_MSI 8
+#define MAX_IPI 4
+#define MAX_IRQ(MAX_EXT + MAX_INT + MAX_TMR + MAX_MSG + MAX_MSI + (MAX_IPI
* MAX_CPU))
+
+#define VECTOR_BITS 8
+#define VID 0x0 /* MPIC version ID */
+#define VENI0x /* Vendor ID */
+
+enum {
+IRQ_IPVP = 0,
+IRQ_IDE,
+};
+
+enum ide_bits {
+IDR_EP = 0,
+IDR_CI0 = 1,
+IDR_CI1 = 2,
+IDR_P1 = 30,
+IDR_P0 = 31,
+};
+
+#define OPENPIC_LITTLE_ENDIAN 0
+#define OPENPIC_BIG_ENDIAN1
+
+/* Interrupt definitions */
+#define EXT_IRQ0
+#define INT_IRQ(EXT_IRQ + MAX_EXT)
+#define TMR_IRQ(INT_IRQ + MAX_INT)
+#define MSG_IRQ(TMR_IRQ + MAX_TMR)
+#define MSI_IRQ(MSG_IRQ + MAX_MSG)
+#define IPI_IRQ(MSI_IRQ + MAX_MSI)
+
+#define IRQ_IPI0IPI_IRQ
+#define IRQ_TIM0TMR_IRQ
+
+#else
+#error Please select which OpenPic implementation is to be emulated
+#endif
+
+#if (OPENPIC_BIG_ENDIAN !TARGET_WORDS_BIGENDIAN) || \
+(OPENPIC_LITTLE_ENDIAN TARGET_WORDS_BIGENDIAN)
+#define OPENPIC_SWAP
+#endif
+
#define BF_WIDTH(_bits_) \
(((_bits_) + (sizeof(uint32_t) * 8) - 1) / (sizeof(uint32_t) * 8))
@@ -157,6 +204,7 @@ enum IPVP_bits {
#define IPVP_VECTOR(_ipvpr_) ((_ipvpr_) IPVP_VECTOR_MASK)
typedef struct IRQ_dst_t {
+uint32_t tfrr;
uint32_t pctp; /* CPU current task priority */
uint32_t pcsr; /* CPU sensitivity register */
IRQ_queue_t raised;
@@ -200,6 +248,8 @@ typedef struct openpic_t {
#endif
/* IRQ out is used when in bypass mode (not implemented) */
qemu_irq irq_out;
+void (*reset) (struct openpic_t *);
+void (*irq_raise) (struct openpic_t *, int, IRQ_src_t *);
} openpic_t;
static inline void IRQ_setbit (IRQ_queue_t *q, int n_IRQ)
@@ -286,7 +336,7 @@ static void IRQ_local_pipe (openpic_t *opp, int n_CPU, int
n_IRQ)
return;
}
DPRINTF(Raise OpenPIC INT output cpu %d irq %d\n, n_CPU, n_IRQ);
-qemu_irq_raise(dst-irqs[OPENPIC_OUTPUT_INT]);
+opp-irq_raise(opp, n_CPU, src);
}
/* update pic state because registers for n_IRQ have changed value */
@@ -551,8 +601,8 @@ static void openpic_gbl_write (void *opaque, uint32_t addr,
uint32_t val)
case 0x00: /* FREP */
break;
case 0x20: /* GLBC */
-if (val 0x8000)
-openpic_reset(opp);
+if (val 0x8000 opp-reset)
+opp-reset(opp);
opp-glbc = val ~0x8000;
break;
case 0x80: /* VENI */
@@ -818,7 +868,7 @@ static void openpic_cpu_write (void *opaque, uint32_t addr,
uint32_t val)
IPVP_PRIORITY(src-ipvp) dst-servicing.priority)) {
DPRINTF(Raise OpenPIC INT output cpu %d irq %d\n,
idx, n_IRQ);
-qemu_irq_raise(dst-irqs[OPENPIC_OUTPUT_INT]);
+opp-irq_raise(opp, idx, src);
}
break;
default:
@@ -1001,6 +1051,11 @@ static void openpic_map(PCIDevice *pci_dev, int
region_num,
#endif
}
+static void openpic_irq_raise(openpic_t *opp, int n_CPU, IRQ_src_t *src)
+{
+
[PATCH 3/6] kvm/powerpc: Add irq support for E500 core
Signed-off-by: Liu Yu yu@freescale.com
---
hw/ppc.c| 89 +++
hw/ppc.h|1 +
target-ppc/cpu.h| 10 +
target-ppc/translate_init.c |6 ++-
4 files changed, 104 insertions(+), 2 deletions(-)
diff --git a/hw/ppc.c b/hw/ppc.c
index 05e787f..7a44951 100644
--- a/hw/ppc.c
+++ b/hw/ppc.c
@@ -314,6 +314,95 @@ void ppc40x_irq_init (CPUState *env)
env, PPC40x_INPUT_NB);
}
+/* PowerPC E500 internal IRQ controller */
+static void ppce500_set_irq (void *opaque, int pin, int level)
+{
+CPUState *env = opaque;
+int cur_level;
+
+#if defined(PPC_DEBUG_IRQ)
+if (loglevel CPU_LOG_INT) {
+fprintf(logfile, %s: env %p pin %d level %d\n, __func__,
+env, pin, level);
+}
+#endif
+cur_level = (env-irq_input_state pin) 1;
+/* Don't generate spurious events */
+if ((cur_level == 1 level == 0) || (cur_level == 0 level != 0)) {
+switch (pin) {
+case PPCE500_INPUT_MCK:
+if (level) {
+#if defined(PPC_DEBUG_IRQ)
+if (loglevel CPU_LOG_INT) {
+fprintf(logfile, %s: reset the PowerPC system\n,
+__func__);
+}
+#endif
+ fprintf(stderr,PowerPC E500 reset core\n);
+ qemu_system_reset_request();
+}
+break;
+case PPCE500_INPUT_RESET_CORE:
+if (level) {
+#if defined(PPC_DEBUG_IRQ)
+if (loglevel CPU_LOG_INT) {
+fprintf(logfile, %s: reset the PowerPC core\n, __func__);
+}
+#endif
+ ppc_set_irq(env, PPC_INTERRUPT_MCK, level);
+}
+break;
+case PPCE500_INPUT_CINT:
+/* Level sensitive - active high */
+#if defined(PPC_DEBUG_IRQ)
+if (loglevel CPU_LOG_INT) {
+fprintf(logfile, %s: set the critical IRQ state to %d\n,
+__func__, level);
+}
+#endif
+ppc_set_irq(env, PPC_INTERRUPT_CEXT, level);
+break;
+case PPCE500_INPUT_INT:
+/* Level sensitive - active high */
+#if defined(PPC_DEBUG_IRQ)
+if (loglevel CPU_LOG_INT) {
+fprintf(logfile, %s: set the core IRQ state to %d\n,
+__func__, level);
+}
+#endif
+ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
+break;
+case PPCE500_INPUT_DEBUG:
+/* Level sensitive - active high */
+#if defined(PPC_DEBUG_IRQ)
+if (loglevel CPU_LOG_INT) {
+fprintf(logfile, %s: set the debug pin state to %d\n,
+__func__, level);
+}
+#endif
+ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level);
+break;
+default:
+/* Unknown pin - do nothing */
+#if defined(PPC_DEBUG_IRQ)
+if (loglevel CPU_LOG_INT) {
+fprintf(logfile, %s: unknown IRQ pin %d\n, __func__, pin);
+}
+#endif
+return;
+}
+if (level)
+env-irq_input_state |= 1 pin;
+else
+env-irq_input_state = ~(1 pin);
+}
+}
+
+void ppce500_irq_init (CPUState *env)
+{
+env-irq_inputs = (void **)qemu_allocate_irqs(ppce500_set_irq,
+ env, PPCE500_INPUT_NB);
+}
/*/
/* PowerPC time base and decrementer emulation */
struct ppc_tb_t {
diff --git a/hw/ppc.h b/hw/ppc.h
index 75eb11a..2ec4680 100644
--- a/hw/ppc.h
+++ b/hw/ppc.h
@@ -31,6 +31,7 @@ extern CPUReadMemoryFunc *PPC_io_read[];
void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
void ppc40x_irq_init (CPUState *env);
+void ppce500_irq_init (CPUState *env);
void ppc6xx_irq_init (CPUState *env);
void ppc970_irq_init (CPUState *env);
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index f7a12da..0eb794f 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1352,6 +1352,16 @@ enum {
};
enum {
+/* PowerPC E500 input pins */
+PPCE500_INPUT_RESET_CORE = 0,
+PPCE500_INPUT_MCK= 1,
+PPCE500_INPUT_CINT = 3,
+PPCE500_INPUT_INT= 4,
+PPCE500_INPUT_DEBUG = 6,
+PPCE500_INPUT_NB,
+};
+
+enum {
/* PowerPC 40x input pins */
PPC40x_INPUT_RESET_CORE = 0,
PPC40x_INPUT_RESET_CHIP = 1,
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 5008a3a..7953c69 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -4154,7 +4154,8 @@ static void init_proc_e300 (CPUPPCState *env)
POWERPC_FLAG_BUS_CLK)
#define check_pow_e500 check_pow_hid0
-__attribute__ (( unused ))
+extern void ppce500_irq_init (CPUState *env);
+
static void init_proc_e500 (CPUPPCState *env)
[PATCH 4/6] kvm/powerpc: extern one function for MPC85xx code use
Signed-off-by: Liu Yu yu@freescale.com
---
target-ppc/kvm_ppc.c |2 +-
target-ppc/kvm_ppc.h |2 ++
2 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/target-ppc/kvm_ppc.c b/target-ppc/kvm_ppc.c
index f7ce52b..82c0f42 100644
--- a/target-ppc/kvm_ppc.c
+++ b/target-ppc/kvm_ppc.c
@@ -22,7 +22,7 @@ static QEMUTimer *kvmppc_timer;
static unsigned int kvmppc_timer_rate;
#ifdef HAVE_FDT
-static int kvmppc_read_host_property(const char *node_path, const char *prop,
+int kvmppc_read_host_property(const char *node_path, const char *prop,
void *val, size_t len)
{
char *path;
diff --git a/target-ppc/kvm_ppc.h b/target-ppc/kvm_ppc.h
index e536a88..3792ef7 100644
--- a/target-ppc/kvm_ppc.h
+++ b/target-ppc/kvm_ppc.h
@@ -11,5 +11,7 @@
void kvmppc_init(void);
void kvmppc_fdt_update(void *fdt);
+int kvmppc_read_host_property(const char *node_path, const char *prop,
+ void *val, size_t len);
#endif /* __KVM_PPC_H__ */
--
1.5.4
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[PATCH 5/6] kvm/powerpc: Add MPC85xx board support
All MPC85xx boards use E500v1/v2 core.
This patch add emulation of a virtual MPC85xx board,
so that any MPC85xx host could run this emulation.
Only tested it on MPC8544DS and MPC8572DS hosts,
but it should work on other MPC85xx boards.
Signed-off-by: Liu Yu yu@freescale.com
---
Makefile.target |2 +-
hw/boards.h |1 +
hw/ppce500.h | 22 +++
hw/ppce500_mpc85xx.c | 346 ++
target-ppc/machine.c |1 +
5 files changed, 371 insertions(+), 1 deletions(-)
create mode 100644 hw/ppce500.h
create mode 100644 hw/ppce500_mpc85xx.c
diff --git a/Makefile.target b/Makefile.target
index 5cae257..3852f53 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -599,7 +599,7 @@ OBJS+= unin_pci.o ppc_chrp.o
OBJS+= pflash_cfi02.o ppc4xx_devs.o ppc4xx_pci.o ppc405_uc.o ppc405_boards.o
OBJS+= ppc440.o ppc440_bamboo.o
# PowerPC E500 boards
-OBJS+= ppce500_pci.o
+OBJS+= ppce500_pci.o ppce500_mpc85xx.o
ifdef FDT_LIBS
OBJS+= device_tree.o
LIBS+= $(FDT_LIBS)
diff --git a/hw/boards.h b/hw/boards.h
index 0577f06..1939f78 100644
--- a/hw/boards.h
+++ b/hw/boards.h
@@ -40,6 +40,7 @@ extern QEMUMachine heathrow_machine;
extern QEMUMachine ref405ep_machine;
extern QEMUMachine taihu_machine;
extern QEMUMachine bamboo_machine;
+extern QEMUMachine mpc85xx_machine;
/* mips_r4k.c */
extern QEMUMachine mips_machine;
diff --git a/hw/ppce500.h b/hw/ppce500.h
new file mode 100644
index 000..24d49bb
--- /dev/null
+++ b/hw/ppce500.h
@@ -0,0 +1,22 @@
+/*
+ * QEMU PowerPC E500 emulation shared definitions
+ *
+ * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * Author: Yu Liu, yu@freescale.com
+ *
+ * This file is derived from hw/ppc440.h
+ * the copyright for that material belongs to the original owners.
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#if !defined(PPC_E500_H)
+#define PPC_E500_H
+
+PCIBus *ppce500_pci_init(qemu_irq *pic, target_phys_addr_t registers);
+
+#endif /* !defined(PPC_E500_H) */
diff --git a/hw/ppce500_mpc85xx.c b/hw/ppce500_mpc85xx.c
new file mode 100644
index 000..9dd619d
--- /dev/null
+++ b/hw/ppce500_mpc85xx.c
@@ -0,0 +1,346 @@
+/*
+ * Qemu PowerPC MPC85xx board emualtion
+ *
+ * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * Author: Yu Liu, yu@freescale.com
+ *
+ * This file is derived from hw/ppc440_bamboo.c,
+ * the copyright for that material belongs to the original owners.
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include dirent.h
+
+#include config.h
+#include qemu-common.h
+#include net.h
+#include hw.h
+#include pc.h
+#include pci.h
+#include virtio-blk.h
+#include boards.h
+#include sysemu.h
+#include kvm.h
+#include kvm_ppc.h
+#include device_tree.h
+#include openpic.h
+#include ppce500.h
+
+#define BINARY_DEVICE_TREE_FILE mpc85xx.dtb
+#define UIMAGE_LOAD_BASE 0
+#define DTB_LOAD_BASE0x60
+#define INITRD_LOAD_BASE 0x200
+
+#define RAM_SIZES_ALIGN (64UL 20)
+
+#define MPC85xx_CCSRBAR_BASE 0xE000
+#define MPC85xx_MPIC_REGS_BASE (MPC85xx_CCSRBAR_BASE + 0x4)
+#define MPC85xx_SERIAL0_REGS_BASE (MPC85xx_CCSRBAR_BASE + 0x4500)
+#define MPC85xx_SERIAL1_REGS_BASE (MPC85xx_CCSRBAR_BASE + 0x4600)
+#define MPC85xx_PCI_REGS_BASE (MPC85xx_CCSRBAR_BASE + 0x8000)
+#define MPC85xx_PCI_REGS_SIZE 0x1000
+#define MPC85xx_PCI_IO 0xE100
+#define MPC85xx_PCI_IOLEN 0x1
+
+struct board {
+const char *model;
+const char *compatible;
+};
+
+#define BOARD_DEF(_model, _compatible) \
+{\
+.model = _model, \
+.compatible = _compatible, \
+}
+
+/* Supported host boards */
+static const struct board mpc85xx_table[] = {
+BOARD_DEF(MPC8544DS,MPC8544DS), /* MPC8544DS */
+BOARD_DEF(fsl,MPC8572DS,fsl,MPC8572DS), /* MPC8572DS */
+BOARD_DEF(fsl,mpc8536ds,fsl,mpc8536ds), /* MPC8536DS */
+BOARD_DEF(MPC8548CDS, MPC8548CDS),/* MPC8548CDS */
+BOARD_DEF(MPC8555CDS, MPC8555CDS),/* MPC8555CDS */
+BOARD_DEF(MPC8541CDS, MPC8541CDS),/* MPC8541CDS */
+BOARD_DEF(MPC8540ADS, MPC8540ADS),/* MPC8540ADS */
+BOARD_DEF(MPC8560ADS, MPC8560ADS),/* MPC8560ADS */
+BOARD_DEF(MPC8568EMDS, MPC8568EMDS), /* MPC8568EMDS */
+};
+
+#define BOARDS_NUM (sizeof(mpc85xx_table)/sizeof(struct board))
+
+static int
Re: [PATCH 5/6] kvm/powerpc: Add MPC85xx board support
On Thu, 2009-01-22 at 18:14 +0800, Liu Yu wrote:
All MPC85xx boards use E500v1/v2 core.
This patch add emulation of a virtual MPC85xx board,
so that any MPC85xx host could run this emulation.
Only tested it on MPC8544DS and MPC8572DS hosts,
but it should work on other MPC85xx boards.
Signed-off-by: Liu Yu yu@freescale.com
...
+struct board {
+const char *model;
+const char *compatible;
+};
+
+#define BOARD_DEF(_model, _compatible) \
+{\
+.model = _model, \
+.compatible = _compatible, \
+}
+
+/* Supported host boards */
+static const struct board mpc85xx_table[] = {
+BOARD_DEF(MPC8544DS,MPC8544DS), /* MPC8544DS */
+BOARD_DEF(fsl,MPC8572DS,fsl,MPC8572DS), /* MPC8572DS */
+BOARD_DEF(fsl,mpc8536ds,fsl,mpc8536ds), /* MPC8536DS */
+BOARD_DEF(MPC8548CDS, MPC8548CDS),/* MPC8548CDS */
+BOARD_DEF(MPC8555CDS, MPC8555CDS),/* MPC8555CDS */
+BOARD_DEF(MPC8541CDS, MPC8541CDS),/* MPC8541CDS */
+BOARD_DEF(MPC8540ADS, MPC8540ADS),/* MPC8540ADS */
+BOARD_DEF(MPC8560ADS, MPC8560ADS),/* MPC8560ADS */
+BOARD_DEF(MPC8568EMDS, MPC8568EMDS), /* MPC8568EMDS */
+};
+
+#define BOARDS_NUM (sizeof(mpc85xx_table)/sizeof(struct board))
...
+static void *mpc85xx_load_device_tree(void *addr,
+ uint32_t ramsize,
+ target_phys_addr_t initrd_base,
+ target_phys_addr_t initrd_size,
+ const char *kernel_cmdline)
+{
...
+if (kvm_enabled()) {
+ FILE *fp;
+ char *model;
+ char const *compatible = NULL;
+ struct dirent *dirp;
+ DIR *dp;
+ int i;
+ char buf[128];
+
+ if ((fp = fopen(/proc/cpuinfo, r)) == NULL) {
+ printf(Can't open file /proc/cpuinfo\n);
+ goto out;
+ }
+ while (fgets(buf, 128, fp) != NULL) {
+ if (strncmp(buf, model, 5) == 0) {
+ model = buf + 9;
+ break;
+ }
+ }
+ fclose(fp);
+
+ for (i = 0; i BOARDS_NUM; i++) {
+ if (strncmp(model, mpc85xx_table[i].model,
+ strlen(mpc85xx_table[i].model)) == 0) {
+ compatible = mpc85xx_table[i].compatible;
+ }
+ }
+
+ if (compatible == NULL) {
+ printf(Unknow host board!\n);
+ goto out;
+ }
+
+ ret = qemu_devtree_setprop_string(fdt, /, compatible, compatible);
+ if (ret 0)
+ fprintf(stderr, couldn't set /compatible = %s\n, compatible);
+
+ if ((dp = opendir(/proc/device-tree/cpus/)) == NULL) {
+ printf(Can't open directory /proc/device-tree/cpus/\n);
+ goto out;
+ }
+
+ buf[0] = '\0';
+ while ((dirp = readdir(dp)) != NULL) {
+ if (strncmp(dirp-d_name, PowerPC, 7) == 0) {
+ sprintf(buf, /proc/device-tree/cpus/%s, dirp-d_name);
+ break;
+ }
+ }
+ closedir(dp);
+ if (buf[0] == '\0') {
+ printf(Unknow host!\n);
+ goto out;
+ }
+ path = buf + 17;
I don't think you should do this at all. As long as the core is known,
it doesn't matter what the host board is. You *always* emulate the
MPC8544DS board (that's what your device tree says). You should be able
to emulate a MPC8544DS on *any* e500v2 host board or chip.
For comparison, on 440 we have tested with Sequoia (440EPx) and Bamboo
(440EP) hosts, but qemu always emulates a Bamboo guest. The chips aren't
the same, but that's irrelevant because the core is (440 x5).
The rest of this patch looks good.
--
Hollis Blanchard
IBM Linux Technology Center
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Re: [PATCH 0/6] kvm/powerpc: Add emulation for MPC85xx in KVM mode
On Thu, 2009-01-22 at 18:14 +0800, Liu Yu wrote: This patch set enable another KVM PowerPC platform E500. Like the 440 core, the MMU and a few other bits are not currently emulated in Qemu itself, so right now it's only functional in conjunction with KVM. The emulation of MPC85xx boards (which use E500 as its core) can be run on any MPC85xx hosts. The code has been tested on MPC8544DS and MPC8572DS. Patch 1: enable the MPIC for MPC85xx platform Patch 2: add emulation of freescale PCI controller for MPC85xx platform Patch 3: add IRQ support for E500 core Patch 4: extern one function for MPC85xx code use Patch 5: add MPC85xx board emulation Patch 6: flat device tree of MPC85xx Patches 1-4: Acked-by: Hollis Blanchard holl...@us.ibm.com I've posted some comments on patches 5 and 6. Aurelian, would you mind reviewing patches 1-3? -- Hollis Blanchard IBM Linux Technology Center -- To unsubscribe from this list: send the line unsubscribe kvm-ppc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
RE: [PATCH 4/5] qemu/kvm: Add MPC85xx support
Oops. I just saw this mail.
I don't know why it's junked by my client...
OK. I will change it to MPC8544 and remove redundant node in fdt.
-Original Message-
From: kvm-ppc-ow...@vger.kernel.org
[mailto:kvm-ppc-ow...@vger.kernel.org] On Behalf Of Hollis Blanchard
Sent: Saturday, January 10, 2009 4:36 AM
To: Liu Yu-B13201
Cc: kvm-ppc@vger.kernel.org
Subject: Re: [PATCH 4/5] qemu/kvm: Add MPC85xx support
On Fri, 2009-01-09 at 15:56 +0800, Liu Yu wrote:
As E500 exists in various boards such as MPC8544ds,
MPC8572ds, MPC8560ads, etc..
So I would like to implement a general virtual board
MPC85xx to simplify the case.
When 'cat /proc/cpuinfo' in guest, it will show:
processor : 0
cpu : e500v2
clock : 1499.985015MHz
revision: 3.0 (pvr 8021 0030)
bogomips: 285.69
timebase: 74999250
platform: MPC8572 DS Host platform
model : KVM MPC85xx
The current method is that change guest dts
/compatible=host model,
this seems somewhat dirty. It works for 8544, 8572 but not
sure for others.
I'll change it to search a table next time.
Signed-off-by: Liu Yu yu@freescale.com
---
Makefile.target |2 +
hw/boards.h |1 +
hw/ppc.c| 89 +++
hw/ppc.h|1 +
hw/ppce500_mpc85xx.c| 284
++
pc-bios/mpc85xx.dtb | Bin 0 - 12288 bytes
pc-bios/mpc85xx.dts | 361
+++
target-ppc/cpu.h| 12 ++
target-ppc/machine.c|1 +
target-ppc/translate_init.c |6 +-
10 files changed, 755 insertions(+), 2 deletions(-)
create mode 100644 hw/ppce500_mpc85xx.c
create mode 100644 pc-bios/mpc85xx.dtb
create mode 100644 pc-bios/mpc85xx.dts
diff --git a/Makefile.target b/Makefile.target
index b66b699..abf0d59 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -657,6 +657,8 @@ OBJS+= unin_pci.o ppc_chrp.o
# PowerPC 4xx boards
OBJS+= pflash_cfi02.o ppc4xx_devs.o ppc4xx_pci.o
ppc405_uc.o ppc405_boards.o
OBJS+= ppc440.o ppc440_bamboo.o
+# PowerPC E500 boards
+OBJS+= ppce500.o ppce500_mpc85xx.o ppce500_pci.o mpic.o
ifdef FDT_LIBS
OBJS+= device_tree.o
LIBS+= $(FDT_LIBS)
diff --git a/hw/boards.h b/hw/boards.h
index bff1cf0..35bd5ae 100644
--- a/hw/boards.h
+++ b/hw/boards.h
@@ -39,6 +39,7 @@ extern QEMUMachine heathrow_machine;
extern QEMUMachine ref405ep_machine;
extern QEMUMachine taihu_machine;
extern QEMUMachine bamboo_machine;
+extern QEMUMachine mpc85xx_machine;
/* mips_r4k.c */
extern QEMUMachine mips_machine;
diff --git a/hw/ppc.c b/hw/ppc.c
index 60d6e86..fbce211 100644
--- a/hw/ppc.c
+++ b/hw/ppc.c
@@ -421,6 +421,95 @@ void ppc40x_irq_init (CPUState *env)
env,
PPC40x_INPUT_NB);
}
+/* PowerPC E500 internal IRQ controller */
+static void ppce500_set_irq (void *opaque, int pin, int level)
+{
+CPUState *env = opaque;
+int cur_level;
+
+#if defined(PPC_DEBUG_IRQ)
+if (loglevel CPU_LOG_INT) {
+fprintf(logfile, %s: env %p pin %d level %d\n, __func__,
+env, pin, level);
+}
+#endif
+cur_level = (env-irq_input_state pin) 1;
+/* Don't generate spurious events */
+if ((cur_level == 1 level == 0) || (cur_level == 0
level != 0)) {
+switch (pin) {
+case PPCE500_INPUT_MCK:
+if (level) {
+#if defined(PPC_DEBUG_IRQ)
+if (loglevel CPU_LOG_INT) {
+fprintf(logfile, %s: reset the
PowerPC system\n,
+__func__);
+}
+#endif
+ fprintf(stderr,PowerPC E500 reset core\n);
+ qemu_system_reset_request();
+}
+break;
+case PPCE500_INPUT_RESET_CORE:
+if (level) {
+#if defined(PPC_DEBUG_IRQ)
+if (loglevel CPU_LOG_INT) {
+fprintf(logfile, %s: reset the
PowerPC core\n, __func__);
+}
+#endif
+ ppc_set_irq(env, PPC_INTERRUPT_MCK, level);
+}
+break;
+case PPCE500_INPUT_CINT:
+/* Level sensitive - active high */
+#if defined(PPC_DEBUG_IRQ)
+if (loglevel CPU_LOG_INT) {
+fprintf(logfile, %s: set the critical IRQ
state to %d\n,
+__func__, level);
+}
+#endif
+ppc_set_irq(env, PPC_INTERRUPT_CEXT, level);
+break;
+case PPCE500_INPUT_INT:
+/* Level sensitive - active high */
+#if defined(PPC_DEBUG_IRQ)
+if (loglevel CPU_LOG_INT) {
+fprintf(logfile, %s: set the core IRQ
state to %d\n,
+
