[PATCH 1/5] kvm/powerpc: Enable MPIC for E500 platform.
MPIC and OpenPIC have very similar design.
So a lot of code can be reused.
Modification mainly include:
1. keep struct openpic_t to the maximum size of both MPIC and OpenPIC.
2. endianess swap.
MPIC has the same endianess as target, so no need to swap for MPIC.
3. using different init functions and function pointers for reset and irq raise.
Haven't test OpenPIC.
Signed-off-by: Liu Yu yu@freescale.com
---
v4:
1.register different handlers for different memory areas.
2.increase openpic save version number.
3.register mpic reset handler with qemu_register_reset.
hw/openpic.c | 673 +++--
hw/openpic.h | 18 ++
hw/ppc_mac.h | 13 -
hw/ppc_newworld.c |1 +
4 files changed, 618 insertions(+), 87 deletions(-)
create mode 100644 hw/openpic.h
diff --git a/hw/openpic.c b/hw/openpic.c
index 6dfb590..6e4126b 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -35,6 +35,7 @@
#include hw.h
#include ppc_mac.h
#include pci.h
+#include openpic.h
//#define DEBUG_OPENPIC
@@ -60,14 +61,10 @@
#define VID (0x)
-#define OPENPIC_LITTLE_ENDIAN 1
-#define OPENPIC_BIG_ENDIAN0
-
#elif defined(USE_MPCxxx)
#define MAX_CPU 2
-#define MAX_IRQ64
-#define EXT_IRQ48
+#define MAX_IRQ 128
#define MAX_DBL 0
#define MAX_MBX 0
#define MAX_TMR 4
@@ -81,28 +78,68 @@ enum {
IRQ_IDE,
};
-#define OPENPIC_LITTLE_ENDIAN 1
-#define OPENPIC_BIG_ENDIAN0
+/* OpenPIC */
+#define OPENPIC_MAX_CPU 2
+#define OPENPIC_MAX_IRQ 64
+#define OPENPIC_EXT_IRQ 48
+#define OPENPIC_MAX_TMR MAX_TMR
+#define OPENPIC_MAX_IPI MAX_IPI
+/* Interrupt definitions */
+#define OPENPIC_IRQ_FE (OPENPIC_EXT_IRQ) /* Internal functional IRQ */
+#define OPENPIC_IRQ_ERR(OPENPIC_EXT_IRQ + 1) /* Error IRQ */
+#define OPENPIC_IRQ_TIM0 (OPENPIC_EXT_IRQ + 2) /* First timer IRQ */
+#if OPENPIC_MAX_IPI 0
+#define OPENPIC_IRQ_IPI0 (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First IPI
IRQ */
+#define OPENPIC_IRQ_DBL0 (OPENPIC_IRQ_IPI0 + (OPENPIC_MAX_CPU *
OPENPIC_MAX_IPI)) /* First doorbell IRQ */
#else
-#error Please select which OpenPic implementation is to be emulated
+#define OPENPIC_IRQ_DBL0 (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First
doorbell IRQ */
+#define OPENPIC_IRQ_MBX0 (OPENPIC_IRQ_DBL0 + OPENPIC_MAX_DBL) /* First
mailbox IRQ */
#endif
-#if (OPENPIC_BIG_ENDIAN !TARGET_WORDS_BIGENDIAN) || \
-(OPENPIC_LITTLE_ENDIAN TARGET_WORDS_BIGENDIAN)
-#define OPENPIC_SWAP
-#endif
+/* MPIC */
+#define MPIC_MAX_CPU 1
+#define MPIC_MAX_EXT 12
+#define MPIC_MAX_INT 64
+#define MPIC_MAX_MSG 4
+#define MPIC_MAX_MSI 8
+#define MPIC_MAX_TMR MAX_TMR
+#define MPIC_MAX_IPI MAX_IPI
+#define MPIC_MAX_IRQ (MPIC_MAX_EXT + MPIC_MAX_INT + MPIC_MAX_TMR +
MPIC_MAX_MSG + MPIC_MAX_MSI + (MPIC_MAX_IPI * MPIC_MAX_CPU))
/* Interrupt definitions */
-#define IRQ_FE (EXT_IRQ) /* Internal functional IRQ */
-#define IRQ_ERR(EXT_IRQ + 1) /* Error IRQ */
-#define IRQ_TIM0 (EXT_IRQ + 2) /* First timer IRQ */
-#if MAX_IPI 0
-#define IRQ_IPI0 (IRQ_TIM0 + MAX_TMR) /* First IPI IRQ */
-#define IRQ_DBL0 (IRQ_IPI0 + (MAX_CPU * MAX_IPI)) /* First doorbell IRQ */
+#define MPIC_EXT_IRQ 0
+#define MPIC_INT_IRQ (MPIC_EXT_IRQ + MPIC_MAX_EXT)
+#define MPIC_TMR_IRQ (MPIC_INT_IRQ + MPIC_MAX_INT)
+#define MPIC_MSG_IRQ (MPIC_TMR_IRQ + MPIC_MAX_TMR)
+#define MPIC_MSI_IRQ (MPIC_MSG_IRQ + MPIC_MAX_MSG)
+#define MPIC_IPI_IRQ (MPIC_MSI_IRQ + MPIC_MAX_MSI)
+
+#define MPIC_GLB_REG_START0x0
+#define MPIC_GLB_REG_SIZE 0x10F0
+#define MPIC_TMR_REG_START0x10F0
+#define MPIC_TMR_REG_SIZE 0x220
+#define MPIC_EXT_REG_START0x1
+#define MPIC_EXT_REG_SIZE 0x180
+#define MPIC_INT_REG_START0x10200
+#define MPIC_INT_REG_SIZE 0x800
+#define MPIC_MSG_REG_START0x11600
+#define MPIC_MSG_REG_SIZE 0x100
+#define MPIC_MSI_REG_START0x11C00
+#define MPIC_MSI_REG_SIZE 0x100
+#define MPIC_CPU_REG_START0x2
+#define MPIC_CPU_REG_SIZE 0x100
+
+enum mpic_ide_bits {
+IDR_EP = 0,
+IDR_CI0 = 1,
+IDR_CI1 = 2,
+IDR_P1 = 30,
+IDR_P0 = 31,
+};
+
#else
-#define IRQ_DBL0 (IRQ_TIM0 + MAX_TMR) /* First doorbell IRQ */
-#define IRQ_MBX0 (IRQ_DBL0 + MAX_DBL) /* First mailbox IRQ */
+#error Please select which OpenPic implementation is to be emulated
#endif
#define BF_WIDTH(_bits_) \
@@ -157,6 +194,7 @@ enum IPVP_bits {
#define IPVP_VECTOR(_ipvpr_) ((_ipvpr_) IPVP_VECTOR_MASK)
typedef struct IRQ_dst_t {
+uint32_t tfrr;
uint32_t pctp; /* CPU current task priority */
uint32_t pcsr; /* CPU sensitivity register */
IRQ_queue_t raised;
@@ -200,8 +238,22 @@ typedef struct openpic_t {
#endif
/* IRQ out is used when in bypass mode (not implemented) */
qemu_irq irq_out;
+int max_irq;
+int irq_ipi0;
[PATCH 3/5] kvm/powerpc: Add irq support for E500 core
Signed-off-by: Liu Yu yu@freescale.com
---
hw/ppc.c| 60 +++
hw/ppc.h|1 +
target-ppc/cpu.h| 10 +++
target-ppc/translate_init.c |5 ++-
4 files changed, 74 insertions(+), 2 deletions(-)
diff --git a/hw/ppc.c b/hw/ppc.c
index 9a01c01..b534e39 100644
--- a/hw/ppc.c
+++ b/hw/ppc.c
@@ -314,6 +314,66 @@ void ppc40x_irq_init (CPUState *env)
env, PPC40x_INPUT_NB);
}
+/* PowerPC E500 internal IRQ controller */
+static void ppce500_set_irq (void *opaque, int pin, int level)
+{
+CPUState *env = opaque;
+int cur_level;
+
+LOG_IRQ(%s: env %p pin %d level %d\n, __func__,
+env, pin, level);
+cur_level = (env-irq_input_state pin) 1;
+/* Don't generate spurious events */
+if ((cur_level == 1 level == 0) || (cur_level == 0 level != 0)) {
+switch (pin) {
+case PPCE500_INPUT_MCK:
+if (level) {
+LOG_IRQ(%s: reset the PowerPC system\n,
+__func__);
+qemu_system_reset_request();
+}
+break;
+case PPCE500_INPUT_RESET_CORE:
+if (level) {
+LOG_IRQ(%s: reset the PowerPC core\n, __func__);
+ppc_set_irq(env, PPC_INTERRUPT_MCK, level);
+}
+break;
+case PPCE500_INPUT_CINT:
+/* Level sensitive - active high */
+LOG_IRQ(%s: set the critical IRQ state to %d\n,
+__func__, level);
+ppc_set_irq(env, PPC_INTERRUPT_CEXT, level);
+break;
+case PPCE500_INPUT_INT:
+/* Level sensitive - active high */
+LOG_IRQ(%s: set the core IRQ state to %d\n,
+__func__, level);
+ppc_set_irq(env, PPC_INTERRUPT_EXT, level);
+break;
+case PPCE500_INPUT_DEBUG:
+/* Level sensitive - active high */
+LOG_IRQ(%s: set the debug pin state to %d\n,
+__func__, level);
+ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level);
+break;
+default:
+/* Unknown pin - do nothing */
+LOG_IRQ(%s: unknown IRQ pin %d\n, __func__, pin);
+return;
+}
+if (level)
+env-irq_input_state |= 1 pin;
+else
+env-irq_input_state = ~(1 pin);
+}
+}
+
+void ppce500_irq_init (CPUState *env)
+{
+env-irq_inputs = (void **)qemu_allocate_irqs(ppce500_set_irq,
+env, PPCE500_INPUT_NB);
+}
/*/
/* PowerPC time base and decrementer emulation */
struct ppc_tb_t {
diff --git a/hw/ppc.h b/hw/ppc.h
index 75eb11a..2ec4680 100644
--- a/hw/ppc.h
+++ b/hw/ppc.h
@@ -31,6 +31,7 @@ extern CPUReadMemoryFunc *PPC_io_read[];
void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
void ppc40x_irq_init (CPUState *env);
+void ppce500_irq_init (CPUState *env);
void ppc6xx_irq_init (CPUState *env);
void ppc970_irq_init (CPUState *env);
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 80ee76c..bdc3cf9 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1356,6 +1356,16 @@ enum {
};
enum {
+/* PowerPC E500 input pins */
+PPCE500_INPUT_RESET_CORE = 0,
+PPCE500_INPUT_MCK= 1,
+PPCE500_INPUT_CINT = 3,
+PPCE500_INPUT_INT= 4,
+PPCE500_INPUT_DEBUG = 6,
+PPCE500_INPUT_NB,
+};
+
+enum {
/* PowerPC 40x input pins */
PPC40x_INPUT_RESET_CORE = 0,
PPC40x_INPUT_RESET_CHIP = 1,
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 889708f..5d1c0b4 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -63,6 +63,7 @@ void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
PPC_IRQ_INIT_FN(40x);
PPC_IRQ_INIT_FN(6xx);
PPC_IRQ_INIT_FN(970);
+PPC_IRQ_INIT_FN(e500);
/* Generic callbacks:
* do nothing but store/retrieve spr value
@@ -4185,7 +4186,6 @@ static void init_proc_e300 (CPUPPCState *env)
#define check_pow_e500v2 check_pow_hid0
#define init_proc_e500v2 init_proc_e500
-__attribute__ (( unused ))
static void init_proc_e500 (CPUPPCState *env)
{
/* Time base */
@@ -4287,7 +4287,8 @@ static void init_proc_e500 (CPUPPCState *env)
init_excp_e200(env);
env-dcache_line_size = 32;
env-icache_line_size = 32;
-/* XXX: TODO: allocate internal IRQ controller */
+/* Allocate hardware IRQ controller */
+ppce500_irq_init(env);
}
/* Non-embedded PowerPC */
--
1.5.4
--
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[PATCH 4/5] kvm/powerpc: Add MPC8544DS board support
This patch add an emulation of MPC8544DS board.
It can work on All E500 platforms.
Signed-off-by: Liu Yu yu@freescale.com
---
v4:
1. remove checking return value from qemu_malloc.
2. use qemu_free instead of free.
3. use snprintf instead of sprintf.
Makefile.target|2 +-
hw/boards.h|1 +
hw/ppce500.h | 22
hw/ppce500_mpc8544ds.c | 284
target-ppc/machine.c |1 +
5 files changed, 309 insertions(+), 1 deletions(-)
create mode 100644 hw/ppce500.h
create mode 100644 hw/ppce500_mpc8544ds.c
diff --git a/Makefile.target b/Makefile.target
index 90b5eb7..f33f762 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -603,7 +603,7 @@ OBJS+= unin_pci.o ppc_newworld.o
OBJS+= pflash_cfi02.o ppc4xx_devs.o ppc4xx_pci.o ppc405_uc.o ppc405_boards.o
OBJS+= ppc440.o ppc440_bamboo.o
# PowerPC E500 boards
-OBJS+= ppce500_pci.o
+OBJS+= ppce500_pci.o ppce500_mpc8544ds.o
ifdef FDT_LIBS
OBJS+= device_tree.o
LIBS+= $(FDT_LIBS)
diff --git a/hw/boards.h b/hw/boards.h
index 7384817..1e62594 100644
--- a/hw/boards.h
+++ b/hw/boards.h
@@ -42,6 +42,7 @@ extern QEMUMachine heathrow_machine;
extern QEMUMachine ref405ep_machine;
extern QEMUMachine taihu_machine;
extern QEMUMachine bamboo_machine;
+extern QEMUMachine mpc8544ds_machine;
/* mips_r4k.c */
extern QEMUMachine mips_machine;
diff --git a/hw/ppce500.h b/hw/ppce500.h
new file mode 100644
index 000..24d49bb
--- /dev/null
+++ b/hw/ppce500.h
@@ -0,0 +1,22 @@
+/*
+ * QEMU PowerPC E500 emulation shared definitions
+ *
+ * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * Author: Yu Liu, yu@freescale.com
+ *
+ * This file is derived from hw/ppc440.h
+ * the copyright for that material belongs to the original owners.
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#if !defined(PPC_E500_H)
+#define PPC_E500_H
+
+PCIBus *ppce500_pci_init(qemu_irq *pic, target_phys_addr_t registers);
+
+#endif /* !defined(PPC_E500_H) */
diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c
new file mode 100644
index 000..8fa0383
--- /dev/null
+++ b/hw/ppce500_mpc8544ds.c
@@ -0,0 +1,284 @@
+/*
+ * Qemu PowerPC MPC8544DS board emualtion
+ *
+ * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * Author: Yu Liu, yu@freescale.com
+ *
+ * This file is derived from hw/ppc440_bamboo.c,
+ * the copyright for that material belongs to the original owners.
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include dirent.h
+
+#include config.h
+#include qemu-common.h
+#include net.h
+#include hw.h
+#include pc.h
+#include pci.h
+#include virtio-blk.h
+#include boards.h
+#include sysemu.h
+#include kvm.h
+#include kvm_ppc.h
+#include device_tree.h
+#include openpic.h
+#include ppce500.h
+
+#define BINARY_DEVICE_TREE_FILEmpc8544ds.dtb
+#define UIMAGE_LOAD_BASE 0
+#define DTB_LOAD_BASE 0x60
+#define INITRD_LOAD_BASE 0x200
+
+#define RAM_SIZES_ALIGN(64UL 20)
+
+#define MPC8544_CCSRBAR_BASE 0xE000
+#define MPC8544_MPIC_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4)
+#define MPC8544_SERIAL0_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4500)
+#define MPC8544_SERIAL1_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4600)
+#define MPC8544_PCI_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x8000)
+#define MPC8544_PCI_REGS_SIZE 0x1000
+#define MPC8544_PCI_IO 0xE100
+#define MPC8544_PCI_IOLEN 0x1
+
+static int mpc8544_copy_soc_cell(void *fdt, const char *node, const char *prop)
+{
+uint32_t cell;
+int ret;
+
+ret = kvmppc_read_host_property(node, prop, cell, sizeof(cell));
+if (ret 0) {
+fprintf(stderr, couldn't read host %s/%s\n, node, prop);
+goto out;
+}
+
+ret = qemu_devtree_setprop_cell(fdt, /cpus/PowerPC,8...@0,
+prop, cell);
+if (ret 0) {
+fprintf(stderr, couldn't set guest /cpus/PowerPC,8...@0/%s\n, prop);
+goto out;
+}
+
+out:
+return ret;
+}
+
+static void *mpc8544_load_device_tree(void *addr,
+ uint32_t ramsize,
+ target_phys_addr_t initrd_base,
+ target_phys_addr_t initrd_size,
+ const char *kernel_cmdline)
+{
+void *fdt = NULL;
+#ifdef HAVE_FDT
+uint32_t mem_reg_property[] = {0, ramsize};
+char *path;
+int pathlen;
+int ret;
+
+pathlen = snprintf(NULL, 0,
[PATCH 2/5] kvm/powerpc: Add freescale pci controller's support
This patch add the emulation of freescale's pci controller for MPC85xx platform.
Signed-off-by: Liu Yu yu@freescale.com
---
v4:
1. use use pci_config_set_vendor_id and pci_config_set_device_id functions,
and add the ID #defines to hw/pci.h.
Makefile.target |2 +
hw/pci.h |4 +
hw/ppce500_pci.c | 365 ++
3 files changed, 371 insertions(+), 0 deletions(-)
create mode 100644 hw/ppce500_pci.c
diff --git a/Makefile.target b/Makefile.target
index 9e7a1bb..90b5eb7 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -602,6 +602,8 @@ OBJS+= unin_pci.o ppc_newworld.o
# PowerPC 4xx boards
OBJS+= pflash_cfi02.o ppc4xx_devs.o ppc4xx_pci.o ppc405_uc.o ppc405_boards.o
OBJS+= ppc440.o ppc440_bamboo.o
+# PowerPC E500 boards
+OBJS+= ppce500_pci.o
ifdef FDT_LIBS
OBJS+= device_tree.o
LIBS+= $(FDT_LIBS)
diff --git a/hw/pci.h b/hw/pci.h
index 8c301d0..56381e8 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -40,6 +40,7 @@ extern target_phys_addr_t pci_mem_base;
#define PCI_CLASS_BRIDGE_OTHER 0x0680
#define PCI_CLASS_PROCESSOR_CO 0x0b40
+#define PCI_CLASS_PROCESSOR_POWERPC 0x0b20
#define PCI_CLASS_OTHERS 0xff
@@ -112,6 +113,9 @@ extern target_phys_addr_t pci_mem_base;
#define PCI_DEVICE_ID_INTEL_82371AB_20x7112
#define PCI_DEVICE_ID_INTEL_82371AB_30x7113
+#define PCI_VENDOR_ID_FSL0x1957
+#define PCI_DEVICE_ID_FSL_E500 0x0030
+
/* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
#define PCI_VENDOR_ID_REDHAT_QUMRANET0x1af4
#define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c
new file mode 100644
index 000..d5892e8
--- /dev/null
+++ b/hw/ppce500_pci.c
@@ -0,0 +1,365 @@
+/*
+ * QEMU PowerPC E500 embedded processors pci controller emulation
+ *
+ * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * Author: Yu Liu, yu@freescale.com
+ *
+ * This file is derived from hw/ppc4xx_pci.c,
+ * the copyright for that material belongs to the original owners.
+ *
+ * This is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include hw.h
+#include ppc.h
+#include ppce500.h
+typedef target_phys_addr_t pci_addr_t;
+#include pci.h
+#include pci_host.h
+#include bswap.h
+#include qemu-log.h
+
+#ifdef DEBUG_PCI
+#define pci_debug(fmt, arg...) fprintf(stderr, fmt, ##arg)
+#else
+#define pci_debug(fmt, arg...)
+#endif
+
+#define PCIE500_CFGADDR 0x0
+#define PCIE500_CFGDATA 0x4
+#define PCIE500_REG_BASE 0xC00
+#define PCIE500_REG_SIZE (0x1000 - PCIE500_REG_BASE)
+
+#define PPCE500_PCI_CONFIG_ADDR 0x0
+#define PPCE500_PCI_CONFIG_DATA 0x4
+#define PPCE500_PCI_INTACK 0x8
+
+#define PPCE500_PCI_OW1 (0xC20 - PCIE500_REG_BASE)
+#define PPCE500_PCI_OW2 (0xC40 - PCIE500_REG_BASE)
+#define PPCE500_PCI_OW3 (0xC60 - PCIE500_REG_BASE)
+#define PPCE500_PCI_OW4 (0xC80 - PCIE500_REG_BASE)
+#define PPCE500_PCI_IW3 (0xDA0 - PCIE500_REG_BASE)
+#define PPCE500_PCI_IW2 (0xDC0 - PCIE500_REG_BASE)
+#define PPCE500_PCI_IW1 (0xDE0 - PCIE500_REG_BASE)
+
+#define PPCE500_PCI_GASKET_TIMR (0xE20 - PCIE500_REG_BASE)
+
+#define PCI_POTAR 0x0
+#define PCI_POTEAR 0x4
+#define PCI_POWBAR 0x8
+#define PCI_POWAR 0x10
+
+#define PCI_PITAR 0x0
+#define PCI_PIWBAR 0x8
+#define PCI_PIWBEAR 0xC
+#define PCI_PIWAR 0x10
+
+#define PPCE500_PCI_NR_POBS 5
+#define PPCE500_PCI_NR_PIBS 3
+
+struct pci_outbound {
+uint32_t potar;
+uint32_t potear;
+uint32_t powbar;
+uint32_t powar;
+};
+
+struct pci_inbound {
+uint32_t pitar;
+uint32_t piwbar;
+uint32_t piwbear;
+uint32_t piwar;
+};
+
+struct PPCE500PCIState {
+struct pci_outbound pob[PPCE500_PCI_NR_POBS];
+struct pci_inbound pib[PPCE500_PCI_NR_PIBS];
+uint32_t gasket_time;
+PCIHostState pci_state;
+PCIDevice *pci_dev;
+};
+
+typedef struct PPCE500PCIState PPCE500PCIState;
+
+static uint32_t pcie500_cfgaddr_readl(void *opaque, target_phys_addr_t addr)
+{
+PPCE500PCIState *pci = opaque;
+
+pci_debug(%s: (addr:%Lx) - value:%x\n, __func__, addr,
+pci-pci_state.config_reg);
+return pci-pci_state.config_reg;
+}
+
+static CPUReadMemoryFunc *pcie500_cfgaddr_read[] = {
+pcie500_cfgaddr_readl,
+pcie500_cfgaddr_readl,
+pcie500_cfgaddr_readl,
+};
+
+static void pcie500_cfgaddr_writel(void *opaque, target_phys_addr_t addr,
+ uint32_t value)
+{
+PPCE500PCIState *controller = opaque;
+
+
Re: [PATCH 5/5] kvm/powerpc: flat device tree files for MPC8544DS
On Thu, 2009-02-26 at 18:35 +0800, Liu Yu wrote:
mpc8544ds.dts is copied from kerenl.
Non-supported devices has been removed.
Signed-off-by: Liu Yu yu@freescale.com
---
pc-bios/mpc8544ds.dtb | Bin 0 - 12288 bytes
pc-bios/mpc8544ds.dts | 122
+
2 files changed, 122 insertions(+), 0 deletions(-)
create mode 100644 pc-bios/mpc8544ds.dtb
create mode 100644 pc-bios/mpc8544ds.dts
diff --git a/pc-bios/mpc8544ds.dts b/pc-bios/mpc8544ds.dts
new file mode 100644
index 000..872152d
--- /dev/null
+++ b/pc-bios/mpc8544ds.dts
@@ -0,0 +1,122 @@
+/*
+ * MPC8544 DS Device Tree Source
+ *
+ * Copyright 2007, 2008 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+/dts-v1/;
+/ {
+ model = MPC8544DS;
+ compatible = MPC8544DS, MPC85xxDS;
+ #address-cells = 1;
+ #size-cells = 1;
+
+ aliases {
+ serial0 = serial0;
+ serial1 = serial1;
+ pci0 = pci0;
+ };
+
+ cpus {
+ #address-cells = 1;
+ #size-cells = 0;
+
+ PowerPC,8...@0 {
+ device_type = cpu;
+ reg = 0x0;
+ d-cache-line-size = 32; // 32 bytes
+ i-cache-line-size = 32; // 32 bytes
+ d-cache-size = 0x8000;// L1, 32K
+ i-cache-size = 0x8000;// L1, 32K
+ timebase-frequency = 0;
+ bus-frequency = 0;
+ clock-frequency = 0;
It might be helpful to comment that these properties are overwritten at
runtime.
+ };
+ };
+
+ memory {
+ device_type = memory;
+ reg = 0x0 0x0;// Filled by U-Boot
+ };
Filled by qemu
+ soc8...@e000 {
+ #address-cells = 1;
+ #size-cells = 1;
+ device_type = soc;
+ compatible = simple-bus;
+
+ ranges = 0x0 0xe000 0x10;
+ reg = 0xe000 0x1000; // CCSRBAR 1M
+ bus-frequency = 0;// Filled out by uboot.
Not filled by anybody...
Anyways, these are minor cosmetic issues; I'd be happy if the patch were
committed in its current form.
Acked-by: Hollis Blanchard holl...@us.ibm.com
--
Hollis Blanchard
IBM Linux Technology Center
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