[PATCH 0/3] adding MSI/MSIX for PCI on POWER
The following patches add MSIX support for PCI on POWER. The first aim is virtio-pci so it was tested. It will also support VFIO when it becomes available in public. Alexey Kardashevskiy (3): msi/msix: added functions to API to set up message address and data pseries: added allocator for a block of IRQs pseries pci: added MSI/MSIX support hw/msi.c | 14 +++ hw/msi.h |1 + hw/msix.c | 10 ++ hw/msix.h |3 + hw/spapr.c | 26 +- hw/spapr.h |1 + hw/spapr_pci.c | 266 +-- hw/spapr_pci.h | 13 +++- trace-events |9 ++ 9 files changed, 331 insertions(+), 12 deletions(-) -- 1.7.7.3 -- To unsubscribe from this list: send the line unsubscribe kvm-ppc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/3] msi/msix: added functions to API to set up message address and data
Normally QEMU expects the guest to initialize MSI/MSIX vectors.
However on POWER the guest uses RTAS subsystem to configure MSI/MSIX and
does not write these vectors to device's config space or MSIX BAR.
On the other hand, msi_notify()/msix_notify() write to these vectors to
signal the guest about an interrupt so we have to write correct vectors
to the devices in order not to change every user of MSI/MSIX.
The first aim is to support MSIX for virtio-pci on POWER. There is
another patch for POWER coming which introduces a special memory region
where MSI/MSIX vectors point to.
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
hw/msi.c | 14 ++
hw/msi.h |1 +
hw/msix.c | 10 ++
hw/msix.h |3 +++
4 files changed, 28 insertions(+), 0 deletions(-)
diff --git a/hw/msi.c b/hw/msi.c
index 5d6ceb6..124878a 100644
--- a/hw/msi.c
+++ b/hw/msi.c
@@ -358,3 +358,17 @@ unsigned int msi_nr_vectors_allocated(const PCIDevice *dev)
uint16_t flags = pci_get_word(dev-config + msi_flags_off(dev));
return msi_nr_vectors(flags);
}
+
+void msi_set_address_data(PCIDevice *dev, uint64_t address, uint16_t data)
+{
+uint16_t flags = pci_get_word(dev-config + msi_flags_off(dev));
+bool msi64bit = flags PCI_MSI_FLAGS_64BIT;
+
+if (msi64bit) {
+pci_set_quad(dev-config + msi_address_lo_off(dev), address);
+} else {
+pci_set_long(dev-config + msi_address_lo_off(dev), address);
+}
+pci_set_word(dev-config + msi_data_off(dev, msi64bit), data);
+}
+
diff --git a/hw/msi.h b/hw/msi.h
index 3040bb0..0acf434 100644
--- a/hw/msi.h
+++ b/hw/msi.h
@@ -34,6 +34,7 @@ void msi_reset(PCIDevice *dev);
void msi_notify(PCIDevice *dev, unsigned int vector);
void msi_write_config(PCIDevice *dev, uint32_t addr, uint32_t val, int len);
unsigned int msi_nr_vectors_allocated(const PCIDevice *dev);
+void msi_set_address_data(PCIDevice *dev, uint64_t address, uint16_t data);
static inline bool msi_present(const PCIDevice *dev)
{
diff --git a/hw/msix.c b/hw/msix.c
index 3835eaa..c57c299 100644
--- a/hw/msix.c
+++ b/hw/msix.c
@@ -414,3 +414,13 @@ void msix_unuse_all_vectors(PCIDevice *dev)
return;
msix_free_irq_entries(dev);
}
+
+void msix_set_address_data(PCIDevice *dev, int vector,
+ uint64_t address, uint32_t data)
+{
+uint8_t *table_entry = dev-msix_table_page + vector * PCI_MSIX_ENTRY_SIZE;
+pci_set_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR, address);
+pci_set_long(table_entry + PCI_MSIX_ENTRY_DATA, data);
+table_entry[PCI_MSIX_ENTRY_VECTOR_CTRL] = ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
+}
+
diff --git a/hw/msix.h b/hw/msix.h
index 5aba22b..e6bb696 100644
--- a/hw/msix.h
+++ b/hw/msix.h
@@ -29,4 +29,7 @@ void msix_notify(PCIDevice *dev, unsigned vector);
void msix_reset(PCIDevice *dev);
+void msix_set_address_data(PCIDevice *dev, int vector,
+ uint64_t address, uint32_t data);
+
#endif
--
1.7.7.3
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[PATCH 2/3] pseries: added allocator for a block of IRQs
The patch adds a simple helper which allocates a consecutive sequence
of IRQs calling spapr_allocate_irq for each and checks that allocated
IRQs go consequently.
The patch is required for upcoming support of MSI/MSIX on POWER.
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
hw/spapr.c | 19 +++
hw/spapr.h |1 +
2 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/hw/spapr.c b/hw/spapr.c
index 2e0b4b8..ef6ffcb 100644
--- a/hw/spapr.c
+++ b/hw/spapr.c
@@ -113,6 +113,25 @@ qemu_irq spapr_allocate_irq(uint32_t hint, uint32_t
*irq_num,
return qirq;
}
+/* Allocate block of consequtive IRQs, returns a number of the first */
+int spapr_allocate_irq_block(uint32_t num, enum xics_irq_type type)
+{
+int i, ret;
+uint32_t irq = -1;
+
+for (i = 0; i num; ++i) {
+if (!spapr_allocate_irq(0, irq, type)) {
+return -1;
+}
+if (0 == i) {
+ret = irq;
+} else if (ret + i != irq) {
+return -1;
+}
+}
+return ret;
+}
+
static int spapr_set_associativity(void *fdt, sPAPREnvironment *spapr)
{
int ret = 0, offset;
diff --git a/hw/spapr.h b/hw/spapr.h
index 502393a..408b470 100644
--- a/hw/spapr.h
+++ b/hw/spapr.h
@@ -289,6 +289,7 @@ target_ulong spapr_hypercall(CPUPPCState *env, target_ulong
opcode,
qemu_irq spapr_allocate_irq(uint32_t hint, uint32_t *irq_num,
enum xics_irq_type type);
+int spapr_allocate_irq_block(uint32_t num, enum xics_irq_type type);
static inline qemu_irq spapr_allocate_msi(uint32_t hint, uint32_t *irq_num)
{
--
1.7.7.3
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[PATCH 3/3] pseries pci: added MSI/MSIX support
virtio-pci expects the guest to set up MSI message address and data, and
to do other initialization such as a vector number negotiation.
It also notifies the guest via writing an MSI message to a previously set
address.
This patch includes:
1. RTAS call ibm,change-msi which sets up number of MSI vectors per
a device. Note that this call may configure and return lesser number of
vectors than requested.
2. RTAS call ibm,query-interrupt-source-number which translates MSI
vector to interrupt controller (XICS) IRQ number.
3. A config_space_address to msi_table map to provide IRQ resolving from
config-address as MSI RTAS calls take a PCI config space address as
an identifier.
4. A MSIX memory region is added to catch msi_notify()/msix_notiry()
from virtio-pci and pass them to the guest via qemu_irq_pulse().
This patch depends on the msi/msix: added functions to API to set up
message address and data patch.
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
hw/spapr.c |9 ++-
hw/spapr_pci.c | 266 +--
hw/spapr_pci.h | 13 +++-
trace-events |9 ++
4 files changed, 284 insertions(+), 13 deletions(-)
diff --git a/hw/spapr.c b/hw/spapr.c
index ef6ffcb..35ad075 100644
--- a/hw/spapr.c
+++ b/hw/spapr.c
@@ -43,6 +43,7 @@
#include hw/spapr_vio.h
#include hw/spapr_pci.h
#include hw/xics.h
+#include hw/msi.h
#include kvm.h
#include kvm_ppc.h
@@ -82,6 +83,7 @@
#define SPAPR_PCI_MEM_WIN_ADDR (0x100ULL + 0xA000)
#define SPAPR_PCI_MEM_WIN_SIZE 0x2000
#define SPAPR_PCI_IO_WIN_ADDR (0x100ULL + 0x8000)
+#define SPAPR_PCI_MSI_WIN_ADDR (0x100ULL + 0x9000)
#define PHANDLE_XICP0x
@@ -116,7 +118,7 @@ qemu_irq spapr_allocate_irq(uint32_t hint, uint32_t
*irq_num,
/* Allocate block of consequtive IRQs, returns a number of the first */
int spapr_allocate_irq_block(uint32_t num, enum xics_irq_type type)
{
-int i, ret;
+int i, ret = 0;
uint32_t irq = -1;
for (i = 0; i num; ++i) {
@@ -690,6 +692,8 @@ static void ppc_spapr_init(ram_addr_t ram_size,
long pteg_shift = 17;
char *filename;
+msi_supported = true;
+
spapr = g_malloc0(sizeof(*spapr));
QLIST_INIT(spapr-phbs);
@@ -804,7 +808,8 @@ static void ppc_spapr_init(ram_addr_t ram_size,
spapr_create_phb(spapr, pci, SPAPR_PCI_BUID,
SPAPR_PCI_MEM_WIN_ADDR,
SPAPR_PCI_MEM_WIN_SIZE,
- SPAPR_PCI_IO_WIN_ADDR);
+ SPAPR_PCI_IO_WIN_ADDR,
+ SPAPR_PCI_MSI_WIN_ADDR);
for (i = 0; i nb_nics; i++) {
NICInfo *nd = nd_table[i];
diff --git a/hw/spapr_pci.c b/hw/spapr_pci.c
index 93017cd..21fbc50 100644
--- a/hw/spapr_pci.c
+++ b/hw/spapr_pci.c
@@ -24,31 +24,46 @@
*/
#include hw.h
#include pci.h
+#include msix.h
+#include msi.h
#include pci_host.h
#include hw/spapr.h
#include hw/spapr_pci.h
#include exec-memory.h
#include libfdt.h
+#include trace.h
#include hw/pci_internals.h
-static PCIDevice *find_dev(sPAPREnvironment *spapr,
- uint64_t buid, uint32_t config_addr)
+static sPAPRPHBState *find_phb(sPAPREnvironment *spapr, uint64_t buid)
{
-DeviceState *qdev;
-int devfn = (config_addr 8) 0xFF;
sPAPRPHBState *phb;
QLIST_FOREACH(phb, spapr-phbs, list) {
if (phb-buid != buid) {
continue;
}
+return phb;
+}
-QTAILQ_FOREACH(qdev, phb-host_state.bus-qbus.children, sibling) {
-PCIDevice *dev = (PCIDevice *)qdev;
-if (dev-devfn == devfn) {
-return dev;
-}
+return NULL;
+}
+
+static PCIDevice *find_dev(sPAPREnvironment *spapr, uint64_t buid,
+ uint32_t config_addr)
+{
+sPAPRPHBState *phb = find_phb(spapr, buid);
+DeviceState *qdev;
+int devfn = (config_addr 8) 0xFF;
+
+if (!phb) {
+return NULL;
+}
+
+QTAILQ_FOREACH(qdev, phb-host_state.bus-qbus.children, sibling) {
+PCIDevice *dev = (PCIDevice *)qdev;
+if (dev-devfn == devfn) {
+return dev;
}
}
@@ -138,6 +153,220 @@ static void rtas_write_pci_config(sPAPREnvironment *spapr,
rtas_st(rets, 0, 0);
}
+/*
+ * Initializes req_num vectors for a device.
+ * The code assumes that MSI/MSIX is enabled in the config space
+ * as a result of msix_init() or msi_init().
+ */
+static int spapr_pci_config_msi(sPAPRPHBState *ph, int ndev,
+PCIDevice *pdev, bool msix, unsigned req_num)
+{
+unsigned i;
+int irq;
+uint64_t msi_address;
+uint32_t config_addr = pdev-devfn 8;
+
+/* Disabling - nothing to do */
+if (0 == req_num) {
+return 0;
+}
+
+/* Enabling! */
+if (ph-msi_table[ndev].nvec (req_num != ph-msi_table[ndev].nvec)) {
+/* Unexpected behaviour */
+fprintf(stderr, Cannot reuse cached MSI config
[PATCH] pseries pci: removed redundand busdev
The PCIHostState struct already contains SysBusDevice so
the one in sPAPRPHBState has to go.
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
hw/spapr_pci.c |4 ++--
hw/spapr_pci.h |1 -
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/hw/spapr_pci.c b/hw/spapr_pci.c
index 75943cf..1c0b605 100644
--- a/hw/spapr_pci.c
+++ b/hw/spapr_pci.c
@@ -215,7 +215,7 @@ static DMAContext *spapr_pci_dma_context_fn(PCIBus *bus,
void *opaque,
static int spapr_phb_init(SysBusDevice *s)
{
-sPAPRPHBState *phb = FROM_SYSBUS(sPAPRPHBState, s);
+sPAPRPHBState *phb = DO_UPCAST(sPAPRPHBState, host_state.busdev, s);
char *namebuf;
int i;
PCIBus *bus;
@@ -253,7 +253,7 @@ static int spapr_phb_init(SysBusDevice *s)
memory_region_add_subregion(get_system_memory(), phb-io_win_addr,
phb-iowindow);
-bus = pci_register_bus(phb-busdev.qdev,
+bus = pci_register_bus(phb-host_state.busdev.qdev,
phb-busname ? phb-busname : phb-dtbusname,
pci_spapr_set_irq, pci_spapr_map_irq, phb,
phb-memspace, phb-iospace,
diff --git a/hw/spapr_pci.h b/hw/spapr_pci.h
index d9e46e2..a141764 100644
--- a/hw/spapr_pci.h
+++ b/hw/spapr_pci.h
@@ -28,7 +28,6 @@
#include hw/xics.h
typedef struct sPAPRPHBState {
-SysBusDevice busdev;
PCIHostState host_state;
uint64_t buid;
--
1.7.7.3
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[PATCH] pseries pci: spapr_populate_pci_devices renamed to spapr_populate_pci_dt
spapr_populate_pci_devices() populates the device tree only with bus
properties and has nothing to do with the devices on it as PCI BAR
allocation is done by the system firmware (SLOF).
New name - spapr_populate_pci_dt() - describes the functionality better.
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
hw/spapr.c |2 +-
hw/spapr_pci.c |6 +++---
hw/spapr_pci.h |6 +++---
3 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/hw/spapr.c b/hw/spapr.c
index 47b26ee..2e0b4b8 100644
--- a/hw/spapr.c
+++ b/hw/spapr.c
@@ -551,7 +551,7 @@ static void spapr_finalize_fdt(sPAPREnvironment *spapr,
}
QLIST_FOREACH(phb, spapr-phbs, list) {
-ret = spapr_populate_pci_devices(phb, PHANDLE_XICP, fdt);
+ret = spapr_populate_pci_dt(phb, PHANDLE_XICP, fdt);
}
if (ret 0) {
diff --git a/hw/spapr_pci.c b/hw/spapr_pci.c
index 1c0b605..269dbbf 100644
--- a/hw/spapr_pci.c
+++ b/hw/spapr_pci.c
@@ -345,9 +345,9 @@ void spapr_create_phb(sPAPREnvironment *spapr,
#define b_fff(x)b_x((x), 8, 3) /* function number */
#define b_(x) b_x((x), 0, 8) /* register number */
-int spapr_populate_pci_devices(sPAPRPHBState *phb,
- uint32_t xics_phandle,
- void *fdt)
+int spapr_populate_pci_dt(sPAPRPHBState *phb,
+ uint32_t xics_phandle,
+ void *fdt)
{
int bus_off, i, j;
char nodename[256];
diff --git a/hw/spapr_pci.h b/hw/spapr_pci.h
index a141764..dd66f4b 100644
--- a/hw/spapr_pci.h
+++ b/hw/spapr_pci.h
@@ -55,8 +55,8 @@ void spapr_create_phb(sPAPREnvironment *spapr,
uint64_t mem_win_addr, uint64_t mem_win_size,
uint64_t io_win_addr);
-int spapr_populate_pci_devices(sPAPRPHBState *phb,
- uint32_t xics_phandle,
- void *fdt);
+int spapr_populate_pci_dt(sPAPRPHBState *phb,
+ uint32_t xics_phandle,
+ void *fdt);
#endif /* __HW_SPAPR_PCI_H__ */
--
1.7.7.3
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[PATCH] trace: added ability to comment out events in the list
It is convenient for debug to be able to switch on/off some events easily.
The only possibility now is to remove event name from the file completely
and type it again when we want it back.
The patch adds '#' symbol handling as a comment specifier.
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
trace/control.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/trace/control.c b/trace/control.c
index 4c5527d..22d5863 100644
--- a/trace/control.c
+++ b/trace/control.c
@@ -27,6 +27,9 @@ void trace_backend_init_events(const char *fname)
size_t len = strlen(line_buf);
if (len 1) { /* skip empty lines */
line_buf[len - 1] = '\0';
+if ('#' == line_buf[0]) { /* skip commented lines */
+continue;
+}
if (!trace_event_set_state(line_buf, true)) {
fprintf(stderr,
error: trace event '%s' does not exist\n, line_buf);
--
1.7.7.3
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Re: [PATCH 0/3] adding MSI/MSIX for PCI on POWER
Forgot to CC: someone :) On 14/06/12 14:29, Alexey Kardashevskiy wrote: The following patches add MSIX support for PCI on POWER. The first aim is virtio-pci so it was tested. It will also support VFIO when it becomes available in public. Alexey Kardashevskiy (3): msi/msix: added functions to API to set up message address and data pseries: added allocator for a block of IRQs pseries pci: added MSI/MSIX support hw/msi.c | 14 +++ hw/msi.h |1 + hw/msix.c | 10 ++ hw/msix.h |3 + hw/spapr.c | 26 +- hw/spapr.h |1 + hw/spapr_pci.c | 266 +-- hw/spapr_pci.h | 13 +++- trace-events |9 ++ 9 files changed, 331 insertions(+), 12 deletions(-) -- Alexey -- To unsubscribe from this list: send the line unsubscribe kvm-ppc in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [Qemu-devel] [PATCH 1/3] msi/msix: added functions to API to set up message address and data
On Thu, 2012-06-14 at 14:31 +1000, Alexey Kardashevskiy wrote:
Normally QEMU expects the guest to initialize MSI/MSIX vectors.
However on POWER the guest uses RTAS subsystem to configure MSI/MSIX and
does not write these vectors to device's config space or MSIX BAR.
On the other hand, msi_notify()/msix_notify() write to these vectors to
signal the guest about an interrupt so we have to write correct vectors
to the devices in order not to change every user of MSI/MSIX.
The first aim is to support MSIX for virtio-pci on POWER. There is
another patch for POWER coming which introduces a special memory region
where MSI/MSIX vectors point to.
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
hw/msi.c | 14 ++
hw/msi.h |1 +
hw/msix.c | 10 ++
hw/msix.h |3 +++
4 files changed, 28 insertions(+), 0 deletions(-)
diff --git a/hw/msi.c b/hw/msi.c
index 5d6ceb6..124878a 100644
--- a/hw/msi.c
+++ b/hw/msi.c
@@ -358,3 +358,17 @@ unsigned int msi_nr_vectors_allocated(const PCIDevice
*dev)
uint16_t flags = pci_get_word(dev-config + msi_flags_off(dev));
return msi_nr_vectors(flags);
}
+
+void msi_set_address_data(PCIDevice *dev, uint64_t address, uint16_t data)
+{
+uint16_t flags = pci_get_word(dev-config + msi_flags_off(dev));
+bool msi64bit = flags PCI_MSI_FLAGS_64BIT;
+
+if (msi64bit) {
+pci_set_quad(dev-config + msi_address_lo_off(dev), address);
+} else {
+pci_set_long(dev-config + msi_address_lo_off(dev), address);
+}
+pci_set_word(dev-config + msi_data_off(dev, msi64bit), data);
+}
Why not make it msi_set_message() and pass MSIMessage? I'd be great if
you tossed in a msi_get_message() as well, I think we need it to be able
to do a kvm_irqchip_add_msi_route() with MSI. Thanks,
Alex
+
diff --git a/hw/msi.h b/hw/msi.h
index 3040bb0..0acf434 100644
--- a/hw/msi.h
+++ b/hw/msi.h
@@ -34,6 +34,7 @@ void msi_reset(PCIDevice *dev);
void msi_notify(PCIDevice *dev, unsigned int vector);
void msi_write_config(PCIDevice *dev, uint32_t addr, uint32_t val, int len);
unsigned int msi_nr_vectors_allocated(const PCIDevice *dev);
+void msi_set_address_data(PCIDevice *dev, uint64_t address, uint16_t data);
static inline bool msi_present(const PCIDevice *dev)
{
diff --git a/hw/msix.c b/hw/msix.c
index 3835eaa..c57c299 100644
--- a/hw/msix.c
+++ b/hw/msix.c
@@ -414,3 +414,13 @@ void msix_unuse_all_vectors(PCIDevice *dev)
return;
msix_free_irq_entries(dev);
}
+
+void msix_set_address_data(PCIDevice *dev, int vector,
+ uint64_t address, uint32_t data)
+{
+uint8_t *table_entry = dev-msix_table_page + vector *
PCI_MSIX_ENTRY_SIZE;
+pci_set_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR, address);
+pci_set_long(table_entry + PCI_MSIX_ENTRY_DATA, data);
+table_entry[PCI_MSIX_ENTRY_VECTOR_CTRL] = ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
+}
+
diff --git a/hw/msix.h b/hw/msix.h
index 5aba22b..e6bb696 100644
--- a/hw/msix.h
+++ b/hw/msix.h
@@ -29,4 +29,7 @@ void msix_notify(PCIDevice *dev, unsigned vector);
void msix_reset(PCIDevice *dev);
+void msix_set_address_data(PCIDevice *dev, int vector,
+ uint64_t address, uint32_t data);
+
#endif
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Re: [Qemu-devel] [PATCH 1/3] msi/msix: added functions to API to set up message address and data
On 14/06/12 14:56, Alex Williamson wrote:
On Thu, 2012-06-14 at 14:31 +1000, Alexey Kardashevskiy wrote:
Normally QEMU expects the guest to initialize MSI/MSIX vectors.
However on POWER the guest uses RTAS subsystem to configure MSI/MSIX and
does not write these vectors to device's config space or MSIX BAR.
On the other hand, msi_notify()/msix_notify() write to these vectors to
signal the guest about an interrupt so we have to write correct vectors
to the devices in order not to change every user of MSI/MSIX.
The first aim is to support MSIX for virtio-pci on POWER. There is
another patch for POWER coming which introduces a special memory region
where MSI/MSIX vectors point to.
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
hw/msi.c | 14 ++
hw/msi.h |1 +
hw/msix.c | 10 ++
hw/msix.h |3 +++
4 files changed, 28 insertions(+), 0 deletions(-)
diff --git a/hw/msi.c b/hw/msi.c
index 5d6ceb6..124878a 100644
--- a/hw/msi.c
+++ b/hw/msi.c
@@ -358,3 +358,17 @@ unsigned int msi_nr_vectors_allocated(const PCIDevice
*dev)
uint16_t flags = pci_get_word(dev-config + msi_flags_off(dev));
return msi_nr_vectors(flags);
}
+
+void msi_set_address_data(PCIDevice *dev, uint64_t address, uint16_t data)
+{
+uint16_t flags = pci_get_word(dev-config + msi_flags_off(dev));
+bool msi64bit = flags PCI_MSI_FLAGS_64BIT;
+
+if (msi64bit) {
+pci_set_quad(dev-config + msi_address_lo_off(dev), address);
+} else {
+pci_set_long(dev-config + msi_address_lo_off(dev), address);
+}
+pci_set_word(dev-config + msi_data_off(dev, msi64bit), data);
+}
Why not make it msi_set_message() and pass MSIMessage? I'd be great if
you tossed in a msi_get_message() as well, I think we need it to be able
to do a kvm_irqchip_add_msi_route() with MSI. Thanks,
I am missing the point. What is that MSIMessage?
It is just an address and data, making a struct from this is a bit too much :)
I am totally unfamiliar with kvm_irqchip_add_msi_route to see the bigger
picture, sorry.
Alex
+
diff --git a/hw/msi.h b/hw/msi.h
index 3040bb0..0acf434 100644
--- a/hw/msi.h
+++ b/hw/msi.h
@@ -34,6 +34,7 @@ void msi_reset(PCIDevice *dev);
void msi_notify(PCIDevice *dev, unsigned int vector);
void msi_write_config(PCIDevice *dev, uint32_t addr, uint32_t val, int len);
unsigned int msi_nr_vectors_allocated(const PCIDevice *dev);
+void msi_set_address_data(PCIDevice *dev, uint64_t address, uint16_t data);
static inline bool msi_present(const PCIDevice *dev)
{
diff --git a/hw/msix.c b/hw/msix.c
index 3835eaa..c57c299 100644
--- a/hw/msix.c
+++ b/hw/msix.c
@@ -414,3 +414,13 @@ void msix_unuse_all_vectors(PCIDevice *dev)
return;
msix_free_irq_entries(dev);
}
+
+void msix_set_address_data(PCIDevice *dev, int vector,
+ uint64_t address, uint32_t data)
+{
+uint8_t *table_entry = dev-msix_table_page + vector *
PCI_MSIX_ENTRY_SIZE;
+pci_set_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR, address);
+pci_set_long(table_entry + PCI_MSIX_ENTRY_DATA, data);
+table_entry[PCI_MSIX_ENTRY_VECTOR_CTRL] = ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
+}
+
diff --git a/hw/msix.h b/hw/msix.h
index 5aba22b..e6bb696 100644
--- a/hw/msix.h
+++ b/hw/msix.h
@@ -29,4 +29,7 @@ void msix_notify(PCIDevice *dev, unsigned vector);
void msix_reset(PCIDevice *dev);
+void msix_set_address_data(PCIDevice *dev, int vector,
+ uint64_t address, uint32_t data);
+
#endif
--
Alexey
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Re: [Qemu-devel] [PATCH 1/3] msi/msix: added functions to API to set up message address and data
On 14/06/12 15:38, Alex Williamson wrote:
On Thu, 2012-06-14 at 15:17 +1000, Alexey Kardashevskiy wrote:
On 14/06/12 14:56, Alex Williamson wrote:
On Thu, 2012-06-14 at 14:31 +1000, Alexey Kardashevskiy wrote:
Normally QEMU expects the guest to initialize MSI/MSIX vectors.
However on POWER the guest uses RTAS subsystem to configure MSI/MSIX and
does not write these vectors to device's config space or MSIX BAR.
On the other hand, msi_notify()/msix_notify() write to these vectors to
signal the guest about an interrupt so we have to write correct vectors
to the devices in order not to change every user of MSI/MSIX.
The first aim is to support MSIX for virtio-pci on POWER. There is
another patch for POWER coming which introduces a special memory region
where MSI/MSIX vectors point to.
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
hw/msi.c | 14 ++
hw/msi.h |1 +
hw/msix.c | 10 ++
hw/msix.h |3 +++
4 files changed, 28 insertions(+), 0 deletions(-)
diff --git a/hw/msi.c b/hw/msi.c
index 5d6ceb6..124878a 100644
--- a/hw/msi.c
+++ b/hw/msi.c
@@ -358,3 +358,17 @@ unsigned int msi_nr_vectors_allocated(const PCIDevice
*dev)
uint16_t flags = pci_get_word(dev-config + msi_flags_off(dev));
return msi_nr_vectors(flags);
}
+
+void msi_set_address_data(PCIDevice *dev, uint64_t address, uint16_t data)
+{
+uint16_t flags = pci_get_word(dev-config + msi_flags_off(dev));
+bool msi64bit = flags PCI_MSI_FLAGS_64BIT;
+
+if (msi64bit) {
+pci_set_quad(dev-config + msi_address_lo_off(dev), address);
+} else {
+pci_set_long(dev-config + msi_address_lo_off(dev), address);
+}
+pci_set_word(dev-config + msi_data_off(dev, msi64bit), data);
+}
Why not make it msi_set_message() and pass MSIMessage? I'd be great if
you tossed in a msi_get_message() as well, I think we need it to be able
to do a kvm_irqchip_add_msi_route() with MSI. Thanks,
I am missing the point. What is that MSIMessage?
It is just an address and data, making a struct from this is a bit too much
:)
I am totally unfamiliar with kvm_irqchip_add_msi_route to see the bigger
picture, sorry.
MSIVectorUseNotifier passes a MSIMessage back to the device when a
vector is unmasked. We can then add a route in KVM for that message
with kvm_irqchip_add_msi_route. Finally, kvm_irqchip_add_irqfd allows
us to connect that MSI route to an eventfd, such as from virtio or vfio.
Then MSI eventfds can bypass qemu and be injected directly into KVM and
on into the guest. So we seem to already have some standardization on
passing address/data via an MSIMessage.
You need a set interface, I need a get interface. msix already has
a static msix_get_message(). So I'd suggest that an exported
get/set_message for each seems like the right way to go. Thanks,
Ok. Slowly :) What QEMU tree are you talking about? git, branch?
There is neither MSIVectorUseNotifier nor MSIMessage in your or mine trees.
--
Alexey
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Re: [Qemu-devel] [PATCH 1/3] msi/msix: added functions to API to set up message address and data
On 2012-06-14 07:17, Alexey Kardashevskiy wrote:
On 14/06/12 14:56, Alex Williamson wrote:
On Thu, 2012-06-14 at 14:31 +1000, Alexey Kardashevskiy wrote:
Normally QEMU expects the guest to initialize MSI/MSIX vectors.
However on POWER the guest uses RTAS subsystem to configure MSI/MSIX and
does not write these vectors to device's config space or MSIX BAR.
On the other hand, msi_notify()/msix_notify() write to these vectors to
signal the guest about an interrupt so we have to write correct vectors
to the devices in order not to change every user of MSI/MSIX.
The first aim is to support MSIX for virtio-pci on POWER. There is
another patch for POWER coming which introduces a special memory region
where MSI/MSIX vectors point to.
Signed-off-by: Alexey Kardashevskiy a...@ozlabs.ru
---
hw/msi.c | 14 ++
hw/msi.h |1 +
hw/msix.c | 10 ++
hw/msix.h |3 +++
4 files changed, 28 insertions(+), 0 deletions(-)
diff --git a/hw/msi.c b/hw/msi.c
index 5d6ceb6..124878a 100644
--- a/hw/msi.c
+++ b/hw/msi.c
@@ -358,3 +358,17 @@ unsigned int msi_nr_vectors_allocated(const PCIDevice
*dev)
uint16_t flags = pci_get_word(dev-config + msi_flags_off(dev));
return msi_nr_vectors(flags);
}
+
+void msi_set_address_data(PCIDevice *dev, uint64_t address, uint16_t data)
+{
+uint16_t flags = pci_get_word(dev-config + msi_flags_off(dev));
+bool msi64bit = flags PCI_MSI_FLAGS_64BIT;
+
+if (msi64bit) {
+pci_set_quad(dev-config + msi_address_lo_off(dev), address);
+} else {
+pci_set_long(dev-config + msi_address_lo_off(dev), address);
+}
+pci_set_word(dev-config + msi_data_off(dev, msi64bit), data);
+}
Why not make it msi_set_message() and pass MSIMessage? I'd be great if
you tossed in a msi_get_message() as well, I think we need it to be able
to do a kvm_irqchip_add_msi_route() with MSI. Thanks,
I am missing the point. What is that MSIMessage?
It is just an address and data, making a struct from this is a bit too much :)
This is about consistent APIs. In practice (assembly), MSIMessage will
make no difference from open-coded address/data tuples, but it is
cleaner to pass around. Please follow the existing patterns.
I am totally unfamiliar with kvm_irqchip_add_msi_route to see the bigger
picture, sorry.
The kvm_irqchip_* API come into play when you implement some interrupt
controller models in the kernel for performance reasons. We have this on
x86, we will see it on Book3E and ARM soon. You are targeting Book3S,
right? Not sure what the plans are there.
And, yes, msi_get_message() will be needed soon as well, at latest when
I push vector notifiers for classic MSI. If you have a need for reading
the message back, please add this helper already.
Jan
--
Siemens AG, Corporate Technology, CT T DE IT 1
Corporate Competence Center Embedded Linux
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