Re: [PATCH 05/11] KVM: PPC: Book3S HV: Add support for guest Program Priority Register
On 16.09.2013, at 22:29, Benjamin Herrenschmidt wrote: > On Fri, 2013-09-06 at 13:22 +1000, Paul Mackerras wrote: >> POWER7 and later IBM server processors have a register called the >> Program Priority Register (PPR), which controls the priority of >> each hardware CPU SMT thread, and affects how fast it runs compared >> to other SMT threads. This priority can be controlled by writing to >> the PPR or by use of a set of instructions of the form or rN,rN,rN >> which are otherwise no-ops but have been defined to set the priority >> to particular levels. >> >> This adds code to context switch the PPR when entering and exiting >> guests and to make the PPR value accessible through the SET/GET_ONE_REG >> interface. When entering the guest, we set the PPR as late as >> possible, because if we are setting a low thread priority it will >> make the code run slowly from that point on. Similarly, the >> first-level interrupt handlers save the PPR value in the PACA very >> early on, and set the thread priority to the medium level, so that >> the interrupt handling code runs at a reasonable speed. >> >> Signed-off-by: Paul Mackerras > > Acked-by: Benjamin Herrenschmidt > > Alex, can you take this via your tree ? Yes, on the next respin :). Or is this one urgent? Alex -- To unsubscribe from this list: send the line "unsubscribe kvm-ppc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 05/11] KVM: PPC: Book3S HV: Add support for guest Program Priority Register
On Fri, 2013-09-06 at 13:22 +1000, Paul Mackerras wrote:
> POWER7 and later IBM server processors have a register called the
> Program Priority Register (PPR), which controls the priority of
> each hardware CPU SMT thread, and affects how fast it runs compared
> to other SMT threads. This priority can be controlled by writing to
> the PPR or by use of a set of instructions of the form or rN,rN,rN
> which are otherwise no-ops but have been defined to set the priority
> to particular levels.
>
> This adds code to context switch the PPR when entering and exiting
> guests and to make the PPR value accessible through the SET/GET_ONE_REG
> interface. When entering the guest, we set the PPR as late as
> possible, because if we are setting a low thread priority it will
> make the code run slowly from that point on. Similarly, the
> first-level interrupt handlers save the PPR value in the PACA very
> early on, and set the thread priority to the medium level, so that
> the interrupt handling code runs at a reasonable speed.
>
> Signed-off-by: Paul Mackerras
Acked-by: Benjamin Herrenschmidt
Alex, can you take this via your tree ?
Cheers,
Ben.
> ---
> Documentation/virtual/kvm/api.txt | 1 +
> arch/powerpc/include/asm/exception-64s.h | 8
> arch/powerpc/include/asm/kvm_book3s_asm.h | 1 +
> arch/powerpc/include/asm/kvm_host.h | 1 +
> arch/powerpc/include/uapi/asm/kvm.h | 1 +
> arch/powerpc/kernel/asm-offsets.c | 2 ++
> arch/powerpc/kvm/book3s_hv.c | 6 ++
> arch/powerpc/kvm/book3s_hv_rmhandlers.S | 12 +++-
> 8 files changed, 31 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/virtual/kvm/api.txt
> b/Documentation/virtual/kvm/api.txt
> index 1030ac9..34a32b6 100644
> --- a/Documentation/virtual/kvm/api.txt
> +++ b/Documentation/virtual/kvm/api.txt
> @@ -1836,6 +1836,7 @@ registers, find a list below:
>PPC | KVM_REG_PPC_ACOP | 64
>PPC | KVM_REG_PPC_VRSAVE | 32
>PPC | KVM_REG_PPC_LPCR | 64
> + PPC | KVM_REG_PPC_PPR| 64
>PPC | KVM_REG_PPC_TM_GPR0| 64
>...
>PPC | KVM_REG_PPC_TM_GPR31 | 64
> diff --git a/arch/powerpc/include/asm/exception-64s.h
> b/arch/powerpc/include/asm/exception-64s.h
> index 07ca627..b86c4db 100644
> --- a/arch/powerpc/include/asm/exception-64s.h
> +++ b/arch/powerpc/include/asm/exception-64s.h
> @@ -203,6 +203,10 @@ do_kvm_##n:
> \
> ld r10,area+EX_CFAR(r13); \
> std r10,HSTATE_CFAR(r13); \
> END_FTR_SECTION_NESTED(CPU_FTR_CFAR,CPU_FTR_CFAR,947); \
> + BEGIN_FTR_SECTION_NESTED(948) \
> + ld r10,area+EX_PPR(r13); \
> + std r10,HSTATE_PPR(r13);\
> + END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948);\
> ld r10,area+EX_R10(r13); \
> stw r9,HSTATE_SCRATCH1(r13);\
> ld r9,area+EX_R9(r13); \
> @@ -216,6 +220,10 @@ do_kvm_##n:
> \
> ld r10,area+EX_R10(r13); \
> beq 89f;\
> stw r9,HSTATE_SCRATCH1(r13);\
> + BEGIN_FTR_SECTION_NESTED(948) \
> + ld r9,area+EX_PPR(r13);\
> + std r9,HSTATE_PPR(r13); \
> + END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948);\
> ld r9,area+EX_R9(r13); \
> std r12,HSTATE_SCRATCH0(r13); \
> li r12,n; \
> diff --git a/arch/powerpc/include/asm/kvm_book3s_asm.h
> b/arch/powerpc/include/asm/kvm_book3s_asm.h
> index 9039d3c..22f4606 100644
> --- a/arch/powerpc/include/asm/kvm_book3s_asm.h
> +++ b/arch/powerpc/include/asm/kvm_book3s_asm.h
> @@ -101,6 +101,7 @@ struct kvmppc_host_state {
> #endif
> #ifdef CONFIG_PPC_BOOK3S_64
> u64 cfar;
> + u64 ppr;
> #endif
> };
>
> diff --git a/arch/powerpc/include/asm/kvm_host.h
> b/arch/powerpc/include/asm/kvm_host.h
> index 9741bf0..b0dcd18 100644
> --- a/arch/powerpc/include/asm/kvm_host.h
> +++ b/arch/powerpc/include/asm/kvm_host.h
> @@ -464,6 +464,7 @@ struct kvm_vcpu_arch {
> u32 ctrl;
> ulong dabr;
> ulong cfar;
> + ulong ppr;
> #endif
> u32 vrsave; /* also USPRG0 */
> u32 mmucr;
> diff --git a/arch/powerpc/include/uapi/asm/kvm.h
> b/arch/powerpc/include/uapi/asm/kvm.h
> index e42127d..fab6bc1 100644
> --- a/arch/powerpc
Re: [PATCH 05/11] KVM: PPC: Book3S HV: Add support for guest Program Priority Register
On 05.09.2013, at 22:22, Paul Mackerras wrote: > POWER7 and later IBM server processors have a register called the > Program Priority Register (PPR), which controls the priority of > each hardware CPU SMT thread, and affects how fast it runs compared > to other SMT threads. This priority can be controlled by writing to > the PPR or by use of a set of instructions of the form or rN,rN,rN > which are otherwise no-ops but have been defined to set the priority > to particular levels. > > This adds code to context switch the PPR when entering and exiting > guests and to make the PPR value accessible through the SET/GET_ONE_REG > interface. When entering the guest, we set the PPR as late as > possible, because if we are setting a low thread priority it will > make the code run slowly from that point on. Similarly, the > first-level interrupt handlers save the PPR value in the PACA very > early on, and set the thread priority to the medium level, so that > the interrupt handling code runs at a reasonable speed. > > Signed-off-by: Paul Mackerras Reviewed-by: Alexander Graf Alex -- To unsubscribe from this list: send the line "unsubscribe kvm-ppc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 05/11] KVM: PPC: Book3S HV: Add support for guest Program Priority Register
POWER7 and later IBM server processors have a register called the
Program Priority Register (PPR), which controls the priority of
each hardware CPU SMT thread, and affects how fast it runs compared
to other SMT threads. This priority can be controlled by writing to
the PPR or by use of a set of instructions of the form or rN,rN,rN
which are otherwise no-ops but have been defined to set the priority
to particular levels.
This adds code to context switch the PPR when entering and exiting
guests and to make the PPR value accessible through the SET/GET_ONE_REG
interface. When entering the guest, we set the PPR as late as
possible, because if we are setting a low thread priority it will
make the code run slowly from that point on. Similarly, the
first-level interrupt handlers save the PPR value in the PACA very
early on, and set the thread priority to the medium level, so that
the interrupt handling code runs at a reasonable speed.
Signed-off-by: Paul Mackerras
---
Documentation/virtual/kvm/api.txt | 1 +
arch/powerpc/include/asm/exception-64s.h | 8
arch/powerpc/include/asm/kvm_book3s_asm.h | 1 +
arch/powerpc/include/asm/kvm_host.h | 1 +
arch/powerpc/include/uapi/asm/kvm.h | 1 +
arch/powerpc/kernel/asm-offsets.c | 2 ++
arch/powerpc/kvm/book3s_hv.c | 6 ++
arch/powerpc/kvm/book3s_hv_rmhandlers.S | 12 +++-
8 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/Documentation/virtual/kvm/api.txt
b/Documentation/virtual/kvm/api.txt
index 1030ac9..34a32b6 100644
--- a/Documentation/virtual/kvm/api.txt
+++ b/Documentation/virtual/kvm/api.txt
@@ -1836,6 +1836,7 @@ registers, find a list below:
PPC | KVM_REG_PPC_ACOP | 64
PPC | KVM_REG_PPC_VRSAVE | 32
PPC | KVM_REG_PPC_LPCR | 64
+ PPC | KVM_REG_PPC_PPR | 64
PPC | KVM_REG_PPC_TM_GPR0 | 64
...
PPC | KVM_REG_PPC_TM_GPR31 | 64
diff --git a/arch/powerpc/include/asm/exception-64s.h
b/arch/powerpc/include/asm/exception-64s.h
index 07ca627..b86c4db 100644
--- a/arch/powerpc/include/asm/exception-64s.h
+++ b/arch/powerpc/include/asm/exception-64s.h
@@ -203,6 +203,10 @@ do_kvm_##n:
\
ld r10,area+EX_CFAR(r13); \
std r10,HSTATE_CFAR(r13); \
END_FTR_SECTION_NESTED(CPU_FTR_CFAR,CPU_FTR_CFAR,947); \
+ BEGIN_FTR_SECTION_NESTED(948) \
+ ld r10,area+EX_PPR(r13); \
+ std r10,HSTATE_PPR(r13);\
+ END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948);\
ld r10,area+EX_R10(r13); \
stw r9,HSTATE_SCRATCH1(r13);\
ld r9,area+EX_R9(r13); \
@@ -216,6 +220,10 @@ do_kvm_##n:
\
ld r10,area+EX_R10(r13); \
beq 89f;\
stw r9,HSTATE_SCRATCH1(r13);\
+ BEGIN_FTR_SECTION_NESTED(948) \
+ ld r9,area+EX_PPR(r13);\
+ std r9,HSTATE_PPR(r13); \
+ END_FTR_SECTION_NESTED(CPU_FTR_HAS_PPR,CPU_FTR_HAS_PPR,948);\
ld r9,area+EX_R9(r13); \
std r12,HSTATE_SCRATCH0(r13); \
li r12,n; \
diff --git a/arch/powerpc/include/asm/kvm_book3s_asm.h
b/arch/powerpc/include/asm/kvm_book3s_asm.h
index 9039d3c..22f4606 100644
--- a/arch/powerpc/include/asm/kvm_book3s_asm.h
+++ b/arch/powerpc/include/asm/kvm_book3s_asm.h
@@ -101,6 +101,7 @@ struct kvmppc_host_state {
#endif
#ifdef CONFIG_PPC_BOOK3S_64
u64 cfar;
+ u64 ppr;
#endif
};
diff --git a/arch/powerpc/include/asm/kvm_host.h
b/arch/powerpc/include/asm/kvm_host.h
index 9741bf0..b0dcd18 100644
--- a/arch/powerpc/include/asm/kvm_host.h
+++ b/arch/powerpc/include/asm/kvm_host.h
@@ -464,6 +464,7 @@ struct kvm_vcpu_arch {
u32 ctrl;
ulong dabr;
ulong cfar;
+ ulong ppr;
#endif
u32 vrsave; /* also USPRG0 */
u32 mmucr;
diff --git a/arch/powerpc/include/uapi/asm/kvm.h
b/arch/powerpc/include/uapi/asm/kvm.h
index e42127d..fab6bc1 100644
--- a/arch/powerpc/include/uapi/asm/kvm.h
+++ b/arch/powerpc/include/uapi/asm/kvm.h
@@ -534,6 +534,7 @@ struct kvm_get_htab_header {
#define KVM_REG_PPC_VRSAVE (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb4)
#define KVM_REG_PPC_LPCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb5)
+#define KVM_REG_PPC_PPR
