Re: [PATCH 1/5] kvm/powerpc: Enable MPIC for E500 platform.

2009-03-02 Thread Aurelien Jarno 
On Fri, Feb 27, 2009 at 10:04:17PM +0200, Blue Swirl wrote:
 On 2/27/09, Liu Yu-B13201 yu@freescale.com wrote:
 
 
-Original Message-
From: Blue Swirl [mailto:blauwir...@gmail.com]
Sent: Friday, February 27, 2009 2:47 AM
To: Liu Yu-B13201
Cc: qemu-de...@nongnu.org; aurel...@aurel32.net;
holl...@us.ibm.com; kvm-ppc@vger.kernel.org
Subject: Re: [PATCH 1/5] kvm/powerpc: Enable MPIC for E500 platform.
   
On 2/26/09, Liu Yu yu@freescale.com wrote:
 MPIC and OpenPIC have very similar design.
  So a lot of code can be reused.

  Modification mainly include:
  1. keep struct openpic_t to the maximum size of both MPIC
and OpenPIC.
  2. endianess swap.
MPIC has the same endianess as target, so no need to
swap for MPIC.
  3. using different init functions and function pointers
for reset and irq raise.

  Haven't test OpenPIC.

  Signed-off-by: Liu Yu yu@freescale.com
   
  +struct {
  +CPUReadMemoryFunc **read;
  +CPUWriteMemoryFunc **write;
  +target_phys_addr_t start_addr;
  +ram_addr_t size;
  +} list[] = {
  +{mpic_glb_read, mpic_glb_write,
MPIC_GLB_REG_START, MPIC_GLB_REG_SIZE},
  +{mpic_tmr_read, mpic_tmr_write,
MPIC_TMR_REG_START, MPIC_TMR_REG_SIZE},
  +{mpic_ext_read, mpic_ext_write,
MPIC_EXT_REG_START, MPIC_EXT_REG_SIZE},
  +{mpic_int_read, mpic_int_write,
MPIC_INT_REG_START, MPIC_INT_REG_SIZE},
  +{mpic_msg_read, mpic_msg_write,
MPIC_MSG_REG_START, MPIC_MSG_REG_SIZE},
  +{mpic_msi_read, mpic_msi_write,
MPIC_MSI_REG_START, MPIC_MSI_REG_SIZE},
  +{mpic_cpu_read, mpic_cpu_write,
MPIC_CPU_REG_START, MPIC_CPU_REG_SIZE},
  +};
   
static const ?
   
 
 
  Why static? It's allocated on stack and will be free when function return.
 
 True, but it will be constructed for every call. But as this function
 will be called only once, it does not matter too much.
 

I have committed another patch to fix that.

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Re: [PATCH 1/5] kvm/powerpc: Enable MPIC for E500 platform.

2009-02-27 Thread Blue Swirl 
On 2/27/09, Liu Yu-B13201 yu@freescale.com wrote:


   -Original Message-
   From: Blue Swirl [mailto:blauwir...@gmail.com]
   Sent: Friday, February 27, 2009 2:47 AM
   To: Liu Yu-B13201
   Cc: qemu-de...@nongnu.org; aurel...@aurel32.net;
   holl...@us.ibm.com; kvm-ppc@vger.kernel.org
   Subject: Re: [PATCH 1/5] kvm/powerpc: Enable MPIC for E500 platform.
  
   On 2/26/09, Liu Yu yu@freescale.com wrote:
MPIC and OpenPIC have very similar design.
 So a lot of code can be reused.
   
 Modification mainly include:
 1. keep struct openpic_t to the maximum size of both MPIC
   and OpenPIC.
 2. endianess swap.
   MPIC has the same endianess as target, so no need to
   swap for MPIC.
 3. using different init functions and function pointers
   for reset and irq raise.
   
 Haven't test OpenPIC.
   
 Signed-off-by: Liu Yu yu@freescale.com
  
 +struct {
 +CPUReadMemoryFunc **read;
 +CPUWriteMemoryFunc **write;
 +target_phys_addr_t start_addr;
 +ram_addr_t size;
 +} list[] = {
 +{mpic_glb_read, mpic_glb_write,
   MPIC_GLB_REG_START, MPIC_GLB_REG_SIZE},
 +{mpic_tmr_read, mpic_tmr_write,
   MPIC_TMR_REG_START, MPIC_TMR_REG_SIZE},
 +{mpic_ext_read, mpic_ext_write,
   MPIC_EXT_REG_START, MPIC_EXT_REG_SIZE},
 +{mpic_int_read, mpic_int_write,
   MPIC_INT_REG_START, MPIC_INT_REG_SIZE},
 +{mpic_msg_read, mpic_msg_write,
   MPIC_MSG_REG_START, MPIC_MSG_REG_SIZE},
 +{mpic_msi_read, mpic_msi_write,
   MPIC_MSI_REG_START, MPIC_MSI_REG_SIZE},
 +{mpic_cpu_read, mpic_cpu_write,
   MPIC_CPU_REG_START, MPIC_CPU_REG_SIZE},
 +};
  
   static const ?
  


 Why static? It's allocated on stack and will be free when function return.

True, but it will be constructed for every call. But as this function
will be called only once, it does not matter too much.
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[PATCH 1/5] kvm/powerpc: Enable MPIC for E500 platform.

2009-02-26 Thread Liu Yu 
MPIC and OpenPIC have very similar design.
So a lot of code can be reused.

Modification mainly include:
1. keep struct openpic_t to the maximum size of both MPIC and OpenPIC.
2. endianess swap.
   MPIC has the same endianess as target, so no need to swap for MPIC.
3. using different init functions and function pointers for reset and irq raise.

Haven't test OpenPIC.

Signed-off-by: Liu Yu yu@freescale.com
---
v4:
1.register different handlers for different memory areas.
2.increase openpic save version number.
3.register mpic reset handler with qemu_register_reset.

 hw/openpic.c  |  673 +++--
 hw/openpic.h  |   18 ++
 hw/ppc_mac.h  |   13 -
 hw/ppc_newworld.c |1 +
 4 files changed, 618 insertions(+), 87 deletions(-)
 create mode 100644 hw/openpic.h

diff --git a/hw/openpic.c b/hw/openpic.c
index 6dfb590..6e4126b 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -35,6 +35,7 @@
 #include hw.h
 #include ppc_mac.h
 #include pci.h
+#include openpic.h
 
 //#define DEBUG_OPENPIC
 
@@ -60,14 +61,10 @@
 
 #define VID (0x)
 
-#define OPENPIC_LITTLE_ENDIAN 1
-#define OPENPIC_BIG_ENDIAN0
-
 #elif defined(USE_MPCxxx)
 
 #define MAX_CPU 2
-#define MAX_IRQ64
-#define EXT_IRQ48
+#define MAX_IRQ   128
 #define MAX_DBL 0
 #define MAX_MBX 0
 #define MAX_TMR 4
@@ -81,28 +78,68 @@ enum {
 IRQ_IDE,
 };
 
-#define OPENPIC_LITTLE_ENDIAN 1
-#define OPENPIC_BIG_ENDIAN0
+/* OpenPIC */
+#define OPENPIC_MAX_CPU  2
+#define OPENPIC_MAX_IRQ 64
+#define OPENPIC_EXT_IRQ 48
+#define OPENPIC_MAX_TMR  MAX_TMR
+#define OPENPIC_MAX_IPI  MAX_IPI
 
+/* Interrupt definitions */
+#define OPENPIC_IRQ_FE (OPENPIC_EXT_IRQ) /* Internal functional IRQ */
+#define OPENPIC_IRQ_ERR(OPENPIC_EXT_IRQ + 1) /* Error IRQ */
+#define OPENPIC_IRQ_TIM0   (OPENPIC_EXT_IRQ + 2) /* First timer IRQ */
+#if OPENPIC_MAX_IPI  0
+#define OPENPIC_IRQ_IPI0   (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First IPI 
IRQ */
+#define OPENPIC_IRQ_DBL0   (OPENPIC_IRQ_IPI0 + (OPENPIC_MAX_CPU * 
OPENPIC_MAX_IPI)) /* First doorbell IRQ */
 #else
-#error Please select which OpenPic implementation is to be emulated
+#define OPENPIC_IRQ_DBL0   (OPENPIC_IRQ_TIM0 + OPENPIC_MAX_TMR) /* First 
doorbell IRQ */
+#define OPENPIC_IRQ_MBX0   (OPENPIC_IRQ_DBL0 + OPENPIC_MAX_DBL) /* First 
mailbox IRQ */
 #endif
 
-#if (OPENPIC_BIG_ENDIAN  !TARGET_WORDS_BIGENDIAN) || \
-(OPENPIC_LITTLE_ENDIAN  TARGET_WORDS_BIGENDIAN)
-#define OPENPIC_SWAP
-#endif
+/* MPIC */
+#define MPIC_MAX_CPU  1
+#define MPIC_MAX_EXT 12
+#define MPIC_MAX_INT 64
+#define MPIC_MAX_MSG  4
+#define MPIC_MAX_MSI  8
+#define MPIC_MAX_TMR  MAX_TMR
+#define MPIC_MAX_IPI  MAX_IPI
+#define MPIC_MAX_IRQ (MPIC_MAX_EXT + MPIC_MAX_INT + MPIC_MAX_TMR + 
MPIC_MAX_MSG + MPIC_MAX_MSI + (MPIC_MAX_IPI * MPIC_MAX_CPU))
 
 /* Interrupt definitions */
-#define IRQ_FE (EXT_IRQ) /* Internal functional IRQ */
-#define IRQ_ERR(EXT_IRQ + 1) /* Error IRQ */
-#define IRQ_TIM0   (EXT_IRQ + 2) /* First timer IRQ */
-#if MAX_IPI  0
-#define IRQ_IPI0   (IRQ_TIM0 + MAX_TMR) /* First IPI IRQ */
-#define IRQ_DBL0   (IRQ_IPI0 + (MAX_CPU * MAX_IPI)) /* First doorbell IRQ */
+#define MPIC_EXT_IRQ  0
+#define MPIC_INT_IRQ  (MPIC_EXT_IRQ + MPIC_MAX_EXT)
+#define MPIC_TMR_IRQ  (MPIC_INT_IRQ + MPIC_MAX_INT)
+#define MPIC_MSG_IRQ  (MPIC_TMR_IRQ + MPIC_MAX_TMR)
+#define MPIC_MSI_IRQ  (MPIC_MSG_IRQ + MPIC_MAX_MSG)
+#define MPIC_IPI_IRQ  (MPIC_MSI_IRQ + MPIC_MAX_MSI)
+
+#define MPIC_GLB_REG_START0x0
+#define MPIC_GLB_REG_SIZE 0x10F0
+#define MPIC_TMR_REG_START0x10F0
+#define MPIC_TMR_REG_SIZE 0x220
+#define MPIC_EXT_REG_START0x1
+#define MPIC_EXT_REG_SIZE 0x180
+#define MPIC_INT_REG_START0x10200
+#define MPIC_INT_REG_SIZE 0x800
+#define MPIC_MSG_REG_START0x11600
+#define MPIC_MSG_REG_SIZE 0x100
+#define MPIC_MSI_REG_START0x11C00
+#define MPIC_MSI_REG_SIZE 0x100
+#define MPIC_CPU_REG_START0x2
+#define MPIC_CPU_REG_SIZE 0x100
+
+enum mpic_ide_bits {
+IDR_EP = 0,
+IDR_CI0 = 1,
+IDR_CI1 = 2,
+IDR_P1 = 30,
+IDR_P0 = 31,
+};
+
 #else
-#define IRQ_DBL0   (IRQ_TIM0 + MAX_TMR) /* First doorbell IRQ */
-#define IRQ_MBX0   (IRQ_DBL0 + MAX_DBL) /* First mailbox IRQ */
+#error Please select which OpenPic implementation is to be emulated
 #endif
 
 #define BF_WIDTH(_bits_) \
@@ -157,6 +194,7 @@ enum IPVP_bits {
 #define IPVP_VECTOR(_ipvpr_)   ((_ipvpr_)  IPVP_VECTOR_MASK)
 
 typedef struct IRQ_dst_t {
+uint32_t tfrr;
 uint32_t pctp; /* CPU current task priority */
 uint32_t pcsr; /* CPU sensitivity register */
 IRQ_queue_t raised;
@@ -200,8 +238,22 @@ typedef struct openpic_t {
 #endif
 /* IRQ out is used when in bypass mode (not implemented) */
 qemu_irq irq_out;
+int max_irq;
+int irq_ipi0;

Re: [Qemu-devel] [PATCH 1/5] kvm/powerpc: Enable MPIC for E500 platform.

2009-02-20 Thread Blue Swirl 
On 2/20/09, Aurelien Jarno aurel...@aurel32.net wrote:
 On Tue, Feb 17, 2009 at 04:55:51PM +0200, Blue Swirl wrote:
   On 2/17/09, Liu Yu yu@freescale.com wrote:
MPIC and OpenPIC have very similar design.
 So a lot of code can be reused.
   
 Modification mainly include:
 1. keep struct openpic_t to the maximum size of both MPIC and OpenPIC.
 2. endianess swap.
   MPIC has the same endianess as target, so no need to swap for MPIC.
  
   I don't think this is correct, the host can still be different endian
   from target.
  


 I do not agree. As long as we don't manipulate host memory, the host
  endianess has nothing to do. The values are simply passed by value, they
  don't need to be swapped.

Sorry, I stand corrected.
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Re: [Qemu-devel] [PATCH 1/5] kvm/powerpc: Enable MPIC for E500 platform.

2009-02-19 Thread Aurelien Jarno 
On Tue, Feb 17, 2009 at 04:55:51PM +0200, Blue Swirl wrote:
 On 2/17/09, Liu Yu yu@freescale.com wrote:
  MPIC and OpenPIC have very similar design.
   So a lot of code can be reused.
 
   Modification mainly include:
   1. keep struct openpic_t to the maximum size of both MPIC and OpenPIC.
   2. endianess swap.
 MPIC has the same endianess as target, so no need to swap for MPIC.
 
 I don't think this is correct, the host can still be different endian
 from target.
 

I do not agree. As long as we don't manipulate host memory, the host
endianess has nothing to do. The values are simply passed by value, they
don't need to be swapped.

-- 
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aurel...@aurel32.net http://www.aurel32.net
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RE: [Qemu-devel] [PATCH 1/5] kvm/powerpc: Enable MPIC for E500 platform.

2009-02-17 Thread Liu Yu-B13201 

 -Original Message-
 From: Blue Swirl [mailto:blauwir...@gmail.com] 
 Sent: Tuesday, February 17, 2009 10:56 PM
 To: qemu-de...@nongnu.org
 Cc: aurel...@aurel32.net; holl...@us.ibm.com; Liu Yu-B13201; 
 kvm-ppc@vger.kernel.org
 Subject: Re: [Qemu-devel] [PATCH 1/5] kvm/powerpc: Enable 
 MPIC for E500 platform.
 
 On 2/17/09, Liu Yu yu@freescale.com wrote:
  MPIC and OpenPIC have very similar design.
   So a lot of code can be reused.
 
   Modification mainly include:
   1. keep struct openpic_t to the maximum size of both MPIC 
 and OpenPIC.
   2. endianess swap.
 MPIC has the same endianess as target, so no need to 
 swap for MPIC.
 
 I don't think this is correct, the host can still be different endian
 from target.
 

How does host endian involve?
Test a certain bit written by guest?


   3. using different init functions and function pointers 
 for reset and irq raise.
 
 You didn't register the reset handler with qemu_register_reset.
 

Fixed.

   Haven't test OpenPIC.
 
   Signed-off-by: Liu Yu yu@freescale.com
 
   +static void mpic_src_write (void *opaque, uint32_t addr, 
 uint32_t val)
 
   +if (addr  0x180) {
   +idx = MPIC_EXT_IRQ;
   +} else if (addr = 0x200  addr  0xa00) {
   +idx = MPIC_INT_IRQ;
   +addr -= 0x200;
   +} else if (addr = 0x1600  addr  0x1700) {
   +idx = MPIC_MSG_IRQ;
   +addr -= 0x1600;
   +} else if (addr = 0x1C00  addr  0x1D00) {
   +idx = MPIC_MSI_IRQ;
   +addr -= 0x1C00;
   +} else {
   +return;
 
 It would be faster and simpler to register different handlers for
 these memory areas, same goes for mpic_src_read, mpic_writel and
 mpic_readl.
 
Hmmm, will fix.

   +register_savevm(mpic, 0, 1, openpic_save, 
 openpic_load,  mpp);
 
 When the save format changes, the version number should be bumped.
 

Fixed.