[PATCH 1/8] Move PPC4xx SDRAM controller emulation from ppc405_uc.c to ppc4xx_devs.c

2008-12-15 Thread Hollis Blanchard 
The SDRAM controller is shared across almost all 405 and 440 embedded
processors, with some slight differences such as the sizes supported for each
memory bank.

Code movement only; no functional changes.

Signed-off-by: Hollis Blanchard holl...@us.ibm.com
---
I think all device emulation should move from ppc405_uc.c to ppc4xx_devs.c,
since it is shared between all 4xx SoCs (405 and 440). At the moment, the SDRAM
controller is the only piece I have code for, so I'm only moving it.

(I can only guess uc means microcontroller; the file should be renamed as
well.)
---
 hw/ppc405.h  |5 -
 hw/ppc405_uc.c   |  341 --
 hw/ppc4xx.h  |5 +
 hw/ppc4xx_devs.c |  341 ++
 4 files changed, 346 insertions(+), 346 deletions(-)

diff --git a/hw/ppc405.h b/hw/ppc405.h
index e032170..eebcef3 100644
--- a/hw/ppc405.h
+++ b/hw/ppc405.h
@@ -66,11 +66,6 @@ void ppc4xx_pob_init (CPUState *env);
 /* OPB arbitrer */
 void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,
target_phys_addr_t offset);
-/* SDRAM controller */
-void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
-target_phys_addr_t *ram_bases,
-target_phys_addr_t *ram_sizes,
-int do_init);
 /* Peripheral controller */
 void ppc405_ebc_init (CPUState *env);
 /* DMA controller */
diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c
index 25bcfd8..7e7fb38 100644
--- a/hw/ppc405_uc.c
+++ b/hw/ppc405_uc.c
@@ -401,347 +401,6 @@ void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,
 /* XXX: TODO */
 
 /*/
-/* SDRAM controller */
-typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
-struct ppc4xx_sdram_t {
-uint32_t addr;
-int nbanks;
-target_phys_addr_t ram_bases[4];
-target_phys_addr_t ram_sizes[4];
-uint32_t besr0;
-uint32_t besr1;
-uint32_t bear;
-uint32_t cfg;
-uint32_t status;
-uint32_t rtr;
-uint32_t pmit;
-uint32_t bcr[4];
-uint32_t tr;
-uint32_t ecccfg;
-uint32_t eccesr;
-qemu_irq irq;
-};
-
-enum {
-SDRAM0_CFGADDR = 0x010,
-SDRAM0_CFGDATA = 0x011,
-};
-
-/* XXX: TOFIX: some patches have made this code become inconsistent:
- *  there are type inconsistencies, mixing target_phys_addr_t, target_ulong
- *  and uint32_t
- */
-static uint32_t sdram_bcr (target_phys_addr_t ram_base,
-   target_phys_addr_t ram_size)
-{
-uint32_t bcr;
-
-switch (ram_size) {
-case (4 * 1024 * 1024):
-bcr = 0x;
-break;
-case (8 * 1024 * 1024):
-bcr = 0x0002;
-break;
-case (16 * 1024 * 1024):
-bcr = 0x0004;
-break;
-case (32 * 1024 * 1024):
-bcr = 0x0006;
-break;
-case (64 * 1024 * 1024):
-bcr = 0x0008;
-break;
-case (128 * 1024 * 1024):
-bcr = 0x000A;
-break;
-case (256 * 1024 * 1024):
-bcr = 0x000C;
-break;
-default:
-printf(%s: invalid RAM size  PADDRX \n, __func__, ram_size);
-return 0x;
-}
-bcr |= ram_base  0xFF80;
-bcr |= 1;
-
-return bcr;
-}
-
-static always_inline target_phys_addr_t sdram_base (uint32_t bcr)
-{
-return bcr  0xFF80;
-}
-
-static target_ulong sdram_size (uint32_t bcr)
-{
-target_ulong size;
-int sh;
-
-sh = (bcr  17)  0x7;
-if (sh == 7)
-size = -1;
-else
-size = (4 * 1024 * 1024)  sh;
-
-return size;
-}
-
-static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
-{
-if (*bcrp  0x0001) {
-/* Unmap RAM */
-#ifdef DEBUG_SDRAM
-printf(%s: unmap RAM area  PADDRX   ADDRX \n,
-   __func__, sdram_base(*bcrp), sdram_size(*bcrp));
-#endif
-cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp),
- IO_MEM_UNASSIGNED);
-}
-*bcrp = bcr  0xFFDEE001;
-if (enabled  (bcr  0x0001)) {
-#ifdef DEBUG_SDRAM
-printf(%s: Map RAM area  PADDRX   ADDRX \n,
-   __func__, sdram_base(bcr), sdram_size(bcr));
-#endif
-cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr),
- sdram_base(bcr) | IO_MEM_RAM);
-}
-}
-
-static void sdram_map_bcr (ppc4xx_sdram_t *sdram)
-{
-int i;
-
-for (i = 0; i  sdram-nbanks; i++) {
-if (sdram-ram_sizes[i] != 0) {
-sdram_set_bcr(sdram-bcr[i],
-  sdram_bcr(sdram-ram_bases[i], sdram-ram_sizes[i]),
-  1);
-} else {
-sdram_set_bcr(sdram-bcr[i], 0x, 0);
-}
-}
-}
-
-static void sdram_unmap_bcr (ppc4xx_sdram_t *sdram)
-{
-int i;
-
-for (i = 0; i  sdram-nbanks; i++) {
-#ifdef DEBUG_SDRAM
-

Re: [Qemu-devel] [PATCH 1/8] Move PPC4xx SDRAM controller emulation from ppc405_uc.c to ppc4xx_devs.c

2008-12-15 Thread Aurelien Jarno 
On Mon, Dec 15, 2008 at 10:44:12AM -0600, Hollis Blanchard wrote:
 The SDRAM controller is shared across almost all 405 and 440 embedded
 processors, with some slight differences such as the sizes supported for each
 memory bank.
 
 Code movement only; no functional changes.
 
 Signed-off-by: Hollis Blanchard holl...@us.ibm.com

Thanks, applied.

 ---
 I think all device emulation should move from ppc405_uc.c to ppc4xx_devs.c,
 since it is shared between all 4xx SoCs (405 and 440). At the moment, the 
 SDRAM
 controller is the only piece I have code for, so I'm only moving it.
 
 (I can only guess uc means microcontroller; the file should be renamed as
 well.)
 ---
  hw/ppc405.h  |5 -
  hw/ppc405_uc.c   |  341 
 --
  hw/ppc4xx.h  |5 +
  hw/ppc4xx_devs.c |  341 
 ++
  4 files changed, 346 insertions(+), 346 deletions(-)
 
 diff --git a/hw/ppc405.h b/hw/ppc405.h
 index e032170..eebcef3 100644
 --- a/hw/ppc405.h
 +++ b/hw/ppc405.h
 @@ -66,11 +66,6 @@ void ppc4xx_pob_init (CPUState *env);
  /* OPB arbitrer */
  void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,
 target_phys_addr_t offset);
 -/* SDRAM controller */
 -void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
 -target_phys_addr_t *ram_bases,
 -target_phys_addr_t *ram_sizes,
 -int do_init);
  /* Peripheral controller */
  void ppc405_ebc_init (CPUState *env);
  /* DMA controller */
 diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c
 index 25bcfd8..7e7fb38 100644
 --- a/hw/ppc405_uc.c
 +++ b/hw/ppc405_uc.c
 @@ -401,347 +401,6 @@ void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t 
 *mmio,
  /* XXX: TODO */
  
  
 /*/
 -/* SDRAM controller */
 -typedef struct ppc4xx_sdram_t ppc4xx_sdram_t;
 -struct ppc4xx_sdram_t {
 -uint32_t addr;
 -int nbanks;
 -target_phys_addr_t ram_bases[4];
 -target_phys_addr_t ram_sizes[4];
 -uint32_t besr0;
 -uint32_t besr1;
 -uint32_t bear;
 -uint32_t cfg;
 -uint32_t status;
 -uint32_t rtr;
 -uint32_t pmit;
 -uint32_t bcr[4];
 -uint32_t tr;
 -uint32_t ecccfg;
 -uint32_t eccesr;
 -qemu_irq irq;
 -};
 -
 -enum {
 -SDRAM0_CFGADDR = 0x010,
 -SDRAM0_CFGDATA = 0x011,
 -};
 -
 -/* XXX: TOFIX: some patches have made this code become inconsistent:
 - *  there are type inconsistencies, mixing target_phys_addr_t, 
 target_ulong
 - *  and uint32_t
 - */
 -static uint32_t sdram_bcr (target_phys_addr_t ram_base,
 -   target_phys_addr_t ram_size)
 -{
 -uint32_t bcr;
 -
 -switch (ram_size) {
 -case (4 * 1024 * 1024):
 -bcr = 0x;
 -break;
 -case (8 * 1024 * 1024):
 -bcr = 0x0002;
 -break;
 -case (16 * 1024 * 1024):
 -bcr = 0x0004;
 -break;
 -case (32 * 1024 * 1024):
 -bcr = 0x0006;
 -break;
 -case (64 * 1024 * 1024):
 -bcr = 0x0008;
 -break;
 -case (128 * 1024 * 1024):
 -bcr = 0x000A;
 -break;
 -case (256 * 1024 * 1024):
 -bcr = 0x000C;
 -break;
 -default:
 -printf(%s: invalid RAM size  PADDRX \n, __func__, ram_size);
 -return 0x;
 -}
 -bcr |= ram_base  0xFF80;
 -bcr |= 1;
 -
 -return bcr;
 -}
 -
 -static always_inline target_phys_addr_t sdram_base (uint32_t bcr)
 -{
 -return bcr  0xFF80;
 -}
 -
 -static target_ulong sdram_size (uint32_t bcr)
 -{
 -target_ulong size;
 -int sh;
 -
 -sh = (bcr  17)  0x7;
 -if (sh == 7)
 -size = -1;
 -else
 -size = (4 * 1024 * 1024)  sh;
 -
 -return size;
 -}
 -
 -static void sdram_set_bcr (uint32_t *bcrp, uint32_t bcr, int enabled)
 -{
 -if (*bcrp  0x0001) {
 -/* Unmap RAM */
 -#ifdef DEBUG_SDRAM
 -printf(%s: unmap RAM area  PADDRX   ADDRX \n,
 -   __func__, sdram_base(*bcrp), sdram_size(*bcrp));
 -#endif
 -cpu_register_physical_memory(sdram_base(*bcrp), sdram_size(*bcrp),
 - IO_MEM_UNASSIGNED);
 -}
 -*bcrp = bcr  0xFFDEE001;
 -if (enabled  (bcr  0x0001)) {
 -#ifdef DEBUG_SDRAM
 -printf(%s: Map RAM area  PADDRX   ADDRX \n,
 -   __func__, sdram_base(bcr), sdram_size(bcr));
 -#endif
 -cpu_register_physical_memory(sdram_base(bcr), sdram_size(bcr),
 - sdram_base(bcr) | IO_MEM_RAM);
 -}
 -}
 -
 -static void sdram_map_bcr (ppc4xx_sdram_t *sdram)
 -{
 -int i;
 -
 -for (i = 0; i  sdram-nbanks; i++) {
 -if (sdram-ram_sizes[i] != 0) {
 -sdram_set_bcr(sdram-bcr[i],
 -  sdram_bcr(sdram-ram_bases[i], 
 sdram-ram_sizes[i]),
 -