The SDRAM controller is shared across almost all 405 and 440 embedded
processors, with some slight differences such as the sizes supported for each
memory bank.
Rename only; no functional changes.
Signed-off-by: Hollis Blanchard <holl...@us.ibm.com>
---
hw/ppc405_uc.c | 4 ++--
hw/ppc4xx.h | 2 +-
hw/ppc4xx_devs.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/ppc405_uc.c b/hw/ppc405_uc.c
index 7e7fb38..9275416 100644
--- a/hw/ppc405_uc.c
+++ b/hw/ppc405_uc.c
@@ -2230,7 +2230,7 @@ CPUState *ppc405cr_init (target_phys_addr_t ram_bases[4],
pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
*picp = pic;
/* SDRAM controller */
- ppc405_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init);
+ ppc4xx_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init);
offset = 0;
for (i = 0; i < 4; i++)
offset += ram_sizes[i];
@@ -2588,7 +2588,7 @@ CPUState *ppc405ep_init (target_phys_addr_t ram_bases[2],
*picp = pic;
/* SDRAM controller */
/* XXX 405EP has no ECC interrupt */
- ppc405_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init);
+ ppc4xx_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init);
offset = 0;
for (i = 0; i < 2; i++)
offset += ram_sizes[i];
diff --git a/hw/ppc4xx.h b/hw/ppc4xx.h
index 8c2878a..3b98662 100644
--- a/hw/ppc4xx.h
+++ b/hw/ppc4xx.h
@@ -48,7 +48,7 @@ enum {
qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,
uint32_t dcr_base, int has_ssr, int has_vr);
-void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
+void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
target_phys_addr_t *ram_bases,
target_phys_addr_t *ram_sizes,
int do_init);
diff --git a/hw/ppc4xx_devs.c b/hw/ppc4xx_devs.c
index c6be2d6..2d27e23 100644
--- a/hw/ppc4xx_devs.c
+++ b/hw/ppc4xx_devs.c
@@ -846,7 +846,7 @@ static void sdram_reset (void *opaque)
sdram_unmap_bcr(sdram);
}
-void ppc405_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
+void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
target_phys_addr_t *ram_bases,
target_phys_addr_t *ram_sizes,
int do_init)
--
1.5.6.5
--
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