On Tue, 2008-12-16 at 11:45 +0100, Aurelien Jarno wrote: > On Mon, Dec 15, 2008 at 06:17:31PM -0600, Hollis Blanchard wrote: > > Wire up the system-on-chip devices present on 440EP chips. > > > > This patch is a little unusual in that qemu doesn't actually emulate the 440 > > core, but we use this board code with KVM (which does). If/when 440 core > > emulation is supported, the kvm_enabled() hack can be removed. > > > > What are the mains differences between 405 and 440 cores? Would it be > easy to add support for 440 core in QEMU?
It's been a while since I programmed for the 405, but from memory: Unlike the 405, the 440 is a Book E core. The biggest difference is that there is no real mode; MMU translation is always active. MSR[IR] and DR have been replaced with IS and DS, and those "address space" bits contribute to the 41-bit virtual address (32-bit effective, 8-bit PID like 405, 1-bit AS). The TLB organization is pretty much the same as 405 (64-entry fully associative), though the data in each entry has changed a little. Fixed interrupt vectors have been replaced with programmable ones, via the IVPR base register and 16 IVOR registers, indicating the offset of each vector from IVPR. There is a Application Note that more fully lists the software differences: https://www.amcc.com/MyAMCC/retrieveDocument/PowerPC/440GP/PPC440GP_AN2020_SWC405GP.pdf Because the MMU is always on, tlbia doesn't exist any more. There are a few other minor instruction and register changes. As I've mentioned, most 440 peripherals are the same or similar to 405, which is definitely helpful. -- Hollis Blanchard IBM Linux Technology Center -- To unsubscribe from this list: send the line "unsubscribe kvm-ppc" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html