Re: [PATCH 00/59] KVM: arm64: ARMv8.3 Nested Virtualization support
On 8/22/19 12:57 PM, Alexandru Elisei wrote:
> [..]
> I tried to fix it with the following patch, inject_undef64 was similarly
> broken:
>
> diff --git a/arch/arm64/kvm/inject_fault.c b/arch/arm64/kvm/inject_fault.c
> index fac962b467bd..aee8a9ef36d5 100644
> --- a/arch/arm64/kvm/inject_fault.c
> +++ b/arch/arm64/kvm/inject_fault.c
> @@ -53,15 +53,7 @@ static void inject_abt64(struct kvm_vcpu *vcpu, bool
> is_iabt,
> unsigned long addr
> {
> unsigned long cpsr = *vcpu_cpsr(vcpu);
> bool is_aarch32 = vcpu_mode_is_32bit(vcpu);
> - u32 esr = 0;
> -
> - vcpu_write_elr_el1(vcpu, *vcpu_pc(vcpu));
> - *vcpu_pc(vcpu) = get_except_vector(vcpu, except_type_sync);
> -
> - *vcpu_cpsr(vcpu) = PSTATE_FAULT_BITS_64;
> - vcpu_write_spsr(vcpu, cpsr);
> -
> - vcpu_write_sys_reg(vcpu, addr, FAR_EL1);
> + u32 esr = ESR_ELx_FSC_EXTABT;
>
> /*
> * Build an {i,d}abort, depending on the level and the
> @@ -82,13 +74,12 @@ static void inject_abt64(struct kvm_vcpu *vcpu, bool
> is_iabt, unsigned long addr
> if (!is_iabt)
> esr |= ESR_ELx_EC_DABT_LOW << ESR_ELx_EC_SHIFT;
>
> - vcpu_write_sys_reg(vcpu, esr | ESR_ELx_FSC_EXTABT, ESR_EL1);
> -}
> + if (nested_virt_in_use(vcpu)) {
> + kvm_inject_nested_sync(vcpu, esr);
> + return;
> + }
>
> -static void inject_undef64(struct kvm_vcpu *vcpu)
> -{
> - unsigned long cpsr = *vcpu_cpsr(vcpu);
> - u32 esr = (ESR_ELx_EC_UNKNOWN << ESR_ELx_EC_SHIFT);
> + vcpu_write_sys_reg(vcpu, esr, ESR_EL1);
>
> vcpu_write_elr_el1(vcpu, *vcpu_pc(vcpu));
> *vcpu_pc(vcpu) = get_except_vector(vcpu, except_type_sync);
> @@ -96,6 +87,14 @@ static void inject_undef64(struct kvm_vcpu *vcpu)
> *vcpu_cpsr(vcpu) = PSTATE_FAULT_BITS_64;
> vcpu_write_spsr(vcpu, cpsr);
>
> + vcpu_write_sys_reg(vcpu, addr, FAR_EL1);
> +}
> +
> +static void inject_undef64(struct kvm_vcpu *vcpu)
> +{
> + unsigned long cpsr = *vcpu_cpsr(vcpu);
> + u32 esr = ESR_ELx_EC_UNKNOWN << ESR_ELx_EC_SHIFT;
> +
> /*
> * Build an unknown exception, depending on the instruction
> * set.
> @@ -103,7 +102,18 @@ static void inject_undef64(struct kvm_vcpu *vcpu)
> if (kvm_vcpu_trap_il_is32bit(vcpu))
> esr |= ESR_ELx_IL;
>
> + if (nested_virt_in_use(vcpu)) {
> + kvm_inject_nested_sync(vcpu, esr);
> + return;
> + }
> +
> vcpu_write_sys_reg(vcpu, esr, ESR_EL1);
> +
> + vcpu_write_elr_el1(vcpu, *vcpu_pc(vcpu));
> + *vcpu_pc(vcpu) = get_except_vector(vcpu, except_type_sync);
> +
> + *vcpu_cpsr(vcpu) = PSTATE_FAULT_BITS_64;
> + vcpu_write_spsr(vcpu, cpsr);
> }
>
> /**
>
Oops, the above is broken for anything running under a L1 guest hypervisor.
Hopefully this is better:
diff --git a/arch/arm64/kvm/inject_fault.c b/arch/arm64/kvm/inject_fault.c
index fac962b467bd..952e49aeb6f0 100644
--- a/arch/arm64/kvm/inject_fault.c
+++ b/arch/arm64/kvm/inject_fault.c
@@ -53,15 +53,7 @@ static void inject_abt64(struct kvm_vcpu *vcpu, bool is_iabt,
unsigned long addr
{
unsigned long cpsr = *vcpu_cpsr(vcpu);
bool is_aarch32 = vcpu_mode_is_32bit(vcpu);
- u32 esr = 0;
-
- vcpu_write_elr_el1(vcpu, *vcpu_pc(vcpu));
- *vcpu_pc(vcpu) = get_except_vector(vcpu, except_type_sync);
-
- *vcpu_cpsr(vcpu) = PSTATE_FAULT_BITS_64;
- vcpu_write_spsr(vcpu, cpsr);
-
- vcpu_write_sys_reg(vcpu, addr, FAR_EL1);
+ u32 esr = ESR_ELx_FSC_EXTABT;
/*
* Build an {i,d}abort, depending on the level and the
@@ -82,13 +74,12 @@ static void inject_abt64(struct kvm_vcpu *vcpu, bool
is_iabt, unsigned long addr
if (!is_iabt)
esr |= ESR_ELx_EC_DABT_LOW << ESR_ELx_EC_SHIFT;
- vcpu_write_sys_reg(vcpu, esr | ESR_ELx_FSC_EXTABT, ESR_EL1);
-}
+ if (is_hyp_ctxt(vcpu)) {
+ kvm_inject_nested_sync(vcpu, esr);
+ return;
+ }
-static void inject_undef64(struct kvm_vcpu *vcpu)
-{
- unsigned long cpsr = *vcpu_cpsr(vcpu);
- u32 esr = (ESR_ELx_EC_UNKNOWN << ESR_ELx_EC_SHIFT);
+ vcpu_write_sys_reg(vcpu, esr, ESR_EL1);
vcpu_write_elr_el1(vcpu, *vcpu_pc(vcpu));
*vcpu_pc(vcpu) = get_except_vector(vcpu, except_type_sync);
@@ -96,6 +87,14 @@ static void inject_undef64(struct kvm_vcpu *vcpu)
*vcpu_cpsr(vcpu) = PSTATE_FAULT_BITS_64;
vcpu_write_spsr(vcpu, cpsr);
+ vcpu_write_sys_reg(vcpu, addr, FAR_EL1);
+}
+
+static void inject_undef64(struct kvm_vcpu *vcpu)
+{
+ unsigned long cpsr = *vcpu_cpsr(vcpu);
+ u32 esr = ESR_ELx_EC_UNKNOWN << ESR_ELx_EC_SHIFT;
+
/*
* Build an unknown exception, depending on the instruction
* set.
@@ -103,7 +102,18 @@ static void inject_undef64(struct kvm_vcpu *vcpu)
if (kvm_vcpu_trap_il_is32bit(vcpu))
esr |= ESR_ELx_IL;
+ if (is_hyp_ctxt(vcpu)) {
+ kvm_inject_nested_sync(vcpu, esr);
+ return;
+ }
+
vcpu_write_sys_reg(vcpu, esr, ESR_EL1);
+
+ vcpu_write_elr_el1(vcpu, *vcpu_pc(vcpu));
+ *vcpu_pc(vcpu) = get_except_vector(vcpu,
Re: [PATCH 00/59] KVM: arm64: ARMv8.3 Nested Virtualization support
On 8/9/19 11:01 AM, Alexandru Elisei wrote: > On 8/2/19 11:11 AM, Alexandru Elisei wrote: >> Hi, >> >> On 6/21/19 10:37 AM, Marc Zyngier wrote: >> When working on adding support for EL2 to kvm-unit-tests I was able to >> trigger >> the following warning: >> >> # ./lkvm run -f psci.flat -m 128 -c 8 --console serial --irqchip gicv3 >> --nested >> # lkvm run --firmware psci.flat -m 128 -c 8 --name guest-151 >> Info: Placing fdt at 0x8020 - 0x8021 >> # Warning: The maximum recommended amount of VCPUs is 4 >> chr_testdev_init: chr-testdev: can't find a virtio-console >> INFO: PSCI version 1.0 >> PASS: invalid-function >> PASS: affinity-info-on >> PASS: affinity-info-off >> [ 24.381266] WARNING: CPU: 3 PID: 160 at >> arch/arm64/kvm/../../../virt/kvm/arm/arch_timer.c:170 >> kvm_timer_irq_can_fire+0xc/0x30 >> [ 24.381366] Modules linked in: >> [ 24.381466] CPU: 3 PID: 160 Comm: kvm-vcpu-1 Not tainted >> 5.2.0-rc5-00060-g7dbce63bd1c7 #145 >> [ 24.381566] Hardware name: Foundation-v8A (DT) >> [ 24.381566] pstate: 4049 (nZcv daif +PAN -UAO) >> [ 24.381666] pc : kvm_timer_irq_can_fire+0xc/0x30 >> [ 24.381766] lr : timer_emulate+0x24/0x98 >> [ 24.381766] sp : 13d8b780 >> [ 24.381866] x29: 13d8b780 x28: 80087a639b80 >> [ 24.381966] x27: 10ba8648 x26: 10b71b40 >> [ 24.382066] x25: 80087a63a100 x24: >> [ 24.382111] x23: 80086ca54000 x22: 100ce260 >> [ 24.382166] x21: 800875e7c918 x20: 800875e7a800 >> [ 24.382275] x19: 800875e7ca08 x18: >> [ 24.382366] x17: x16: >> [ 24.382466] x15: x14: 2118 >> [ 24.382566] x13: 2190 x12: 2280 >> [ 24.382566] x11: 2208 x10: 0040 >> [ 24.382666] x9 : 12dc3b38 x8 : >> [ 24.382766] x7 : x6 : 80087ac00248 >> [ 24.382866] x5 : 80086ca54000 x4 : 2118 >> [ 24.382966] x3 : eeef x2 : 800875e7c918 >> [ 24.383066] x1 : 0001 x0 : 800875e7ca08 >> [ 24.383066] Call trace: >> [ 24.383166] kvm_timer_irq_can_fire+0xc/0x30 >> [ 24.383266] kvm_timer_vcpu_load+0x9c/0x1a0 >> [ 24.383366] kvm_arch_vcpu_load+0xb0/0x1f0 >> [ 24.383366] kvm_sched_in+0x1c/0x28 >> [ 24.383466] finish_task_switch+0xd8/0x1d8 >> [ 24.383566] __schedule+0x248/0x4a0 >> [ 24.383666] preempt_schedule_irq+0x60/0x90 >> [ 24.383666] el1_irq+0xd0/0x180 >> [ 24.383766] kvm_handle_guest_abort+0x0/0x3a0 >> [ 24.383866] kvm_arch_vcpu_ioctl_run+0x41c/0x688 >> [ 24.383866] kvm_vcpu_ioctl+0x4c0/0x838 >> [ 24.383966] do_vfs_ioctl+0xb8/0x878 >> [ 24.384077] ksys_ioctl+0x84/0x90 >> [ 24.384166] __arm64_sys_ioctl+0x18/0x28 >> [ 24.384166] el0_svc_common.constprop.0+0xb0/0x168 >> [ 24.384266] el0_svc_handler+0x28/0x78 >> [ 24.384366] el0_svc+0x8/0xc >> [ 24.384366] ---[ end trace 37a32293e43ac12c ]--- >> [ 24.384666] WARNING: CPU: 3 PID: 160 at >> arch/arm64/kvm/../../../virt/kvm/arm/arch_timer.c:170 >> kvm_timer_irq_can_fire+0xc/0x30 >> [ 24.384766] Modules linked in: >> [ 24.384866] CPU: 3 PID: 160 Comm: kvm-vcpu-1 Tainted: GW >> 5.2.0-rc5-00060-g7dbce63bd1c7 #145 >> [ 24.384966] Hardware name: Foundation-v8A (DT) >> [ 24.384966] pstate: 4049 (nZcv daif +PAN -UAO) >> [ 24.385066] pc : kvm_timer_irq_can_fire+0xc/0x30 >> [ 24.385166] lr : timer_emulate+0x24/0x98 >> [ 24.385166] sp : 13d8b780 >> [ 24.385266] x29: 13d8b780 x28: 80087a639b80 >> [ 24.385366] x27: 10ba8648 x26: 10b71b40 >> [ 24.385466] x25: 80087a63a100 x24: >> [ 24.385466] x23: 80086ca54000 x22: 100ce260 >> [ 24.385566] x21: 800875e7c918 x20: 800875e7a800 >> [ 24.385666] x19: 800875e7ca80 x18: >> [ 24.385766] x17: x16: >> [ 24.385866] x15: x14: 2118 >> [ 24.385966] x13: 2190 x12: 2280 >> [ 24.385966] x11: 2208 x10: 0040 >> [ 24.386066] x9 : 12dc3b38 x8 : >> [ 24.386166] x7 : x6 : 80087ac00248 >> [ 24.386266] x5 : 80086ca54000 x4 : 2118 >> [ 24.386366] x3 : eeef x2 : 800875e7c918 >> [ 24.386466] x1 : 0001 x0 : 800875e7ca80 >> [ 24.386466] Call trace: >> [ 24.386566] kvm_timer_irq_can_fire+0xc/0x30 >> [ 24.38] kvm_timer_vcpu_load+0xa8/0x1a0 >> [ 24.38] kvm_arch_vcpu_load+0xb0/0x1f0 >> [ 24.386898] kvm_sched_in+0x1c/0x28 >> [ 24.386966] finish_task_switch+0xd8/0x1d8 >> [ 24.387166] __schedule+0x248/0x4a0 >> [ 24.387354] preempt_schedule_irq+0x60/0x90 >> [ 24.387366] el1_irq+0xd0/0x180 >> [ 24.387466] kvm_handle_guest_abort+0x0/0x3a0 >> [ 24.387566] kvm_arch_vcpu_ioctl_run+0x41c/0x688 >
Re: [PATCH 00/59] KVM: arm64: ARMv8.3 Nested Virtualization support
On Fri, Aug 09, 2019 at 01:00:02PM +0100, Alexandru Elisei wrote: > Hi Andrew, > > On 8/9/19 12:44 PM, Andrew Jones wrote: > > On Fri, Aug 09, 2019 at 11:01:51AM +0100, Alexandru Elisei wrote: > >> On 8/2/19 11:11 AM, Alexandru Elisei wrote: > >>> Hi, > >>> > >>> On 6/21/19 10:37 AM, Marc Zyngier wrote: > I've taken over the maintenance of this series originally written by > Jintack and Christoffer. Since then, the series has been substantially > reworked, new features (and most probably bugs) have been added, and > the whole thing rebased multiple times. If anything breaks, please > blame me, and nobody else. > > As you can tell, this is quite big. It is also remarkably incomplete > (we're missing many critical bits for fully emulate EL2), but the idea > is to start merging things early in order to reduce the maintenance > headache. What we want to achieve is that with NV disabled, there is > no performance overhead and no regression. The only thing I intend to > merge ASAP is the first patch in the series, because it should have > zero effect and is a reasonable cleanup. > > The series is roughly divided in 4 parts: exception handling, memory > virtualization, interrupts and timers. There are of course some > dependencies, but you'll hopefully get the gist of it. > > For the most courageous of you, I've put out a branch[1] containing this > and a bit more. Of course, you'll need some userspace. Andre maintains > a hacked version of kvmtool[1] that takes a --nested option, allowing > the guest to be started at EL2. You can run the whole stack in the > Foundation model. Don't be in a hurry ;-). > > [1] git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git > kvm-arm64/nv-wip-5.2-rc5 > [2] git://linux-arm.org/kvmtool.git nv/nv-wip-5.2-rc5 > > Andre Przywara (4): > KVM: arm64: nv: Handle virtual EL2 registers in > vcpu_read/write_sys_reg() > KVM: arm64: nv: Save/Restore vEL2 sysregs > KVM: arm64: nv: Handle traps for timer _EL02 and _EL2 sysregs > accessors > KVM: arm64: nv: vgic: Allow userland to set VGIC maintenance IRQ > > Christoffer Dall (16): > KVM: arm64: nv: Introduce nested virtualization VCPU feature > KVM: arm64: nv: Reset VCPU to EL2 registers if VCPU nested virt is set > KVM: arm64: nv: Allow userspace to set PSR_MODE_EL2x > KVM: arm64: nv: Add nested virt VCPU primitives for vEL2 VCPU state > KVM: arm64: nv: Handle trapped ERET from virtual EL2 > KVM: arm64: nv: Emulate PSTATE.M for a guest hypervisor > KVM: arm64: nv: Trap EL1 VM register accesses in virtual EL2 > KVM: arm64: nv: Only toggle cache for virtual EL2 when SCTLR_EL2 > changes > KVM: arm/arm64: nv: Support multiple nested stage 2 mmu structures > KVM: arm64: nv: Implement nested Stage-2 page table walk logic > KVM: arm64: nv: Handle shadow stage 2 page faults > KVM: arm64: nv: Unmap/flush shadow stage 2 page tables > KVM: arm64: nv: arch_timer: Support hyp timer emulation > KVM: arm64: nv: vgic-v3: Take cpu_if pointer directly instead of vcpu > KVM: arm64: nv: vgic: Emulate the HW bit in software > KVM: arm64: nv: Add nested GICv3 tracepoints > > Dave Martin (1): > KVM: arm64: Migrate _elx sysreg accessors to msr_s/mrs_s > > Jintack Lim (21): > arm64: Add ARM64_HAS_NESTED_VIRT cpufeature > KVM: arm64: nv: Add EL2 system registers to vcpu context > KVM: arm64: nv: Support virtual EL2 exceptions > KVM: arm64: nv: Inject HVC exceptions to the virtual EL2 > KVM: arm64: nv: Trap SPSR_EL1, ELR_EL1 and VBAR_EL1 from virtual EL2 > KVM: arm64: nv: Trap CPACR_EL1 access in virtual EL2 > KVM: arm64: nv: Set a handler for the system instruction traps > KVM: arm64: nv: Handle PSCI call via smc from the guest > KVM: arm64: nv: Respect virtual HCR_EL2.TWX setting > KVM: arm64: nv: Respect virtual CPTR_EL2.TFP setting > KVM: arm64: nv: Respect the virtual HCR_EL2.NV bit setting > KVM: arm64: nv: Respect virtual HCR_EL2.TVM and TRVM settings > KVM: arm64: nv: Respect the virtual HCR_EL2.NV1 bit setting > KVM: arm64: nv: Emulate EL12 register accesses from the virtual EL2 > KVM: arm64: nv: Configure HCR_EL2 for nested virtualization > KVM: arm64: nv: Pretend we only support larger-than-host page sizes > KVM: arm64: nv: Introduce sys_reg_desc.forward_trap > KVM: arm64: nv: Rework the system instruction emulation framework > KVM: arm64: nv: Trap and emulate AT instructions from virtual EL2 > KVM: arm64: nv: Trap and emulate TLBI instructions from virtual EL2 > KVM: arm64: nv: Nested GICv3 Support > > Marc Zyngier (17): > KVM: arm64:
Re: [PATCH 00/59] KVM: arm64: ARMv8.3 Nested Virtualization support
Hi Andrew,
On 8/9/19 12:44 PM, Andrew Jones wrote:
> On Fri, Aug 09, 2019 at 11:01:51AM +0100, Alexandru Elisei wrote:
>> On 8/2/19 11:11 AM, Alexandru Elisei wrote:
>>> Hi,
>>>
>>> On 6/21/19 10:37 AM, Marc Zyngier wrote:
I've taken over the maintenance of this series originally written by
Jintack and Christoffer. Since then, the series has been substantially
reworked, new features (and most probably bugs) have been added, and
the whole thing rebased multiple times. If anything breaks, please
blame me, and nobody else.
As you can tell, this is quite big. It is also remarkably incomplete
(we're missing many critical bits for fully emulate EL2), but the idea
is to start merging things early in order to reduce the maintenance
headache. What we want to achieve is that with NV disabled, there is
no performance overhead and no regression. The only thing I intend to
merge ASAP is the first patch in the series, because it should have
zero effect and is a reasonable cleanup.
The series is roughly divided in 4 parts: exception handling, memory
virtualization, interrupts and timers. There are of course some
dependencies, but you'll hopefully get the gist of it.
For the most courageous of you, I've put out a branch[1] containing this
and a bit more. Of course, you'll need some userspace. Andre maintains
a hacked version of kvmtool[1] that takes a --nested option, allowing
the guest to be started at EL2. You can run the whole stack in the
Foundation model. Don't be in a hurry ;-).
[1] git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
kvm-arm64/nv-wip-5.2-rc5
[2] git://linux-arm.org/kvmtool.git nv/nv-wip-5.2-rc5
Andre Przywara (4):
KVM: arm64: nv: Handle virtual EL2 registers in
vcpu_read/write_sys_reg()
KVM: arm64: nv: Save/Restore vEL2 sysregs
KVM: arm64: nv: Handle traps for timer _EL02 and _EL2 sysregs
accessors
KVM: arm64: nv: vgic: Allow userland to set VGIC maintenance IRQ
Christoffer Dall (16):
KVM: arm64: nv: Introduce nested virtualization VCPU feature
KVM: arm64: nv: Reset VCPU to EL2 registers if VCPU nested virt is set
KVM: arm64: nv: Allow userspace to set PSR_MODE_EL2x
KVM: arm64: nv: Add nested virt VCPU primitives for vEL2 VCPU state
KVM: arm64: nv: Handle trapped ERET from virtual EL2
KVM: arm64: nv: Emulate PSTATE.M for a guest hypervisor
KVM: arm64: nv: Trap EL1 VM register accesses in virtual EL2
KVM: arm64: nv: Only toggle cache for virtual EL2 when SCTLR_EL2
changes
KVM: arm/arm64: nv: Support multiple nested stage 2 mmu structures
KVM: arm64: nv: Implement nested Stage-2 page table walk logic
KVM: arm64: nv: Handle shadow stage 2 page faults
KVM: arm64: nv: Unmap/flush shadow stage 2 page tables
KVM: arm64: nv: arch_timer: Support hyp timer emulation
KVM: arm64: nv: vgic-v3: Take cpu_if pointer directly instead of vcpu
KVM: arm64: nv: vgic: Emulate the HW bit in software
KVM: arm64: nv: Add nested GICv3 tracepoints
Dave Martin (1):
KVM: arm64: Migrate _elx sysreg accessors to msr_s/mrs_s
Jintack Lim (21):
arm64: Add ARM64_HAS_NESTED_VIRT cpufeature
KVM: arm64: nv: Add EL2 system registers to vcpu context
KVM: arm64: nv: Support virtual EL2 exceptions
KVM: arm64: nv: Inject HVC exceptions to the virtual EL2
KVM: arm64: nv: Trap SPSR_EL1, ELR_EL1 and VBAR_EL1 from virtual EL2
KVM: arm64: nv: Trap CPACR_EL1 access in virtual EL2
KVM: arm64: nv: Set a handler for the system instruction traps
KVM: arm64: nv: Handle PSCI call via smc from the guest
KVM: arm64: nv: Respect virtual HCR_EL2.TWX setting
KVM: arm64: nv: Respect virtual CPTR_EL2.TFP setting
KVM: arm64: nv: Respect the virtual HCR_EL2.NV bit setting
KVM: arm64: nv: Respect virtual HCR_EL2.TVM and TRVM settings
KVM: arm64: nv: Respect the virtual HCR_EL2.NV1 bit setting
KVM: arm64: nv: Emulate EL12 register accesses from the virtual EL2
KVM: arm64: nv: Configure HCR_EL2 for nested virtualization
KVM: arm64: nv: Pretend we only support larger-than-host page sizes
KVM: arm64: nv: Introduce sys_reg_desc.forward_trap
KVM: arm64: nv: Rework the system instruction emulation framework
KVM: arm64: nv: Trap and emulate AT instructions from virtual EL2
KVM: arm64: nv: Trap and emulate TLBI instructions from virtual EL2
KVM: arm64: nv: Nested GICv3 Support
Marc Zyngier (17):
KVM: arm64: Move __load_guest_stage2 to kvm_mmu.h
KVM: arm64: nv: Reset VMPIDR_EL2 and VPIDR_EL2 to sane values
KVM: arm64: nv: Handle SPSR_EL2 specially
KVM: arm64: nv: Refactor vcpu_{read,write}_sys_reg
KVM: arm64: nv: Don't expos
Re: [PATCH 00/59] KVM: arm64: ARMv8.3 Nested Virtualization support
On Fri, Aug 09, 2019 at 11:01:51AM +0100, Alexandru Elisei wrote:
> On 8/2/19 11:11 AM, Alexandru Elisei wrote:
> > Hi,
> >
> > On 6/21/19 10:37 AM, Marc Zyngier wrote:
> >> I've taken over the maintenance of this series originally written by
> >> Jintack and Christoffer. Since then, the series has been substantially
> >> reworked, new features (and most probably bugs) have been added, and
> >> the whole thing rebased multiple times. If anything breaks, please
> >> blame me, and nobody else.
> >>
> >> As you can tell, this is quite big. It is also remarkably incomplete
> >> (we're missing many critical bits for fully emulate EL2), but the idea
> >> is to start merging things early in order to reduce the maintenance
> >> headache. What we want to achieve is that with NV disabled, there is
> >> no performance overhead and no regression. The only thing I intend to
> >> merge ASAP is the first patch in the series, because it should have
> >> zero effect and is a reasonable cleanup.
> >>
> >> The series is roughly divided in 4 parts: exception handling, memory
> >> virtualization, interrupts and timers. There are of course some
> >> dependencies, but you'll hopefully get the gist of it.
> >>
> >> For the most courageous of you, I've put out a branch[1] containing this
> >> and a bit more. Of course, you'll need some userspace. Andre maintains
> >> a hacked version of kvmtool[1] that takes a --nested option, allowing
> >> the guest to be started at EL2. You can run the whole stack in the
> >> Foundation model. Don't be in a hurry ;-).
> >>
> >> [1] git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
> >> kvm-arm64/nv-wip-5.2-rc5
> >> [2] git://linux-arm.org/kvmtool.git nv/nv-wip-5.2-rc5
> >>
> >> Andre Przywara (4):
> >> KVM: arm64: nv: Handle virtual EL2 registers in
> >> vcpu_read/write_sys_reg()
> >> KVM: arm64: nv: Save/Restore vEL2 sysregs
> >> KVM: arm64: nv: Handle traps for timer _EL02 and _EL2 sysregs
> >> accessors
> >> KVM: arm64: nv: vgic: Allow userland to set VGIC maintenance IRQ
> >>
> >> Christoffer Dall (16):
> >> KVM: arm64: nv: Introduce nested virtualization VCPU feature
> >> KVM: arm64: nv: Reset VCPU to EL2 registers if VCPU nested virt is set
> >> KVM: arm64: nv: Allow userspace to set PSR_MODE_EL2x
> >> KVM: arm64: nv: Add nested virt VCPU primitives for vEL2 VCPU state
> >> KVM: arm64: nv: Handle trapped ERET from virtual EL2
> >> KVM: arm64: nv: Emulate PSTATE.M for a guest hypervisor
> >> KVM: arm64: nv: Trap EL1 VM register accesses in virtual EL2
> >> KVM: arm64: nv: Only toggle cache for virtual EL2 when SCTLR_EL2
> >> changes
> >> KVM: arm/arm64: nv: Support multiple nested stage 2 mmu structures
> >> KVM: arm64: nv: Implement nested Stage-2 page table walk logic
> >> KVM: arm64: nv: Handle shadow stage 2 page faults
> >> KVM: arm64: nv: Unmap/flush shadow stage 2 page tables
> >> KVM: arm64: nv: arch_timer: Support hyp timer emulation
> >> KVM: arm64: nv: vgic-v3: Take cpu_if pointer directly instead of vcpu
> >> KVM: arm64: nv: vgic: Emulate the HW bit in software
> >> KVM: arm64: nv: Add nested GICv3 tracepoints
> >>
> >> Dave Martin (1):
> >> KVM: arm64: Migrate _elx sysreg accessors to msr_s/mrs_s
> >>
> >> Jintack Lim (21):
> >> arm64: Add ARM64_HAS_NESTED_VIRT cpufeature
> >> KVM: arm64: nv: Add EL2 system registers to vcpu context
> >> KVM: arm64: nv: Support virtual EL2 exceptions
> >> KVM: arm64: nv: Inject HVC exceptions to the virtual EL2
> >> KVM: arm64: nv: Trap SPSR_EL1, ELR_EL1 and VBAR_EL1 from virtual EL2
> >> KVM: arm64: nv: Trap CPACR_EL1 access in virtual EL2
> >> KVM: arm64: nv: Set a handler for the system instruction traps
> >> KVM: arm64: nv: Handle PSCI call via smc from the guest
> >> KVM: arm64: nv: Respect virtual HCR_EL2.TWX setting
> >> KVM: arm64: nv: Respect virtual CPTR_EL2.TFP setting
> >> KVM: arm64: nv: Respect the virtual HCR_EL2.NV bit setting
> >> KVM: arm64: nv: Respect virtual HCR_EL2.TVM and TRVM settings
> >> KVM: arm64: nv: Respect the virtual HCR_EL2.NV1 bit setting
> >> KVM: arm64: nv: Emulate EL12 register accesses from the virtual EL2
> >> KVM: arm64: nv: Configure HCR_EL2 for nested virtualization
> >> KVM: arm64: nv: Pretend we only support larger-than-host page sizes
> >> KVM: arm64: nv: Introduce sys_reg_desc.forward_trap
> >> KVM: arm64: nv: Rework the system instruction emulation framework
> >> KVM: arm64: nv: Trap and emulate AT instructions from virtual EL2
> >> KVM: arm64: nv: Trap and emulate TLBI instructions from virtual EL2
> >> KVM: arm64: nv: Nested GICv3 Support
> >>
> >> Marc Zyngier (17):
> >> KVM: arm64: Move __load_guest_stage2 to kvm_mmu.h
> >> KVM: arm64: nv: Reset VMPIDR_EL2 and VPIDR_EL2 to sane values
> >> KVM: arm64: nv: Handle SPSR_EL2 specially
> >> KVM: arm64: nv: Refactor vcpu_{read,write}_sys_reg
> >> KVM: arm64: nv: Don't expose SVE to nested guests
> >> KVM: arm64: nv: Hide RAS
Re: [PATCH 00/59] KVM: arm64: ARMv8.3 Nested Virtualization support
On 8/2/19 11:11 AM, Alexandru Elisei wrote:
> Hi,
>
> On 6/21/19 10:37 AM, Marc Zyngier wrote:
>> I've taken over the maintenance of this series originally written by
>> Jintack and Christoffer. Since then, the series has been substantially
>> reworked, new features (and most probably bugs) have been added, and
>> the whole thing rebased multiple times. If anything breaks, please
>> blame me, and nobody else.
>>
>> As you can tell, this is quite big. It is also remarkably incomplete
>> (we're missing many critical bits for fully emulate EL2), but the idea
>> is to start merging things early in order to reduce the maintenance
>> headache. What we want to achieve is that with NV disabled, there is
>> no performance overhead and no regression. The only thing I intend to
>> merge ASAP is the first patch in the series, because it should have
>> zero effect and is a reasonable cleanup.
>>
>> The series is roughly divided in 4 parts: exception handling, memory
>> virtualization, interrupts and timers. There are of course some
>> dependencies, but you'll hopefully get the gist of it.
>>
>> For the most courageous of you, I've put out a branch[1] containing this
>> and a bit more. Of course, you'll need some userspace. Andre maintains
>> a hacked version of kvmtool[1] that takes a --nested option, allowing
>> the guest to be started at EL2. You can run the whole stack in the
>> Foundation model. Don't be in a hurry ;-).
>>
>> [1] git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
>> kvm-arm64/nv-wip-5.2-rc5
>> [2] git://linux-arm.org/kvmtool.git nv/nv-wip-5.2-rc5
>>
>> Andre Przywara (4):
>> KVM: arm64: nv: Handle virtual EL2 registers in
>> vcpu_read/write_sys_reg()
>> KVM: arm64: nv: Save/Restore vEL2 sysregs
>> KVM: arm64: nv: Handle traps for timer _EL02 and _EL2 sysregs
>> accessors
>> KVM: arm64: nv: vgic: Allow userland to set VGIC maintenance IRQ
>>
>> Christoffer Dall (16):
>> KVM: arm64: nv: Introduce nested virtualization VCPU feature
>> KVM: arm64: nv: Reset VCPU to EL2 registers if VCPU nested virt is set
>> KVM: arm64: nv: Allow userspace to set PSR_MODE_EL2x
>> KVM: arm64: nv: Add nested virt VCPU primitives for vEL2 VCPU state
>> KVM: arm64: nv: Handle trapped ERET from virtual EL2
>> KVM: arm64: nv: Emulate PSTATE.M for a guest hypervisor
>> KVM: arm64: nv: Trap EL1 VM register accesses in virtual EL2
>> KVM: arm64: nv: Only toggle cache for virtual EL2 when SCTLR_EL2
>> changes
>> KVM: arm/arm64: nv: Support multiple nested stage 2 mmu structures
>> KVM: arm64: nv: Implement nested Stage-2 page table walk logic
>> KVM: arm64: nv: Handle shadow stage 2 page faults
>> KVM: arm64: nv: Unmap/flush shadow stage 2 page tables
>> KVM: arm64: nv: arch_timer: Support hyp timer emulation
>> KVM: arm64: nv: vgic-v3: Take cpu_if pointer directly instead of vcpu
>> KVM: arm64: nv: vgic: Emulate the HW bit in software
>> KVM: arm64: nv: Add nested GICv3 tracepoints
>>
>> Dave Martin (1):
>> KVM: arm64: Migrate _elx sysreg accessors to msr_s/mrs_s
>>
>> Jintack Lim (21):
>> arm64: Add ARM64_HAS_NESTED_VIRT cpufeature
>> KVM: arm64: nv: Add EL2 system registers to vcpu context
>> KVM: arm64: nv: Support virtual EL2 exceptions
>> KVM: arm64: nv: Inject HVC exceptions to the virtual EL2
>> KVM: arm64: nv: Trap SPSR_EL1, ELR_EL1 and VBAR_EL1 from virtual EL2
>> KVM: arm64: nv: Trap CPACR_EL1 access in virtual EL2
>> KVM: arm64: nv: Set a handler for the system instruction traps
>> KVM: arm64: nv: Handle PSCI call via smc from the guest
>> KVM: arm64: nv: Respect virtual HCR_EL2.TWX setting
>> KVM: arm64: nv: Respect virtual CPTR_EL2.TFP setting
>> KVM: arm64: nv: Respect the virtual HCR_EL2.NV bit setting
>> KVM: arm64: nv: Respect virtual HCR_EL2.TVM and TRVM settings
>> KVM: arm64: nv: Respect the virtual HCR_EL2.NV1 bit setting
>> KVM: arm64: nv: Emulate EL12 register accesses from the virtual EL2
>> KVM: arm64: nv: Configure HCR_EL2 for nested virtualization
>> KVM: arm64: nv: Pretend we only support larger-than-host page sizes
>> KVM: arm64: nv: Introduce sys_reg_desc.forward_trap
>> KVM: arm64: nv: Rework the system instruction emulation framework
>> KVM: arm64: nv: Trap and emulate AT instructions from virtual EL2
>> KVM: arm64: nv: Trap and emulate TLBI instructions from virtual EL2
>> KVM: arm64: nv: Nested GICv3 Support
>>
>> Marc Zyngier (17):
>> KVM: arm64: Move __load_guest_stage2 to kvm_mmu.h
>> KVM: arm64: nv: Reset VMPIDR_EL2 and VPIDR_EL2 to sane values
>> KVM: arm64: nv: Handle SPSR_EL2 specially
>> KVM: arm64: nv: Refactor vcpu_{read,write}_sys_reg
>> KVM: arm64: nv: Don't expose SVE to nested guests
>> KVM: arm64: nv: Hide RAS from nested guests
>> KVM: arm/arm64: nv: Factor out stage 2 page table data from struct kvm
>> KVM: arm64: nv: Move last_vcpu_ran to be per s2 mmu
>> KVM: arm64: nv: Don't always start an S2 MMU search from the beginning
>> KVM: arm64: nv: P
Re: [PATCH 00/59] KVM: arm64: ARMv8.3 Nested Virtualization support
On Fri, Aug 02, 2019 at 10:11:38AM +, Alexandru Elisei wrote:
> These are the changes that I made to kvm-unit-tests (the diff can be applied
> on
> top of upstream master, 2130fd4154ad ("tscdeadline_latency: Check condition
> first before loop")):
It's great to hear that you're doing this. You may find these bit-rotted
commits useful too
https://github.com/rhdrjones/kvm-unit-tests/commits/arm64/hyp-mode
Thanks,
drew
>
> diff --git a/arm/cstart64.S b/arm/cstart64.S
> index b0e8baa1a23a..a7631b5a1801 100644
> --- a/arm/cstart64.S
> +++ b/arm/cstart64.S
> @@ -51,6 +51,17 @@ start:
> b 1b
>
> 1:
> + mrs x4, CurrentEL
> + cmp x4, CurrentEL_EL2
> + b.ne1f
> + mrs x4, mpidr_el1
> + msr vmpidr_el2, x4
> + mrs x4, midr_el1
> + msr vpidr_el2, x4
> + ldr x4, =(HCR_EL2_TGE | HCR_EL2_E2H)
> + msr hcr_el2, x4
> + isb
> +1:
> /* set up stack */
> mov x4, #1
> msr spsel, x4
> @@ -101,6 +112,17 @@ get_mmu_off:
>
> .globl secondary_entry
> secondary_entry:
> + mrs x0, CurrentEL
> + cmp x0, CurrentEL_EL2
> + b.ne1f
> + mrs x0, mpidr_el1
> + msr vmpidr_el2, x0
> + mrs x0, midr_el1
> + msr vpidr_el2, x0
> + ldr x0, =(HCR_EL2_TGE | HCR_EL2_E2H)
> + msr hcr_el2, x0
> + isb
> +1:
> /* Enable FP/ASIMD */
> mov x0, #(3 << 20)
> msr cpacr_el1, x0
> diff --git a/lib/arm/asm/psci.h b/lib/arm/asm/psci.h
> index 7b956bf5987d..07297a27e0ce 100644
> --- a/lib/arm/asm/psci.h
> +++ b/lib/arm/asm/psci.h
> @@ -3,6 +3,15 @@
> #include
> #include
>
> +enum psci_conduit {
> + PSCI_CONDUIT_HVC,
> + PSCI_CONDUIT_SMC,
> +};
> +
> +extern void psci_init(void);
> +extern void psci_set_conduit(enum psci_conduit conduit);
> +extern enum psci_conduit psci_get_conduit(void);
> +
> extern int psci_invoke(unsigned long function_id, unsigned long arg0,
>unsigned long arg1, unsigned long arg2);
> extern int psci_cpu_on(unsigned long cpuid, unsigned long entry_point);
> diff --git a/lib/arm/psci.c b/lib/arm/psci.c
> index c3d399064ae3..20ad4b944738 100644
> --- a/lib/arm/psci.c
> +++ b/lib/arm/psci.c
> @@ -6,13 +6,14 @@
> *
> * This work is licensed under the terms of the GNU LGPL, version 2.
> */
> +#include
> +#include
> #include
> #include
> #include
> #include
>
> -__attribute__((noinline))
> -int psci_invoke(unsigned long function_id, unsigned long arg0,
> +static int psci_invoke_hvc(unsigned long function_id, unsigned long arg0,
> unsigned long arg1, unsigned long arg2)
> {
> asm volatile(
> @@ -22,6 +23,63 @@ int psci_invoke(unsigned long function_id, unsigned long
> arg0,
> return function_id;
> }
>
> +static int psci_invoke_smc(unsigned long function_id, unsigned long arg0,
> + unsigned long arg1, unsigned long arg2)
> +{
> + asm volatile(
> + "smc #0"
> + : "+r" (function_id)
> + : "r" (arg0), "r" (arg1), "r" (arg2));
> + return function_id;
> +}
> +
> +/*
> + * Initialize to something sensible, so the exit fallback psci_system_off
> still
> + * works before calling psci_init when booted at EL1.
> + */
> +static enum psci_conduit psci_conduit = PSCI_CONDUIT_HVC;
> +static int (*psci_fn)(unsigned long, unsigned long, unsigned long,
> + unsigned long) = &psci_invoke_hvc;
> +
> +void psci_set_conduit(enum psci_conduit conduit)
> +{
> + psci_conduit = conduit;
> + if (conduit == PSCI_CONDUIT_HVC)
> + psci_fn = &psci_invoke_hvc;
> + else
> + psci_fn = &psci_invoke_smc;
> +}
> +
> +enum psci_conduit psci_get_conduit(void)
> +{
> + return psci_conduit;
> +}
> +
> +int psci_invoke(unsigned long function_id, unsigned long arg0,
> + unsigned long arg1, unsigned long arg2)
> +{
> + return psci_fn(function_id, arg0, arg1, arg2);
> +}
> +
> +void psci_init(void)
> +{
> + const char *conduit;
> + int ret;
> +
> + ret = dt_get_psci_conduit(&conduit);
> + assert(ret == 0 || ret == -FDT_ERR_NOTFOUND);
> +
> + if (ret == -FDT_ERR_NOTFOUND)
> + conduit = "hvc";
> +
> + assert(strcmp(conduit, "hvc") == 0 || strcmp(conduit, "smc") == 0);
> +
> + if (strcmp(conduit, "hvc") == 0)
> + psci_set_conduit(PSCI_CONDUIT_HVC);
> + else
> + psci_set_conduit(PSCI_CONDUIT_SMC);
> +}
> +
> int psci_cpu_on(unsigned long cpuid, unsigned long entry_point)
> {
> #ifdef __arm__
> diff --git a/lib/arm/setup.c b/lib/arm/setup.c
> index 4f02fca85607..e0dc9e4801b0 100644
> --- a/lib/arm/setup.c
> +++ b/lib/arm/setup.c
> @@ -21,6 +21,7 @@
> #include
> #include
> #include
> +#include
>
> #include "io.h"
>
> @@ -164,7 +165,11 @@ void setup(const void *fdt)
> freemem +=
Re: [PATCH 00/59] KVM: arm64: ARMv8.3 Nested Virtualization support
Hi,
On 6/21/19 10:37 AM, Marc Zyngier wrote:
> I've taken over the maintenance of this series originally written by
> Jintack and Christoffer. Since then, the series has been substantially
> reworked, new features (and most probably bugs) have been added, and
> the whole thing rebased multiple times. If anything breaks, please
> blame me, and nobody else.
>
> As you can tell, this is quite big. It is also remarkably incomplete
> (we're missing many critical bits for fully emulate EL2), but the idea
> is to start merging things early in order to reduce the maintenance
> headache. What we want to achieve is that with NV disabled, there is
> no performance overhead and no regression. The only thing I intend to
> merge ASAP is the first patch in the series, because it should have
> zero effect and is a reasonable cleanup.
>
> The series is roughly divided in 4 parts: exception handling, memory
> virtualization, interrupts and timers. There are of course some
> dependencies, but you'll hopefully get the gist of it.
>
> For the most courageous of you, I've put out a branch[1] containing this
> and a bit more. Of course, you'll need some userspace. Andre maintains
> a hacked version of kvmtool[1] that takes a --nested option, allowing
> the guest to be started at EL2. You can run the whole stack in the
> Foundation model. Don't be in a hurry ;-).
>
> [1] git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
> kvm-arm64/nv-wip-5.2-rc5
> [2] git://linux-arm.org/kvmtool.git nv/nv-wip-5.2-rc5
>
> Andre Przywara (4):
> KVM: arm64: nv: Handle virtual EL2 registers in
> vcpu_read/write_sys_reg()
> KVM: arm64: nv: Save/Restore vEL2 sysregs
> KVM: arm64: nv: Handle traps for timer _EL02 and _EL2 sysregs
> accessors
> KVM: arm64: nv: vgic: Allow userland to set VGIC maintenance IRQ
>
> Christoffer Dall (16):
> KVM: arm64: nv: Introduce nested virtualization VCPU feature
> KVM: arm64: nv: Reset VCPU to EL2 registers if VCPU nested virt is set
> KVM: arm64: nv: Allow userspace to set PSR_MODE_EL2x
> KVM: arm64: nv: Add nested virt VCPU primitives for vEL2 VCPU state
> KVM: arm64: nv: Handle trapped ERET from virtual EL2
> KVM: arm64: nv: Emulate PSTATE.M for a guest hypervisor
> KVM: arm64: nv: Trap EL1 VM register accesses in virtual EL2
> KVM: arm64: nv: Only toggle cache for virtual EL2 when SCTLR_EL2
> changes
> KVM: arm/arm64: nv: Support multiple nested stage 2 mmu structures
> KVM: arm64: nv: Implement nested Stage-2 page table walk logic
> KVM: arm64: nv: Handle shadow stage 2 page faults
> KVM: arm64: nv: Unmap/flush shadow stage 2 page tables
> KVM: arm64: nv: arch_timer: Support hyp timer emulation
> KVM: arm64: nv: vgic-v3: Take cpu_if pointer directly instead of vcpu
> KVM: arm64: nv: vgic: Emulate the HW bit in software
> KVM: arm64: nv: Add nested GICv3 tracepoints
>
> Dave Martin (1):
> KVM: arm64: Migrate _elx sysreg accessors to msr_s/mrs_s
>
> Jintack Lim (21):
> arm64: Add ARM64_HAS_NESTED_VIRT cpufeature
> KVM: arm64: nv: Add EL2 system registers to vcpu context
> KVM: arm64: nv: Support virtual EL2 exceptions
> KVM: arm64: nv: Inject HVC exceptions to the virtual EL2
> KVM: arm64: nv: Trap SPSR_EL1, ELR_EL1 and VBAR_EL1 from virtual EL2
> KVM: arm64: nv: Trap CPACR_EL1 access in virtual EL2
> KVM: arm64: nv: Set a handler for the system instruction traps
> KVM: arm64: nv: Handle PSCI call via smc from the guest
> KVM: arm64: nv: Respect virtual HCR_EL2.TWX setting
> KVM: arm64: nv: Respect virtual CPTR_EL2.TFP setting
> KVM: arm64: nv: Respect the virtual HCR_EL2.NV bit setting
> KVM: arm64: nv: Respect virtual HCR_EL2.TVM and TRVM settings
> KVM: arm64: nv: Respect the virtual HCR_EL2.NV1 bit setting
> KVM: arm64: nv: Emulate EL12 register accesses from the virtual EL2
> KVM: arm64: nv: Configure HCR_EL2 for nested virtualization
> KVM: arm64: nv: Pretend we only support larger-than-host page sizes
> KVM: arm64: nv: Introduce sys_reg_desc.forward_trap
> KVM: arm64: nv: Rework the system instruction emulation framework
> KVM: arm64: nv: Trap and emulate AT instructions from virtual EL2
> KVM: arm64: nv: Trap and emulate TLBI instructions from virtual EL2
> KVM: arm64: nv: Nested GICv3 Support
>
> Marc Zyngier (17):
> KVM: arm64: Move __load_guest_stage2 to kvm_mmu.h
> KVM: arm64: nv: Reset VMPIDR_EL2 and VPIDR_EL2 to sane values
> KVM: arm64: nv: Handle SPSR_EL2 specially
> KVM: arm64: nv: Refactor vcpu_{read,write}_sys_reg
> KVM: arm64: nv: Don't expose SVE to nested guests
> KVM: arm64: nv: Hide RAS from nested guests
> KVM: arm/arm64: nv: Factor out stage 2 page table data from struct kvm
> KVM: arm64: nv: Move last_vcpu_ran to be per s2 mmu
> KVM: arm64: nv: Don't always start an S2 MMU search from the beginning
> KVM: arm64: nv: Propagate CNTVOFF_EL2 to the virtual EL1 timer
> KVM: arm64: nv: Load timer before the GIC
> KVM: arm64: nv: Implement maintenance interru
Re: [PATCH 00/59] KVM: arm64: ARMv8.3 Nested Virtualization support
Marc,
Only possible way to test this series is to get
on Fast Model?
On Fri, Jun 21, 2019 at 18:55 Marc Zyngier wrote:
> I've taken over the maintenance of this series originally written by
> Jintack and Christoffer. Since then, the series has been substantially
> reworked, new features (and most probably bugs) have been added, and
> the whole thing rebased multiple times. If anything breaks, please
> blame me, and nobody else.
>
> As you can tell, this is quite big. It is also remarkably incomplete
> (we're missing many critical bits for fully emulate EL2), but the idea
> is to start merging things early in order to reduce the maintenance
> headache. What we want to achieve is that with NV disabled, there is
> no performance overhead and no regression. The only thing I intend to
> merge ASAP is the first patch in the series, because it should have
> zero effect and is a reasonable cleanup.
>
> The series is roughly divided in 4 parts: exception handling, memory
> virtualization, interrupts and timers. There are of course some
> dependencies, but you'll hopefully get the gist of it.
>
> For the most courageous of you, I've put out a branch[1] containing this
> and a bit more. Of course, you'll need some userspace. Andre maintains
> a hacked version of kvmtool[1] that takes a --nested option, allowing
> the guest to be started at EL2. You can run the whole stack in the
> Foundation model. Don't be in a hurry ;-).
>
> [1] git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
> kvm-arm64/nv-wip-5.2-rc5
> [2] git://linux-arm.org/kvmtool.git nv/nv-wip-5.2-rc5
>
> Andre Przywara (4):
> KVM: arm64: nv: Handle virtual EL2 registers in
> vcpu_read/write_sys_reg()
> KVM: arm64: nv: Save/Restore vEL2 sysregs
> KVM: arm64: nv: Handle traps for timer _EL02 and _EL2 sysregs
> accessors
> KVM: arm64: nv: vgic: Allow userland to set VGIC maintenance IRQ
>
> Christoffer Dall (16):
> KVM: arm64: nv: Introduce nested virtualization VCPU feature
> KVM: arm64: nv: Reset VCPU to EL2 registers if VCPU nested virt is set
> KVM: arm64: nv: Allow userspace to set PSR_MODE_EL2x
> KVM: arm64: nv: Add nested virt VCPU primitives for vEL2 VCPU state
> KVM: arm64: nv: Handle trapped ERET from virtual EL2
> KVM: arm64: nv: Emulate PSTATE.M for a guest hypervisor
> KVM: arm64: nv: Trap EL1 VM register accesses in virtual EL2
> KVM: arm64: nv: Only toggle cache for virtual EL2 when SCTLR_EL2
> changes
> KVM: arm/arm64: nv: Support multiple nested stage 2 mmu structures
> KVM: arm64: nv: Implement nested Stage-2 page table walk logic
> KVM: arm64: nv: Handle shadow stage 2 page faults
> KVM: arm64: nv: Unmap/flush shadow stage 2 page tables
> KVM: arm64: nv: arch_timer: Support hyp timer emulation
> KVM: arm64: nv: vgic-v3: Take cpu_if pointer directly instead of vcpu
> KVM: arm64: nv: vgic: Emulate the HW bit in software
> KVM: arm64: nv: Add nested GICv3 tracepoints
>
> Dave Martin (1):
> KVM: arm64: Migrate _elx sysreg accessors to msr_s/mrs_s
>
> Jintack Lim (21):
> arm64: Add ARM64_HAS_NESTED_VIRT cpufeature
> KVM: arm64: nv: Add EL2 system registers to vcpu context
> KVM: arm64: nv: Support virtual EL2 exceptions
> KVM: arm64: nv: Inject HVC exceptions to the virtual EL2
> KVM: arm64: nv: Trap SPSR_EL1, ELR_EL1 and VBAR_EL1 from virtual EL2
> KVM: arm64: nv: Trap CPACR_EL1 access in virtual EL2
> KVM: arm64: nv: Set a handler for the system instruction traps
> KVM: arm64: nv: Handle PSCI call via smc from the guest
> KVM: arm64: nv: Respect virtual HCR_EL2.TWX setting
> KVM: arm64: nv: Respect virtual CPTR_EL2.TFP setting
> KVM: arm64: nv: Respect the virtual HCR_EL2.NV bit setting
> KVM: arm64: nv: Respect virtual HCR_EL2.TVM and TRVM settings
> KVM: arm64: nv: Respect the virtual HCR_EL2.NV1 bit setting
> KVM: arm64: nv: Emulate EL12 register accesses from the virtual EL2
> KVM: arm64: nv: Configure HCR_EL2 for nested virtualization
> KVM: arm64: nv: Pretend we only support larger-than-host page sizes
> KVM: arm64: nv: Introduce sys_reg_desc.forward_trap
> KVM: arm64: nv: Rework the system instruction emulation framework
> KVM: arm64: nv: Trap and emulate AT instructions from virtual EL2
> KVM: arm64: nv: Trap and emulate TLBI instructions from virtual EL2
> KVM: arm64: nv: Nested GICv3 Support
>
> Marc Zyngier (17):
> KVM: arm64: Move __load_guest_stage2 to kvm_mmu.h
> KVM: arm64: nv: Reset VMPIDR_EL2 and VPIDR_EL2 to sane values
> KVM: arm64: nv: Handle SPSR_EL2 specially
> KVM: arm64: nv: Refactor vcpu_{read,write}_sys_reg
> KVM: arm64: nv: Don't expose SVE to nested guests
> KVM: arm64: nv: Hide RAS from nested guests
> KVM: arm/arm64: nv: Factor out stage 2 page table data from struct kvm
> KVM: arm64: nv: Move last_vcpu_ran to be per s2 mmu
> KVM: arm64: nv: Don't always start an S2 MMU search from the beginning
> KVM: arm64: nv: Propagate CNTVOFF_EL2 to the virtual EL1 timer
> KVM: arm64: nv:
Re: [PATCH 00/59] KVM: arm64: ARMv8.3 Nested Virtualization support
On 21/06/2019 10:57, Itaru Kitayama wrote: > Marc, > Only possible way to test this series is to get > on Fast Model? Unless you have some ARMv8.3-capable hardware lying around, yes. Note that the Foundation model is also a good option. Thanks, M. -- Jazz is not dead. It just smells funny... ___ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
[PATCH 00/59] KVM: arm64: ARMv8.3 Nested Virtualization support
I've taken over the maintenance of this series originally written by
Jintack and Christoffer. Since then, the series has been substantially
reworked, new features (and most probably bugs) have been added, and
the whole thing rebased multiple times. If anything breaks, please
blame me, and nobody else.
As you can tell, this is quite big. It is also remarkably incomplete
(we're missing many critical bits for fully emulate EL2), but the idea
is to start merging things early in order to reduce the maintenance
headache. What we want to achieve is that with NV disabled, there is
no performance overhead and no regression. The only thing I intend to
merge ASAP is the first patch in the series, because it should have
zero effect and is a reasonable cleanup.
The series is roughly divided in 4 parts: exception handling, memory
virtualization, interrupts and timers. There are of course some
dependencies, but you'll hopefully get the gist of it.
For the most courageous of you, I've put out a branch[1] containing this
and a bit more. Of course, you'll need some userspace. Andre maintains
a hacked version of kvmtool[1] that takes a --nested option, allowing
the guest to be started at EL2. You can run the whole stack in the
Foundation model. Don't be in a hurry ;-).
[1] git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
kvm-arm64/nv-wip-5.2-rc5
[2] git://linux-arm.org/kvmtool.git nv/nv-wip-5.2-rc5
Andre Przywara (4):
KVM: arm64: nv: Handle virtual EL2 registers in
vcpu_read/write_sys_reg()
KVM: arm64: nv: Save/Restore vEL2 sysregs
KVM: arm64: nv: Handle traps for timer _EL02 and _EL2 sysregs
accessors
KVM: arm64: nv: vgic: Allow userland to set VGIC maintenance IRQ
Christoffer Dall (16):
KVM: arm64: nv: Introduce nested virtualization VCPU feature
KVM: arm64: nv: Reset VCPU to EL2 registers if VCPU nested virt is set
KVM: arm64: nv: Allow userspace to set PSR_MODE_EL2x
KVM: arm64: nv: Add nested virt VCPU primitives for vEL2 VCPU state
KVM: arm64: nv: Handle trapped ERET from virtual EL2
KVM: arm64: nv: Emulate PSTATE.M for a guest hypervisor
KVM: arm64: nv: Trap EL1 VM register accesses in virtual EL2
KVM: arm64: nv: Only toggle cache for virtual EL2 when SCTLR_EL2
changes
KVM: arm/arm64: nv: Support multiple nested stage 2 mmu structures
KVM: arm64: nv: Implement nested Stage-2 page table walk logic
KVM: arm64: nv: Handle shadow stage 2 page faults
KVM: arm64: nv: Unmap/flush shadow stage 2 page tables
KVM: arm64: nv: arch_timer: Support hyp timer emulation
KVM: arm64: nv: vgic-v3: Take cpu_if pointer directly instead of vcpu
KVM: arm64: nv: vgic: Emulate the HW bit in software
KVM: arm64: nv: Add nested GICv3 tracepoints
Dave Martin (1):
KVM: arm64: Migrate _elx sysreg accessors to msr_s/mrs_s
Jintack Lim (21):
arm64: Add ARM64_HAS_NESTED_VIRT cpufeature
KVM: arm64: nv: Add EL2 system registers to vcpu context
KVM: arm64: nv: Support virtual EL2 exceptions
KVM: arm64: nv: Inject HVC exceptions to the virtual EL2
KVM: arm64: nv: Trap SPSR_EL1, ELR_EL1 and VBAR_EL1 from virtual EL2
KVM: arm64: nv: Trap CPACR_EL1 access in virtual EL2
KVM: arm64: nv: Set a handler for the system instruction traps
KVM: arm64: nv: Handle PSCI call via smc from the guest
KVM: arm64: nv: Respect virtual HCR_EL2.TWX setting
KVM: arm64: nv: Respect virtual CPTR_EL2.TFP setting
KVM: arm64: nv: Respect the virtual HCR_EL2.NV bit setting
KVM: arm64: nv: Respect virtual HCR_EL2.TVM and TRVM settings
KVM: arm64: nv: Respect the virtual HCR_EL2.NV1 bit setting
KVM: arm64: nv: Emulate EL12 register accesses from the virtual EL2
KVM: arm64: nv: Configure HCR_EL2 for nested virtualization
KVM: arm64: nv: Pretend we only support larger-than-host page sizes
KVM: arm64: nv: Introduce sys_reg_desc.forward_trap
KVM: arm64: nv: Rework the system instruction emulation framework
KVM: arm64: nv: Trap and emulate AT instructions from virtual EL2
KVM: arm64: nv: Trap and emulate TLBI instructions from virtual EL2
KVM: arm64: nv: Nested GICv3 Support
Marc Zyngier (17):
KVM: arm64: Move __load_guest_stage2 to kvm_mmu.h
KVM: arm64: nv: Reset VMPIDR_EL2 and VPIDR_EL2 to sane values
KVM: arm64: nv: Handle SPSR_EL2 specially
KVM: arm64: nv: Refactor vcpu_{read,write}_sys_reg
KVM: arm64: nv: Don't expose SVE to nested guests
KVM: arm64: nv: Hide RAS from nested guests
KVM: arm/arm64: nv: Factor out stage 2 page table data from struct kvm
KVM: arm64: nv: Move last_vcpu_ran to be per s2 mmu
KVM: arm64: nv: Don't always start an S2 MMU search from the beginning
KVM: arm64: nv: Propagate CNTVOFF_EL2 to the virtual EL1 timer
KVM: arm64: nv: Load timer before the GIC
KVM: arm64: nv: Implement maintenance interrupt forwarding
arm64: KVM: nv: Add handling of EL2-specific timer registers
arm64: KVM: nv: Honor SCTLR_EL2.SPAN on entering vEL2
arm64: KVM: nv: Handle SCTLR_EL2 RES0/RES1 bits
arm64: KVM: nv: Restrict S2 RD/WR permis
