subject:"\[PATCH V3 06\/16\] arm64\/cpufeature\: Introduce ID

Re: [PATCH V3 06/16] arm64/cpufeature: Introduce ID_MMFR5 CPU register

2020-05-05 Thread Anshuman Khandual




On 05/05/2020 02:03 AM, Will Deacon wrote:
> On Sat, May 02, 2020 at 07:03:55PM +0530, Anshuman Khandual wrote:
>> This adds basic building blocks required for ID_MMFR5 CPU register which
>> provides information about the implemented memory model and memory
>> management support in AArch32 state. This is added per ARM DDI 0487F.a
>> specification.
>>
>> Cc: Catalin Marinas 
>> Cc: Will Deacon 
>> Cc: Marc Zyngier 
>> Cc: Mark Rutland 
>> Cc: James Morse 
>> Cc: Suzuki K Poulose 
>> Cc: kvmarm@lists.cs.columbia.edu
>> Cc: linux-arm-ker...@lists.infradead.org
>> Cc: linux-ker...@vger.kernel.org
>>
>> Suggested-by: Will Deacon 
>> Signed-off-by: Anshuman Khandual 
>> ---
>>  arch/arm64/include/asm/cpu.h|  1 +
>>  arch/arm64/include/asm/sysreg.h |  3 +++
>>  arch/arm64/kernel/cpufeature.c  | 10 ++
>>  arch/arm64/kernel/cpuinfo.c |  1 +
>>  arch/arm64/kvm/sys_regs.c   |  2 +-
>>  5 files changed, 16 insertions(+), 1 deletion(-)
> 
> [...]
> 
>> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
>> index 2ce952d9668d..c790cc200bb1 100644
>> --- a/arch/arm64/kernel/cpufeature.c
>> +++ b/arch/arm64/kernel/cpufeature.c
>> @@ -403,6 +403,11 @@ static const struct arm64_ftr_bits ftr_id_isar4[] = {
>>  ARM64_FTR_END,
>>  };
>>  
>> +static const struct arm64_ftr_bits ftr_id_mmfr5[] = {
>> +ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 
>> ID_MMFR5_ETS_SHIFT, 4, 0),
>> +ARM64_FTR_END,
>> +};
>> +
>>  static const struct arm64_ftr_bits ftr_id_isar6[] = {
>>  ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 
>> ID_ISAR6_I8MM_SHIFT, 4, 0),
>>  ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 
>> ID_ISAR6_BF16_SHIFT, 4, 0),
>> @@ -527,6 +532,7 @@ static const struct __ftr_reg_entry {
>>  ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
>>  ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2),
>>  ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1),
>> +ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5),
>>  
>>  /* Op1 = 0, CRn = 0, CRm = 4 */
>>  ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
>> @@ -732,6 +738,7 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info)
>>  init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
>>  init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
>>  init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
>> +init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5);
>>  init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
>>  init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
>>  init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2);
>> @@ -866,6 +873,8 @@ static int update_32bit_cpu_features(int cpu, struct 
>> cpuinfo_arm64 *info,
>>info->reg_id_mmfr2, boot->reg_id_mmfr2);
>>  taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
>>info->reg_id_mmfr3, boot->reg_id_mmfr3);
> 
> Looks like MMFR4 is missing here?

ID_MMFR4 is missing from cpuinfo_arm64 itself, hence from init_cpu_features()
and update_cpu_features() as well. But it is defined in arm64_ftr_regs[]. I
was wondering about it but left as it is (due to lack of complete context).
Unless there is any other concern, will add it up in cpuinfo_arm64 and make
it a part of the CPU context.
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Re: [PATCH V3 06/16] arm64/cpufeature: Introduce ID_MMFR5 CPU register

2020-05-04 Thread Will Deacon

On Sat, May 02, 2020 at 07:03:55PM +0530, Anshuman Khandual wrote:
> This adds basic building blocks required for ID_MMFR5 CPU register which
> provides information about the implemented memory model and memory
> management support in AArch32 state. This is added per ARM DDI 0487F.a
> specification.
> 
> Cc: Catalin Marinas 
> Cc: Will Deacon 
> Cc: Marc Zyngier 
> Cc: Mark Rutland 
> Cc: James Morse 
> Cc: Suzuki K Poulose 
> Cc: kvmarm@lists.cs.columbia.edu
> Cc: linux-arm-ker...@lists.infradead.org
> Cc: linux-ker...@vger.kernel.org
> 
> Suggested-by: Will Deacon 
> Signed-off-by: Anshuman Khandual 
> ---
>  arch/arm64/include/asm/cpu.h|  1 +
>  arch/arm64/include/asm/sysreg.h |  3 +++
>  arch/arm64/kernel/cpufeature.c  | 10 ++
>  arch/arm64/kernel/cpuinfo.c |  1 +
>  arch/arm64/kvm/sys_regs.c   |  2 +-
>  5 files changed, 16 insertions(+), 1 deletion(-)

[...]

> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 2ce952d9668d..c790cc200bb1 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -403,6 +403,11 @@ static const struct arm64_ftr_bits ftr_id_isar4[] = {
>   ARM64_FTR_END,
>  };
>  
> +static const struct arm64_ftr_bits ftr_id_mmfr5[] = {
> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 
> ID_MMFR5_ETS_SHIFT, 4, 0),
> + ARM64_FTR_END,
> +};
> +
>  static const struct arm64_ftr_bits ftr_id_isar6[] = {
>   ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 
> ID_ISAR6_I8MM_SHIFT, 4, 0),
>   ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 
> ID_ISAR6_BF16_SHIFT, 4, 0),
> @@ -527,6 +532,7 @@ static const struct __ftr_reg_entry {
>   ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
>   ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2),
>   ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1),
> + ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5),
>  
>   /* Op1 = 0, CRn = 0, CRm = 4 */
>   ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
> @@ -732,6 +738,7 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info)
>   init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
>   init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
>   init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
> + init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5);
>   init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
>   init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
>   init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2);
> @@ -866,6 +873,8 @@ static int update_32bit_cpu_features(int cpu, struct 
> cpuinfo_arm64 *info,
> info->reg_id_mmfr2, boot->reg_id_mmfr2);
>   taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
> info->reg_id_mmfr3, boot->reg_id_mmfr3);

Looks like MMFR4 is missing here?

> + taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu,
> +   info->reg_id_mmfr5, boot->reg_id_mmfr5);

Will
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[PATCH V3 06/16] arm64/cpufeature: Introduce ID_MMFR5 CPU register

2020-05-02 Thread Anshuman Khandual

This adds basic building blocks required for ID_MMFR5 CPU register which
provides information about the implemented memory model and memory
management support in AArch32 state. This is added per ARM DDI 0487F.a
specification.

Cc: Catalin Marinas 
Cc: Will Deacon 
Cc: Marc Zyngier 
Cc: Mark Rutland 
Cc: James Morse 
Cc: Suzuki K Poulose 
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-arm-ker...@lists.infradead.org
Cc: linux-ker...@vger.kernel.org

Suggested-by: Will Deacon 
Signed-off-by: Anshuman Khandual 
---
 arch/arm64/include/asm/cpu.h|  1 +
 arch/arm64/include/asm/sysreg.h |  3 +++
 arch/arm64/kernel/cpufeature.c  | 10 ++
 arch/arm64/kernel/cpuinfo.c |  1 +
 arch/arm64/kvm/sys_regs.c   |  2 +-
 5 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h
index d9a78bdec409..e1f5ef437671 100644
--- a/arch/arm64/include/asm/cpu.h
+++ b/arch/arm64/include/asm/cpu.h
@@ -45,6 +45,7 @@ struct cpuinfo_arm64 {
u32 reg_id_mmfr1;
u32 reg_id_mmfr2;
u32 reg_id_mmfr3;
+   u32 reg_id_mmfr5;
u32 reg_id_pfr0;
u32 reg_id_pfr1;
u32 reg_id_pfr2;
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 2e1e922e1409..fe1725bbc4bb 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -155,6 +155,7 @@
 #define SYS_MVFR2_EL1  sys_reg(3, 0, 0, 3, 2)
 #define SYS_ID_PFR2_EL1sys_reg(3, 0, 0, 3, 4)
 #define SYS_ID_DFR1_EL1sys_reg(3, 0, 0, 3, 5)
+#define SYS_ID_MMFR5_EL1   sys_reg(3, 0, 0, 3, 6)
 
 #define SYS_ID_AA64PFR0_EL1sys_reg(3, 0, 0, 4, 0)
 #define SYS_ID_AA64PFR1_EL1sys_reg(3, 0, 0, 4, 1)
@@ -789,6 +790,8 @@
 #define ID_ISAR6_DP_SHIFT  4
 #define ID_ISAR6_JSCVT_SHIFT   0
 
+#define ID_MMFR5_ETS_SHIFT 0
+
 #define ID_PFR2_SSBS_SHIFT 4
 #define ID_PFR2_CSV3_SHIFT 0
 
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 2ce952d9668d..c790cc200bb1 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -403,6 +403,11 @@ static const struct arm64_ftr_bits ftr_id_isar4[] = {
ARM64_FTR_END,
 };
 
+static const struct arm64_ftr_bits ftr_id_mmfr5[] = {
+   ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 
ID_MMFR5_ETS_SHIFT, 4, 0),
+   ARM64_FTR_END,
+};
+
 static const struct arm64_ftr_bits ftr_id_isar6[] = {
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 
ID_ISAR6_I8MM_SHIFT, 4, 0),
ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, 
ID_ISAR6_BF16_SHIFT, 4, 0),
@@ -527,6 +532,7 @@ static const struct __ftr_reg_entry {
ARM64_FTR_REG(SYS_MVFR2_EL1, ftr_mvfr2),
ARM64_FTR_REG(SYS_ID_PFR2_EL1, ftr_id_pfr2),
ARM64_FTR_REG(SYS_ID_DFR1_EL1, ftr_id_dfr1),
+   ARM64_FTR_REG(SYS_ID_MMFR5_EL1, ftr_id_mmfr5),
 
/* Op1 = 0, CRn = 0, CRm = 4 */
ARM64_FTR_REG(SYS_ID_AA64PFR0_EL1, ftr_id_aa64pfr0),
@@ -732,6 +738,7 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info)
init_cpu_ftr_reg(SYS_ID_MMFR1_EL1, info->reg_id_mmfr1);
init_cpu_ftr_reg(SYS_ID_MMFR2_EL1, info->reg_id_mmfr2);
init_cpu_ftr_reg(SYS_ID_MMFR3_EL1, info->reg_id_mmfr3);
+   init_cpu_ftr_reg(SYS_ID_MMFR5_EL1, info->reg_id_mmfr5);
init_cpu_ftr_reg(SYS_ID_PFR0_EL1, info->reg_id_pfr0);
init_cpu_ftr_reg(SYS_ID_PFR1_EL1, info->reg_id_pfr1);
init_cpu_ftr_reg(SYS_ID_PFR2_EL1, info->reg_id_pfr2);
@@ -866,6 +873,8 @@ static int update_32bit_cpu_features(int cpu, struct 
cpuinfo_arm64 *info,
  info->reg_id_mmfr2, boot->reg_id_mmfr2);
taint |= check_update_ftr_reg(SYS_ID_MMFR3_EL1, cpu,
  info->reg_id_mmfr3, boot->reg_id_mmfr3);
+   taint |= check_update_ftr_reg(SYS_ID_MMFR5_EL1, cpu,
+ info->reg_id_mmfr5, boot->reg_id_mmfr5);
taint |= check_update_ftr_reg(SYS_ID_PFR0_EL1, cpu,
  info->reg_id_pfr0, boot->reg_id_pfr0);
taint |= check_update_ftr_reg(SYS_ID_PFR1_EL1, cpu,
@@ -1006,6 +1015,7 @@ static u64 __read_sysreg_by_encoding(u32 sys_id)
read_sysreg_case(SYS_ID_MMFR1_EL1);
read_sysreg_case(SYS_ID_MMFR2_EL1);
read_sysreg_case(SYS_ID_MMFR3_EL1);
+   read_sysreg_case(SYS_ID_MMFR5_EL1);
read_sysreg_case(SYS_ID_ISAR0_EL1);
read_sysreg_case(SYS_ID_ISAR1_EL1);
read_sysreg_case(SYS_ID_ISAR2_EL1);
diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
index 50a281703d9d..54579bf08f74 100644
--- a/arch/arm64/kernel/cpuinfo.c
+++ b/arch/arm64/kernel/cpuinfo.c
@@ -374,6 +374,7 @@ stat

Re: [PATCH V3 06/16] arm64/cpufeature: Introduce ID_MMFR5 CPU register

Re: [PATCH V3 06/16] arm64/cpufeature: Introduce ID_MMFR5 CPU register

[PATCH V3 06/16] arm64/cpufeature: Introduce ID_MMFR5 CPU register

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