Re: [PATCH v2 3/3] arm64: Add workaround for Arm Cortex-A77 erratum 1508412
On Thu, Jul 02, 2020 at 08:56:05AM -0600, Rob Herring wrote: > On Thu, Jul 2, 2020 at 5:42 AM Will Deacon wrote: > > > > On Wed, Jul 01, 2020 at 03:53:08PM -0600, Rob Herring wrote: > > > On Cortex-A77 r0p0 and r1p0, a sequence of a non-cacheable or device load > > > and a store exclusive or PAR_EL1 read can cause a deadlock. > > > > > > The workaround requires a DMB SY before and after a PAR_EL1 register read > > > and the disabling of KVM. KVM must be disabled to prevent the problematic > > > sequence in guests' EL1. This workaround also depends on a firmware > > > counterpart to enable the h/w to insert DMB SY after load and store > > > exclusive instructions. See the errata document SDEN-1152370 v10 [1] for > > > more information. > > > > This ^^ is out of date not that we're not disabling KVM. > > Indeed, I fixed the kconfig text, but missed this. > > > > All the other PAR_EL1 reads besides the one in > > > is_spurious_el1_translation_fault() are in KVM code, so the work-around is > > > not needed for them. > > > > And I think this now needs some extra work. > > Ugg, that was too easy... > > The KVM code in __translate_far_to_hpfar() has: > > read PAR > read PAR > write PAR > > I'm wondering if we need 2 dmbs or 4 here. I'm checking on that. Also worth checking what happens if the PAR access is executed speculatively, as in that case we probably can't guarantee that the DMB instructions are executed at all... Will ___ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
Re: [PATCH v2 3/3] arm64: Add workaround for Arm Cortex-A77 erratum 1508412
On Thu, Jul 2, 2020 at 5:42 AM Will Deacon wrote: > > On Wed, Jul 01, 2020 at 03:53:08PM -0600, Rob Herring wrote: > > On Cortex-A77 r0p0 and r1p0, a sequence of a non-cacheable or device load > > and a store exclusive or PAR_EL1 read can cause a deadlock. > > > > The workaround requires a DMB SY before and after a PAR_EL1 register read > > and the disabling of KVM. KVM must be disabled to prevent the problematic > > sequence in guests' EL1. This workaround also depends on a firmware > > counterpart to enable the h/w to insert DMB SY after load and store > > exclusive instructions. See the errata document SDEN-1152370 v10 [1] for > > more information. > > This ^^ is out of date not that we're not disabling KVM. Indeed, I fixed the kconfig text, but missed this. > > All the other PAR_EL1 reads besides the one in > > is_spurious_el1_translation_fault() are in KVM code, so the work-around is > > not needed for them. > > And I think this now needs some extra work. Ugg, that was too easy... The KVM code in __translate_far_to_hpfar() has: read PAR read PAR write PAR I'm wondering if we need 2 dmbs or 4 here. I'm checking on that. Rob ___ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
Re: [PATCH v2 3/3] arm64: Add workaround for Arm Cortex-A77 erratum 1508412
On Wed, Jul 01, 2020 at 03:53:08PM -0600, Rob Herring wrote:
> On Cortex-A77 r0p0 and r1p0, a sequence of a non-cacheable or device load
> and a store exclusive or PAR_EL1 read can cause a deadlock.
>
> The workaround requires a DMB SY before and after a PAR_EL1 register read
> and the disabling of KVM. KVM must be disabled to prevent the problematic
> sequence in guests' EL1. This workaround also depends on a firmware
> counterpart to enable the h/w to insert DMB SY after load and store
> exclusive instructions. See the errata document SDEN-1152370 v10 [1] for
> more information.
This ^^ is out of date not that we're not disabling KVM.
> All the other PAR_EL1 reads besides the one in
> is_spurious_el1_translation_fault() are in KVM code, so the work-around is
> not needed for them.
And I think this now needs some extra work.
> [1]
> https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf
>
> Cc: Catalin Marinas
> Cc: James Morse
> Cc: Suzuki K Poulose
> Cc: Will Deacon
> Cc: Marc Zyngier
> Cc: Julien Thierry
> Cc: kvmarm@lists.cs.columbia.edu
> Signed-off-by: Rob Herring
> ---
> v2:
> - Don't disable KVM, just print warning
> ---
> Documentation/arm64/silicon-errata.rst | 2 ++
> arch/arm64/Kconfig | 19 +++
> arch/arm64/include/asm/cpucaps.h | 3 ++-
> arch/arm64/kernel/cpu_errata.c | 10 ++
> arch/arm64/kvm/arm.c | 3 ++-
> arch/arm64/mm/fault.c | 10 ++
> 6 files changed, 45 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/arm64/silicon-errata.rst
> b/Documentation/arm64/silicon-errata.rst
> index 936cf2a59ca4..716b279e3b33 100644
> --- a/Documentation/arm64/silicon-errata.rst
> +++ b/Documentation/arm64/silicon-errata.rst
> @@ -90,6 +90,8 @@ stable kernels.
>
> ++-+-+-+
> | ARM| Cortex-A76 | #1463225| ARM64_ERRATUM_1463225
> |
>
> ++-+-+-+
> +| ARM| Cortex-A77 | #1508412| ARM64_ERRATUM_1508412
> |
> +++-+-+-+
> | ARM| Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040
> |
>
> ++-+-+-+
> | ARM| Neoverse-N1 | #1349291| N/A
> |
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index a4a094bedcb2..28993ad4c649 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -626,6 +626,25 @@ config ARM64_ERRATUM_1542419
>
> If unsure, say Y.
>
> +config ARM64_ERRATUM_1508412
> + bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device
> load and store exclusive or PAR read"
> + default y
> + help
> + This option adds a workaround for Arm Cortex-A77 erratum 1508412.
> +
> + Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
> + of a store-exclusive or read of PAR_EL1 and a load with device or
> + non-cacheable memory attributes. The workaround depends on a firmware
> + counterpart.
> +
> + KVM guests must also have the work-around implemented or they can
work-around => workaround
> + deadlock the system.
> +
> + Workaround the issue by inserting DMB SY barriers around PAR_EL1
Workaround => work around
> + register reads and warning KVM users.
> +
> + If unsure, say Y.
> +
> config CAVIUM_ERRATUM_22375
> bool "Cavium erratum 22375, 24313"
> default y
> diff --git a/arch/arm64/include/asm/cpucaps.h
> b/arch/arm64/include/asm/cpucaps.h
> index d7b3bb0cb180..2a2cdb4ced8b 100644
> --- a/arch/arm64/include/asm/cpucaps.h
> +++ b/arch/arm64/include/asm/cpucaps.h
> @@ -62,7 +62,8 @@
> #define ARM64_HAS_GENERIC_AUTH 52
> #define ARM64_HAS_32BIT_EL1 53
> #define ARM64_BTI54
> +#define ARM64_WORKAROUND_1508412 55
>
> -#define ARM64_NCAPS 55
> +#define ARM64_NCAPS 56
>
> #endif /* __ASM_CPUCAPS_H */
> diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
> index ad06d6802d2e..5eee8a75540c 100644
> --- a/arch/arm64/kernel/cpu_errata.c
> +++ b/arch/arm64/kernel/cpu_errata.c
> @@ -938,6 +938,16 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
> .matches = has_neoverse_n1_erratum_1542419,
> .cpu_enable = cpu_enable_trap_ctr_access,
> },
> +#endif
> +#ifdef CONFIG_ARM64_ERRATUM_1508412
> + {
> + /* we depend on the firmware portion for correctness */
> + .desc = "ARM erratum 1508412 (kernel portion)",
> + .capability =
[PATCH v2 3/3] arm64: Add workaround for Arm Cortex-A77 erratum 1508412
On Cortex-A77 r0p0 and r1p0, a sequence of a non-cacheable or device load
and a store exclusive or PAR_EL1 read can cause a deadlock.
The workaround requires a DMB SY before and after a PAR_EL1 register read
and the disabling of KVM. KVM must be disabled to prevent the problematic
sequence in guests' EL1. This workaround also depends on a firmware
counterpart to enable the h/w to insert DMB SY after load and store
exclusive instructions. See the errata document SDEN-1152370 v10 [1] for
more information.
All the other PAR_EL1 reads besides the one in
is_spurious_el1_translation_fault() are in KVM code, so the work-around is
not needed for them.
[1]
https://static.docs.arm.com/101992/0010/Arm_Cortex_A77_MP074_Software_Developer_Errata_Notice_v10.pdf
Cc: Catalin Marinas
Cc: James Morse
Cc: Suzuki K Poulose
Cc: Will Deacon
Cc: Marc Zyngier
Cc: Julien Thierry
Cc: kvmarm@lists.cs.columbia.edu
Signed-off-by: Rob Herring
---
v2:
- Don't disable KVM, just print warning
---
Documentation/arm64/silicon-errata.rst | 2 ++
arch/arm64/Kconfig | 19 +++
arch/arm64/include/asm/cpucaps.h | 3 ++-
arch/arm64/kernel/cpu_errata.c | 10 ++
arch/arm64/kvm/arm.c | 3 ++-
arch/arm64/mm/fault.c | 10 ++
6 files changed, 45 insertions(+), 2 deletions(-)
diff --git a/Documentation/arm64/silicon-errata.rst
b/Documentation/arm64/silicon-errata.rst
index 936cf2a59ca4..716b279e3b33 100644
--- a/Documentation/arm64/silicon-errata.rst
+++ b/Documentation/arm64/silicon-errata.rst
@@ -90,6 +90,8 @@ stable kernels.
++-+-+-+
| ARM| Cortex-A76 | #1463225| ARM64_ERRATUM_1463225
|
++-+-+-+
+| ARM| Cortex-A77 | #1508412| ARM64_ERRATUM_1508412
|
+++-+-+-+
| ARM| Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040
|
++-+-+-+
| ARM| Neoverse-N1 | #1349291| N/A
|
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index a4a094bedcb2..28993ad4c649 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -626,6 +626,25 @@ config ARM64_ERRATUM_1542419
If unsure, say Y.
+config ARM64_ERRATUM_1508412
+ bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device
load and store exclusive or PAR read"
+ default y
+ help
+ This option adds a workaround for Arm Cortex-A77 erratum 1508412.
+
+ Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
+ of a store-exclusive or read of PAR_EL1 and a load with device or
+ non-cacheable memory attributes. The workaround depends on a firmware
+ counterpart.
+
+ KVM guests must also have the work-around implemented or they can
+ deadlock the system.
+
+ Workaround the issue by inserting DMB SY barriers around PAR_EL1
+ register reads and warning KVM users.
+
+ If unsure, say Y.
+
config CAVIUM_ERRATUM_22375
bool "Cavium erratum 22375, 24313"
default y
diff --git a/arch/arm64/include/asm/cpucaps.h b/arch/arm64/include/asm/cpucaps.h
index d7b3bb0cb180..2a2cdb4ced8b 100644
--- a/arch/arm64/include/asm/cpucaps.h
+++ b/arch/arm64/include/asm/cpucaps.h
@@ -62,7 +62,8 @@
#define ARM64_HAS_GENERIC_AUTH 52
#define ARM64_HAS_32BIT_EL153
#define ARM64_BTI 54
+#define ARM64_WORKAROUND_1508412 55
-#define ARM64_NCAPS55
+#define ARM64_NCAPS56
#endif /* __ASM_CPUCAPS_H */
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index ad06d6802d2e..5eee8a75540c 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -938,6 +938,16 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
.matches = has_neoverse_n1_erratum_1542419,
.cpu_enable = cpu_enable_trap_ctr_access,
},
+#endif
+#ifdef CONFIG_ARM64_ERRATUM_1508412
+ {
+ /* we depend on the firmware portion for correctness */
+ .desc = "ARM erratum 1508412 (kernel portion)",
+ .capability = ARM64_WORKAROUND_1508412,
+ ERRATA_MIDR_RANGE(MIDR_CORTEX_A77,
+ 0, 0,
+ 1, 0),
+ },
#endif
{
}
diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
index e2f50fa4d825..9f50e01eea00 100644
--- a/arch/arm64/kvm/arm.c
+++ b/arch/arm64/kvm/arm.c
@@ -1653,7 +1653,8 @@ int kvm_arch_init(void *opaque)
