Re: [Libva] [PATCH v2 1/9] ENC: move gpe related function into src/i965_gpe_utils.h/c
-Original Message-
From: Zhao, Yakui
Sent: Monday, January 23, 2017 10:11 AM
To: Qu, Pengfei
Cc: libva@lists.freedesktop.org
Subject: Re: [Libva] [PATCH v2 1/9] ENC: move gpe related function into
src/i965_gpe_utils.h/c
On 01/22/2017 03:36 PM, Pengfei Qu wrote:
> v1:
> add align version for obj surface conversion to gpe surface remove
> comments and enum value
>
> Signed-off-by: Pengfei Qu
> Reviewed-by: Sean V Kelley
> ---
> src/gen9_vp9_encoder.c | 154 ++---
> src/gen9_vp9_encoder.h | 10 --
> src/i965_defines.h | 3 +
> src/i965_gpe_utils.c | 256
> +
> src/i965_gpe_utils.h | 75 +++
> 5 files changed, 340 insertions(+), 158 deletions(-)
> mode change 100755 => 100644 src/i965_defines.h
>
> diff --git a/src/gen9_vp9_encoder.c b/src/gen9_vp9_encoder.c index
> 05d86da..32ed729 100644
> --- a/src/gen9_vp9_encoder.c
> +++ b/src/gen9_vp9_encoder.c
> @@ -58,7 +58,6 @@
> #define BRC_KERNEL_AVBR 0x0040
> #define BRC_KERNEL_CQL 0x0080
>
> -#define DEFAULT_MOCS 0x02
> #define VP9_PIC_STATE_BUFFER_SIZE 192
>
> typedef struct _intel_kernel_header_ @@ -842,7 +841,7 @@
> gen9_vp9_free_resources(struct gen9_encoder_context_vp9 *vme_context)
>
> static void
> gen9_init_media_object_walker_parameter(struct intel_encoder_context
> *encoder_context,
> -struct
> vp9_encoder_kernel_walker_parameter *kernel_walker_param,
> +struct
> + gpe_encoder_kernel_walker_parameter *kernel_walker_param,
> struct
> gpe_media_object_walker_parameter *walker_param)
> {
> memset(walker_param, 0, sizeof(*walker_param)); @@ -924,147
> +923,6 @@ gen9_init_media_object_walker_parameter(struct
> intel_encoder_context *encoder_co
> }
>
> static void
> -gen9_add_2d_gpe_surface(VADriverContextP ctx,
> -struct i965_gpe_context *gpe_context,
> -struct object_surface *obj_surface,
> -int is_uv_surface,
> -int is_media_block_rw,
> -unsigned int format,
> -int index)
> -{
> -struct i965_gpe_resource gpe_resource;
> -struct i965_gpe_surface gpe_surface;
> -
> -memset(&gpe_surface, 0, sizeof(gpe_surface));
> -
> -i965_object_surface_to_2d_gpe_resource(&gpe_resource, obj_surface);
> -gpe_surface.gpe_resource =&gpe_resource;
> -gpe_surface.is_2d_surface = 1;
> -gpe_surface.is_uv_surface = !!is_uv_surface;
> -gpe_surface.is_media_block_rw = !!is_media_block_rw;
> -
> -gpe_surface.cacheability_control = DEFAULT_MOCS;
> -gpe_surface.format = format;
> -
> -gen9_gpe_context_add_surface(gpe_context,&gpe_surface, index);
> -i965_free_gpe_resource(&gpe_resource);
> -}
> -
> -static void
> -gen9_add_adv_gpe_surface(VADriverContextP ctx,
> - struct i965_gpe_context *gpe_context,
> - struct object_surface *obj_surface,
> - int index)
> -{
> -struct i965_gpe_resource gpe_resource;
> -struct i965_gpe_surface gpe_surface;
> -
> -memset(&gpe_surface, 0, sizeof(gpe_surface));
> -
> -i965_object_surface_to_2d_gpe_resource(&gpe_resource, obj_surface);
> -gpe_surface.gpe_resource =&gpe_resource;
> -gpe_surface.is_adv_surface = 1;
> -gpe_surface.cacheability_control = DEFAULT_MOCS;
> -gpe_surface.v_direction = 2;
> -
> -gen9_gpe_context_add_surface(gpe_context,&gpe_surface, index);
> -i965_free_gpe_resource(&gpe_resource);
> -}
> -
> -static void
> -gen9_add_buffer_gpe_surface(VADriverContextP ctx,
> -struct i965_gpe_context *gpe_context,
> -struct i965_gpe_resource *gpe_buffer,
> -int is_raw_buffer,
> -unsigned int size,
> -unsigned int offset,
> -int index)
> -{
> -struct i965_gpe_surface gpe_surface;
> -
> -memset(&gpe_surface, 0, sizeof(gpe_surface));
> -
> -gpe_surface.gpe_resource = gpe_buffer;
> -gpe_surface.is_buffer = 1;
> -gpe_surface.is_raw_buffer = !!is_raw_buffer;
> -gpe_surface.cacheability_control = DEFAULT_MOCS;
> -gpe_surface.size = size;
> -gpe_surface.offset = offset;
> -
> -gen9_gpe_context_add_surface(gpe_context,&gpe_surface, index);
> -
Re: [Libva] [PATCH v2 2/9] ENC: add common structure for AVC/HEVC encoder
-Original Message- From: Zhao, Yakui Sent: Monday, January 23, 2017 10:25 AM To: Qu, Pengfei Cc: libva@lists.freedesktop.org Subject: Re: [Libva] [PATCH v2 2/9] ENC: add common structure for AVC/HEVC encoder On 01/22/2017 03:36 PM, Pengfei Qu wrote: > v1: > add context init function for AVC encoder > > v2: > add file in the Makefile.am > > Signed-off-by: Pengfei Qu > Reviewed-by: Sean V Kelley > --- > src/Makefile.am | 3 + > src/i965_encoder_api.h| 47 > src/i965_encoder_common.c | 124 +++ > src/i965_encoder_common.h | 530 > ++ > 4 files changed, 704 insertions(+) > mode change 100755 => 100644 src/Makefile.am > create mode 100644 src/i965_encoder_api.h > create mode 100644 src/i965_encoder_common.c > create mode 100644 src/i965_encoder_common.h > > diff --git a/src/Makefile.am b/src/Makefile.am old mode 100755 new > mode 100644 index 424812b..a7508e5 > --- a/src/Makefile.am > +++ b/src/Makefile.am > @@ -102,6 +102,7 @@ source_c = \ > gen9_vp9_const_def.c \ > gen9_vp9_encoder.c \ > intel_common_vpp_internal.c \ > +i965_encoder_common.c\ > $(NULL) > > source_h = \ > @@ -156,6 +157,8 @@ source_h = \ > gen9_vp9_encoder_kernels.h \ > intel_gen_vppapi.h \ > intel_common_vpp_internal.h \ > +i965_encoder_common.h\ > +i965_encoder_api.h\ > $(NULL) > > # convenience library that can be linked by driver and tests diff > --git a/src/i965_encoder_api.h b/src/i965_encoder_api.h new file mode > 100644 index 000..ebb0edc > --- /dev/null > +++ b/src/i965_encoder_api.h > @@ -0,0 +1,47 @@ > +/* > + * Copyright © 2016 Intel Corporation > + * > + * Permission is hereby granted, free of charge, to any person > +obtaining a > + * copy of this software and associated documentation files (the > + * "Software"), to deal in the Software without restriction, > +including > + * without limitation the rights to use, copy, modify, merge, > +publish, > + * distribute, sub license, and/or sell copies of the Software, and > +to > + * permit persons to whom the Software is furnished to do so, subject > +to > + * the following conditions: > + * > + * The above copyright notice and this permission notice (including > +the > + * next paragraph) shall be included in all copies or substantial > +portions > + * of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > +EXPRESS > + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF > + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. > + * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE > +FOR > + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF > +CONTRACT, > + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE > + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. > + * > + * Authors: > + * Pengfei Qu > + * > + */ > + > +#ifndef _I965_ENCODER_API_H_ > +#define _I965_ENCODER_API_H_ > + > +#include > + > +struct intel_encoder_context; > +struct hw_context; > + > +/* H264/AVC */ > +extern Bool > +gen9_avc_vme_context_init(VADriverContextP ctx, struct > +intel_encoder_context *encoder_context); > + > +extern Bool > +gen9_avc_pak_context_init(VADriverContextP ctx, struct > +intel_encoder_context *encoder_context); > + > +extern VAStatus > +gen9_avc_coded_status(VADriverContextP ctx, char *buffer, struct > +hw_context *hw_context); > + > +#endif // _I965_ENCODER_API_H_ > diff --git a/src/i965_encoder_common.c b/src/i965_encoder_common.c new > file mode 100644 index 000..a045701 > --- /dev/null > +++ b/src/i965_encoder_common.c > @@ -0,0 +1,124 @@ > +/* > + * Copyright @ 2016 Intel Corporation > + * > + * Permission is hereby granted, free of charge, to any person > +obtaining a > + * copy of this software and associated documentation files (the > + * "Software"), to deal in the Software without restriction, > +including > + * without limitation the rights to use, copy, modify, merge, > +publish, > + * distribute, sub license, and/or sell copies of the Software, and > +to > + * permit persons to whom the Software is furnished to do so, subject > +to > + * the following conditions: > + * > + * The above copyright notice and this permission notice (including > +the > + * next paragraph) shall be included in all copies or substantial > +portions > + * of the Software
Re: [Libva] [PATCH v1 7/9] ENC: add VME pipeline for AVC encoder
-Original Message- From: Mark Thompson [mailto:s...@jkqxz.net] Sent: Sunday, January 22, 2017 7:48 AM To: libva@lists.freedesktop.org; Qu, Pengfei Subject: Re: [Libva] [PATCH v1 7/9] ENC: add VME pipeline for AVC encoder On 13/01/17 09:24, Pengfei Qu wrote: > VME pipeline: > add resource and surface allocation and free function add init table > for frame mbbrc update add scaling kernel for AVC encoder add BRC init > reset kernel for AVC RC logic add BRC frame update-kernel for AVC RC > logic add BRC MB level update kernel for AVC RC logic add REF frame QA > caculation and MB level const data add MBENC kernel for AVC encoder > add ME kernel for AVC encoder add WP/SFD kernel for AVC encoder add > kernel init/destroy function for AVC encoder add kernel related > parameter check function for AVC add VME pipeline init prepare/run > function for AVC encoder > > Reviewed-by: Sean V Kelley > Signed-off-by: Pengfei Qu > --- > src/gen9_avc_encoder.c | 5745 > > 1 file changed, 5745 insertions(+) > create mode 100755 src/gen9_avc_encoder.c This patch and the following one are confused about the meaning of generic_enc_codec_state.internal_rate_mode - it appears both as a VA_RC_* value (bitmask, values 0x01 to 0x20) and as an INTEL_BRC_* value (#defined like an enum, values 0-4). It happens that both VA_RC_CBR and INTEL_BRC_CBR have the same value (2) which probably means that that mode is fine, but I think it may be having weird effects on other modes - particularly VBR because VA_RC_VBR == INTEL_BRC_AVBR (4). [Pengfei] I will fix it. - Mark ___ Libva mailing list Libva@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/libva
Re: [Libva] [PATCH v1 2/9] ENC: add common structure for AVC/HEVC encoder
Yes. I will fix it. -Original Message- From: Mark Thompson [mailto:s...@jkqxz.net] Sent: Sunday, January 22, 2017 7:28 AM To: libva@lists.freedesktop.org; Qu, Pengfei Subject: Re: [Libva] [PATCH v1 2/9] ENC: add common structure for AVC/HEVC encoder Two minor cosmetic issues: On 13/01/17 09:24, Pengfei Qu wrote: > add context init function for AVC encoder > > Signed-off-by: Pengfei Qu > Reviewed-by: Sean V Kelley > --- > src/i965_encoder_api.h| 47 > src/i965_encoder_common.c | 124 +++ > src/i965_encoder_common.h | 533 > ++ > 3 files changed, 704 insertions(+) > create mode 100755 src/i965_encoder_api.h create mode 100755 > src/i965_encoder_common.c create mode 100755 > src/i965_encoder_common.h Many of your new files have the execute bit set, in this and other patches. > ... > diff --git a/src/i965_encoder_common.c b/src/i965_encoder_common.c new > file mode 100755 index 000..930aba9 > --- /dev/null > +++ b/src/i965_encoder_common.c > @@ -0,0 +1,124 @@ > +/* > + * Copyright ? 2016 Intel Corporation > + * > + * Permission is hereby granted, free of charge, to any person > +obtaining a > + * copy of this software and associated documentation files (the > + * "Software"), to deal in the Software without restriction, > +including > + * without limitation the rights to use, copy, modify, merge, > +publish, > + * distribute, sub license, and/or sell copies of the Software, and > +to > + * permit persons to whom the Software is furnished to do so, subject > +to > + * the following conditions: > + * > + * The above copyright notice and this permission notice (including > +the > + * next paragraph) shall be included in all copies or substantial > +portions > + * of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > +EXPRESS > + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF > + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. > + * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE > +FOR > + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF > +CONTRACT, > + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE > + * SOFTWAR > + * Similarly, the licence header on some new files is truncated. - Mark ___ Libva mailing list Libva@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/libva
Re: [Libva] [PATCH v1 0/9]Encoder Architecture Changes (Primarily AVC)
From: Qu, Pengfei Sent: Friday, January 20, 2017 10:07 AM To: Mark Thompson ; libva@lists.freedesktop.org Subject: RE: [Libva] [PATCH v1 0/9]Encoder Architecture Changes (Primarily AVC) Update again. -Original Message- From: Mark Thompson [mailto:s...@jkqxz.net] Sent: Thursday, January 19, 2017 8:25 AM To: libva@lists.freedesktop.org<mailto:libva@lists.freedesktop.org>; Qu, Pengfei mailto:pengfei...@intel.com>> Subject: Re: [Libva] [PATCH v1 0/9]Encoder Architecture Changes (Primarily AVC) On 13/01/17 09:24, Pengfei Qu wrote: > Encoder architecture restructuring for H.264 (with some impact to HEVC now) > on HSW+ > * Improvements to the shaders > * Improvements to the B frame efficiency > * Improvements to the low bit rate mode > * Improved features in two stage VME/PAK pipeline > > v1: > Reduce the patch number and re org for VME and MFX related patches. > Patch re org for VME pipeline > Patch re org for MFX pipeline > keep assert for internal logic and replace assert for input validation > function. > Remove unnecessary comments and enum value. > Use the 64bit version OUT_BCS_RELOC64. > Move kernel binary into header file. > use misc parameter from encoder_context structure. I've had a go with this on Skylake. In general, I see significant gains in quality with similar performance (yay), however I found some issues as well. [Pengfei] It is great to know you try it. ☺ Yes. Quality improvement is as our expectation. CQP mode seems to have regressed significantly in speed - it is maybe 25% slower than CBR/VBR now (though indeed higher quality, particularly on B-frames). Is this expected? I would have thought it should be the "easiest" (and therefore fastest) mode. [Pengfei]yes, CQP is the easiest way. it is “quality level” related. i think you are using “avcenc” to do test. One new parameter “quality level” will be set in the driver by now, and “avcenc” does not set this parameter by now. So in default mode, CQP use the “best quality level” and CBR/VBR use the “normal quality level”, that is the reason why the CQP performance slower. I will add support in the “avcenc” and also fix the same default “quality level” in the driver. [Pengfei] sorry. Double confirm, now the same quality level is used for CQP and CBR/VBR in the default mode(Best quality level). I will do investigation why CQP slower than CBR/VBR. Also, there seems to be something funny going on in the VBR rate controller. Sometimes (nondeterministically, with the same parameters) the beginning of the stream gets stuck at a very high QP / low bitrate for a long period, making the output video terrible quality. After some time (maybe a few thousand frames) it recovers and thereafter acts normally. It seems to happen entirely randomly with low probability (less than 10%, maybe?), with no obvious connection to the encoding parameters. I found some things which might be related (but equally could just be perturbing something else, for example by changing the timing): * It never seems to happen if the encoder input comes directly from a decoder - I have only seen it when there is a VPP instance in between them (though it need not do anything to the video - it can just copy to a new surface of the same size). * I tested on two different machines and it only seems to happen on one of them: it happens on a 6260U (GT3), but not on a 6300 (GT2). Can you offer any thoughts on what might be relevant which I could test for? (Currently my reproduction method is just "transcode videos between sizes repeatedly until it happens", which I realise is not very helpful. I am happy to try to narrow that down a bit if I could have any idea what I can look for.) [Pengfei]How about CBR? VPP seems increase the probability, right? I think it is RC related or GT3 related. If CBR has the same issue, I think it is GT3 related. Thanks, - Mark ___ Libva mailing list Libva@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/libva
Re: [Libva] [PATCH v1 0/9]Encoder Architecture Changes (Primarily AVC)
-Original Message- From: Mark Thompson [mailto:s...@jkqxz.net] Sent: Thursday, January 19, 2017 8:25 AM To: libva@lists.freedesktop.org; Qu, Pengfei Subject: Re: [Libva] [PATCH v1 0/9]Encoder Architecture Changes (Primarily AVC) On 13/01/17 09:24, Pengfei Qu wrote: > Encoder architecture restructuring for H.264 (with some impact to HEVC now) > on HSW+ > * Improvements to the shaders > * Improvements to the B frame efficiency > * Improvements to the low bit rate mode > * Improved features in two stage VME/PAK pipeline > > v1: > Reduce the patch number and re org for VME and MFX related patches. > Patch re org for VME pipeline > Patch re org for MFX pipeline > keep assert for internal logic and replace assert for input validation > function. > Remove unnecessary comments and enum value. > Use the 64bit version OUT_BCS_RELOC64. > Move kernel binary into header file. > use misc parameter from encoder_context structure. I've had a go with this on Skylake. In general, I see significant gains in quality with similar performance (yay), however I found some issues as well. [Pengfei] It is great to know you try it. ☺ Yes. Quality improvement is as our expectation. CQP mode seems to have regressed significantly in speed - it is maybe 25% slower than CBR/VBR now (though indeed higher quality, particularly on B-frames). Is this expected? I would have thought it should be the "easiest" (and therefore fastest) mode. [Pengfei]yes, CQP is the easiest way. it is “quality level” related. i think you are using “avcenc” to do test. One new parameter “quality level” will be set in the driver by now, and “avcenc” does not set this parameter by now. So in default mode, CQP use the “best quality level” and CBR/VBR use the “normal quality level”, that is the reason why the CQP performance slower. I will add support in the “avcenc” and also fix the same default “quality level” in the driver. Also, there seems to be something funny going on in the VBR rate controller. Sometimes (nondeterministically, with the same parameters) the beginning of the stream gets stuck at a very high QP / low bitrate for a long period, making the output video terrible quality. After some time (maybe a few thousand frames) it recovers and thereafter acts normally. It seems to happen entirely randomly with low probability (less than 10%, maybe?), with no obvious connection to the encoding parameters. I found some things which might be related (but equally could just be perturbing something else, for example by changing the timing): * It never seems to happen if the encoder input comes directly from a decoder - I have only seen it when there is a VPP instance in between them (though it need not do anything to the video - it can just copy to a new surface of the same size). * I tested on two different machines and it only seems to happen on one of them: it happens on a 6260U (GT3), but not on a 6300 (GT2). Can you offer any thoughts on what might be relevant which I could test for? (Currently my reproduction method is just "transcode videos between sizes repeatedly until it happens", which I realise is not very helpful. I am happy to try to narrow that down a bit if I could have any idea what I can look for.) [Pengfei]How about CBR? VPP seems increase the probability, right? I think it is RC related or GT3 related. If CBR has the same issue, I think it is GT3 related. Thanks, - Mark ___ Libva mailing list Libva@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/libva
Re: [Libva] [PATCH v1 7/9] ENC: add VME pipeline for AVC encoder
-Original Message-
From: Mark Thompson [mailto:s...@jkqxz.net]
Sent: Thursday, January 19, 2017 7:25 AM
To: libva@lists.freedesktop.org; Qu, Pengfei
Subject: Re: [Libva] [PATCH v1 7/9] ENC: add VME pipeline for AVC encoder
On 13/01/17 09:24, Pengfei Qu wrote:
> VME pipeline:
> add resource and surface allocation and free function add init table
> for frame mbbrc update add scaling kernel for AVC encoder add BRC init
> reset kernel for AVC RC logic add BRC frame update-kernel for AVC RC
> logic add BRC MB level update kernel for AVC RC logic add REF frame QA
> caculation and MB level const data add MBENC kernel for AVC encoder
> add ME kernel for AVC encoder add WP/SFD kernel for AVC encoder add
> kernel init/destroy function for AVC encoder add kernel related
> parameter check function for AVC add VME pipeline init prepare/run
> function for AVC encoder
>
> Reviewed-by: Sean V Kelley
> Signed-off-by: Pengfei Qu
> ---
> src/gen9_avc_encoder.c | 5745
>
> 1 file changed, 5745 insertions(+)
> create mode 100755 src/gen9_avc_encoder.c
>
> diff --git a/src/gen9_avc_encoder.c b/src/gen9_avc_encoder.c new file
> mode 100755 index 000..5caa9f4
> --- /dev/null
> +++ b/src/gen9_avc_encoder.c
> ...
> +
> +static void
> +gen9_avc_update_misc_parameters(VADriverContextP ctx,
> +struct encode_state *encode_state,
> +struct intel_encoder_context
> +*encoder_context) {
> +struct encoder_vme_mfc_context * vme_context = (struct
> encoder_vme_mfc_context *)encoder_context->vme_context;
> +struct generic_enc_codec_state * generic_state = (struct
> generic_enc_codec_state * )vme_context->generic_enc_state;
> +int i;
> +
> +/* brc */
> +generic_state->max_bit_rate =
> ALIGN(encoder_context->brc.bits_per_second[0], 1000) / 1000;
> +generic_state->window_size = encoder_context->brc.window_size;
> +generic_state->brc_need_reset = encoder_context->brc.need_reset;
> +
> +if (generic_state->internal_rate_mode == VA_RC_CBR) {
> +generic_state->min_bit_rate = generic_state->max_bit_rate;
> +generic_state->mb_brc_enabled =
> + encoder_context->brc.mb_rate_control[0];
> +
> +if (generic_state->target_bit_rate != generic_state->max_bit_rate) {
> +generic_state->target_bit_rate = generic_state->max_bit_rate;
> +generic_state->brc_need_reset = 1;
> +}
> +} else if (generic_state->internal_rate_mode == VA_RC_VBR) {
> +generic_state->min_bit_rate = generic_state->max_bit_rate * (2 *
> encoder_context->brc.target_percentage[0] - 100) / 100;
> +generic_state->mb_brc_enabled =
> + encoder_context->brc.mb_rate_control[0];
> +
> +if (generic_state->target_bit_rate != generic_state->max_bit_rate *
> encoder_context->brc.target_percentage[0] / 100) {
> +generic_state->target_bit_rate = generic_state->max_bit_rate *
> encoder_context->brc.target_percentage[0] / 100;
> +generic_state->brc_need_reset = 1;
> +}
> +}
> +
> +/* frame rate */
> +generic_state->frames_per_100s =
> + encoder_context->brc.framerate[0].num/encoder_context->brc.framerate
> + [0].den * 100;
The framerate need not be set in CQP mode - this crashes with a division by
zero in that case.
[Pengfei] sure. I will add check here to fix it.
Also, it discards the fractional part of the framerate by rounding down before
multiplying by 100 - is that deliberate?
[Pengfei] I check the RC algorithm interface, it use 100x to do calculation.
> +generic_state->frame_rate =
> + encoder_context->brc.framerate[0].num/encoder_context->brc.framerate
> + [0].den ;
> +
> +/* HRD */
> +if (generic_state->internal_rate_mode != VA_RC_CQP)
> +{
> +generic_state->vbv_buffer_size_in_bit =
> encoder_context->brc.hrd_buffer_size;//misc->buffer_size;
> +generic_state->init_vbv_buffer_fullness_in_bit =
> encoder_context->brc.hrd_initial_buffer_fullness;//misc->initial_buffer_fullness;
> +}
> +
> +/* ROI */
> +generic_state->num_roi = MIN(encoder_context->brc.num_roi, 3);
> +if (generic_state->num_roi > 0) {
> +generic_state->max_delta_qp = encoder_context->brc.roi_max_delta_qp;
> +generic_state->min_delta_qp =
> + encoder_context->brc.roi_min_delta_qp;
> +
> +for (i = 0; i < generic_state->num_roi; i++) {
> +generic_state->roi[i].left = encoder_context->brc.roi[
Re: [Libva] [PATCH v1 8/9] ENC: add MFX pipeline for AVC encoder
-Original Message-
From: Zhao, Yakui
Sent: Tuesday, January 17, 2017 10:47 AM
To: Qu, Pengfei
Cc: libva@lists.freedesktop.org
Subject: Re: [Libva] [PATCH v1 8/9] ENC: add MFX pipeline for AVC encoder
On 01/13/2017 05:24 PM, Pengfei Qu wrote:
> MFX pipeline:
> add MFX command for AVC encoder
> add MFX Picture slice level command init for AVC
> add MFX pipeline init prepare run for AVC encode
> add VME/MFX context init for AVC encoder
>
Please see the inline comment.
> Reviewed-by: Sean V Kelley
> Signed-off-by: Pengfei Qu
> ---
> src/gen9_avc_encoder.c | 1887
> +++-
> 1 file changed, 1886 insertions(+), 1 deletion(-)
>
> diff --git a/src/gen9_avc_encoder.c b/src/gen9_avc_encoder.c
> index 5caa9f4..a7545f1 100755
> --- a/src/gen9_avc_encoder.c
> +++ b/src/gen9_avc_encoder.c
> @@ -5742,4 +5742,1889 @@ gen9_avc_kernel_init(VADriverContextP ctx,
> generic_ctx->pfn_send_brc_mb_update_surface =
> gen9_avc_send_surface_brc_mb_update;
> generic_ctx->pfn_send_sfd_surface = gen9_avc_send_surface_sfd;
> generic_ctx->pfn_send_wp_surface = gen9_avc_send_surface_wp;
> -}
> \ No newline at end of file
> +}
> +
> +/*
> +PAK pipeline related function
> +*/
> +extern int
> +intel_avc_enc_slice_type_fixup(int slice_type);
> +
> +static void
> +gen9_mfc_avc_pipe_mode_select(VADriverContextP ctx,
> + struct encode_state *encode_state,
> + struct intel_encoder_context *encoder_context)
> +{
> +struct encoder_vme_mfc_context * pak_context = (struct
> encoder_vme_mfc_context *)encoder_context->vme_context;
> +struct gen9_avc_encoder_context * avc_ctx = (struct
> gen9_avc_encoder_context * )pak_context->private_enc_ctx;
> +struct generic_enc_codec_state * generic_state = (struct
> generic_enc_codec_state * )pak_context->generic_enc_state;
> +struct intel_batchbuffer *batch = encoder_context->base.batch;
> +
> +BEGIN_BCS_BATCH(batch, 5);
> +
> +OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
> +OUT_BCS_BATCH(batch,
> + (0<< 29) |
> + (MFX_LONG_MODE<< 17) | /* Must be long format for
> encoder */
> + (MFD_MODE_VLD<< 15) |
> + (0<< 13) | /* VDEnc mode is 1*/
> + ((generic_state->curr_pak_pass !=
> (generic_state->num_pak_passes -1))<< 10) | /* Stream-Out
> Enable */
> + ((!!avc_ctx->res_post_deblocking_output.bo)<< 9) |/*
> Post Deblocking Output */
> + ((!!avc_ctx->res_pre_deblocking_output.bo)<< 8) | /*
> Pre Deblocking Output */
> + (0<< 7) | /* Scaled surface enable */
> + (0<< 6) | /* Frame statistics stream
> out enable, always '1' in VDEnc mode */
> + (0<< 5) | /* not in stitch mode */
> + (1<< 4) | /* encoding mode */
> + (MFX_FORMAT_AVC<< 0));
> +OUT_BCS_BATCH(batch,
> + (0<< 7) | /* expand NOA bus flag */
> + (0<< 6) | /* disable slice-level clock gating */
> + (0<< 5) | /* disable clock gating for NOA */
> + (0<< 4) | /* terminate if AVC motion and POC table error
> occurs */
> + (0<< 3) | /* terminate if AVC mbdata error occurs */
> + (0<< 2) | /* terminate if AVC CABAC/CAVLC decode error
> occurs */
> + (0<< 1) |
> + (0<< 0));
> +OUT_BCS_BATCH(batch, 0);
> +OUT_BCS_BATCH(batch, 0);
> +
> +ADVANCE_BCS_BATCH(batch);
> +}
> +
> +static void
> +gen9_mfc_avc_surface_state(VADriverContextP ctx,
> + struct intel_encoder_context *encoder_context,
> + struct i965_gpe_resource *gpe_resource,
> + int id)
> +{
> +struct intel_batchbuffer *batch = encoder_context->base.batch;
> +
> +BEGIN_BCS_BATCH(batch, 6);
> +
> +OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
> +OUT_BCS_BATCH(batch, id);
> +OUT_BCS_BATCH(batch,
> + ((gpe_resource->height - 1)<< 18) |
> + ((gpe_resource->width - 1)<< 4));
> +OUT_BCS_BATCH(batch,
> + (MFX_SURFACE_PLANAR_420_8<< 28) |/* 420 planar YUV
> surface */
> +
Re: [Libva] [PATCH v1 0/9]Encoder Architecture Changes (Primarily AVC)
-Original Message- From: Zhao, Yakui Sent: Tuesday, January 17, 2017 10:30 AM To: Qu, Pengfei Cc: libva@lists.freedesktop.org Subject: Re: [Libva] [PATCH v1 0/9]Encoder Architecture Changes (Primarily AVC) On 01/13/2017 05:24 PM, Pengfei Qu wrote: > Encoder architecture restructuring for H.264 (with some impact to HEVC > now) on HSW+ > * Improvements to the shaders > * Improvements to the B frame efficiency > * Improvements to the low bit rate mode > * Improved features in two stage VME/PAK pipeline > > v1: > Reduce the patch number and re org for VME and MFX related patches. > Patch re org for VME pipeline > Patch re org for MFX pipeline > keep assert for internal logic and replace assert for input validation > function. > Remove unnecessary comments and enum value. > Use the 64bit version OUT_BCS_RELOC64. > Move kernel binary into header file. > use misc parameter from encoder_context structure. > The patch set looks much clearer. But it seems that sometimes the newly added file is not added into src/Makefile.am in time. In such case it is not compiled before the last patch is applied. It will be better that the newly added file is added into src/Makefile.am in time, which is also convenient to cherry-pick them. [Pengfei] sure. As there are big code changes in this series patches and so add into Makefile.am at the last patch. > > Pengfe (9): >ENC: move gpe related function into src/i965_gpe_utils.h/c >ENC: add common structure for AVC/HEVC encoder >ENC: add const data/table for AVC encoder >ENC: add AVC kernel binary on SKL >ENC: add AVC common structure and functions >ENC: add kernel related structure and define for AVC >ENC: add VME pipeline for AVC encoder >ENC: add MFX pipeline for AVC encoder >ENC:support more quality level and switch to new AVC encoder solution > on SKL > > src/Makefile.am|10 + > src/gen9_avc_const_def.c | 1090 > src/gen9_avc_const_def.h | 115 + > src/gen9_avc_encoder.c | 7630 + > src/gen9_avc_encoder.h | 2339 > src/gen9_avc_encoder_kernels.h | 12078 > +++ > src/gen9_vp9_encoder.c | 154 +- > src/gen9_vp9_encoder.h |10 - > src/i965_avc_encoder_common.c | 319 ++ > src/i965_avc_encoder_common.h | 305 + > src/i965_defines.h | 3 + > src/i965_drv_video.c | 8 +- > src/i965_drv_video.h | 2 + > src/i965_encoder.c |52 +- > src/i965_encoder_api.h |47 + > src/i965_encoder_common.c | 124 + > src/i965_encoder_common.h | 541 ++ > src/i965_gpe_utils.c | 282 + > src/i965_gpe_utils.h |86 + > 19 files changed, 25027 insertions(+), 168 deletions(-) > create mode 100755 src/gen9_avc_const_def.c > create mode 100755 src/gen9_avc_const_def.h > create mode 100755 src/gen9_avc_encoder.c > create mode 100755 src/gen9_avc_encoder.h > create mode 100755 src/gen9_avc_encoder_kernels.h > create mode 100755 src/i965_avc_encoder_common.c > create mode 100755 src/i965_avc_encoder_common.h > create mode 100755 src/i965_encoder_api.h > create mode 100755 src/i965_encoder_common.c > create mode 100755 src/i965_encoder_common.h > ___ Libva mailing list Libva@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/libva
Re: [Libva] [PATCH v1 2/9] ENC: add common structure for AVC/HEVC encoder
-Original Message- From: Zhao, Yakui Sent: Tuesday, January 17, 2017 9:15 AM To: Qu, Pengfei Cc: libva@lists.freedesktop.org Subject: Re: [Libva] [PATCH v1 2/9] ENC: add common structure for AVC/HEVC encoder On 01/13/2017 05:24 PM, Pengfei Qu wrote: > add context init function for AVC encoder > More comments are added. > Signed-off-by: Pengfei Qu > Reviewed-by: Sean V Kelley > --- > src/i965_encoder_api.h| 47 > src/i965_encoder_common.c | 124 +++ > src/i965_encoder_common.h | 533 > ++ > 3 files changed, 704 insertions(+) > create mode 100755 src/i965_encoder_api.h > create mode 100755 src/i965_encoder_common.c > create mode 100755 src/i965_encoder_common.h > > diff --git a/src/i965_encoder_api.h b/src/i965_encoder_api.h new file > mode 100755 index 000..ebb0edc > --- /dev/null > +++ b/src/i965_encoder_api.h > @@ -0,0 +1,47 @@ > +/* > + * Copyright © 2016 Intel Corporation > + * > + * Permission is hereby granted, free of charge, to any person > +obtaining a > + * copy of this software and associated documentation files (the > + * "Software"), to deal in the Software without restriction, > +including > + * without limitation the rights to use, copy, modify, merge, > +publish, > + * distribute, sub license, and/or sell copies of the Software, and > +to > + * permit persons to whom the Software is furnished to do so, subject > +to > + * the following conditions: > + * > + * The above copyright notice and this permission notice (including > +the > + * next paragraph) shall be included in all copies or substantial > +portions > + * of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > +EXPRESS > + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF > + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. > + * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE > +FOR > + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF > +CONTRACT, > + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE > + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. > + * > + * Authors: > + * Pengfei Qu > + * > + */ > + > +#ifndef _I965_ENCODER_API_H_ > +#define _I965_ENCODER_API_H_ > + > +#include > + > +struct intel_encoder_context; > +struct hw_context; > + > +/* H264/AVC */ > +extern Bool > +gen9_avc_vme_context_init(VADriverContextP ctx, struct > +intel_encoder_context *encoder_context); > + > +extern Bool > +gen9_avc_pak_context_init(VADriverContextP ctx, struct > +intel_encoder_context *encoder_context); > + > +extern VAStatus > +gen9_avc_coded_status(VADriverContextP ctx, char *buffer, struct > +hw_context *hw_context); > + > +#endif // _I965_ENCODER_API_H_ > diff --git a/src/i965_encoder_common.c b/src/i965_encoder_common.c new > file mode 100755 index 000..930aba9 > --- /dev/null > +++ b/src/i965_encoder_common.c > @@ -0,0 +1,124 @@ > +/* > + * Copyright ? 2016 Intel Corporation > + * > + * Permission is hereby granted, free of charge, to any person > +obtaining a > + * copy of this software and associated documentation files (the > + * "Software"), to deal in the Software without restriction, > +including > + * without limitation the rights to use, copy, modify, merge, > +publish, > + * distribute, sub license, and/or sell copies of the Software, and > +to > + * permit persons to whom the Software is furnished to do so, subject > +to > + * the following conditions: > + * > + * The above copyright notice and this permission notice (including > +the > + * next paragraph) shall be included in all copies or substantial > +portions > + * of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > +EXPRESS > + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF > + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. > + * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE > +FOR > + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF > +CONTRACT, > + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE > + * SOFTWAR > + * > + * Authors: > + * Pengfei Qu > + * > + */ > +#include > +#include > +#include "intel_batchbuffer.h" > +#include "intel_driver.h" > +#include "i965_encoder_common.h" > +#include "i965_gpe_utils.h" > + > + > +const unsigned int table_enc_search_path[2][8][16] =
Re: [Libva] [PATCH v1 2/9] ENC: add common structure for AVC/HEVC encoder
-Original Message-
From: Zhao, Yakui
Sent: Tuesday, January 17, 2017 9:06 AM
To: Qu, Pengfei
Cc: libva@lists.freedesktop.org
Subject: Re: [Libva] [PATCH v1 2/9] ENC: add common structure for AVC/HEVC
encoder
On 01/13/2017 05:24 PM, Pengfei Qu wrote:
> add context init function for AVC encoder
>
> Signed-off-by: Pengfei Qu
> Reviewed-by: Sean V Kelley
> ---
> src/i965_encoder_api.h| 47
> src/i965_encoder_common.c | 124 +++
> src/i965_encoder_common.h | 533
> ++
> 3 files changed, 704 insertions(+)
> create mode 100755 src/i965_encoder_api.h
> create mode 100755 src/i965_encoder_common.c
> create mode 100755 src/i965_encoder_common.h
>
> diff --git a/src/i965_encoder_api.h b/src/i965_encoder_api.h new file
> mode 100755 index 000..ebb0edc
> --- /dev/null
> +++ b/src/i965_encoder_api.h
> @@ -0,0 +1,47 @@
> +/*
> + * Copyright © 2016 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person
> +obtaining a
> + * copy of this software and associated documentation files (the
> + * "Software"), to deal in the Software without restriction,
> +including
> + * without limitation the rights to use, copy, modify, merge,
> +publish,
> + * distribute, sub license, and/or sell copies of the Software, and
> +to
> + * permit persons to whom the Software is furnished to do so, subject
> +to
> + * the following conditions:
> + *
> + * The above copyright notice and this permission notice (including
> +the
> + * next paragraph) shall be included in all copies or substantial
> +portions
> + * of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> +EXPRESS
> + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
> + * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE
> +FOR
> + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
> +CONTRACT,
> + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
> + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
> + *
> + * Authors:
> + * Pengfei Qu
> + *
> + */
> +
> +#ifndef _I965_ENCODER_API_H_
> +#define _I965_ENCODER_API_H_
> +
> +#include
> +
> +struct intel_encoder_context;
> +struct hw_context;
> +
> +/* H264/AVC */
> +extern Bool
> +gen9_avc_vme_context_init(VADriverContextP ctx, struct
> +intel_encoder_context *encoder_context);
> +
> +extern Bool
> +gen9_avc_pak_context_init(VADriverContextP ctx, struct
> +intel_encoder_context *encoder_context);
> +
> +extern VAStatus
> +gen9_avc_coded_status(VADriverContextP ctx, char *buffer, struct
> +hw_context *hw_context);
> +
> +#endif // _I965_ENCODER_API_H_
> diff --git a/src/i965_encoder_common.c b/src/i965_encoder_common.c new
> file mode 100755 index 000..930aba9
> --- /dev/null
> +++ b/src/i965_encoder_common.c
> @@ -0,0 +1,124 @@
> +/*
> + * Copyright ? 2016 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person
> +obtaining a
> + * copy of this software and associated documentation files (the
> + * "Software"), to deal in the Software without restriction,
> +including
> + * without limitation the rights to use, copy, modify, merge,
> +publish,
> + * distribute, sub license, and/or sell copies of the Software, and
> +to
> + * permit persons to whom the Software is furnished to do so, subject
> +to
> + * the following conditions:
> + *
> + * The above copyright notice and this permission notice (including
> +the
> + * next paragraph) shall be included in all copies or substantial
> +portions
> + * of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> +EXPRESS
> + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
> + * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE
> +FOR
> + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
> +CONTRACT,
> + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
> + * SOFTWAR
> + *
> + * Authors:
> + * Pengfei Qu
> + *
> + */
> +#include
> +#include
> +#include "intel_batchbuffer.h"
> +#include "intel_driver.h"
> +#include "i965_encoder_common.h"
> +#include "i965_gpe_utils.h"
> +
> +
> +const unsigned int table_enc_search_path[2][8][16] = {
> +// I-Frame& P-Frame
> +{
&g
Re: [Libva] [PATCH v1 1/9] ENC: move gpe related function into src/i965_gpe_utils.h/c
-Original Message-
From: Zhao, Yakui
Sent: Tuesday, January 17, 2017 8:55 AM
To: Qu, Pengfei
Cc: libva@lists.freedesktop.org
Subject: Re: [Libva] [PATCH v1 1/9] ENC: move gpe related function into
src/i965_gpe_utils.h/c
On 01/13/2017 05:24 PM, Pengfei Qu wrote:
> v1:
> add align version for obj surface conversion to gpe surface remove
> comments and enum value
>
This version patch looks much clearer.
But it seems that the this patch still adds more defintions besides moving the
GPE functions for generic usage.
[Pengfei] the function will be commented out.
> Signed-off-by: Pengfei Qu
> Reviewed-by: Sean V Kelley
> ---
> src/gen9_vp9_encoder.c | 154 ++-
> src/gen9_vp9_encoder.h | 10 --
> src/i965_defines.h | 3 +
> src/i965_gpe_utils.c | 282
> +
> src/i965_gpe_utils.h | 86 +++
> 5 files changed, 377 insertions(+), 158 deletions(-)
>
> diff --git a/src/gen9_vp9_encoder.c b/src/gen9_vp9_encoder.c index
> 05d86da..32ed729 100644
> --- a/src/gen9_vp9_encoder.c
> +++ b/src/gen9_vp9_encoder.c
> @@ -58,7 +58,6 @@
> #define BRC_KERNEL_AVBR 0x0040
> #define BRC_KERNEL_CQL 0x0080
>
> -#define DEFAULT_MOCS 0x02
> #define VP9_PIC_STATE_BUFFER_SIZE 192
>
> typedef struct _intel_kernel_header_ @@ -842,7 +841,7 @@
> gen9_vp9_free_resources(struct gen9_encoder_context_vp9 *vme_context)
>
> static void
> gen9_init_media_object_walker_parameter(struct intel_encoder_context
> *encoder_context,
> -struct
> vp9_encoder_kernel_walker_parameter *kernel_walker_param,
> +struct
> + gpe_encoder_kernel_walker_parameter *kernel_walker_param,
> struct
> gpe_media_object_walker_parameter *walker_param)
> {
> memset(walker_param, 0, sizeof(*walker_param)); @@ -924,147
> +923,6 @@ gen9_init_media_object_walker_parameter(struct
> intel_encoder_context *encoder_co
> }
>
> static void
> -gen9_add_2d_gpe_surface(VADriverContextP ctx,
> -struct i965_gpe_context *gpe_context,
> -struct object_surface *obj_surface,
> -int is_uv_surface,
> -int is_media_block_rw,
> -unsigned int format,
> -int index)
> -{
> -struct i965_gpe_resource gpe_resource;
> -struct i965_gpe_surface gpe_surface;
> -
> -memset(&gpe_surface, 0, sizeof(gpe_surface));
> -
> -i965_object_surface_to_2d_gpe_resource(&gpe_resource, obj_surface);
> -gpe_surface.gpe_resource =&gpe_resource;
> -gpe_surface.is_2d_surface = 1;
> -gpe_surface.is_uv_surface = !!is_uv_surface;
> -gpe_surface.is_media_block_rw = !!is_media_block_rw;
> -
> -gpe_surface.cacheability_control = DEFAULT_MOCS;
> -gpe_surface.format = format;
> -
> -gen9_gpe_context_add_surface(gpe_context,&gpe_surface, index);
> -i965_free_gpe_resource(&gpe_resource);
> -}
> -
> -static void
> -gen9_add_adv_gpe_surface(VADriverContextP ctx,
> - struct i965_gpe_context *gpe_context,
> - struct object_surface *obj_surface,
> - int index)
> -{
> -struct i965_gpe_resource gpe_resource;
> -struct i965_gpe_surface gpe_surface;
> -
> -memset(&gpe_surface, 0, sizeof(gpe_surface));
> -
> -i965_object_surface_to_2d_gpe_resource(&gpe_resource, obj_surface);
> -gpe_surface.gpe_resource =&gpe_resource;
> -gpe_surface.is_adv_surface = 1;
> -gpe_surface.cacheability_control = DEFAULT_MOCS;
> -gpe_surface.v_direction = 2;
> -
> -gen9_gpe_context_add_surface(gpe_context,&gpe_surface, index);
> -i965_free_gpe_resource(&gpe_resource);
> -}
> -
> -static void
> -gen9_add_buffer_gpe_surface(VADriverContextP ctx,
> -struct i965_gpe_context *gpe_context,
> -struct i965_gpe_resource *gpe_buffer,
> -int is_raw_buffer,
> -unsigned int size,
> -unsigned int offset,
> -int index)
> -{
> -struct i965_gpe_surface gpe_surface;
> -
> -memset(&gpe_surface, 0, sizeof(gpe_surface));
> -
> -gpe_surface.gpe_resource = gpe_buffer;
> -gpe_surface.is_buffer = 1;
> -gpe_surface.is_raw_buffer = !!is_raw_buffer;
> -gpe_surface.cacheability_control = DEFAULT
Re: [Libva] [PATCH 00/31] Encoder Architecture Changes (Primarily AVC)
-Original Message- From: Libva [mailto:libva-boun...@lists.freedesktop.org] On Behalf Of Xiang, Haihao Sent: Thursday, January 12, 2017 10:15 AM To: Zhao, Yakui ; sea...@posteo.de Cc: libva@lists.freedesktop.org Subject: Re: [Libva] [PATCH 00/31] Encoder Architecture Changes (Primarily AVC) On Thu, 2017-01-12 at 09:40 +0800, Zhao Yakui wrote: > On 01/11/2017 07:37 AM, Sean V Kelley wrote: > > Encoder architecture restructuring for H.264 (with some impact to > > HEVC now) on HSW+ > > * Improvements to the shaders > > * Improvements to the B frame efficiency > > * Improvements to the low bit rate mode > > * Improved features in two stage VME/PAK pipeline > > > > After checking the code, it seems that assert is used widely. > But the assert is only for the debug purpose, which causes that the > program will abort. This doesn't make sense. It will be better that > the failure status is returned instead of crash program. > > At the same time if the NDEBUG definition is added, the check is > disabled. In such case the driver should handle the failure scenario > and return the failure status to upper middleware. > > That is to say: The assert had better be avoided and add more check to > check the failure status. We can add some assert() for internal logic check in the driver, it would be better not use assert() for input validation. Thanks Haihao [Pengfei] I will keep assert for internal logic and replace assert for input validation. > Thanks. > > > > > Pengfei Qu (31): > > ENC: move gpe related function into src/i965_gpe_utils.h/c > > ENC: add common structure for AVC/HEVC encoder > > ENC:add context init function for AVC/HEVC encoder > > ENC: add const data/table for AVC encoder > > ENC: add AVC kernel binary on SKL > > ENC: add AVC common structure and functions > > ENC: add kernel related structure and define for AVC > > ENC: add misc parameter check for AVC encoder > > ENC: add resource and surface allocation and free function for > > AVC > > encoder > > ENC: add init table for frame/mb brc update > > ENC: add resource/surface allocation/free function for AVC > > encoder > > ENC: add kernel media object related functions for AVC encoder > > ENC: add scaling kernel for AVC encoder > > ENC: add const data/table init function for AVC RC logic > > ENC: add BRC init/reset kernel for AVC RC logic > > ENC: add BRC frame update kernel for AVC RC logic > > ENC: add BRC MB level update kernel for AVC RC logic > > ENC: add REF frame QA caculation and MB level const data init for > > AVC > > MBenc stage > > ENC: MBENC kernel for AVC encoder > > ENC: ME kernel for AVC encoder > > ENC: WP/SFD kernel for AVC encoder > > ENC: kernel init/destroy function for AVC encoder > > ENC: kernel related parameter check function for AVC encoder > > ENC: VME pipeline init/prepare/run function for AVC encoder > > ENC: add MFX command for AVC encoder > > ENC: add MFX command for AVC encoder > > ENC: add MFX Picture/slice level command init for AVC encoder > > ENC: add MFX pipeline init/prepare/run for AVC encoder > > ENC: add VME/MFX context init for AVC encoder > > ENC: add Misc parameter check for AVC encoder > > ENC:support more quality level and switch to new AVC encoder > > solution > > on SKL > > > > src/Makefile.am|11 + > > src/gen9_avc_const_def.c | 1090 > > src/gen9_avc_const_def.h | 115 + > > src/gen9_avc_encoder.c | 7613 > > src/gen9_avc_encoder.h | 2345 > > src/gen9_avc_encoder_kernels.c | 12081 > > +++ > > src/gen9_avc_encoder_kernels.h |36 + > > src/gen9_vp9_encoder.c | 154 +- > > src/gen9_vp9_encoder.h |10 - > > src/i965_avc_encoder_common.c | 319 ++ > > src/i965_avc_encoder_common.h | 305 + > > src/i965_drv_video.c | 8 +- > > src/i965_drv_video.h | 2 + > > src/i965_encoder.c |39 +- > > src/i965_encoder_api.h |59 + > > src/i965_encoder_common.c | 124 + > > src/i965_encoder_common.h | 533 ++ > > src/i965_gpe_utils.c | 265 +- > > src/i965_gpe_utils.h |87 + > > 19 files changed, 25026 insertions(+), 170 deletions(-) > > create mode 100755 src/gen9_avc_const_def.c > > create mode 100755 src/gen9_avc_const_def.h > > create mode 100755 src/gen9_avc_encoder.c > > create mode 100755 src/gen9_avc_encoder.h > > create mode 100755 src/gen9_avc_encoder_kernels.c > > create mode 100755 src/gen9_avc_encoder_kernels.h > > create mode 100755 src/i965_avc_encoder_common.c > > create mode 100755 src/i965_avc_encoder_common.h > > create mode 100755 src/i965_encoder_api.h > > create mode 100755 src/i965_encoder_common.c > > create mode 100755 src/i965_encoder_common.h > > > >
Re: [Libva] [PATCH 01/31] ENC: move gpe related function into src/i965_gpe_utils.h/c
-Original Message-
From: Libva [mailto:libva-boun...@lists.freedesktop.org] On Behalf Of Zhao Yakui
Sent: Wednesday, January 11, 2017 10:26 PM
To: libva@lists.freedesktop.org
Subject: Re: [Libva] [PATCH 01/31] ENC: move gpe related function into
src/i965_gpe_utils.h/c
On 01/11/2017 07:37 AM, Sean V Kelley wrote:
> From: Pengfei Qu
>
> Signed-off-by: Pengfei Qu
> Reviewed-by: Sean V Kelley
> ---
> src/gen9_vp9_encoder.c | 154 ++--
> src/gen9_vp9_encoder.h | 10 --
> src/i965_gpe_utils.c | 265
> -
> src/i965_gpe_utils.h | 87
> 4 files changed, 356 insertions(+), 160 deletions(-)
>
> diff --git a/src/gen9_vp9_encoder.c b/src/gen9_vp9_encoder.c index
> 05d86dae..32ed729c 100644
> --- a/src/gen9_vp9_encoder.c
> +++ b/src/gen9_vp9_encoder.c
> @@ -58,7 +58,6 @@
> #define BRC_KERNEL_AVBR 0x0040
> #define BRC_KERNEL_CQL 0x0080
>
> -#define DEFAULT_MOCS 0x02
> #define VP9_PIC_STATE_BUFFER_SIZE 192
>
> typedef struct _intel_kernel_header_ @@ -842,7 +841,7 @@
> gen9_vp9_free_resources(struct gen9_encoder_context_vp9 *vme_context)
>
> static void
> gen9_init_media_object_walker_parameter(struct intel_encoder_context
> *encoder_context,
> -struct
> vp9_encoder_kernel_walker_parameter *kernel_walker_param,
> +struct
> + gpe_encoder_kernel_walker_parameter *kernel_walker_param,
> struct
> gpe_media_object_walker_parameter *walker_param)
> {
> memset(walker_param, 0, sizeof(*walker_param)); @@ -924,147
> +923,6 @@ gen9_init_media_object_walker_parameter(struct
> intel_encoder_context *encoder_co
> }
>
> static void
> -gen9_add_2d_gpe_surface(VADriverContextP ctx,
> -struct i965_gpe_context *gpe_context,
> -struct object_surface *obj_surface,
> -int is_uv_surface,
> -int is_media_block_rw,
> -unsigned int format,
> -int index)
> -{
> -struct i965_gpe_resource gpe_resource;
> -struct i965_gpe_surface gpe_surface;
> -
> -memset(&gpe_surface, 0, sizeof(gpe_surface));
> -
> -i965_object_surface_to_2d_gpe_resource(&gpe_resource, obj_surface);
> -gpe_surface.gpe_resource =&gpe_resource;
> -gpe_surface.is_2d_surface = 1;
> -gpe_surface.is_uv_surface = !!is_uv_surface;
> -gpe_surface.is_media_block_rw = !!is_media_block_rw;
> -
> -gpe_surface.cacheability_control = DEFAULT_MOCS;
> -gpe_surface.format = format;
> -
> -gen9_gpe_context_add_surface(gpe_context,&gpe_surface, index);
> -i965_free_gpe_resource(&gpe_resource);
> -}
> -
> -static void
> -gen9_add_adv_gpe_surface(VADriverContextP ctx,
> - struct i965_gpe_context *gpe_context,
> - struct object_surface *obj_surface,
> - int index)
> -{
> -struct i965_gpe_resource gpe_resource;
> -struct i965_gpe_surface gpe_surface;
> -
> -memset(&gpe_surface, 0, sizeof(gpe_surface));
> -
> -i965_object_surface_to_2d_gpe_resource(&gpe_resource, obj_surface);
> -gpe_surface.gpe_resource =&gpe_resource;
> -gpe_surface.is_adv_surface = 1;
> -gpe_surface.cacheability_control = DEFAULT_MOCS;
> -gpe_surface.v_direction = 2;
> -
> -gen9_gpe_context_add_surface(gpe_context,&gpe_surface, index);
> -i965_free_gpe_resource(&gpe_resource);
> -}
> -
> -static void
> -gen9_add_buffer_gpe_surface(VADriverContextP ctx,
> -struct i965_gpe_context *gpe_context,
> -struct i965_gpe_resource *gpe_buffer,
> -int is_raw_buffer,
> -unsigned int size,
> -unsigned int offset,
> -int index)
> -{
> -struct i965_gpe_surface gpe_surface;
> -
> -memset(&gpe_surface, 0, sizeof(gpe_surface));
> -
> -gpe_surface.gpe_resource = gpe_buffer;
> -gpe_surface.is_buffer = 1;
> -gpe_surface.is_raw_buffer = !!is_raw_buffer;
> -gpe_surface.cacheability_control = DEFAULT_MOCS;
> -gpe_surface.size = size;
> -gpe_surface.offset = offset;
> -
> -gen9_gpe_context_add_surface(gpe_context,&gpe_surface, index);
> -}
> -
> -static void
> -gen9_add_buffer_2d_gpe_surface(VADriverContextP ctx,
> - struct i965_gpe_context *gpe_context,
> - struct i965_gpe_resource *gpe_buffer,
> - int is_media_block_rw,
> - unsigned int format,
> - int index)
> -{
> -struct i965_gpe_surface gpe_surface;
> -
> -memset(&gpe_surface, 0, sizeof(gpe_surface));
> -
> -gpe_surface.gpe_resource =
Re: [Libva] [PATCH 03/31] ENC:add context init function for AVC/HEVC encoder
-Original Message- From: Libva [mailto:libva-boun...@lists.freedesktop.org] On Behalf Of Zhao Yakui Sent: Wednesday, January 11, 2017 9:37 AM To: libva@lists.freedesktop.org Subject: Re: [Libva] [PATCH 03/31] ENC:add context init function for AVC/HEVC encoder On 01/11/2017 07:37 AM, Sean V Kelley wrote: > From: Pengfei Qu > > Signed-off-by: Pengfei Qu > Reviewed-by: Sean V Kelley > --- > src/i965_encoder_api.h | 59 > ++ > 1 file changed, 59 insertions(+) > create mode 100755 src/i965_encoder_api.h > > diff --git a/src/i965_encoder_api.h b/src/i965_encoder_api.h new file > mode 100755 index ..0f1ab6cd > --- /dev/null > +++ b/src/i965_encoder_api.h > @@ -0,0 +1,59 @@ > +/* > + * Copyright © 2016 Intel Corporation > + * > + * Permission is hereby granted, free of charge, to any person > +obtaining a > + * copy of this software and associated documentation files (the > + * "Software"), to deal in the Software without restriction, > +including > + * without limitation the rights to use, copy, modify, merge, > +publish, > + * distribute, sub license, and/or sell copies of the Software, and > +to > + * permit persons to whom the Software is furnished to do so, subject > +to > + * the following conditions: > + * > + * The above copyright notice and this permission notice (including > +the > + * next paragraph) shall be included in all copies or substantial > +portions > + * of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, > +EXPRESS > + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF > + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. > + * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE > +FOR > + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF > +CONTRACT, > + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE > + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. > + * > + * Authors: > + * Pengfei Qu > + * > + */ > + > +#ifndef _I965_ENCODER_API_H_ > +#define _I965_ENCODER_API_H_ > + > +#include > + > +struct intel_encoder_context; > +struct hw_context; > + > +/* H264/AVC */ > +extern Bool > +gen9_avc_vme_context_init(VADriverContextP ctx, struct > +intel_encoder_context *encoder_context); > + > +extern Bool > +gen9_avc_pak_context_init(VADriverContextP ctx, struct > +intel_encoder_context *encoder_context); > + > +extern VAStatus > +gen9_avc_coded_status(VADriverContextP ctx, char *buffer, struct > +hw_context *hw_context); > + > + > +/* H265/HEVC */ > +extern Bool > +gen9_hevc_vme_context_init(VADriverContextP ctx, struct > +intel_encoder_context *encoder_context); > + > +extern Bool > +gen9_hevc_pak_context_init(VADriverContextP ctx, struct > +intel_encoder_context *encoder_context); > + > +extern VAStatus > +gen9_hevc_coded_status(VADriverContextP ctx, char *buffer, struct > +hw_context *hw_context); > + It seems that the function API is defined. But there is no implementation. In such case the compiler will complain the warning message. So it will be better to declare them after the implementation is added. At the same time this patch set is mainly added for H264. It will be better to focus the stuff related with H264. Thanks [Pengfei] I will only keep H264 part. Here this file is not in the Makefile.am and we will not see the warning. This file is added into Makefile.am when it really need compling. > + > +#endif // _I965_ENCODER_API_H_ ___ Libva mailing list Libva@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/libva ___ Libva mailing list Libva@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/libva
Re: [Libva] [PATCH 06/31] ENC: add AVC common structure and functions
-Original Message-
From: Libva [mailto:libva-boun...@lists.freedesktop.org] On Behalf Of Zhao Yakui
Sent: Wednesday, January 11, 2017 11:08 AM
To: Sean V Kelley
Cc: libva@lists.freedesktop.org
Subject: Re: [Libva] [PATCH 06/31] ENC: add AVC common structure and functions
On 01/11/2017 07:37 AM, Sean V Kelley wrote:
> From: Pengfei Qu
>
> Signed-off-by: Pengfei Qu
> Reviewed-by: Sean V Kelley
> ---
> src/i965_avc_encoder_common.c | 319
> ++
> src/i965_avc_encoder_common.h | 305
> 2 files changed, 624 insertions(+)
> create mode 100755 src/i965_avc_encoder_common.c
> create mode 100755 src/i965_avc_encoder_common.h
>
> diff --git a/src/i965_avc_encoder_common.c
> b/src/i965_avc_encoder_common.c new file mode 100755 index
> ..3fc2b54e
> --- /dev/null
> +++ b/src/i965_avc_encoder_common.c
> @@ -0,0 +1,319 @@
> +
> +/*
> + * Copyright ? 2016 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person
> +obtaining a
> + * copy of this software and associated documentation files (the
> + * "Software"), to deal in the Software without restriction,
> +including
> + * without limitation the rights to use, copy, modify, merge,
> +publish,
> + * distribute, sub license, and/or sell copies of the Software, and
> +to
> + * permit persons to whom the Software is furnished to do so, subject
> +to
> + * the following conditions:
> + *
> + * The above copyright notice and this permission notice (including
> +the
> + * next paragraph) shall be included in all copies or substantial
> +portions
> + * of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> +EXPRESS
> + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
> + * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE
> +FOR
> + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
> +CONTRACT,
> + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
> + * SOFTWAR
> + *
> + * Authors:
> + * Pengfei Qu
> + *
> + */
> +
> +#include "i965_avc_encoder_common.h"
> +int
> +i965_avc_get_max_mbps(int level_idc)
> +{
> +int max_mbps = 11880;
> +
> +switch (level_idc) {
> +case INTEL_AVC_LEVEL_2:
> +max_mbps = 11880;
> +break;
> +
> +case INTEL_AVC_LEVEL_21:
> +max_mbps = 19800;
> +break;
> +
> +case INTEL_AVC_LEVEL_22:
> +max_mbps = 20250;
> +break;
> +
> +case INTEL_AVC_LEVEL_3:
> +max_mbps = 40500;
> +break;
> +
> +case INTEL_AVC_LEVEL_31:
> +max_mbps = 108000;
> +break;
> +
> +case INTEL_AVC_LEVEL_32:
> +max_mbps = 216000;
> +break;
> +
> +case INTEL_AVC_LEVEL_4:
> +case INTEL_AVC_LEVEL_41:
> +max_mbps = 245760;
> +break;
> +
> +case INTEL_AVC_LEVEL_42:
> +max_mbps = 522240;
> +break;
> +
> +case INTEL_AVC_LEVEL_5:
> +max_mbps = 589824;
> +break;
> +
> +case INTEL_AVC_LEVEL_51:
> +max_mbps = 983040;
> +break;
> +
> +case INTEL_AVC_LEVEL_52:
> +max_mbps = 2073600;
> +break;
> +
> +default:
> +break;
> +}
> +
> +return max_mbps;
> +};
> +
> +unsigned int
> +i965_avc_get_profile_level_max_frame(struct avc_param * param,
> + int level_idc) {
> +double bits_per_mb, tmpf;
> +int max_mbps, num_mb_per_frame;
> +uint64_t max_byte_per_frame0, max_byte_per_frame1;
> +unsigned int ret;
> +unsigned int scale_factor = 4;
> +
> +
> +if (level_idc>= INTEL_AVC_LEVEL_31&& level_idc<= INTEL_AVC_LEVEL_4)
> +bits_per_mb = 96.0;
> +else
> +{
> +bits_per_mb = 192.0;
> +scale_factor = 2;
> +
> +}
> +
> +max_mbps = i965_avc_get_max_mbps(level_idc);
> +num_mb_per_frame = param->frame_width_in_mbs *
> + param->frame_height_in_mbs;
> +
> +tmpf = (double)num_mb_per_frame;
> +
> +if (tmpf< max_mbps / 172.0)
> +tmpf = max_mbps / 172.0;
> +
> +max_byte_per_frame0 = (uint64_t)(tmpf * bits_per_mb);
> +max_byte_per_frame1 = (uint64_t)(((double)max_mbps * 100) /
> + param->frames_per_100s *bits_per_mb);
> +
> +/* TODO: check VAEncMiscParameterTypeMaxFrameSize */
> +ret = (unsigned int)MIN(max_byte_per_frame0, max_byte_per_frame1);
> +ret = (unsigned int)MIN(ret, param->frame_width_in_pixel *
> + param->frame_height_in_pixel *3 /(2*scale_factor));
> +
> +return ret;
> +}
> +
As it is discussed in another email thread, it will be better to use
frame_rate_nom and frame_rate_denom instead of frames_per_100s.
https://lists.freedesktop.org/archives/libva/2016-December/004973.html
Thanks
Yakui
[Pengfei] It will be kept in internal use
> +int
> +i965_avc_calculate_initial_qp(struct avc_param * par
Re: [Libva] [PATCH 08/31] ENC: add misc parameter check for AVC encoder
-Original Message-
From: Libva [mailto:libva-boun...@lists.freedesktop.org] On Behalf Of Zhao Yakui
Sent: Wednesday, January 11, 2017 11:13 AM
To: Sean V Kelley
Cc: libva@lists.freedesktop.org
Subject: Re: [Libva] [PATCH 08/31] ENC: add misc parameter check for AVC encoder
On 01/11/2017 07:37 AM, Sean V Kelley wrote:
> From: Pengfei Qu
>
> Signed-off-by: Pengfei Qu
> Reviewed-by: Sean V Kelley
> ---
> src/gen9_avc_encoder.c | 548
> +
> 1 file changed, 548 insertions(+)
> create mode 100755 src/gen9_avc_encoder.c
>
> diff --git a/src/gen9_avc_encoder.c b/src/gen9_avc_encoder.c new file
> mode 100755 index ..8f1ad79f
> --- /dev/null
> +++ b/src/gen9_avc_encoder.c
> @@ -0,0 +1,548 @@
> +/*
> + * Copyright ? 2016 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person
> +obtaining a
> + * copy of this software and associated documentation files (the
> + * "Software"), to deal in the Software without restriction,
> +including
> + * without limitation the rights to use, copy, modify, merge,
> +publish,
> + * distribute, sub license, and/or sell copies of the Software, and
> +to
> + * permit persons to whom the Software is furnished to do so, subject
> +to
> + * the following conditions:
> + *
> + * The above copyright notice and this permission notice (including
> +the
> + * next paragraph) shall be included in all copies or substantial
> +portions
> + * of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> +EXPRESS
> + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
> + * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE
> +FOR
> + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
> +CONTRACT,
> + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
> + * SOFTWAR
> + *
> + * Authors:
> + *Pengfei Qu
> + *
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "intel_batchbuffer.h"
> +#include "intel_driver.h"
> +
> +#include "i965_defines.h"
> +#include "i965_structs.h"
> +#include "i965_drv_video.h"
> +#include "i965_encoder.h"
> +#include "i965_encoder_utils.h"
> +#include "intel_media.h"
> +
> +#include "i965_gpe_utils.h"
> +#include "i965_encoder_common.h"
> +#include "i965_avc_encoder_common.h"
> +#include "gen9_avc_encoder_kernels.h"
> +#include "gen9_avc_encoder.h"
> +#include "gen9_avc_const_def.h"
> +
> +#define MAX_URB_SIZE4096 /* In register */
> +#define NUM_KERNELS_PER_GPE_CONTEXT 1
> +#define MBENC_KERNEL_BASE GEN9_AVC_KERNEL_MBENC_QUALITY_I
> +
Please use the OUT_BCS_RELOC64 instead of OUT_BCS_RELOC so that it can work for
48-bit GPU address.
[Pengfei] Good comments. It will be modified.
> +#define OUT_BUFFER_2DW(batch, bo, is_target, delta) do { \
> +if (bo) { \
> +OUT_BCS_RELOC(batch,\
> +bo, \
> +I915_GEM_DOMAIN_INSTRUCTION,\
> +is_target ? I915_GEM_DOMAIN_INSTRUCTION : 0,
> \
> +delta); \
> +OUT_BCS_BATCH(batch, 0);\
> +} else {\
> +OUT_BCS_BATCH(batch, 0);\
> +OUT_BCS_BATCH(batch, 0);\
> +} \
> +} while (0)
> +
> +#define OUT_BUFFER_3DW(batch, bo, is_target, delta, attr) do { \
> +OUT_BUFFER_2DW(batch, bo, is_target, delta);\
> +OUT_BCS_BATCH(batch, attr); \
> +} while (0)
> +
> +
> +static const uint32_t qm_flat[16] = {
> +0x10101010, 0x10101010, 0x10101010, 0x10101010,
> +0x10101010, 0x10101010, 0x10101010, 0x10101010,
> +0x10101010, 0x10101010, 0x10101010, 0x10101010,
> +0x10101010, 0x10101010, 0x10101010, 0x10101010 };
> +
> +static const uint32_t fqm_flat[32] = {
> +0x10001000, 0x10001000, 0x10001000, 0x10001000,
> +0x10001000, 0x10001000, 0x10001000, 0x10001000,
> +0x10001000, 0x10001000, 0x10001000, 0x10001000,
> +0x10001000, 0x10001000, 0x10001000, 0x10001000,
> +0x10001000, 0x10001000, 0x10001000, 0x10001000,
> +0x10001000, 0x10001000, 0x10001000, 0x10001000,
> +0x10001000, 0x10001000, 0x10001000, 0x10001000,
> +0x10001000, 0x10001000, 0x10001000, 0x10001000 };
> +
> +static unsigned int slice_type_kernel[3] = {1,2,0};
> +
> +const gen9_avc_brc_init_reset_curbe_data
> +gen9_avc_brc_init_re
Re: [Libva] [PATCH 02/31] ENC: add common structure for AVC/HEVC encoder
-Original Message-
From: Libva [mailto:libva-boun...@lists.freedesktop.org] On Behalf Of Zhao Yakui
Sent: Wednesday, January 11, 2017 10:33 PM
To: Sean V Kelley
Cc: libva@lists.freedesktop.org
Subject: Re: [Libva] [PATCH 02/31] ENC: add common structure for AVC/HEVC
encoder
On 01/11/2017 07:37 AM, Sean V Kelley wrote:
> From: Pengfei Qu
>
> Signed-off-by: Pengfei Qu
> Reviewed-by: Sean V Kelley
> ---
> src/i965_encoder_common.c | 124 +++
> src/i965_encoder_common.h | 533
> ++
> 2 files changed, 657 insertions(+)
> create mode 100755 src/i965_encoder_common.c
> create mode 100755 src/i965_encoder_common.h
>
> diff --git a/src/i965_encoder_common.c b/src/i965_encoder_common.c new
> file mode 100755 index ..930aba99
> --- /dev/null
> +++ b/src/i965_encoder_common.c
> @@ -0,0 +1,124 @@
> +/*
> + * Copyright ? 2016 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person
> +obtaining a
> + * copy of this software and associated documentation files (the
> + * "Software"), to deal in the Software without restriction,
> +including
> + * without limitation the rights to use, copy, modify, merge,
> +publish,
> + * distribute, sub license, and/or sell copies of the Software, and
> +to
> + * permit persons to whom the Software is furnished to do so, subject
> +to
> + * the following conditions:
> + *
> + * The above copyright notice and this permission notice (including
> +the
> + * next paragraph) shall be included in all copies or substantial
> +portions
> + * of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> +EXPRESS
> + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
> + * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE
> +FOR
> + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
> +CONTRACT,
> + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
> + * SOFTWAR
> + *
> + * Authors:
> + * Pengfei Qu
> + *
> + */
> +#include
> +#include
> +#include "intel_batchbuffer.h"
> +#include "intel_driver.h"
> +#include "i965_encoder_common.h"
> +#include "i965_gpe_utils.h"
> +
> +
> +const unsigned int table_enc_search_path[2][8][16] = {
> +// I-Frame& P-Frame
> +{
> +// MEMethod: 0
> +{
> +0x120FF10F, 0x1E22E20D, 0x20E2FF10, 0x2EDD06FC, 0x11D33FF1,
> 0xEB1FF33D, 0x4EF1F1F1, 0xF1F21211,
> +0x0DE0, 0x11201F1F, 0x1105F1CF, 0x, 0x,
> 0x, 0x, 0x
> +},
> +// MEMethod: 1
> +{
> +0x120FF10F, 0x1E22E20D, 0x20E2FF10, 0x2EDD06FC, 0x11D33FF1,
> 0xEB1FF33D, 0x4EF1F1F1, 0xF1F21211,
> +0x0DE0, 0x11201F1F, 0x1105F1CF, 0x, 0x,
> 0x, 0x, 0x
> +},
> +// MEMethod: 2
> +{
> +0x, 0x, 0x, 0x, 0x,
> 0x, 0x, 0x,
> +0x, 0x, 0x, 0x, 0x,
> 0x, 0x, 0x
> +},
> +// MEMethod: 3
> +{
> +0x01010101, 0x11010101, 0x01010101, 0x11010101, 0x01010101,
> 0x11010101, 0x01010101, 0x11010101,
> +0x01010101, 0x11010101, 0x01010101, 0x00010101, 0x,
> 0x, 0x, 0x
> +},
> +// MEMethod: 4
> +{
> +0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010,
> 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
> +0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F,
> 0xF0F0F0F0, 0x, 0x
> +},
> +// MEMethod: 5
> +{
> +0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010,
> 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
> +0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F,
> 0xF0F0F0F0, 0x, 0x
> +},
> +// MEMethod: 6
> +{
> +0x120FF10F, 0x1E22E20D, 0x20E2FF10, 0x2EDD06FC, 0x11D33FF1,
> 0xEB1FF33D, 0x4EF1F1F1, 0xF1F21211,
> +0x0DE0, 0x11201F1F, 0x1105F1CF, 0x, 0x,
> 0x, 0x, 0x
> +},
> +// MEMethod: 7 used for mpeg2 encoding P frames
> +{
> +0x1F11F10F, 0x2E22E2FE, 0x20E220DF, 0x2EDD06FC, 0x11D33FF1,
> 0xEB1FF33D, 0x02F1F1F1, 0x1F20,
> +0xF1EFFF0C, 0xF01104F1, 0x10FF0A50, 0x000FF1C0, 0x,
> 0x, 0x, 0x
> +}
> +},
> +// B-Frame
> +{
> +// MEMethod: 0
> +{
> +0x0101F00F, 0x0F0F1010, 0xF0F0F00F, 0x01010101, 0x10101010,
> 0x0F0F0F0F, 0xF0F0F00F, 0x0101F0F0,
> +0x01010101, 0x10101010, 0x0F0F1010, 0x0F0F0F0F, 0xF0F0F00F,
> 0xF0F0F0F0, 0x, 0x
> +},
Re: [Libva] [PATCH V3: 1/4] HEVC10bit ENC: add private surface for p010 conversion to nv12
-Original Message-
From: Xiang, Haihao
Sent: Tuesday, September 6, 2016 10:00 PM
To: Qu, Pengfei ; libva@lists.freedesktop.org
Subject: RE: [Libva] [PATCH V3: 1/4] HEVC10bit ENC: add private surface for
p010 conversion to nv12
>-Original Message-
>From: Libva [mailto:libva-boun...@lists.freedesktop.org] On Behalf Of
>Pengfei Qu
>Sent: Tuesday, September 6, 2016 8:09 AM
>To: libva@lists.freedesktop.org
>Subject: [Libva] [PATCH V3: 1/4] HEVC10bit ENC: add private surface for
>p010 conversion to nv12
>
>Signed-off-by: Pengfei Qu
>---
> src/intel_media.h| 5 +
> src/intel_media_common.c | 10 ++
> 2 files changed, 15 insertions(+)
>
>diff --git a/src/intel_media.h b/src/intel_media.h index
>87d315f..4a55a93
>100644
>--- a/src/intel_media.h
>+++ b/src/intel_media.h
>@@ -57,6 +57,11 @@ struct gen_hevc_surface {
> GenCodecSurface base;
> dri_bo *motion_vector_temporal_bo;
>+//Encoding HEVC10:internal surface keep for P010->NV12 , this is
>+ only for
>hevc10 to save the P010->NV12
>+struct object_surface *nv12_surface_obj;
>+VASurfaceID nv12_surface_id;
>+VADriverContextP ctx;
>+int has_p010_to_nv12_done;
> };
>
> typedef struct gen_vp9_surface GenVP9Surface; diff --git
>a/src/intel_media_common.c b/src/intel_media_common.c index
>8821bc4..01828b0 100644
>--- a/src/intel_media_common.c
>+++ b/src/intel_media_common.c
>@@ -29,6 +29,7 @@
>
> #include "intel_driver.h"
> #include "intel_media.h"
>+#include "i965_drv_video.h"
>
> static pthread_mutex_t free_avc_surface_lock =
>PTHREAD_MUTEX_INITIALIZER;
>
>@@ -92,6 +93,9 @@ gen_free_hevc_surface(void **data)
>
> pthread_mutex_lock(&free_hevc_surface_lock);
>
>+if (!data || !*data)
>+return;
Please unlock the mutex first before returning. Actually the above check is
unnecessary because data is non-NULL when gen_free_hevc_surface() is called,
and *data is checked beblow.
[Pengfei]agree
>+
> hevc_surface = *data;
>
> if (!hevc_surface) {
>@@ -102,6 +106,12 @@ gen_free_hevc_surface(void **data)
> dri_bo_unreference(hevc_surface->motion_vector_temporal_bo);
> hevc_surface->motion_vector_temporal_bo = NULL;
>
>+if (hevc_surface->nv12_surface_obj) {
>+i965_DestroySurfaces(hevc_surface->ctx, &hevc_surface-
>>nv12_surface_id, 1);
>+hevc_surface->nv12_surface_id = VA_INVALID_SURFACE;
>+hevc_surface->nv12_surface_obj = NULL;
>+}
>+
> free(hevc_surface);
> *data = NULL;
>
>--
>2.7.4
>
>___
>Libva mailing list
>Libva@lists.freedesktop.org
>https://lists.freedesktop.org/mailman/listinfo/libva
___
Libva mailing list
Libva@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/libva
Re: [Libva] [PATCH V3: 2/4] HEVC10bit ENC:enable hevc 10bit on VME and PAK
-Original Message-
From: Xiang, Haihao
Sent: Wednesday, September 7, 2016 10:09 AM
To: Zhao, Yakui
Cc: Qu, Pengfei ; libva@lists.freedesktop.org
Subject: Re: [Libva] [PATCH V3: 2/4] HEVC10bit ENC:enable hevc 10bit on VME and
PAK
On Wed, 2016-09-07 at 09:02 +0800, Zhao Yakui wrote:
> On 09/06/2016 10:48 PM, Xiang, Haihao wrote:
> >
> >
> > > -Original Message-
> > > From: Libva [mailto:libva-boun...@lists.freedesktop.org] On Behalf
> > > Of Pengfei Qu
> > > Sent: Tuesday, September 6, 2016 8:09 AM
> > > To: libva@lists.freedesktop.org
> > > Subject: [Libva] [PATCH V3: 2/4] HEVC10bit ENC:enable hevc 10bit
> > > on VME and PAK
> > >
> > > 1.add p010->nv12 before VME
> > > 2.add CBR support
> > >
> > > Signed-off-by: Pengfei Qu
> > > ---
> > > src/gen6_mfc_common.c | 13 +
> > > src/gen9_mfc_hevc.c | 105 ++--
> > > src/gen9_vme.c| 146
> > > ++
> > > 3 files changed, 198 insertions(+), 66 deletions(-)
> > >
> > > diff --git a/src/gen6_mfc_common.c b/src/gen6_mfc_common.c index
> > > 9f041d8..faabbe7 100644
> > > --- a/src/gen6_mfc_common.c
> > > +++ b/src/gen6_mfc_common.c
> > > @@ -2089,12 +2089,19 @@
> > > intel_hevc_vme_reference_state(VADriverContextP ctx,
> > > struct object_surface *obj_surface = NULL;
> > > struct i965_driver_data *i965 = i965_driver_data(ctx);
> > > VASurfaceID ref_surface_id;
> > > +VAEncSequenceParameterBufferHEVC *pSequenceParameter =
> > > +(VAEncSequenceParameterBufferHEVC
> > > + *)encode_state->seq_param_ext->buffer;
> > > VAEncPictureParameterBufferHEVC *pic_param =
> > > (VAEncPictureParameterBufferHEVC *)encode_state->pic_param_ext-
> > > > buffer;
> > > VAEncSliceParameterBufferHEVC *slice_param =
> > > (VAEncSliceParameterBufferHEVC *)encode_state-
> > > >slice_params_ext[0]-
> > > > buffer;
> > > int max_num_references;
> > > VAPictureHEVC *curr_pic;
> > > VAPictureHEVC *ref_list;
> > > int ref_idx;
> > > +unsigned int is_hevc10 = 0;
> > > +GenHevcSurface *hevc_encoder_surface = NULL;
> > > +
> > > +if((pSequenceParameter-
> > > >seq_fields.bits.bit_depth_luma_minus8> 0)
> > > +|| (pSequenceParameter-
> > > >seq_fields.bits.bit_depth_chroma_minus8>
> > > 0))
> > > +is_hevc10 = 1;
> > >
> > > if (list_index == 0) {
> > > max_num_references = pic_param-
> > > > num_ref_idx_l0_default_active_minus1 + 1; @@ -2141,6 +2148,12 @@
> > > intel_hevc_vme_reference_state(VADriverContextP ctx,
> > > obj_surface->bo) {
> > > assert(ref_idx>= 0);
> > > vme_context->used_reference_objects[list_index] =
> > > obj_surface;
> > > +
> > > +if(is_hevc10){
> > > +hevc_encoder_surface = (GenHevcSurface *)
> > > obj_surface-
> > > > private_data;
> > > +assert(hevc_encoder_surface);
> > > +obj_surface = hevc_encoder_surface-
> > > >nv12_surface_obj;
> > > +}
> > > vme_source_surface_state(ctx, surface_index, obj_surface,
> > > encoder_context);
> > > vme_context->ref_index_in_mb[list_index] = (ref_idx<< 24
> > > |
> > > ref_idx<< 16 |
> > > diff --git a/src/gen9_mfc_hevc.c b/src/gen9_mfc_hevc.c index
> > > b3ee327..9aaf4e9 100644
> > > --- a/src/gen9_mfc_hevc.c
> > > +++ b/src/gen9_mfc_hevc.c
> > > @@ -193,12 +193,21 @@ gen9_hcpe_surface_state(VADriverContextP
> > > ctx,
> > > struct encode_state *encode_state,
> > > struct intel_batchbuffer *batch = encoder_context-
> > > >base.batch;
> > > struct object_surface *obj_surface = encode_state-
> > > >reconstructed_object;
> > > struct gen9_hcpe_context *mfc_context = encoder_context-
> > > >mfc_context;
> > > +VAEncSequenceParameterBufferHEVC *pSequenceParameter =
> > > (VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext-
> > > > buffer;
> > > +unsigned int surface_format = SURFACE_FORMAT_PLANAR_420_8;
> > >
> > > /* to do */
> > >
Re: [Libva] [PATCH 11/13] Adjust the maximum number of motion vectors for B frame on HSW+
AVC SPEC only allow max 16 frames for 1080P at level 5.1. and Level 4/4.1/4.2
only allow max 4 ref frames. And level 5 allow max 13 ref frames for 1080P.
Here the user should be careful when set “denom”. The driver now use the
default value “1” to set the VME. it is safe by now.
Thanks,
Pengfei
From: Peter Frühberger [mailto:peter.fruehber...@gmail.com]
Sent: Saturday, July 9, 2016 2:05 PM
To: Qu, Pengfei
Cc: libva@lists.freedesktop.org; Meng, Jia
Subject: Re: [Libva] [PATCH 11/13] Adjust the maximum number of motion vectors
for B frame on HSW+
Be careful here, please,
some real life files lie about their spec, e.g. they are announcing Level 4.1
High but ship 16 Reframes at 1920x1080. Afaik mpeg-2 always uses 2 (one past
and one future). That would result in pixelation, right?
Best regards
Peter
2016-07-07 11:18 GMT+02:00 Pengfei Qu
mailto:pengfei...@intel.com>>:
From: Jia Meng mailto:jia.m...@intel.com>>
Signed-off-by: Jia Meng mailto:jia.m...@intel.com>>
Signed-off-by: Pengfei Qu mailto:pengfei...@intel.com>>
---
src/gen75_vme.c | 13 +++--
src/gen8_vme.c | 15 ---
src/gen9_vme.c | 17 +
3 files changed, 24 insertions(+), 21 deletions(-)
diff --git a/src/gen75_vme.c b/src/gen75_vme.c
index 174a642..81925fe 100644
--- a/src/gen75_vme.c
+++ b/src/gen75_vme.c
@@ -330,7 +330,8 @@ static VAStatus gen75_vme_interface_setup(VADriverContextP
ctx,
static VAStatus gen75_vme_constant_setup(VADriverContextP ctx,
struct encode_state *encode_state,
- struct intel_encoder_context
*encoder_context)
+ struct intel_encoder_context
*encoder_context,
+ int denom)
{
struct gen6_vme_context *vme_context = encoder_context->vme_context;
unsigned char *constant_buffer;
@@ -342,13 +343,13 @@ static VAStatus gen75_vme_constant_setup(VADriverContextP
ctx,
if (encoder_context->codec == CODEC_H264 ||
encoder_context->codec == CODEC_H264_MVC) {
if (vme_context->h264_level >= 30) {
-mv_num = 16;
+mv_num = 16 / denom;
if (vme_context->h264_level >= 31)
-mv_num = 8;
+mv_num = 8 / denom;
}
} else if (encoder_context->codec == CODEC_MPEG2) {
-mv_num = 2;
+mv_num = 2 / denom;
}
vme_state_message[31] = mv_num;
@@ -675,7 +676,7 @@ static VAStatus gen75_vme_prepare(VADriverContextP ctx,
gen75_vme_surface_setup(ctx, encode_state, is_intra, encoder_context);
gen75_vme_interface_setup(ctx, encode_state, encoder_context);
//gen75_vme_vme_state_setup(ctx, encode_state, is_intra, encoder_context);
-gen75_vme_constant_setup(ctx, encode_state, encoder_context);
+gen75_vme_constant_setup(ctx, encode_state, encoder_context,
(pSliceParameter->slice_type == SLICE_TYPE_B) ? 2 : 1);
/*Programing media pipeline*/
gen75_vme_pipeline_programing(ctx, encode_state, encoder_context);
@@ -987,7 +988,7 @@ gen75_vme_mpeg2_prepare(VADriverContextP ctx,
gen75_vme_interface_setup(ctx, encode_state, encoder_context);
gen75_vme_vme_state_setup(ctx, encode_state, slice_param->is_intra_slice,
encoder_context);
intel_vme_mpeg2_state_setup(ctx, encode_state, encoder_context);
-gen75_vme_constant_setup(ctx, encode_state, encoder_context);
+gen75_vme_constant_setup(ctx, encode_state, encoder_context, 1);
/*Programing media pipeline*/
gen75_vme_mpeg2_pipeline_programing(ctx, encode_state,
slice_param->is_intra_slice, encoder_context);
diff --git a/src/gen8_vme.c b/src/gen8_vme.c
index 28b8195..f4a874e 100644
--- a/src/gen8_vme.c
+++ b/src/gen8_vme.c
@@ -363,7 +363,8 @@ static VAStatus gen8_vme_interface_setup(VADriverContextP
ctx,
static VAStatus gen8_vme_constant_setup(VADriverContextP ctx,
struct encode_state *encode_state,
-struct intel_encoder_context
*encoder_context)
+struct intel_encoder_context
*encoder_context,
+int denom)
{
struct gen6_vme_context *vme_context = encoder_context->vme_context;
unsigned char *constant_buffer;
@@ -375,13 +376,13 @@ static VAStatus gen8_vme_constant_setup(VADriverContextP
ctx,
if (encoder_context->codec == CODEC_H264 ||
encoder_context->codec == CODEC_H264_MVC) {
if (vme_context->h264_level >= 30) {
-mv_num = 16;
+mv_num = 16 / denom;
if (vme_context->h264_level >= 31)
-mv_num = 8;
+mv_num = 8 / denom;
}
} else if (encoder_context->codec == CODEC_MPEG2) {
-mv_num = 2;
+mv_num = 2 / denom;
}
vme_state_message[31] =
Re: [Libva] [PATCH 13/14] scaling matrix of h264 encoder on gen8/gen9
it is good to change the title to gen7/gen7.5/gen8/gen9. And it is better to
keep the same changes for each platform.
Thanks,
Pengfei
-Original Message-
From: Zhao, Yakui
Sent: Wednesday, July 6, 2016 4:41 PM
To: Qu, Pengfei
Cc: libva@lists.freedesktop.org; Meng, Jia
Subject: Re: [Libva] [PATCH 13/14] scaling matrix of h264 encoder on gen8/gen9
On 06/30/2016 10:33 AM, Pengfei Qu wrote:
> From: Jia Meng
>
> qm is in raster scan order per va api, and fqm is in column wise
> raster scan order per hardware requirement.
The title is inconsistent with what is done.
Can we remove it for gen6/gen7/gen75 and only keep it for gen8/gen9?
Thanks
Yakui
>
> Signed-off-by: Jia Meng
> Signed-off-by: Pengfei Qu
> ---
> src/gen6_mfc.c | 12 --
> src/gen6_mfc.h | 2 +
> src/gen75_mfc.c | 12 --
> src/gen7_mfc.c | 8 +++-
> src/gen8_mfc.c | 122 -
> src/gen9_mfc.c | 127
> ++--
> 6 files changed, 211 insertions(+), 72 deletions(-)
>
> diff --git a/src/gen6_mfc.c b/src/gen6_mfc.c index b482712..e9e76cb
> 100644
> --- a/src/gen6_mfc.c
> +++ b/src/gen6_mfc.c
> @@ -464,7 +464,9 @@ gen6_mfc_avc_slice_state(VADriverContextP ctx,
> ADVANCE_BCS_BATCH(batch);
> }
>
> -static void gen6_mfc_avc_qm_state(VADriverContextP ctx, struct
> intel_encoder_context *encoder_context)
> +static void gen6_mfc_avc_qm_state(VADriverContextP ctx,
> + struct encode_state *encode_state,
> + struct intel_encoder_context
> +*encoder_context)
> {
> struct intel_batchbuffer *batch = encoder_context->base.batch;
> int i;
> @@ -480,7 +482,9 @@ static void gen6_mfc_avc_qm_state(VADriverContextP ctx,
> struct intel_encoder_con
> ADVANCE_BCS_BATCH(batch);
> }
>
> -static void gen6_mfc_avc_fqm_state(VADriverContextP ctx, struct
> intel_encoder_context *encoder_context)
> +static void gen6_mfc_avc_fqm_state(VADriverContextP ctx,
> + struct encode_state *encode_state,
> + struct intel_encoder_context
> +*encoder_context)
> {
> struct intel_batchbuffer *batch = encoder_context->base.batch;
> int i;
> @@ -639,8 +643,8 @@ static void gen6_mfc_avc_pipeline_picture_programing(
> VADriverContextP ctx,
> gen6_mfc_pipe_buf_addr_state(ctx, encoder_context);
> gen6_mfc_bsp_buf_base_addr_state(ctx, encoder_context);
> mfc_context->avc_img_state(ctx, encode_state, encoder_context);
> -mfc_context->avc_qm_state(ctx, encoder_context);
> -mfc_context->avc_fqm_state(ctx, encoder_context);
> +mfc_context->avc_qm_state(ctx, encode_state, encoder_context);
> +mfc_context->avc_fqm_state(ctx, encode_state, encoder_context);
> gen6_mfc_avc_directmode_state(ctx, encoder_context);
> intel_mfc_avc_ref_idx_state(ctx, encode_state, encoder_context);
> }
> diff --git a/src/gen6_mfc.h b/src/gen6_mfc.h index fa610d4..4561d43
> 100644
> --- a/src/gen6_mfc.h
> +++ b/src/gen6_mfc.h
> @@ -319,8 +319,10 @@ struct gen6_mfc_context
> struct encode_state *encode_state,
> struct intel_encoder_context *encoder_context);
> void (*avc_qm_state)(VADriverContextP ctx,
> + struct encode_state *encode_state,
>struct intel_encoder_context *encoder_context);
> void (*avc_fqm_state)(VADriverContextP ctx,
> + struct encode_state *encode_state,
> struct intel_encoder_context *encoder_context);
> void (*insert_object)(VADriverContextP ctx,
> struct intel_encoder_context
> *encoder_context, diff --git a/src/gen75_mfc.c b/src/gen75_mfc.c index
> f69a186..838d0d8 100644
> --- a/src/gen75_mfc.c
> +++ b/src/gen75_mfc.c
> @@ -331,7 +331,9 @@ gen75_mfc_qm_state(VADriverContextP ctx,
> }
>
> static void
> -gen75_mfc_avc_qm_state(VADriverContextP ctx, struct
> intel_encoder_context *encoder_context)
> +gen75_mfc_avc_qm_state(VADriverContextP ctx,
> + struct encode_state *encode_state,
> + struct intel_encoder_context *encoder_context)
> {
> unsigned int qm[16] = {
> 0x10101010, 0x10101010, 0x10101010, 0x10101010, @@ -368,7
> +370,9 @@ gen75_mfc_fqm_state(VADriverContextP ctx,
> }
>
> static void
> -gen75_mfc_avc_fqm_state(VADriverContextP ctx, struct
> intel_encoder_context *encoder_context)
> +gen75_mfc_avc_fqm_state(VADriverContextP ctx,
Re: [Libva] [PATCH 04/14] encoding: Send VME instruction uses one register as the desc parameter instead of hardcode
Sure, Gen8 also has the similar change.
Thanks,
Pengfei
-Original Message-
From: Xiang, Haihao
Sent: Friday, July 1, 2016 2:18 PM
To: Qu, Pengfei ; libva@lists.freedesktop.org
Cc: ceciliap...@intel.com
Subject: Re: [Libva] [PATCH 04/14] encoding: Send VME instruction uses one
register as the desc parameter instead of hardcode
This patch LGTM, but one question: does Gen8+ need a similar patch?
Thanks
Haihao
> From: Zhao Yakui
>
> The desc parameter of current VME send instruction is hardcode. And it
> can't be updated based on the input parameter.
>
> Signed-off-by: Zhao Yakui
> Signed-off-by: pjl
> Signed-off-by: Pengfei Qu
> ---
> src/shaders/vme/inter_bframe_ivb.asm | 17 +++--
> src/shaders/vme/inter_bframe_ivb.g7b | 19 ++-
> src/shaders/vme/inter_frame_ivb.asm | 16 +++-
> src/shaders/vme/inter_frame_ivb.g7b | 7 ---
> src/shaders/vme/intra_frame_ivb.asm | 17 +++--
> src/shaders/vme/intra_frame_ivb.g7b | 3 ++-
> 6 files changed, 25 insertions(+), 54 deletions(-)
>
> diff --git a/src/shaders/vme/inter_bframe_ivb.asm
> b/src/shaders/vme/inter_bframe_ivb.asm
> index e7be377..499e426 100644
> --- a/src/shaders/vme/inter_bframe_ivb.asm
> +++ b/src/shaders/vme/inter_bframe_ivb.asm
> @@ -542,20 +542,9 @@ mov (1) vme_m1.16<1>:ud mb_mvp_ref.0<0,1
> ,0>:ud{align1};
> mov (1) vme_m1.20<1>:ud mb_mvp_ref.4<0,1,0>:ud {align
> 1};
> mov (8) vme_msg_1.0<1>:UD vme_m1.0<8,8,1>:UD {align1};
>
> -
> -send (8)
> -vme_msg_ind
> -vme_wb
> -null
> -vme(
> -BIND_IDX_VME,
> -0,
> -0,
> -VME_MESSAGE_TYPE_MIXED
> -)
> -mlen vme_msg_length
> -rlen vme_inter_wb_length
> -{align1};
> +/* Use one register as the descriptor of send instruction instead of
> hardcode*/
> +mov (1) a0.0<1>:ud 0x0a686000:ud {align1}; send (1)
> +vme_wb.0<1>:ud vme_msg_00x08 a0.0<0,1,0>:ud
> {align1};
>
> and.z.f0.0 (1) null<1>:ud vme_wb0.0<0,1,0>:ud
> INTRAMBFLAG_MASK:ud {align1} ;
>
> diff --git a/src/shaders/vme/inter_bframe_ivb.g7b
> b/src/shaders/vme/inter_bframe_ivb.g7b
> index adcb390..7f24b63 100644
> --- a/src/shaders/vme/inter_bframe_ivb.g7b
> +++ b/src/shaders/vme/inter_bframe_ivb.g7b
> @@ -53,7 +53,7 @@
> { 0x0001, 0x2fa40021, 0x0b80, 0x },
> { 0x0001, 0x2fa80061, 0x, 0x0001 },
> { 0x0040, 0x2fe00c01, 0x1400, 0x0020 },
> - { 0x0020, 0x34001c00, 0x1400, 0x0248 },
> + { 0x0020, 0x34001c00, 0x1400, 0x024a },
> { 0x0001, 0x2aa00129, 0x0fe4, 0x },
> { 0x0110, 0x20002d28, 0x0aa0, 0x },
> { 0x00010001, 0x2af001e9, 0x, 0x00010001 }, @@ -91,7 +91,7
> @@
> { 0x0001, 0x2fa40021, 0x0b80, 0x },
> { 0x0001, 0x2fa80061, 0x, 0x0002 },
> { 0x0040, 0x2fe00c01, 0x1400, 0x0020 },
> - { 0x0020, 0x34001c00, 0x1400, 0x01fc },
> + { 0x0020, 0x34001c00, 0x1400, 0x01fe },
> { 0x0001, 0x2aa00129, 0x0fe4, 0x },
> { 0x0110, 0x20002d28, 0x0aa0, 0x },
> { 0x00010001, 0x2b1001e9, 0x, 0x00010001 }, @@ -127,7
> +127,7 @@
> { 0x0001, 0x2fa40021, 0x0b80, 0x },
> { 0x0001, 0x2fa80061, 0x, 0x0002 },
> { 0x0040, 0x2fe00c01, 0x1400, 0x0020 },
> - { 0x0020, 0x34001c00, 0x1400, 0x01b4 },
> + { 0x0020, 0x34001c00, 0x1400, 0x01b6 },
> { 0x0001, 0x2aa00129, 0x0fe4, 0x },
> { 0x0110, 0x20002d28, 0x0aa0, 0x },
> { 0x00010001, 0x2b3001e9, 0x, 0x00010001 }, @@ -164,7
> +164,7 @@
> { 0x0001, 0x2fa40021, 0x0b80, 0x },
> { 0x0001, 0x2fa80061, 0x, 0x0003 },
> { 0x0040, 0x2fe00c01, 0x1400, 0x0020 },
> - { 0x0020, 0x34001c00, 0x1400, 0x016a },
> + { 0x0020, 0x34001c00, 0x1400, 0x016c },
> { 0x0001, 0x2aa00129, 0x0fe4, 0x },
> { 0x0001, 0x2b3201ed, 0x, 0x00010001 },
> { 0x0110, 0x20002d28, 0x0aa0, 0x }, @@ -205,13
> +205,13 @@
> { 0x0001, 0x2fa401ad, 0x0b04, 0x },
> { 0x0001, 0x2fa801ad, 0x0b24, 0x },
> { 0x0040, 0x2fe00c01, 0x1400, 0x0020 },
> - { 0x0020, 0x34001c00, 0x1400, 0x00f8 },
> + { 0x0020, 0x34001c00, 0x000
Re: [Libva] [PATCH 2/3] Encoding: Add ROI example
-Original Message-
From: Libva [mailto:libva-boun...@lists.freedesktop.org] On Behalf Of Sreerenj
Sent: Thursday, June 30, 2016 9:01 PM
To: libva@lists.freedesktop.org
Subject: Re: [Libva] [PATCH 2/3] Encoding: Add ROI example
On 30.06.2016 04:49, Pengfei Qu wrote:
> From: Zhao Yakui
>
> v1:
> add --roi-test for test only for ROI. default only one region(0,0,120,120)
> has been test.
>
> Signed-off-by: Zhao Yakui
> Signed-off-by: pjl
> Signed-off-by: ceciliapeng
> Signed-off-by: Pengfei Qu
> ---
> test/encode/avcenc.c | 85
>
> 1 file changed, 80 insertions(+), 5 deletions(-)
>
> diff --git a/test/encode/avcenc.c b/test/encode/avcenc.c index
> 74729fb..954ed1e 100644
> --- a/test/encode/avcenc.c
> +++ b/test/encode/avcenc.c
> @@ -91,6 +91,7 @@ static int intra_period = 30;
> static int frame_bit_rate = -1;
> static int frame_rate = 30;
> static int ip_period = 1;
> +static int roi_test_enable = 0;
>
> static VAEntrypoint select_entrypoint = VAEntrypointEncSlice;
>
> @@ -106,6 +107,7 @@ static const struct option longopts[] = {
> {"fb", required_argument, 0, 2},
> {"mode", required_argument, 0, 3},
> {"low-power", no_argument, 0, 4},
> +{"roi-test", no_argument, 0, 5},
> { NULL, 0, NULL, 0}
> };
>
> @@ -154,6 +156,7 @@ static struct {
> VABufferID packed_sei_header_param_buf_id; /* the SEI buffer */
> VABufferID packed_sei_buf_id;
> VABufferID misc_parameter_hrd_buf_id;
> +VABufferID misc_parameter_roi_buf_id;
>
> int num_slices;
> int codedbuf_i_size;
> @@ -185,7 +188,7 @@ static void create_encode_pipe()
> {
> VAEntrypoint entrypoints[5];
> int num_entrypoints,slice_entrypoint;
> -VAConfigAttrib attrib[2];
> +VAConfigAttrib attrib[3];
> int major_ver, minor_ver;
> VAStatus va_status;
>
> @@ -209,8 +212,11 @@ static void create_encode_pipe()
> /* find out the format for the render target, and rate control mode */
> attrib[0].type = VAConfigAttribRTFormat;
> attrib[1].type = VAConfigAttribRateControl;
> +
> +/* This is to query whether the ROI is supported */
> +attrib[2].type = VAConfigAttribEncROI;
> vaGetConfigAttributes(va_dpy, avcenc_context.profile, select_entrypoint,
> - &attrib[0], 2);
> + &attrib[0], 3);
>
> if ((attrib[0].value & VA_RT_FORMAT_YUV420) == 0) {
> /* not find desired YUV420 RT format */ @@ -225,9 +231,15 @@
> static void create_encode_pipe()
>
> attrib[0].value = VA_RT_FORMAT_YUV420; /* set to desired RT format */
> attrib[1].value = avcenc_context.rate_control_method; /* set to
> desired RC mode */
> +/* This is to create one context with ROI supported
> + * Only when it is supported, it is possible to pass ROI buffer on-the
> fly
> + * so that it can use the given ROI config for one frame.
> + * If ROI buffer is not passed, it will continue the original encoding
> mode.
> + */
> +attrib[2].value = 0x0101;
>
Is it read-only? va spec saying so :)
IMHO it could have been better to generate a warning at least, If
(roi_test_enable && attrib[2].num_roi_regions ==0) I would say, In theory it
should assert if there is no roi support ...
[Pengfei] sure. It is a good catch.
> va_status = vaCreateConfig(va_dpy, avcenc_context.profile,
> select_entrypoint,
> - &attrib[0], 2,&avcenc_context.config_id);
> + &attrib[0],
> + 3,&avcenc_context.config_id);
> CHECK_VASTATUS(va_status, "vaCreateConfig");
>
> /* Create a context for this decode pipe */ @@ -814,16 +826,70
> @@ static int begin_picture(FILE *yuv_fp, int frame_num, int
> display_num, int slice
>
> vaUnmapBuffer(va_dpy, avcenc_context.misc_parameter_hrd_buf_id);
>
> +/* ROI parameter: hard code for test on inly one region (0,0,120,120)
> with qp_delta=4 */
> +if(roi_test_enable)
> +{
> +VAEncMiscParameterBufferROI *misc_roi_param;
> +
> +int roi_num = 1;
> +vaCreateBuffer(va_dpy,
> +avcenc_context.context_id,
> +VAEncMiscParameterBufferType,
> +sizeof(VAEncMiscParameterBuffer) +
> sizeof(VAEncMiscParameterBufferROI) + roi_num * sizeof(VAEncROI),
> +1,
> +NULL,
> +&avcenc_context.misc_parameter_roi_buf_id);
> +vaMapBuffer(va_dpy,
> +avcenc_context.misc_parameter_roi_buf_id,
> +(void **)&misc_param);
> +misc_param->type = VAEncMiscParameterTypeROI;
> +misc_roi_param = (VAEncMiscParameterBufferROI
> + *)misc_param->data;
> +
> +{
> +/*
> +* Max/Min delta_qp is only used in CBR mode. It is ingored under
> CQP mode.
> +* max_delta_qp means the allowed upper bound of qp delta. (qp +
> X)
> +* m
[Libva] [PATCH-v2] FIX:this patch fix the green line on output pic when do scaling on SKL. we follow the rule from the setting of user.
v2:follow Haihao's comments and mast the user's setting for scaling Signed-off-by: Qu,Pengfei --- src/i965_post_processing.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/i965_post_processing.c b/src/i965_post_processing.c index a1c0e4d..849fbe1 100755 --- a/src/i965_post_processing.c +++ b/src/i965_post_processing.c @@ -5966,7 +5966,7 @@ i965_proc_picture(VADriverContextP ctx, intel_batchbuffer_flush(hw_context->batch); saved_filter_flag = i965pp_context->filter_flags; -i965pp_context->filter_flags = VA_FILTER_SCALING_HQ; +i965pp_context->filter_flags = (pipeline_param->filter_flags&VA_FILTER_SCALING_MASK); dst_surface.base = (struct object_base *)obj_surface; dst_surface.type = I965_SURFACE_TYPE_SURFACE; -- 1.9.1 ___ Libva mailing list Libva@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/libva
Re: [Libva] [PATCH] FIX:this patch fix the green line on output pic when do scaling on SKL.
Yes, you are right. pipeline_param->filter_flags have been saved before the csc+scaling output. And after it, pipeline_param->filter_flags have been restored. So now change to VA_FILTER_SCALING_DEFAULT only been used when csc+scaling case. -Original Message- From: Xiang, Haihao Sent: Tuesday, September 29, 2015 10:18 AM To: Qu, Pengfei Cc: libva@lists.freedesktop.org Subject: RE: [Libva] [PATCH] FIX:this patch fix the green line on output pic when do scaling on SKL. I am OK to use pipeline_param->filter_flags to follow user's setting. I fixed the broken VA_FILTER_SCALING_HQ in another patch. > How about use the VA_FILTER_SCALING_DEFAULT for this case as > VA_FILTER_SCALING_HQ cause the issue. > > -Original Message- > From: Xiang, Haihao > Sent: Tuesday, September 29, 2015 9:49 AM > To: Qu, Pengfei > Cc: libva@lists.freedesktop.org > Subject: Re: [Libva] [PATCH] FIX:this patch fix the green line on output pic > when do scaling on SKL. > > On Wed, 2015-09-23 at 14:45 +0800, Qu,Pengfei wrote: > > Signed-off-by: Qu,Pengfei > > --- > > src/i965_post_processing.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/src/i965_post_processing.c b/src/i965_post_processing.c > > index a1c0e4d..2ec34b1 100755 > > --- a/src/i965_post_processing.c > > +++ b/src/i965_post_processing.c > > @@ -5966,7 +5966,7 @@ i965_proc_picture(VADriverContextP ctx, > > intel_batchbuffer_flush(hw_context->batch); > > > > saved_filter_flag = i965pp_context->filter_flags; > > -i965pp_context->filter_flags = VA_FILTER_SCALING_HQ; > > +i965pp_context->filter_flags = > > + pipeline_param->filter_flags; > > pipeline_param->filter_flags can be OR'd with non-scaling flags, it would be > better to mask out other flags. > > BTW your patch implies green line was seen with VA_FILTER_SCALING_HQ, the > green line issue still exists if VA_FILTER_SCALING_HQ is set in > pipeline_param->filter_flags. > > > > > > dst_surface.base = (struct object_base *)obj_surface; > > dst_surface.type = I965_SURFACE_TYPE_SURFACE; > > ___ Libva mailing list Libva@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/libva
Re: [Libva] [PATCH] FIX:this patch fix the green line on output pic when do scaling on SKL.
How about use the VA_FILTER_SCALING_DEFAULT for this case as VA_FILTER_SCALING_HQ cause the issue. -Original Message- From: Xiang, Haihao Sent: Tuesday, September 29, 2015 9:49 AM To: Qu, Pengfei Cc: libva@lists.freedesktop.org Subject: Re: [Libva] [PATCH] FIX:this patch fix the green line on output pic when do scaling on SKL. On Wed, 2015-09-23 at 14:45 +0800, Qu,Pengfei wrote: > Signed-off-by: Qu,Pengfei > --- > src/i965_post_processing.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/src/i965_post_processing.c b/src/i965_post_processing.c > index a1c0e4d..2ec34b1 100755 > --- a/src/i965_post_processing.c > +++ b/src/i965_post_processing.c > @@ -5966,7 +5966,7 @@ i965_proc_picture(VADriverContextP ctx, > intel_batchbuffer_flush(hw_context->batch); > > saved_filter_flag = i965pp_context->filter_flags; > -i965pp_context->filter_flags = VA_FILTER_SCALING_HQ; > +i965pp_context->filter_flags = pipeline_param->filter_flags; pipeline_param->filter_flags can be OR'd with non-scaling flags, it would be better to mask out other flags. BTW your patch implies green line was seen with VA_FILTER_SCALING_HQ, the green line issue still exists if VA_FILTER_SCALING_HQ is set in pipeline_param->filter_flags. > > dst_surface.base = (struct object_base *)obj_surface; > dst_surface.type = I965_SURFACE_TYPE_SURFACE; ___ Libva mailing list Libva@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/libva
[Libva] [PATCH] FIX:this patch fix the green line on output pic when do scaling on SKL.
Signed-off-by: Qu,Pengfei --- src/i965_post_processing.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/i965_post_processing.c b/src/i965_post_processing.c index a1c0e4d..2ec34b1 100755 --- a/src/i965_post_processing.c +++ b/src/i965_post_processing.c @@ -5966,7 +5966,7 @@ i965_proc_picture(VADriverContextP ctx, intel_batchbuffer_flush(hw_context->batch); saved_filter_flag = i965pp_context->filter_flags; -i965pp_context->filter_flags = VA_FILTER_SCALING_HQ; +i965pp_context->filter_flags = pipeline_param->filter_flags; dst_surface.base = (struct object_base *)obj_surface; dst_surface.type = I965_SURFACE_TYPE_SURFACE; -- 1.9.1 ___ Libva mailing list Libva@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/libva
[Libva] [PATCH] FIX:HEVC enc cause GPU hang when lcu_size=32 with 720x480 and 176x144
Signed-off-by: Qu,Pengfei
---
src/gen9_mfc_hevc.c | 26 +++---
1 file changed, 15 insertions(+), 11 deletions(-)
diff --git a/src/gen9_mfc_hevc.c b/src/gen9_mfc_hevc.c
index 940146b..5fe34da 100644
--- a/src/gen9_mfc_hevc.c
+++ b/src/gen9_mfc_hevc.c
@@ -1307,9 +1307,11 @@ gen9_hcpe_hevc_fill_indirect_cu_inter(VADriverContextP
ctx,
int cu_size = 1;
int tu_size = 0x55;
int tu_count = 4;
+int inter_mode = 0;
unsigned int *mv_ptr;
{
+inter_mode = (msg[0] & AVC_INTER_MODE_MASK);
submb_pre_mode = (msg[1] & AVC_INTER_SUBMB_PRE_MODE_MASK) >> 16;
#define MSG_MV_OFFSET 4
mv_ptr = msg + MSG_MV_OFFSET;
@@ -1319,7 +1321,7 @@ gen9_hcpe_hevc_fill_indirect_cu_inter(VADriverContextP
ctx,
*/
/* 0/2/4/6/8... ??? l0, 1/3/5/7...: l1 ; now it only support
16x16,16x8,8x16,8x8*/
-if ((msg[0] & AVC_INTER_MODE_MASK) == AVC_INTER_16X16) {
+if (inter_mode == AVC_INTER_16X16) {
mv_ptr[4] = mv_ptr[0];
mv_ptr[5] = mv_ptr[1];
mv_ptr[2] = mv_ptr[0];
@@ -1330,7 +1332,7 @@ gen9_hcpe_hevc_fill_indirect_cu_inter(VADriverContextP
ctx,
cu_size = 1;
tu_size = 0x55;
tu_count = 4;
-} else if ((msg[0] & AVC_INTER_MODE_MASK) == AVC_INTER_8X16) {
+} else if (inter_mode == AVC_INTER_8X16) {
mv_ptr[4] = mv_ptr[0];
mv_ptr[5] = mv_ptr[1];
mv_ptr[2] = mv_ptr[8];
@@ -1341,7 +1343,7 @@ gen9_hcpe_hevc_fill_indirect_cu_inter(VADriverContextP
ctx,
cu_size = 1;
tu_size = 0x55;
tu_count = 4;
-} else if ((msg[0] & AVC_INTER_MODE_MASK) == AVC_INTER_16X8) {
+} else if (inter_mode == AVC_INTER_16X8) {
mv_ptr[2] = mv_ptr[0];
mv_ptr[3] = mv_ptr[1];
mv_ptr[4] = mv_ptr[16];
@@ -1352,7 +1354,7 @@ gen9_hcpe_hevc_fill_indirect_cu_inter(VADriverContextP
ctx,
cu_size = 1;
tu_size = 0x55;
tu_count = 4;
-}else if((msg[0] & AVC_INTER_MODE_MASK) == AVC_INTER_8X8) {
+}else if(inter_mode == AVC_INTER_8X8) {
mv_ptr[0] = mv_ptr[index * 8 + 0 ];
mv_ptr[1] = mv_ptr[index * 8 + 1 ];
mv_ptr[2] = mv_ptr[index * 8 + 0 ];
@@ -1592,8 +1594,9 @@ gen9_hcpe_hevc_pipeline_slice_programing(VADriverContextP
ctx,
int num_mb_in_ctb = ctb_width_in_mb * ctb_width_in_mb;
int i_ctb, ctb_x, ctb_y;
unsigned int split_coding_unit_flag = 0;
-int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
+int width_in_mbs = (pSequenceParameter->pic_width_in_luma_samples + 15) /
16;
int row_pad_flag = (pSequenceParameter->pic_height_in_luma_samples %
ctb_size)> 0 ? 1:0;
+int col_pad_flag = (pSequenceParameter->pic_width_in_luma_samples %
ctb_size)> 0 ? 1:0;
int is_intra = (slice_type == HEVC_SLICE_I);
unsigned int *msg = NULL;
@@ -1655,25 +1658,26 @@
gen9_hcpe_hevc_pipeline_slice_programing(VADriverContextP ctx,
for (i_ctb = pSliceParameter->slice_segment_address;i_ctb <
pSliceParameter->slice_segment_address + pSliceParameter->num_ctu_in_slice;
i_ctb++) {
int last_ctb = (i_ctb == (pSliceParameter->slice_segment_address +
pSliceParameter->num_ctu_in_slice - 1));
-int ctb_height_in_mb = ctb_width_in_mb;
+int ctb_height_in_mb_internal = ctb_width_in_mb;
+int ctb_width_in_mb_internal = ctb_width_in_mb;
ctb_x = i_ctb % width_in_ctb;
ctb_y = i_ctb / width_in_ctb;
-if(ctb_y == (height_in_ctb - 1) && row_pad_flag) ctb_height_in_mb = 1;
+if(ctb_y == (height_in_ctb - 1) && row_pad_flag)
ctb_height_in_mb_internal = 1;
+if(ctb_x == (width_in_ctb - 1) && col_pad_flag)
ctb_width_in_mb_internal = 1;
mb_x = 0;
mb_y = 0;
-macroblock_address = (i_ctb - ctb_x) * num_mb_in_ctb + ctb_x *
ctb_width_in_mb;
+macroblock_address = ctb_y * width_in_mbs * ctb_width_in_mb + ctb_x *
ctb_width_in_mb;
split_coding_unit_flag = ((ctb_width_in_mb == 2) ?
HEVC_SPLIT_CU_FLAG_32_32 : HEVC_SPLIT_CU_FLAG_16_16);
cu_count = 1;
cu_index = 0;
mb_addr = 0;
msg = NULL;
-for (mb_y = 0; mb_y < ctb_height_in_mb; mb_y++)
+for (mb_y = 0; mb_y < ctb_height_in_mb_internal; mb_y++)
{
mb_addr = macroblock_address + mb_y * width_in_mbs ;
-for (mb_x = 0; mb_x < ctb_width_in_mb; mb_x++)
+for (mb_x = 0; mb_x < ctb_width_in_mb_internal; mb_x++)
{
-split_coding_unit_flag = ((ctb_width_in_mb == 2) ?
HEVC_SPLIT_CU_FLAG_32_32 : HEVC_SPLIT_CU_FLAG_16_16);
/* get the mb info from the vme out */
msg = (unsigned int *)(msg_ptr + mb_addr *
vme_context->vme_output.size_block);
--
1
Re: [Libva] [PATCH] HEVC: Fix the Wrong slice type usage
Haihao,
Yes, you are right. I make a mistake. Here I treat one forward B frame as the P
frame to match the test tool.
Thanks,
Pengfei
-Original Message-
From: Xiang, Haihao
Sent: Tuesday, June 2, 2015 1:29 PM
To: Qu, Pengfei
Cc: Balachandran, Sreerenj; libva@lists.freedesktop.org
Subject: Re: [Libva] [PATCH] HEVC: Fix the Wrong slice type usage
Hi Sree, Pengfei,
The vme_state_message[] for H.264 P slice should be used for HEVC P slice, so I
think Sree's original patch is right.
Thanks
Haihao
> It is OK to me.
>
> Thanks,
> Pengfei
> -Original Message-
> From: Libva [mailto:libva-boun...@lists.freedesktop.org] On Behalf Of
> sreerenj.balachand...@intel.com
> Sent: Friday, May 29, 2015 11:27 AM
> To: libva@lists.freedesktop.org
> Subject: [Libva] [PATCH] HEVC: Fix the Wrong slice type usage
>
> From: Sreerenj Balachandran
>
> Don't mix the slice_type values of h264 and h265.
>
> The SLICE_TYPE values of H264 and HEVC are different.
> H264: Bslice_type = 1, Pslice_type = 0
> HEVC: Bslice_type = 0, Pslice_type = 1
>
> Signed-off-by: Sreerenj Balachandran
> ---
> src/gen6_mfc_common.c| 1 +
> src/gen9_vme.c | 12 ++--
> src/i965_encoder_utils.c | 16
> 3 files changed, 15 insertions(+), 14 deletions(-)
>
> diff --git a/src/gen6_mfc_common.c b/src/gen6_mfc_common.c index
> 3b3d0e7..37a355b 100644
> --- a/src/gen6_mfc_common.c
> +++ b/src/gen6_mfc_common.c
> @@ -1864,6 +1864,7 @@ void intel_vme_hevc_update_mbmv_cost(VADriverContextP
> ctx,
> m_costf = lambda * 3.5;
> m_cost = m_costf;
> vme_state_message[MODE_INTRA_NONPRED] =
> intel_format_lutvalue(m_cost, 0x6f);
> +/* Use SLICE_TYPE_P instead of HEVC_SLICE_P since we use AVC
> + VME hardware */
> if (slice_type == SLICE_TYPE_P) {
> m_costf = lambda * 2.5;
> m_cost = m_costf;
> diff --git a/src/gen9_vme.c b/src/gen9_vme.c index 39ac180..b28470b
> 100644
> --- a/src/gen9_vme.c
> +++ b/src/gen9_vme.c
> @@ -1334,7 +1334,7 @@ gen9_vme_hevc_output_buffer_setup(VADriverContextP ctx,
> struct gen6_vme_context *vme_context = encoder_context->vme_context;
> VAEncSequenceParameterBufferHEVC *pSequenceParameter =
> (VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
> VAEncSliceParameterBufferHEVC *pSliceParameter =
> (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[0]->buffer;
> -int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
> +int is_intra = pSliceParameter->slice_type == HEVC_SLICE_I;
> int width_in_mbs = (pSequenceParameter->pic_width_in_luma_samples +
> 15)/16;
> int height_in_mbs =
> (pSequenceParameter->pic_height_in_luma_samples + 15)/16;
>
> @@ -1405,12 +1405,12 @@ gen9_vme_hevc_surface_setup(VADriverContextP ctx,
> int slice_type;
>
> slice_type = slice_param->slice_type;
> -assert(slice_type != SLICE_TYPE_I && slice_type != SLICE_TYPE_SI);
> +assert(slice_type != HEVC_SLICE_I);
>
> /* to do HEVC */
> intel_hevc_vme_reference_state(ctx, encode_state,
> encoder_context, 0, 1, gen9_vme_source_surface_state);
>
> -if (slice_type == SLICE_TYPE_B)
> +if (slice_type == HEVC_SLICE_B)
> intel_hevc_vme_reference_state(ctx, encode_state,
> encoder_context, 1, 2, gen9_vme_source_surface_state);
> }
>
> @@ -1669,9 +1669,9 @@ static void
> gen9_vme_hevc_pipeline_programing(VADriverContextP ctx,
> }
> }
>
> -if (pSliceParameter->slice_type == SLICE_TYPE_I) {
> +if (pSliceParameter->slice_type == HEVC_SLICE_I) {
> kernel_shader = VME_INTRA_SHADER;
> -} else if (pSliceParameter->slice_type == SLICE_TYPE_P) {
> +} else if (pSliceParameter->slice_type == HEVC_SLICE_P) {
> kernel_shader = VME_INTER_SHADER;
> } else {
> kernel_shader = VME_BINTER_SHADER; @@ -1715,7 +1715,7 @@ static
> VAStatus gen9_vme_hevc_prepare(VADriverContextP ctx, {
> VAStatus vaStatus = VA_STATUS_SUCCESS;
> VAEncSliceParameterBufferHEVC *pSliceParameter =
> (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[0]->buffer;
> -int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
> +int is_intra = pSliceParameter->slice_type == HEVC_SLICE_I;
> VAEncSequenceParameterBufferHEVC *pSequenceParameter =
> (VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
> struct gen6_vme_context *vme_context =
> encoder_context->vme_context;
>
> diff --git a/src/i965_encoder_utils.c b/
Re: [Libva] [PATCH] HEVC: Fix the Wrong slice type usage
It is OK to me.
Thanks,
Pengfei
-Original Message-
From: Libva [mailto:libva-boun...@lists.freedesktop.org] On Behalf Of
sreerenj.balachand...@intel.com
Sent: Friday, May 29, 2015 11:27 AM
To: libva@lists.freedesktop.org
Subject: [Libva] [PATCH] HEVC: Fix the Wrong slice type usage
From: Sreerenj Balachandran
Don't mix the slice_type values of h264 and h265.
The SLICE_TYPE values of H264 and HEVC are different.
H264: Bslice_type = 1, Pslice_type = 0
HEVC: Bslice_type = 0, Pslice_type = 1
Signed-off-by: Sreerenj Balachandran
---
src/gen6_mfc_common.c| 1 +
src/gen9_vme.c | 12 ++--
src/i965_encoder_utils.c | 16
3 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/src/gen6_mfc_common.c b/src/gen6_mfc_common.c index
3b3d0e7..37a355b 100644
--- a/src/gen6_mfc_common.c
+++ b/src/gen6_mfc_common.c
@@ -1864,6 +1864,7 @@ void intel_vme_hevc_update_mbmv_cost(VADriverContextP ctx,
m_costf = lambda * 3.5;
m_cost = m_costf;
vme_state_message[MODE_INTRA_NONPRED] = intel_format_lutvalue(m_cost,
0x6f);
+/* Use SLICE_TYPE_P instead of HEVC_SLICE_P since we use AVC
+ VME hardware */
if (slice_type == SLICE_TYPE_P) {
m_costf = lambda * 2.5;
m_cost = m_costf;
diff --git a/src/gen9_vme.c b/src/gen9_vme.c index 39ac180..b28470b 100644
--- a/src/gen9_vme.c
+++ b/src/gen9_vme.c
@@ -1334,7 +1334,7 @@ gen9_vme_hevc_output_buffer_setup(VADriverContextP ctx,
struct gen6_vme_context *vme_context = encoder_context->vme_context;
VAEncSequenceParameterBufferHEVC *pSequenceParameter =
(VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
VAEncSliceParameterBufferHEVC *pSliceParameter =
(VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[0]->buffer;
-int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
+int is_intra = pSliceParameter->slice_type == HEVC_SLICE_I;
int width_in_mbs = (pSequenceParameter->pic_width_in_luma_samples + 15)/16;
int height_in_mbs = (pSequenceParameter->pic_height_in_luma_samples +
15)/16;
@@ -1405,12 +1405,12 @@ gen9_vme_hevc_surface_setup(VADriverContextP ctx,
int slice_type;
slice_type = slice_param->slice_type;
-assert(slice_type != SLICE_TYPE_I && slice_type != SLICE_TYPE_SI);
+assert(slice_type != HEVC_SLICE_I);
/* to do HEVC */
intel_hevc_vme_reference_state(ctx, encode_state, encoder_context, 0,
1, gen9_vme_source_surface_state);
-if (slice_type == SLICE_TYPE_B)
+if (slice_type == HEVC_SLICE_B)
intel_hevc_vme_reference_state(ctx, encode_state, encoder_context,
1, 2, gen9_vme_source_surface_state);
}
@@ -1669,9 +1669,9 @@ static void
gen9_vme_hevc_pipeline_programing(VADriverContextP ctx,
}
}
-if (pSliceParameter->slice_type == SLICE_TYPE_I) {
+if (pSliceParameter->slice_type == HEVC_SLICE_I) {
kernel_shader = VME_INTRA_SHADER;
-} else if (pSliceParameter->slice_type == SLICE_TYPE_P) {
+} else if (pSliceParameter->slice_type == HEVC_SLICE_P) {
kernel_shader = VME_INTER_SHADER;
} else {
kernel_shader = VME_BINTER_SHADER; @@ -1715,7 +1715,7 @@ static
VAStatus gen9_vme_hevc_prepare(VADriverContextP ctx, {
VAStatus vaStatus = VA_STATUS_SUCCESS;
VAEncSliceParameterBufferHEVC *pSliceParameter =
(VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[0]->buffer;
-int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
+int is_intra = pSliceParameter->slice_type == HEVC_SLICE_I;
VAEncSequenceParameterBufferHEVC *pSequenceParameter =
(VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
struct gen6_vme_context *vme_context = encoder_context->vme_context;
diff --git a/src/i965_encoder_utils.c b/src/i965_encoder_utils.c index
08b38a2..8237598 100644
--- a/src/i965_encoder_utils.c
+++ b/src/i965_encoder_utils.c
@@ -891,20 +891,20 @@ void hevc_short_term_ref_pic_set(avc_bitstream
*bs,VAEncSliceParameterBufferHEVC
hevc_rps.inter_ref_pic_set_prediction_flag = 0;
/* s0: between I and P/B; s1 : between P and B */
-hevc_rps.num_negative_pics =
(slice_param->slice_type!=SLICE_TYPE_I) ? 1 : 0;
-hevc_rps.num_positive_pics =
(slice_param->slice_type==SLICE_TYPE_B) ? 1 : 0;
+hevc_rps.num_negative_pics =
(slice_param->slice_type!=HEVC_SLICE_I) ? 1 : 0;
+hevc_rps.num_positive_pics =
(slice_param->slice_type==HEVC_SLICE_B) ? 1 : 0;
hevc_rps.delta_poc_s0_minus1[0] = 0;
hevc_rps.used_by_curr_pic_s0_flag[0] = 0;
hevc_rps.delta_poc_s1_minus1[0] = 0;
hevc_rps.used_by_curr_pic_s1_flag[0] = 0;
if(slice_param->num_ref_idx_l0_active_minus1==0 )
{
-hevc_rps.delta_poc_s0_minus1[0] =
(slice_param->slice_type==SLICE_TYPE_I) ? 0 : ( curPicOrderCnt -
Re: [Libva] [PATCH 1/3] HEVC: Fix the Wrong slice type usage
See comments inline.
-Original Message-
From: Libva [mailto:libva-boun...@lists.freedesktop.org] On Behalf Of
sreerenj.balachand...@intel.com
Sent: Friday, May 22, 2015 9:46 AM
To: libva@lists.freedesktop.org
Subject: [Libva] [PATCH 1/3] HEVC: Fix the Wrong slice type usage
From: Sreerenj Balachandran
Don't mix the slice_type values of h264 and h265.
The SLICE_TYPE values of H264 and HEVC are different.
H264: Bslice_type = 1, Pslice_type = 0
HEVC: Bslice_type = 0, Pslice_type = 1
---
src/gen6_mfc_common.c| 4 ++--
src/gen9_vme.c | 12 ++--
src/i965_encoder_utils.c | 16
3 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/src/gen6_mfc_common.c b/src/gen6_mfc_common.c index
6ae29f3..2babb99 100644
--- a/src/gen6_mfc_common.c
+++ b/src/gen6_mfc_common.c
@@ -1811,7 +1811,7 @@ void intel_vme_hevc_update_mbmv_cost(VADriverContextP ctx,
assert(qp <= QP_MAX);
lambda = intel_lambda_qp(qp);
-if (slice_type == SLICE_TYPE_I) {
+if (slice_type == HEVC_SLICE_I) {
vme_state_message[MODE_INTRA_16X16] = 0;
m_cost = lambda * 4;
vme_state_message[MODE_INTRA_8X8] = intel_format_lutvalue(m_cost,
0x8f); @@ -1857,7 +1857,7 @@ void
intel_vme_hevc_update_mbmv_cost(VADriverContextP ctx,
m_costf = lambda * 3.5;
m_cost = m_costf;
vme_state_message[MODE_INTRA_NONPRED] = intel_format_lutvalue(m_cost,
0x6f);
-if (slice_type == SLICE_TYPE_P) {
+if (slice_type == HEVC_SLICE_P) {
m_costf = lambda * 2.5;
m_cost = m_costf;
vme_state_message[MODE_INTER_16X16] =
intel_format_lutvalue(m_cost, 0x8f); diff --git a/src/gen9_vme.c
b/src/gen9_vme.c index 39ac180..b28470b 100644
[Pengfei] here we should still use SLICE_TYPE_I /SLICE_TYPE_P. As we use the
AVC VME HW. Also this maybe the reason you see B size bigger than P.
--- a/src/gen9_vme.c
+++ b/src/gen9_vme.c
@@ -1334,7 +1334,7 @@ gen9_vme_hevc_output_buffer_setup(VADriverContextP ctx,
struct gen6_vme_context *vme_context = encoder_context->vme_context;
VAEncSequenceParameterBufferHEVC *pSequenceParameter =
(VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
VAEncSliceParameterBufferHEVC *pSliceParameter =
(VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[0]->buffer;
-int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
+int is_intra = pSliceParameter->slice_type == HEVC_SLICE_I;
int width_in_mbs = (pSequenceParameter->pic_width_in_luma_samples + 15)/16;
int height_in_mbs = (pSequenceParameter->pic_height_in_luma_samples +
15)/16;
@@ -1405,12 +1405,12 @@ gen9_vme_hevc_surface_setup(VADriverContextP ctx,
int slice_type;
slice_type = slice_param->slice_type;
-assert(slice_type != SLICE_TYPE_I && slice_type != SLICE_TYPE_SI);
+assert(slice_type != HEVC_SLICE_I);
/* to do HEVC */
intel_hevc_vme_reference_state(ctx, encode_state, encoder_context, 0,
1, gen9_vme_source_surface_state);
-if (slice_type == SLICE_TYPE_B)
+if (slice_type == HEVC_SLICE_B)
intel_hevc_vme_reference_state(ctx, encode_state, encoder_context,
1, 2, gen9_vme_source_surface_state);
}
@@ -1669,9 +1669,9 @@ static void
gen9_vme_hevc_pipeline_programing(VADriverContextP ctx,
}
}
-if (pSliceParameter->slice_type == SLICE_TYPE_I) {
+if (pSliceParameter->slice_type == HEVC_SLICE_I) {
kernel_shader = VME_INTRA_SHADER;
-} else if (pSliceParameter->slice_type == SLICE_TYPE_P) {
+} else if (pSliceParameter->slice_type == HEVC_SLICE_P) {
kernel_shader = VME_INTER_SHADER;
} else {
kernel_shader = VME_BINTER_SHADER; @@ -1715,7 +1715,7 @@ static
VAStatus gen9_vme_hevc_prepare(VADriverContextP ctx, {
VAStatus vaStatus = VA_STATUS_SUCCESS;
VAEncSliceParameterBufferHEVC *pSliceParameter =
(VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[0]->buffer;
-int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
+int is_intra = pSliceParameter->slice_type == HEVC_SLICE_I;
VAEncSequenceParameterBufferHEVC *pSequenceParameter =
(VAEncSequenceParameterBufferHEVC *)encode_state->seq_param_ext->buffer;
struct gen6_vme_context *vme_context = encoder_context->vme_context;
diff --git a/src/i965_encoder_utils.c b/src/i965_encoder_utils.c index
6638491..9c9619c 100644
--- a/src/i965_encoder_utils.c
+++ b/src/i965_encoder_utils.c
@@ -902,20 +902,20 @@ void hevc_short_term_ref_pic_set(avc_bitstream
*bs,VAEncSliceParameterBufferHEVC
hevc_rps.inter_ref_pic_set_prediction_flag = 0;
/* s0: between I and P/B; s1 : between P and B */
-hevc_rps.num_negative_pics =
(slice_param->slice_type!=SLICE_TYPE_I) ? 1 : 0;
-hevc_rps.num_positive_pics =
(slice_param->slice_type==SLICE_TYPE_B) ? 1 : 0;
+hevc_rps.num_negative_pics
[Libva] [PATCH] HEVC enc:Added 4K&2K support; Added Profile&Level 5.1 above
Signed-off-by: Qu,Pengfei
---
src/gen9_mfc_hevc.c | 317 +++-
1 file changed, 164 insertions(+), 153 deletions(-)
diff --git a/src/gen9_mfc_hevc.c b/src/gen9_mfc_hevc.c
index 927e36b..94eb38a 100644
--- a/src/gen9_mfc_hevc.c
+++ b/src/gen9_mfc_hevc.c
@@ -1146,20 +1146,18 @@ gen9_hcpe_hevc_fill_indirect_cu_intra(VADriverContextP
ctx,
int qp, unsigned int *msg,
int ctb_x, int ctb_y,
int mb_x, int mb_y,
- int ctb_width_in_mb, int width_in_ctb,
int num_cu_record, int slice_type)
+ int ctb_width_in_mb, int width_in_ctb,
int num_cu_record, int slice_type,int cu_index,int index)
{
/* here cu == mb, so we use mb address as the cu address */
/* to fill the indirect cu by the vme out */
-static int mb_addr_raster_to_zigzag_64[4][4] = { {0, 1, 4, 5}, {2, 3, 6,
7}, {8, 9, 12, 13}, {10, 11, 14, 15} };
-static int mb_addr_raster_to_zigzag_32[2][2] = { {0, 1}, {2, 3 } };
static int intra_mode_8x8_avc2hevc[9] = {26, 10, 1, 34, 18, 24, 13, 28, 8};
static int intra_mode_16x16_avc2hevc[4] = {26, 10, 1, 34};
struct gen9_hcpe_context *mfc_context = encoder_context->mfc_context;
unsigned char * cu_record_ptr = NULL;
unsigned int * cu_msg = NULL;
int ctb_address = (ctb_y * width_in_ctb + ctb_x) * num_cu_record;
-int mb_address_in_ctb = ((ctb_width_in_mb == 4) ?
mb_addr_raster_to_zigzag_64[mb_x][mb_y] : ((ctb_width_in_mb == 2) ?
mb_addr_raster_to_zigzag_32[mb_x][mb_y] : 0));
-int cu_address = (ctb_address + mb_address_in_ctb) * 16 * 4;
+int mb_address_in_ctb = 0;
+int cu_address = (ctb_address + mb_address_in_ctb + cu_index) * 16 * 4;
int zero = 0;
int is_inter = 0;
int intraMbMode = 0;
@@ -1167,6 +1165,9 @@ gen9_hcpe_hevc_fill_indirect_cu_intra(VADriverContextP
ctx,
int intraMode[4];
int inerpred_idc = 0;
int intra_chroma_mode = 5;
+int cu_size = 1;
+int tu_size = 0x55;
+int tu_count = 4;
if (!is_inter) inerpred_idc = 0xff;
@@ -1176,29 +1177,37 @@ gen9_hcpe_hevc_fill_indirect_cu_intra(VADriverContextP
ctx,
if (intraMbMode == AVC_INTRA_16X16) {
cu_part_mode = 0; //2Nx2N
intra_chroma_mode = 5;
+cu_size = 1;
+tu_size = 0x55;
+tu_count = 4;
intraMode[0] = intra_mode_16x16_avc2hevc[msg[1] & 0xf];
intraMode[1] = intra_mode_16x16_avc2hevc[msg[1] & 0xf];
intraMode[2] = intra_mode_16x16_avc2hevc[msg[1] & 0xf];
intraMode[3] = intra_mode_16x16_avc2hevc[msg[1] & 0xf];
} else if (intraMbMode == AVC_INTRA_8X8) {
-cu_part_mode = 3; //NxN
-intra_chroma_mode = 0;
-intraMode[0] = intra_mode_8x8_avc2hevc[msg[1] & 0xf];
-intraMode[1] = intra_mode_8x8_avc2hevc[(msg[1] >> 4) & 0xf];
-intraMode[2] = intra_mode_8x8_avc2hevc[(msg[1] >> 8) & 0xf];
-intraMode[3] = intra_mode_8x8_avc2hevc[(msg[1] >> 12) & 0xf];
+cu_part_mode = 0; //2Nx2N
+intra_chroma_mode = 5;
+cu_size = 0;
+tu_size = 0;
+tu_count = 4;
+intraMode[0] = intra_mode_8x8_avc2hevc[msg[1] >> (index << 2) & 0xf];
+intraMode[1] = intra_mode_8x8_avc2hevc[msg[1] >> (index << 2) & 0xf];
+intraMode[2] = intra_mode_8x8_avc2hevc[msg[1] >> (index << 2) & 0xf];
+intraMode[3] = intra_mode_8x8_avc2hevc[msg[1] >> (index << 2) & 0xf];
} else { // for 4x4 to use 8x8 replace
cu_part_mode = 3; //NxN
intra_chroma_mode = 0;
-intraMode[0] = intra_mode_8x8_avc2hevc[0];
-intraMode[1] = intra_mode_8x8_avc2hevc[0];
-intraMode[2] = intra_mode_8x8_avc2hevc[0];
-intraMode[3] = intra_mode_8x8_avc2hevc[0];
+cu_size = 0;
+tu_size = 0;
+tu_count = 4;
+intraMode[0] = intra_mode_8x8_avc2hevc[msg[1] >> ((index << 4) + 0) &
0xf];
+intraMode[1] = intra_mode_8x8_avc2hevc[msg[1] >> ((index << 4) + 4) &
0xf];
+intraMode[2] = intra_mode_8x8_avc2hevc[msg[1] >> ((index << 4) + 8) &
0xf];
+intraMode[3] = intra_mode_8x8_avc2hevc[msg[1] >> ((index << 4) + 12) &
0xf];
}
-dri_bo_map(mfc_context->hcp_indirect_cu_object.bo , 1);
cu_record_ptr = (unsigned char
*)mfc_context->hcp_indirect_cu_object.bo->virtual;
/* get the mb info from the vme out */
cu_msg = (unsigned int *)(cu_record_ptr + cu_address);
@@ -1212,7 +1221,7 @@ gen9_hcpe_hevc_fill_indirect_cu_intra(VADriverContextP
ctx,
cu_part_mode << 4 |/* cu_part_mode */
zero << 3 |/* cu_transquant_bypass_flag */
is_inter
[Libva] [PATCH] HEVC ENC: 4K&2K and 5.1 profile level support
added feature as the following: 1. 4K&2K resolution support 2. Profile&Level 5.1 above support Qu,Pengfei (1): HEVC enc:Added 4K&2K support; Added Profile&Level 5.1 above src/gen9_mfc_hevc.c | 317 +++- 1 file changed, 164 insertions(+), 153 deletions(-) -- 1.9.1 ___ Libva mailing list Libva@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/libva
[Libva] [PATCH] Disable the context check to avoid JPEG ENC failed
https://bugs.freedesktop.org/show_bug.cgi?id=88728
Signed-off-by: Qu,Pengfei
---
src/i965_drv_video.c | 32 +---
1 file changed, 1 insertion(+), 31 deletions(-)
diff --git a/src/i965_drv_video.c b/src/i965_drv_video.c
index 7039dd3..d87a232 100644
--- a/src/i965_drv_video.c
+++ b/src/i965_drv_video.c
@@ -1999,21 +1999,8 @@ i965_create_buffer_internal(VADriverContextP ctx,
struct object_buffer *obj_buffer = NULL;
struct buffer_store *buffer_store = NULL;
int bufferID;
-struct object_context *obj_context = NULL;
-struct object_config *obj_config = NULL;
VAStatus vaStatus = VA_STATUS_ERROR_UNKNOWN;
-if (i965->current_context_id == VA_INVALID_ID)
-return vaStatus;
-
-obj_context = CONTEXT(i965->current_context_id);
-
-if (!obj_context)
-return vaStatus;
-
-obj_config = obj_context->obj_config;
-assert(obj_config);
-
/* Validate type */
switch (type) {
case VAPictureParameterBufferType:
@@ -2086,11 +2073,7 @@ i965_create_buffer_internal(VADriverContextP ctx,
struct i965_coded_buffer_segment *coded_buffer_segment;
dri_bo_map(buffer_store->bo, 1);
-if(obj_config->profile == VAProfileHEVCMain){
-coded_buffer_segment = (struct i965_coded_buffer_segment
*)(buffer_store->bo->virtual + ALIGN(size - 0x1000, 0x1000));
-}else {
-coded_buffer_segment = (struct i965_coded_buffer_segment
*)buffer_store->bo->virtual;
-}
+coded_buffer_segment = (struct i965_coded_buffer_segment
*)buffer_store->bo->virtual;
coded_buffer_segment->base.size = size -
I965_CODEDBUFFER_HEADER_SIZE;
coded_buffer_segment->base.bit_offset = 0;
coded_buffer_segment->base.status = 0;
@@ -2168,22 +2151,9 @@ i965_MapBuffer(VADriverContextP ctx,
void **pbuf) /* out */
{
struct i965_driver_data *i965 = i965_driver_data(ctx);
-struct object_context *obj_context = NULL;
-struct object_config *obj_config = NULL;
struct object_buffer *obj_buffer = BUFFER(buf_id);
VAStatus vaStatus = VA_STATUS_ERROR_UNKNOWN;
-if (i965->current_context_id == VA_INVALID_ID)
-return vaStatus;
-
-obj_context = CONTEXT(i965->current_context_id);
-
-if (!obj_context)
-return vaStatus;
-
-obj_config = obj_context->obj_config;
-assert(obj_config);
-
ASSERT_RET(obj_buffer && obj_buffer->buffer_store,
VA_STATUS_ERROR_INVALID_BUFFER);
ASSERT_RET(obj_buffer->buffer_store->bo ||
obj_buffer->buffer_store->buffer, VA_STATUS_ERROR_INVALID_BUFFER);
ASSERT_RET(!(obj_buffer->buffer_store->bo &&
obj_buffer->buffer_store->buffer), VA_STATUS_ERROR_INVALID_BUFFER);
--
1.9.1
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[Libva] [PATCH] FIXED: remove context check in i965_create_buffer_internal to avoid the JPEG failed BUG ID 88728
Signed-off-by: Qu,Pengfei
---
src/i965_drv_video.c | 33 +
1 file changed, 1 insertion(+), 32 deletions(-)
diff --git a/src/i965_drv_video.c b/src/i965_drv_video.c
index ff1ab62..8a1370f 100644
--- a/src/i965_drv_video.c
+++ b/src/i965_drv_video.c
@@ -1994,20 +1994,6 @@ i965_create_buffer_internal(VADriverContextP ctx,
struct object_buffer *obj_buffer = NULL;
struct buffer_store *buffer_store = NULL;
int bufferID;
-struct object_context *obj_context = NULL;
-struct object_config *obj_config = NULL;
-VAStatus vaStatus = VA_STATUS_ERROR_UNKNOWN;
-
-if (i965->current_context_id == VA_INVALID_ID)
-return vaStatus;
-
-obj_context = CONTEXT(i965->current_context_id);
-
-if (!obj_context)
-return vaStatus;
-
-obj_config = obj_context->obj_config;
-assert(obj_config);
/* Validate type */
switch (type) {
@@ -2081,11 +2067,7 @@ i965_create_buffer_internal(VADriverContextP ctx,
struct i965_coded_buffer_segment *coded_buffer_segment;
dri_bo_map(buffer_store->bo, 1);
-if(obj_config->profile == VAProfileHEVCMain){
-coded_buffer_segment = (struct i965_coded_buffer_segment
*)(buffer_store->bo->virtual + ALIGN(size - 0x1000, 0x1000));
-}else {
-coded_buffer_segment = (struct i965_coded_buffer_segment
*)buffer_store->bo->virtual;
-}
+coded_buffer_segment = (struct i965_coded_buffer_segment
*)buffer_store->bo->virtual;
coded_buffer_segment->base.size = size -
I965_CODEDBUFFER_HEADER_SIZE;
coded_buffer_segment->base.bit_offset = 0;
coded_buffer_segment->base.status = 0;
@@ -2163,22 +2145,9 @@ i965_MapBuffer(VADriverContextP ctx,
void **pbuf) /* out */
{
struct i965_driver_data *i965 = i965_driver_data(ctx);
-struct object_context *obj_context = NULL;
-struct object_config *obj_config = NULL;
struct object_buffer *obj_buffer = BUFFER(buf_id);
VAStatus vaStatus = VA_STATUS_ERROR_UNKNOWN;
-if (i965->current_context_id == VA_INVALID_ID)
-return vaStatus;
-
-obj_context = CONTEXT(i965->current_context_id);
-
-if (!obj_context)
-return vaStatus;
-
-obj_config = obj_context->obj_config;
-assert(obj_config);
-
ASSERT_RET(obj_buffer && obj_buffer->buffer_store,
VA_STATUS_ERROR_INVALID_BUFFER);
ASSERT_RET(obj_buffer->buffer_store->bo ||
obj_buffer->buffer_store->buffer, VA_STATUS_ERROR_INVALID_BUFFER);
ASSERT_RET(!(obj_buffer->buffer_store->bo &&
obj_buffer->buffer_store->buffer), VA_STATUS_ERROR_INVALID_BUFFER);
--
1.9.1
___
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[Libva] [PATCH V5 4/7] HEVC ENC:Added VME pipeline
Signed-off-by: Qu,Pengfei
---
src/gen6_mfc_common.c | 222 +++
src/gen6_vme.h| 19 ++
src/gen9_vme.c| 484 ++
3 files changed, 725 insertions(+)
diff --git a/src/gen6_mfc_common.c b/src/gen6_mfc_common.c
index fe41dac..6a5f720 100644
--- a/src/gen6_mfc_common.c
+++ b/src/gen6_mfc_common.c
@@ -1652,3 +1652,225 @@ void
intel_avc_slice_insert_packed_data(VADriverContextP ctx,
return;
}
+/* HEVC */
+static int
+hevc_temporal_find_surface(VAPictureHEVC *curr_pic,
+ VAPictureHEVC *ref_list,
+ int num_pictures,
+ int dir)
+{
+int i, found = -1, min = 0x7FFF;
+
+for (i = 0; i < num_pictures; i++) {
+int tmp;
+
+if ((ref_list[i].flags & VA_PICTURE_HEVC_INVALID) ||
+(ref_list[i].picture_id == VA_INVALID_SURFACE))
+break;
+
+tmp = curr_pic->pic_order_cnt - ref_list[i].pic_order_cnt;
+
+if (dir)
+tmp = -tmp;
+
+if (tmp > 0 && tmp < min) {
+min = tmp;
+found = i;
+}
+}
+
+return found;
+}
+void
+intel_hevc_vme_reference_state(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context,
+ int list_index,
+ int surface_index,
+ void (* vme_source_surface_state)(
+ VADriverContextP ctx,
+ int index,
+ struct object_surface *obj_surface,
+ struct intel_encoder_context
*encoder_context))
+{
+struct gen6_vme_context *vme_context = encoder_context->vme_context;
+struct object_surface *obj_surface = NULL;
+struct i965_driver_data *i965 = i965_driver_data(ctx);
+VASurfaceID ref_surface_id;
+VAEncPictureParameterBufferHEVC *pic_param =
(VAEncPictureParameterBufferHEVC *)encode_state->pic_param_ext->buffer;
+VAEncSliceParameterBufferHEVC *slice_param =
(VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[0]->buffer;
+int max_num_references;
+VAPictureHEVC *curr_pic;
+VAPictureHEVC *ref_list;
+int ref_idx;
+
+if (list_index == 0) {
+max_num_references = pic_param->num_ref_idx_l0_default_active_minus1 +
1;
+ref_list = slice_param->ref_pic_list0;
+} else {
+max_num_references = pic_param->num_ref_idx_l1_default_active_minus1 +
1;
+ref_list = slice_param->ref_pic_list1;
+}
+
+if (max_num_references == 1) {
+if (list_index == 0) {
+ref_surface_id = slice_param->ref_pic_list0[0].picture_id;
+vme_context->used_references[0] = &slice_param->ref_pic_list0[0];
+} else {
+ref_surface_id = slice_param->ref_pic_list1[0].picture_id;
+vme_context->used_references[1] = &slice_param->ref_pic_list1[0];
+}
+
+if (ref_surface_id != VA_INVALID_SURFACE)
+obj_surface = SURFACE(ref_surface_id);
+
+if (!obj_surface ||
+!obj_surface->bo) {
+obj_surface = encode_state->reference_objects[list_index];
+vme_context->used_references[list_index] =
&pic_param->reference_frames[list_index];
+}
+
+ref_idx = 0;
+} else {
+curr_pic = &pic_param->decoded_curr_pic;
+
+/* select the reference frame in temporal space */
+ref_idx = hevc_temporal_find_surface(curr_pic, ref_list,
max_num_references, list_index == 1);
+ref_surface_id = ref_list[ref_idx].picture_id;
+
+if (ref_surface_id != VA_INVALID_SURFACE) /* otherwise warning later */
+obj_surface = SURFACE(ref_surface_id);
+
+vme_context->used_reference_objects[list_index] = obj_surface;
+vme_context->used_references[list_index] = &ref_list[ref_idx];
+}
+
+if (obj_surface &&
+obj_surface->bo) {
+assert(ref_idx >= 0);
+vme_context->used_reference_objects[list_index] = obj_surface;
+vme_source_surface_state(ctx, surface_index, obj_surface,
encoder_context);
+vme_context->ref_index_in_mb[list_index] = (ref_idx << 24 |
+ref_idx << 16 |
+ref_idx << 8 |
+ref_idx);
+} else {
+vme_context->used_reference_objects[list_index] = NULL;
+vme_context->used_references[list_index] = NULL;
+vme_context->ref_index_in_mb[list_index] = 0;
+}
+}
+
+void intel_vme_hevc_update_mbmv_cost(VADriverContextP ctx,
+ struct encode_state *encode_state,
+
[Libva] [PATCH V5 7/7] Just Style alignment
Signed-off-by: Qu,Pengfei
---
src/gen6_mfc_common.c | 464 -
src/gen9_vme.c | 444 +++---
src/i965_device_info.c | 16 +-
src/i965_drv_video.c | 32 ++--
4 files changed, 478 insertions(+), 478 deletions(-)
diff --git a/src/gen6_mfc_common.c b/src/gen6_mfc_common.c
index 6a5f720..cc1b0e6 100644
--- a/src/gen6_mfc_common.c
+++ b/src/gen6_mfc_common.c
@@ -631,8 +631,8 @@ VAStatus intel_mfc_avc_prepare(VADriverContextP ctx,
int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
if (IS_GEN6(i965->intel.device_info)) {
- /* On the SNB it should be fixed to 128 for the DMV buffer */
- width_in_mbs = 128;
+/* On the SNB it should be fixed to 128 for the DMV buffer */
+width_in_mbs = 128;
}
for (j = 0; j < encode_state->num_slice_params_ext && enable_avc_ildb ==
0; j++) {
@@ -735,7 +735,7 @@ VAStatus intel_mfc_avc_prepare(VADriverContextP ctx,
break;
}
}
-
+
mfc_context->uncompressed_picture_source.bo =
encode_state->input_yuv_object->bo;
dri_bo_reference(mfc_context->uncompressed_picture_source.bo);
@@ -807,7 +807,7 @@ int intel_format_lutvalue(int value, int max)
if (temp1 > temp2)
ret = max;
return ret;
-
+
}
@@ -842,40 +842,40 @@ void intel_vme_update_mbmv_cost(VADriverContextP ctx,
if (encoder_context->rate_control_mode == VA_RC_CQP)
- qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
+qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
else
- qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
-
+qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
+
if (vme_state_message == NULL)
- return;
-
+return;
+
assert(qp <= QP_MAX);
lambda = intel_lambda_qp(qp);
if (slice_type == SLICE_TYPE_I) {
- vme_state_message[MODE_INTRA_16X16] = 0;
- m_cost = lambda * 4;
- vme_state_message[MODE_INTRA_8X8] = intel_format_lutvalue(m_cost, 0x8f);
- m_cost = lambda * 16;
- vme_state_message[MODE_INTRA_4X4] = intel_format_lutvalue(m_cost, 0x8f);
- m_cost = lambda * 3;
- vme_state_message[MODE_INTRA_NONPRED] = intel_format_lutvalue(m_cost,
0x6f);
+vme_state_message[MODE_INTRA_16X16] = 0;
+m_cost = lambda * 4;
+vme_state_message[MODE_INTRA_8X8] = intel_format_lutvalue(m_cost,
0x8f);
+m_cost = lambda * 16;
+vme_state_message[MODE_INTRA_4X4] = intel_format_lutvalue(m_cost,
0x8f);
+m_cost = lambda * 3;
+vme_state_message[MODE_INTRA_NONPRED] = intel_format_lutvalue(m_cost,
0x6f);
} else {
- m_cost = 0;
- vme_state_message[MODE_INTER_MV0] = intel_format_lutvalue(m_cost, 0x6f);
- for (j = 1; j < 3; j++) {
+m_cost = 0;
+vme_state_message[MODE_INTER_MV0] = intel_format_lutvalue(m_cost,
0x6f);
+for (j = 1; j < 3; j++) {
m_costf = (log2f((float)(j + 1)) + 1.718f) * lambda;
m_cost = (int)m_costf;
vme_state_message[MODE_INTER_MV0 + j] =
intel_format_lutvalue(m_cost, 0x6f);
- }
- mv_count = 3;
- for (j = 4; j <= 64; j *= 2) {
+}
+mv_count = 3;
+for (j = 4; j <= 64; j *= 2) {
m_costf = (log2f((float)(j + 1)) + 1.718f) * lambda;
m_cost = (int)m_costf;
vme_state_message[MODE_INTER_MV0 + mv_count] =
intel_format_lutvalue(m_cost, 0x6f);
mv_count++;
- }
+}
- if (qp <= 25) {
+if (qp <= 25) {
vme_state_message[MODE_INTRA_16X16] = 0x4a;
vme_state_message[MODE_INTRA_8X8] = 0x4a;
vme_state_message[MODE_INTRA_4X4] = 0x4a;
@@ -887,17 +887,17 @@ void intel_vme_update_mbmv_cost(VADriverContextP ctx,
vme_state_message[MODE_INTER_4X4] = 0x4a;
vme_state_message[MODE_INTER_BWD] = 0x2a;
return;
- }
- m_costf = lambda * 10;
- vme_state_message[MODE_INTRA_16X16] = intel_format_lutvalue(m_cost,
0x8f);
- m_cost = lambda * 14;
- vme_state_message[MODE_INTRA_8X8] = intel_format_lutvalue(m_cost, 0x8f);
- m_cost = lambda * 24;
- vme_state_message[MODE_INTRA_4X4] = intel_format_lutvalue(m_cost, 0x8f);
- m_costf = lambda * 3.5;
- m_cost = m_costf;
- vme_state_message[MODE_INTRA_NONPRED] = intel_format_lutvalue(m_cost,
0x6f);
- if (slice_type == SLICE_TYPE_P) {
+}
+m_costf = lambda * 10;
+vme_state_message[MODE_INTRA_16X16] = intel_format_lutvalue(m_cost,
0x8f);
+m_cost = lambda * 14;
+vme_state_message[MODE_INTRA_8X8] = intel_format_lutvalue(m_cost,
0x8f);
+m_cost = lambda * 24;
+vme_state_message[MODE_INTRA_4X4] = intel_for
[Libva] [PATCH V5 5/7] HEVC ENC:Added pipeline init
Signed-off-by: Qu,Pengfei
---
src/i965_encoder.c | 74 +-
1 file changed, 73 insertions(+), 1 deletion(-)
diff --git a/src/i965_encoder.c b/src/i965_encoder.c
index d924f5a..c9ff2ec 100644
--- a/src/i965_encoder.c
+++ b/src/i965_encoder.c
@@ -39,10 +39,12 @@
#include "i965_encoder.h"
#include "gen6_vme.h"
#include "gen6_mfc.h"
+#include "gen9_mfc.h"
extern Bool gen6_mfc_context_init(VADriverContextP ctx, struct
intel_encoder_context *encoder_context);
extern Bool gen6_vme_context_init(VADriverContextP ctx, struct
intel_encoder_context *encoder_context);
extern Bool gen7_mfc_context_init(VADriverContextP ctx, struct
intel_encoder_context *encoder_context);
+extern Bool gen9_hcpe_context_init(VADriverContextP ctx, struct
intel_encoder_context *encoder_context);
static VAStatus
intel_encoder_check_yuv_surface(VADriverContextP ctx,
@@ -422,6 +424,63 @@ error:
}
static VAStatus
+intel_encoder_check_hevc_parameter(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context
*encoder_context)
+{
+struct i965_driver_data *i965 = i965_driver_data(ctx);
+struct object_surface *obj_surface;
+struct object_buffer *obj_buffer;
+VAEncPictureParameterBufferHEVC *pic_param =
(VAEncPictureParameterBufferHEVC *)encode_state->pic_param_ext->buffer;
+int i;
+
+assert(!(pic_param->decoded_curr_pic.flags & VA_PICTURE_HEVC_INVALID));
+
+if (pic_param->decoded_curr_pic.flags & VA_PICTURE_HEVC_INVALID)
+goto error;
+
+obj_surface = SURFACE(pic_param->decoded_curr_pic.picture_id);
+assert(obj_surface); /* It is possible the store buffer isn't allocated
yet */
+
+if (!obj_surface)
+goto error;
+
+encode_state->reconstructed_object = obj_surface;
+obj_buffer = BUFFER(pic_param->coded_buf);
+assert(obj_buffer && obj_buffer->buffer_store &&
obj_buffer->buffer_store->bo);
+
+if (!obj_buffer || !obj_buffer->buffer_store ||
!obj_buffer->buffer_store->bo)
+goto error;
+
+encode_state->coded_buf_object = obj_buffer;
+
+for (i = 0; i < 15; i++) {
+if (pic_param->reference_frames[i].flags & VA_PICTURE_HEVC_INVALID ||
+pic_param->reference_frames[i].picture_id == VA_INVALID_SURFACE)
+break;
+else {
+obj_surface = SURFACE(pic_param->reference_frames[i].picture_id);
+assert(obj_surface);
+
+if (!obj_surface)
+goto error;
+
+if (obj_surface->bo)
+encode_state->reference_objects[i] = obj_surface;
+else
+encode_state->reference_objects[i] = NULL; /* FIXME: Warning
or Error ??? */
+}
+}
+
+for ( ; i < 15; i++)
+encode_state->reference_objects[i] = NULL;
+
+return VA_STATUS_SUCCESS;
+
+error:
+return VA_STATUS_ERROR_INVALID_PARAMETER;
+}
+static VAStatus
intel_encoder_sanity_check_input(VADriverContextP ctx,
VAProfile profile,
struct encode_state *encode_state,
@@ -459,6 +518,13 @@ intel_encoder_sanity_check_input(VADriverContextP ctx,
break;
}
+case VAProfileHEVCMain: {
+vaStatus = intel_encoder_check_hevc_parameter(ctx, encode_state,
encoder_context);
+if (vaStatus != VA_STATUS_SUCCESS)
+goto out;
+vaStatus = intel_encoder_check_yuv_surface(ctx, profile, encode_state,
encoder_context);
+break;
+}
default:
vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
break;
@@ -554,6 +620,10 @@ intel_enc_hw_context_init(VADriverContextP ctx,
encoder_context->codec = CODEC_JPEG;
break;
+case VAProfileHEVCMain:
+encoder_context->codec = CODEC_HEVC;
+break;
+
default:
/* Never get here */
assert(0);
@@ -617,7 +687,9 @@ gen8_enc_hw_context_init(VADriverContextP ctx, struct
object_config *obj_config)
struct hw_context *
gen9_enc_hw_context_init(VADriverContextP ctx, struct object_config
*obj_config)
{
-if (obj_config->profile == VAProfileJPEGBaseline)
+if (obj_config->profile == VAProfileHEVCMain) {
+return intel_enc_hw_context_init(ctx, obj_config,
gen9_vme_context_init, gen9_hcpe_context_init);
+} else if (obj_config->profile == VAProfileJPEGBaseline)
return intel_enc_hw_context_init(ctx, obj_config,
gen8_vme_context_init, gen8_mfc_context_init);
else
return intel_enc_hw_context_init(ctx, obj_config,
gen9_vme_context_init, gen9_mfc_context_init);
--
1.9.1
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[Libva] [PATCH V5 6/7] HEVC ENC:Added HEVC support in API function
Signed-off-by: Qu,Pengfei
---
src/i965_device_info.c | 1 +
src/i965_drv_video.c | 112 -
2 files changed, 94 insertions(+), 19 deletions(-)
diff --git a/src/i965_device_info.c b/src/i965_device_info.c
index d03aceb..9ccc85e 100755
--- a/src/i965_device_info.c
+++ b/src/i965_device_info.c
@@ -347,6 +347,7 @@ static struct hw_codec_info skl_hw_codec_info = {
.has_blending = 1,
.has_h264_mvc_encoding = 1,
.has_hevc_decoding = 1,
+.has_hevc_encoding = 1,
.num_filters = 5,
.filters = {
diff --git a/src/i965_drv_video.c b/src/i965_drv_video.c
index 74895da..88738cb 100644
--- a/src/i965_drv_video.c
+++ b/src/i965_drv_video.c
@@ -1,5 +1,5 @@
/*
- * Copyright � 2009 Intel Corporation
+ * Copyright ?2009 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
@@ -104,6 +104,9 @@
#define HAS_HEVC_DECODING(ctx) ((ctx)->codec_info->has_hevc_decoding
&& \
(ctx)->intel.has_bsd)
+#define HAS_HEVC_ENCODING(ctx) ((ctx)->codec_info->has_hevc_encoding
&& \
+ (ctx)->intel.has_bsd)
+
static int get_sampling_from_fourcc(unsigned int fourcc);
/* Check whether we are rendering to X11 (VA/X11 or VA/GLX API) */
@@ -376,7 +379,10 @@ is_image_busy(struct i965_driver_data *i965, struct
object_image *obj_image)
}
#define I965_PACKED_HEADER_BASE 0
-#define I965_PACKED_MISC_HEADER_BASE3
+#define I965_SEQ_PACKED_HEADER_BASE 0
+#define I965_SEQ_PACKED_HEADER_END 2
+#define I965_PIC_PACKED_HEADER_BASE 2
+#define I965_PACKED_MISC_HEADER_BASE4
int
va_enc_packed_type_to_idx(int packed_type)
@@ -393,15 +399,15 @@ va_enc_packed_type_to_idx(int packed_type)
switch (packed_type) {
case VAEncPackedHeaderSequence:
-idx = I965_PACKED_HEADER_BASE + 0;
+idx = I965_SEQ_PACKED_HEADER_BASE + 0;
break;
case VAEncPackedHeaderPicture:
-idx = I965_PACKED_HEADER_BASE + 1;
+idx = I965_PIC_PACKED_HEADER_BASE + 0;
break;
case VAEncPackedHeaderSlice:
-idx = I965_PACKED_HEADER_BASE + 2;
+idx = I965_PIC_PACKED_HEADER_BASE + 1;
break;
default:
@@ -411,7 +417,7 @@ va_enc_packed_type_to_idx(int packed_type)
}
}
-ASSERT_RET(idx < 4, 0);
+ASSERT_RET(idx < 5, 0);
return idx;
}
@@ -465,7 +471,8 @@ i965_QueryConfigProfiles(VADriverContextP ctx,
profile_list[i++] = VAProfileH264StereoHigh;
}
-if (HAS_HEVC_DECODING(i965)) {
+if (HAS_HEVC_DECODING(i965)||
+HAS_HEVC_ENCODING(i965)) {
profile_list[i++] = VAProfileHEVCMain;
}
@@ -548,6 +555,9 @@ i965_QueryConfigEntrypoints(VADriverContextP ctx,
if (HAS_HEVC_DECODING(i965))
entrypoint_list[n++] = VAEntrypointVLD;
+if (HAS_HEVC_ENCODING(i965))
+entrypoint_list[n++] = VAEntrypointEncSlice;
+
break;
default:
@@ -639,7 +649,8 @@ i965_validate_config(VADriverContextP ctx, VAProfile
profile,
break;
case VAProfileHEVCMain:
-if (HAS_HEVC_DECODING(i965) && (entrypoint == VAEntrypointVLD))
+if ((HAS_HEVC_DECODING(i965) && (entrypoint == VAEntrypointVLD))||
+(HAS_HEVC_ENCODING(i965) && (entrypoint == VAEntrypointEncSlice)))
va_status = VA_STATUS_SUCCESS;
else
va_status = VA_STATUS_ERROR_UNSUPPORTED_ENTRYPOINT;
@@ -729,7 +740,8 @@ i965_GetConfigAttributes(VADriverContextP ctx,
profile == VAProfileH264Main ||
profile == VAProfileH264High ||
profile == VAProfileH264StereoHigh ||
-profile == VAProfileH264MultiviewHigh) {
+profile == VAProfileH264MultiviewHigh ||
+profile == VAProfileHEVCMain) {
attrib_list[i].value |= (VA_ENC_PACKED_HEADER_RAW_DATA |
VA_ENC_PACKED_HEADER_SLICE);
}
@@ -1894,6 +1906,8 @@ i965_CreateContext(VADriverContextP ctx,
obj_context->codec_state.encode.slice_header_index =
calloc(obj_context->codec_state.encode.max_slice_num,
sizeof(int));
+obj_context->codec_state.encode.vps_sps_seq_index = 0;
+
obj_context->codec_state.encode.slice_index = 0;
packed_attrib = i965_lookup_config_attribute(obj_config,
VAConfigAttribEncPackedHeaders);
if (packed_attrib)
@@ -1980,6 +1994,20 @@ i965_create_buffer_internal(VADriverContextP ctx,
struct object_buffer *obj_buffer = NULL;
struct buffer_store *buffer_store = NULL;
int bufferID;
+struct obje
[Libva] [PATCH V5 1/7] HEVC ENC:Added PAK context for HEVC
Signed-off-by: Qu,Pengfei
---
src/Makefile.am | 1 +
src/gen9_mfc.h | 237
2 files changed, 238 insertions(+)
create mode 100644 src/gen9_mfc.h
diff --git a/src/Makefile.am b/src/Makefile.am
index 9e54fd5..3f43809 100755
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -107,6 +107,7 @@ source_h = \
gen75_vpp_vebox.h \
gen8_post_processing.h \
gen9_mfd.h \
+ gen9_mfc.h \
i965_avc_bsd.h \
i965_avc_hw_scoreboard.h\
i965_avc_ildb.h \
diff --git a/src/gen9_mfc.h b/src/gen9_mfc.h
new file mode 100644
index 000..d891b93
--- /dev/null
+++ b/src/gen9_mfc.h
@@ -0,0 +1,237 @@
+/*
+ * Copyright © 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *Qu Pengfei
+ *
+ */
+
+#ifndef GEN9_MFC_H
+#define GEN9_MFC_H
+
+#include
+#include
+#include
+
+#include "i965_gpe_utils.h"
+
+struct encode_state;
+
+#define MAX_HCP_REFERENCE_SURFACES 8
+#define NUM_HCP_CURRENT_COLLOCATED_MV_TEMPORAL_BUFFERS 9
+
+#define INTRA_MB_FLAG_MASK 0x2000
+
+/* The space required for slice header SLICE_STATE + header.
+ * Is it enough? */
+#define SLICE_HEADER80
+
+/* the space required for slice tail. */
+#define SLICE_TAIL 16
+
+#define __SOFTWARE__0
+
+#define HCP_BATCHBUFFER_HEVC_INTRA 0
+#define HCP_BATCHBUFFER_HEVC_INTER 1
+#define NUM_HCP_KERNEL 2
+
+#define BIND_IDX_VME_OUTPUT 0
+#define BIND_IDX_HCP_SLICE_HEADER 1
+#define BIND_IDX_HCP_BATCHBUFFER2
+
+#define CMD_LEN_IN_OWORD4
+
+struct gen9_hcpe_context {
+struct {
+unsigned int width;
+unsigned int height;
+unsigned int w_pitch;
+unsigned int h_pitch;
+} surface_state;
+
+//HCP_PIPE_BUF_ADDR_STATE
+
+struct {
+dri_bo *bo;
+} deblocking_filter_line_buffer;//OUTPUT: reconstructed
picture with deblocked
+
+struct {
+dri_bo *bo;
+} deblocking_filter_tile_line_buffer; //OUTPUT: reconstructed
picture with deblocked
+
+struct {
+dri_bo *bo;
+} deblocking_filter_tile_column_buffer; //OUTPUT: reconstructed
picture with deblocked
+
+struct {
+dri_bo *bo;
+} uncompressed_picture_source; //INPUT: original compressed
image
+
+struct {
+dri_bo *bo;
+} metadata_line_buffer; //INTERNAL:metadata
+
+struct {
+dri_bo *bo;
+} metadata_tile_line_buffer;//INTERNAL:metadata
+
+struct {
+dri_bo *bo;
+} metadata_tile_column_buffer; //INTERNAL:metadata
+
+struct {
+dri_bo *bo;
+} sao_line_buffer; //INTERNAL:SAO not used in skylake
+
+struct {
+dri_bo *bo;
+} sao_tile_line_buffer;//INTERNAL:SAO not used in skylake
+
+struct {
+dri_bo *bo;
+} sao_tile_column_buffer; //INTERNAL:SAO not used in skylake
+
+struct {
+dri_bo *bo;
+}
current_collocated_mv_temporal_buffer[NUM_HCP_CURRENT_COLLOCATED_MV_TEMPORAL_BUFFERS];
//
+
+struct {
+dri_bo *bo;
+} reference_surfaces[MAX_HCP_REFERENCE_SURFACES]; //INTERNAL: refrence
surfaces
+
+//HCP_IND_OBJ_BASE_ADDR_STATE
+struct {
+dri_bo *bo;
+} hcp_indirect_cu_object; //INPUT: the cu' mv info
+
+struct {
+dri_bo *bo;
+int offset;
+int end_offset;
+} hcp_indirect_pak_bse_object; //OUTPUT: the compressed bitstream
+
+//Bit rate tracking context
+struct {
+unsigned int QpPrimeY;
+unsigned int MaxQpNegModifier;
+unsigned int MaxQpPosModifier;
+unsigned char Ma
[Libva] [PATCH V5 2/7] HEVC ENC:Added slice header generated internally
Signed-off-by: Qu,Pengfei
---
src/i965_drv_video.h | 17 +-
src/i965_encoder_utils.c | 457 +++
src/i965_encoder_utils.h | 29 +++
3 files changed, 500 insertions(+), 3 deletions(-)
diff --git a/src/i965_drv_video.h b/src/i965_drv_video.h
index cb4e8e8..24f2b14 100644
--- a/src/i965_drv_video.h
+++ b/src/i965_drv_video.h
@@ -1,5 +1,5 @@
/*
- * Copyright � 2009 Intel Corporation
+ * Copyright ?2009 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
@@ -33,6 +33,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -150,8 +151,8 @@ struct encode_state
/* for ext */
struct buffer_store *seq_param_ext;
struct buffer_store *pic_param_ext;
-struct buffer_store *packed_header_param[4];
-struct buffer_store *packed_header_data[4];
+struct buffer_store *packed_header_param[5];
+struct buffer_store *packed_header_data[5];
struct buffer_store **slice_params_ext;
int max_slice_params_ext;
int num_slice_params_ext;
@@ -171,6 +172,8 @@ struct encode_state
int max_packed_header_data_ext;
int num_packed_header_data_ext;
+/* the index of current vps and sps ,special for HEVC*/
+int vps_sps_seq_index;
/* the index of current slice */
int slice_index;
/* the array is determined by max_slice_params_ext */
@@ -370,6 +373,7 @@ struct hw_codec_info
unsigned int has_vp8_encoding:1;
unsigned int has_h264_mvc_encoding:1;
unsigned int has_hevc_decoding:1;
+unsigned int has_hevc_encoding:1;
unsigned int num_filters;
struct i965_filter filters[VAProcFilterCount];
@@ -454,6 +458,7 @@ va_enc_packed_type_to_idx(int packed_type);
#define CODEC_MPEG2 1
#define CODEC_H264_MVC 2
#define CODEC_JPEG 3
+#define CODEC_HEVC 5
#define H264_DELIMITER0 0x00
#define H264_DELIMITER1 0x00
@@ -467,6 +472,12 @@ va_enc_packed_type_to_idx(int packed_type);
#define MPEG2_DELIMITER30x00
#define MPEG2_DELIMITER40xb0
+#define HEVC_DELIMITER0 0x00
+#define HEVC_DELIMITER1 0x00
+#define HEVC_DELIMITER2 0x00
+#define HEVC_DELIMITER3 0x00
+#define HEVC_DELIMITER4 0x00
+
struct i965_coded_buffer_segment
{
VACodedBufferSegment base;
diff --git a/src/i965_encoder_utils.c b/src/i965_encoder_utils.c
index e59e7fb..ac6813a 100644
--- a/src/i965_encoder_utils.c
+++ b/src/i965_encoder_utils.c
@@ -29,6 +29,7 @@
#include
#include
#include
+#include
#include "i965_encoder_utils.h"
@@ -62,6 +63,17 @@
#define PROFILE_IDC_MAIN77
#define PROFILE_IDC_HIGH100
+/*HEVC*/
+#define VPS_NUT32
+#define SPS_NUT33
+#define PPS_NUT34
+#define IDR_WRADL_NUT 19
+#define IDR_NLP_NUT20
+#define SLICE_TRAIL_N_NUT 0
+#define SLICE_TRAIL_R_NUT 1
+#define PREFIX_SEI_NUT 39
+#define SUFFIX_SEI_NUT 40
+
struct __avc_bitstream {
unsigned int *buffer;
int bit_offset;
@@ -562,3 +574,448 @@
build_avc_mvc_slice_header(VAEncSequenceParameterBufferH264_MVC *mvc_sps_param,
return bs.bit_offset;
}
+
+/* HEVC to do for internal header generated*/
+
+void nal_header_hevc(avc_bitstream *bs, int nal_unit_type, int temporalid)
+{
+/* forbidden_zero_bit: 0 */
+avc_bitstream_put_ui(bs, 0, 1);
+/* nal unit_type */
+avc_bitstream_put_ui(bs, nal_unit_type, 6);
+/* layer_id. currently it is zero */
+avc_bitstream_put_ui(bs, 0, 6);
+/* teporalid + 1 .*/
+avc_bitstream_put_ui(bs, temporalid + 1, 3);
+}
+
+int build_hevc_sei_buffering_period(int init_cpb_removal_delay_length,
+unsigned int init_cpb_removal_delay,
+unsigned int init_cpb_removal_delay_offset,
+unsigned char **sei_buffer)
+{
+unsigned char *byte_buf;
+int bp_byte_size, i;
+//unsigned int cpb_removal_delay;
+
+avc_bitstream nal_bs;
+avc_bitstream sei_bp_bs;
+
+avc_bitstream_start(&sei_bp_bs);
+avc_bitstream_put_ue(&sei_bp_bs, 0); /*seq_parameter_set_id*/
+/* SEI buffer period info */
+/* NALHrdBpPresentFlag == 1 */
+avc_bitstream_put_ui(&sei_bp_bs,
init_cpb_removal_delay,init_cpb_removal_delay_length);
+avc_bitstream_put_ui(&sei_bp_bs,
init_cpb_removal_delay_offset,init_cpb_removal_delay_length);
+if ( sei_bp_bs.bit_offset & 0x7) {
+avc_bitstream_put_ui(&sei_bp_bs, 1, 1);
+}
+avc_bitstream_end(&sei_bp_bs);
+bp_byte_size = (sei_bp_bs.bit_offset + 7) / 8;
+
+avc_bitstream_start(&nal_bs);
+nal_start_code_prefix(&nal_bs);
+nal_header_hevc(&nal_bs, PREFIX_SEI_NUT ,0);
+
+/* Write the SEI buffer period data */
+avc_bitstream_put_ui(&nal_bs, 0, 8);
+avc_bitstream_put_ui(&nal_bs, bp_byte_size, 8);
+
+byte_
[Libva] [PATCH V5 0/7] HEVC encoder summary
V1-->V2: 1.add the style alignment patch 2.seperate the files into different patch and ensure building successfully. V2-->V3: 1.re-order the PATCH to ensure HEVC entrypoint/profile query in the last commit. 2.seperate file src/i965_encoder.c from the"VME pipeline" patch and as an independent patch. V3-->V4: 1.set coded_buffer_segment at the beginning of output buffer. 2.define the function declare in the patch "Added PAK pipeline" 3.change the HEVC_CODEC value as 5 V4-->V5 1.change _GEN9_MFC_H_ to GEN9_MFC_H in the patch "Added PAK context for HEVC" 2.remove PAK shader related codes for HEVC in the patch "Added PAK pipeline" HEVC enc feature: 1.LCU size is 16x16 only 2.Min CU size is 16x16 only 3.Transform size 16x16~8x8 4.I/P/B frame enabled. 5.Constant QP only Qu,Pengfei (7): HEVC ENC:Added PAK context for HEVC HEVC ENC:Added slice header generated internally HEVC ENC:Added PAK pipeline HEVC ENC:Added VME pipeline HEVC ENC:Added pipeline init HEVC ENC:Added HEVC support in API function Just Style alignment src/Makefile.am |2 + src/gen6_mfc_common.c| 686 +++- src/gen6_vme.h | 19 + src/gen9_mfc.h | 288 ++ src/gen9_mfc_hevc.c | 2586 ++ src/gen9_vme.c | 928 + src/i965_device_info.c | 17 +- src/i965_drv_video.c | 142 ++- src/i965_drv_video.h | 17 +- src/i965_encoder.c | 74 +- src/i965_encoder_utils.c | 457 src/i965_encoder_utils.h | 29 + 12 files changed, 4745 insertions(+), 500 deletions(-) create mode 100644 src/gen9_mfc.h create mode 100644 src/gen9_mfc_hevc.c -- 1.9.1 ___ Libva mailing list Libva@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/libva
[Libva] [PATCH V4 2/7] HEVC ENC:Added slice header generated internally
Signed-off-by: Qu,Pengfei
---
src/i965_drv_video.h | 17 +-
src/i965_encoder_utils.c | 457 +++
src/i965_encoder_utils.h | 29 +++
3 files changed, 500 insertions(+), 3 deletions(-)
diff --git a/src/i965_drv_video.h b/src/i965_drv_video.h
index cb4e8e8..24f2b14 100644
--- a/src/i965_drv_video.h
+++ b/src/i965_drv_video.h
@@ -1,5 +1,5 @@
/*
- * Copyright ? 2009 Intel Corporation
+ * Copyright ?2009 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
@@ -33,6 +33,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -150,8 +151,8 @@ struct encode_state
/* for ext */
struct buffer_store *seq_param_ext;
struct buffer_store *pic_param_ext;
-struct buffer_store *packed_header_param[4];
-struct buffer_store *packed_header_data[4];
+struct buffer_store *packed_header_param[5];
+struct buffer_store *packed_header_data[5];
struct buffer_store **slice_params_ext;
int max_slice_params_ext;
int num_slice_params_ext;
@@ -171,6 +172,8 @@ struct encode_state
int max_packed_header_data_ext;
int num_packed_header_data_ext;
+/* the index of current vps and sps ,special for HEVC*/
+int vps_sps_seq_index;
/* the index of current slice */
int slice_index;
/* the array is determined by max_slice_params_ext */
@@ -370,6 +373,7 @@ struct hw_codec_info
unsigned int has_vp8_encoding:1;
unsigned int has_h264_mvc_encoding:1;
unsigned int has_hevc_decoding:1;
+unsigned int has_hevc_encoding:1;
unsigned int num_filters;
struct i965_filter filters[VAProcFilterCount];
@@ -454,6 +458,7 @@ va_enc_packed_type_to_idx(int packed_type);
#define CODEC_MPEG2 1
#define CODEC_H264_MVC 2
#define CODEC_JPEG 3
+#define CODEC_HEVC 5
#define H264_DELIMITER0 0x00
#define H264_DELIMITER1 0x00
@@ -467,6 +472,12 @@ va_enc_packed_type_to_idx(int packed_type);
#define MPEG2_DELIMITER30x00
#define MPEG2_DELIMITER40xb0
+#define HEVC_DELIMITER0 0x00
+#define HEVC_DELIMITER1 0x00
+#define HEVC_DELIMITER2 0x00
+#define HEVC_DELIMITER3 0x00
+#define HEVC_DELIMITER4 0x00
+
struct i965_coded_buffer_segment
{
VACodedBufferSegment base;
diff --git a/src/i965_encoder_utils.c b/src/i965_encoder_utils.c
index e59e7fb..ac6813a 100644
--- a/src/i965_encoder_utils.c
+++ b/src/i965_encoder_utils.c
@@ -29,6 +29,7 @@
#include
#include
#include
+#include
#include "i965_encoder_utils.h"
@@ -62,6 +63,17 @@
#define PROFILE_IDC_MAIN77
#define PROFILE_IDC_HIGH100
+/*HEVC*/
+#define VPS_NUT32
+#define SPS_NUT33
+#define PPS_NUT34
+#define IDR_WRADL_NUT 19
+#define IDR_NLP_NUT20
+#define SLICE_TRAIL_N_NUT 0
+#define SLICE_TRAIL_R_NUT 1
+#define PREFIX_SEI_NUT 39
+#define SUFFIX_SEI_NUT 40
+
struct __avc_bitstream {
unsigned int *buffer;
int bit_offset;
@@ -562,3 +574,448 @@
build_avc_mvc_slice_header(VAEncSequenceParameterBufferH264_MVC *mvc_sps_param,
return bs.bit_offset;
}
+
+/* HEVC to do for internal header generated*/
+
+void nal_header_hevc(avc_bitstream *bs, int nal_unit_type, int temporalid)
+{
+/* forbidden_zero_bit: 0 */
+avc_bitstream_put_ui(bs, 0, 1);
+/* nal unit_type */
+avc_bitstream_put_ui(bs, nal_unit_type, 6);
+/* layer_id. currently it is zero */
+avc_bitstream_put_ui(bs, 0, 6);
+/* teporalid + 1 .*/
+avc_bitstream_put_ui(bs, temporalid + 1, 3);
+}
+
+int build_hevc_sei_buffering_period(int init_cpb_removal_delay_length,
+unsigned int init_cpb_removal_delay,
+unsigned int init_cpb_removal_delay_offset,
+unsigned char **sei_buffer)
+{
+unsigned char *byte_buf;
+int bp_byte_size, i;
+//unsigned int cpb_removal_delay;
+
+avc_bitstream nal_bs;
+avc_bitstream sei_bp_bs;
+
+avc_bitstream_start(&sei_bp_bs);
+avc_bitstream_put_ue(&sei_bp_bs, 0); /*seq_parameter_set_id*/
+/* SEI buffer period info */
+/* NALHrdBpPresentFlag == 1 */
+avc_bitstream_put_ui(&sei_bp_bs,
init_cpb_removal_delay,init_cpb_removal_delay_length);
+avc_bitstream_put_ui(&sei_bp_bs,
init_cpb_removal_delay_offset,init_cpb_removal_delay_length);
+if ( sei_bp_bs.bit_offset & 0x7) {
+avc_bitstream_put_ui(&sei_bp_bs, 1, 1);
+}
+avc_bitstream_end(&sei_bp_bs);
+bp_byte_size = (sei_bp_bs.bit_offset + 7) / 8;
+
+avc_bitstream_start(&nal_bs);
+nal_start_code_prefix(&nal_bs);
+nal_header_hevc(&nal_bs, PREFIX_SEI_NUT ,0);
+
+/* Write the SEI buffer period data */
+avc_bitstream_put_ui(&nal_bs, 0, 8);
+avc_bitstream_put_ui(&nal_bs, bp_byte_size, 8);
+
+byte_
[Libva] [PATCH V4 4/7] HEVC ENC:Added VME pipeline
Signed-off-by: Qu,Pengfei
---
src/gen6_mfc_common.c | 222 +++
src/gen6_vme.h| 19 ++
src/gen9_vme.c| 484 ++
3 files changed, 725 insertions(+)
diff --git a/src/gen6_mfc_common.c b/src/gen6_mfc_common.c
index fe41dac..6a5f720 100644
--- a/src/gen6_mfc_common.c
+++ b/src/gen6_mfc_common.c
@@ -1652,3 +1652,225 @@ void
intel_avc_slice_insert_packed_data(VADriverContextP ctx,
return;
}
+/* HEVC */
+static int
+hevc_temporal_find_surface(VAPictureHEVC *curr_pic,
+ VAPictureHEVC *ref_list,
+ int num_pictures,
+ int dir)
+{
+int i, found = -1, min = 0x7FFF;
+
+for (i = 0; i < num_pictures; i++) {
+int tmp;
+
+if ((ref_list[i].flags & VA_PICTURE_HEVC_INVALID) ||
+(ref_list[i].picture_id == VA_INVALID_SURFACE))
+break;
+
+tmp = curr_pic->pic_order_cnt - ref_list[i].pic_order_cnt;
+
+if (dir)
+tmp = -tmp;
+
+if (tmp > 0 && tmp < min) {
+min = tmp;
+found = i;
+}
+}
+
+return found;
+}
+void
+intel_hevc_vme_reference_state(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context,
+ int list_index,
+ int surface_index,
+ void (* vme_source_surface_state)(
+ VADriverContextP ctx,
+ int index,
+ struct object_surface *obj_surface,
+ struct intel_encoder_context
*encoder_context))
+{
+struct gen6_vme_context *vme_context = encoder_context->vme_context;
+struct object_surface *obj_surface = NULL;
+struct i965_driver_data *i965 = i965_driver_data(ctx);
+VASurfaceID ref_surface_id;
+VAEncPictureParameterBufferHEVC *pic_param =
(VAEncPictureParameterBufferHEVC *)encode_state->pic_param_ext->buffer;
+VAEncSliceParameterBufferHEVC *slice_param =
(VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[0]->buffer;
+int max_num_references;
+VAPictureHEVC *curr_pic;
+VAPictureHEVC *ref_list;
+int ref_idx;
+
+if (list_index == 0) {
+max_num_references = pic_param->num_ref_idx_l0_default_active_minus1 +
1;
+ref_list = slice_param->ref_pic_list0;
+} else {
+max_num_references = pic_param->num_ref_idx_l1_default_active_minus1 +
1;
+ref_list = slice_param->ref_pic_list1;
+}
+
+if (max_num_references == 1) {
+if (list_index == 0) {
+ref_surface_id = slice_param->ref_pic_list0[0].picture_id;
+vme_context->used_references[0] = &slice_param->ref_pic_list0[0];
+} else {
+ref_surface_id = slice_param->ref_pic_list1[0].picture_id;
+vme_context->used_references[1] = &slice_param->ref_pic_list1[0];
+}
+
+if (ref_surface_id != VA_INVALID_SURFACE)
+obj_surface = SURFACE(ref_surface_id);
+
+if (!obj_surface ||
+!obj_surface->bo) {
+obj_surface = encode_state->reference_objects[list_index];
+vme_context->used_references[list_index] =
&pic_param->reference_frames[list_index];
+}
+
+ref_idx = 0;
+} else {
+curr_pic = &pic_param->decoded_curr_pic;
+
+/* select the reference frame in temporal space */
+ref_idx = hevc_temporal_find_surface(curr_pic, ref_list,
max_num_references, list_index == 1);
+ref_surface_id = ref_list[ref_idx].picture_id;
+
+if (ref_surface_id != VA_INVALID_SURFACE) /* otherwise warning later */
+obj_surface = SURFACE(ref_surface_id);
+
+vme_context->used_reference_objects[list_index] = obj_surface;
+vme_context->used_references[list_index] = &ref_list[ref_idx];
+}
+
+if (obj_surface &&
+obj_surface->bo) {
+assert(ref_idx >= 0);
+vme_context->used_reference_objects[list_index] = obj_surface;
+vme_source_surface_state(ctx, surface_index, obj_surface,
encoder_context);
+vme_context->ref_index_in_mb[list_index] = (ref_idx << 24 |
+ref_idx << 16 |
+ref_idx << 8 |
+ref_idx);
+} else {
+vme_context->used_reference_objects[list_index] = NULL;
+vme_context->used_references[list_index] = NULL;
+vme_context->ref_index_in_mb[list_index] = 0;
+}
+}
+
+void intel_vme_hevc_update_mbmv_cost(VADriverContextP ctx,
+ struct encode_state *encode_state,
+
[Libva] [PATCH V4 0/7] HEVC encoder summary
V1-->V2: 1.add the style alignment patch 2.seperate the files into different patch and ensure building successfully. V2-->V3: 1.re-order the PATCH to ensure HEVC entrypoint/profile query in the last commit. 2.seperate file src/i965_encoder.c from the"VME pipeline" patch and as an independent patch. V3-->V4: 1.set coded_buffer_segment at the beginning of output buffer. 2.define the function declare in the patch "Added PAK pipeline" 3.change the HEVC_CODEC value as 5 HEVC enc feature: 1.LCU size is 16x16 only 2.Min CU size is 16x16 only 3.Transform size 16x16~8x8 4.I/P/B frame enabled. 5.Constant QP only Qu,Pengfei (7): HEVC ENC:Added PAK context for HEVC HEVC ENC:Added slice header generated internally HEVC ENC:Added PAK pipeline HEVC ENC:Added VME pipeline HEVC ENC:Added pipeline init HEVC ENC:Added HEVC support in API function Just Style alignment src/Makefile.am |2 + src/gen6_mfc_common.c| 686 src/gen6_vme.h | 19 + src/gen9_mfc.h | 288 + src/gen9_mfc_hevc.c | 2631 ++ src/gen9_vme.c | 928 src/i965_device_info.c | 17 +- src/i965_drv_video.c | 142 ++- src/i965_drv_video.h | 17 +- src/i965_encoder.c | 74 +- src/i965_encoder_utils.c | 457 src/i965_encoder_utils.h | 29 + 12 files changed, 4790 insertions(+), 500 deletions(-) create mode 100644 src/gen9_mfc.h create mode 100644 src/gen9_mfc_hevc.c -- 1.9.1 ___ Libva mailing list Libva@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/libva
[Libva] [PATCH V4 5/7] HEVC ENC:Added pipeline init
Signed-off-by: Qu,Pengfei
---
src/i965_encoder.c | 74 +-
1 file changed, 73 insertions(+), 1 deletion(-)
diff --git a/src/i965_encoder.c b/src/i965_encoder.c
index d924f5a..c9ff2ec 100644
--- a/src/i965_encoder.c
+++ b/src/i965_encoder.c
@@ -39,10 +39,12 @@
#include "i965_encoder.h"
#include "gen6_vme.h"
#include "gen6_mfc.h"
+#include "gen9_mfc.h"
extern Bool gen6_mfc_context_init(VADriverContextP ctx, struct
intel_encoder_context *encoder_context);
extern Bool gen6_vme_context_init(VADriverContextP ctx, struct
intel_encoder_context *encoder_context);
extern Bool gen7_mfc_context_init(VADriverContextP ctx, struct
intel_encoder_context *encoder_context);
+extern Bool gen9_hcpe_context_init(VADriverContextP ctx, struct
intel_encoder_context *encoder_context);
static VAStatus
intel_encoder_check_yuv_surface(VADriverContextP ctx,
@@ -422,6 +424,63 @@ error:
}
static VAStatus
+intel_encoder_check_hevc_parameter(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context
*encoder_context)
+{
+struct i965_driver_data *i965 = i965_driver_data(ctx);
+struct object_surface *obj_surface;
+struct object_buffer *obj_buffer;
+VAEncPictureParameterBufferHEVC *pic_param =
(VAEncPictureParameterBufferHEVC *)encode_state->pic_param_ext->buffer;
+int i;
+
+assert(!(pic_param->decoded_curr_pic.flags & VA_PICTURE_HEVC_INVALID));
+
+if (pic_param->decoded_curr_pic.flags & VA_PICTURE_HEVC_INVALID)
+goto error;
+
+obj_surface = SURFACE(pic_param->decoded_curr_pic.picture_id);
+assert(obj_surface); /* It is possible the store buffer isn't allocated
yet */
+
+if (!obj_surface)
+goto error;
+
+encode_state->reconstructed_object = obj_surface;
+obj_buffer = BUFFER(pic_param->coded_buf);
+assert(obj_buffer && obj_buffer->buffer_store &&
obj_buffer->buffer_store->bo);
+
+if (!obj_buffer || !obj_buffer->buffer_store ||
!obj_buffer->buffer_store->bo)
+goto error;
+
+encode_state->coded_buf_object = obj_buffer;
+
+for (i = 0; i < 15; i++) {
+if (pic_param->reference_frames[i].flags & VA_PICTURE_HEVC_INVALID ||
+pic_param->reference_frames[i].picture_id == VA_INVALID_SURFACE)
+break;
+else {
+obj_surface = SURFACE(pic_param->reference_frames[i].picture_id);
+assert(obj_surface);
+
+if (!obj_surface)
+goto error;
+
+if (obj_surface->bo)
+encode_state->reference_objects[i] = obj_surface;
+else
+encode_state->reference_objects[i] = NULL; /* FIXME: Warning
or Error ??? */
+}
+}
+
+for ( ; i < 15; i++)
+encode_state->reference_objects[i] = NULL;
+
+return VA_STATUS_SUCCESS;
+
+error:
+return VA_STATUS_ERROR_INVALID_PARAMETER;
+}
+static VAStatus
intel_encoder_sanity_check_input(VADriverContextP ctx,
VAProfile profile,
struct encode_state *encode_state,
@@ -459,6 +518,13 @@ intel_encoder_sanity_check_input(VADriverContextP ctx,
break;
}
+case VAProfileHEVCMain: {
+vaStatus = intel_encoder_check_hevc_parameter(ctx, encode_state,
encoder_context);
+if (vaStatus != VA_STATUS_SUCCESS)
+goto out;
+vaStatus = intel_encoder_check_yuv_surface(ctx, profile, encode_state,
encoder_context);
+break;
+}
default:
vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
break;
@@ -554,6 +620,10 @@ intel_enc_hw_context_init(VADriverContextP ctx,
encoder_context->codec = CODEC_JPEG;
break;
+case VAProfileHEVCMain:
+encoder_context->codec = CODEC_HEVC;
+break;
+
default:
/* Never get here */
assert(0);
@@ -617,7 +687,9 @@ gen8_enc_hw_context_init(VADriverContextP ctx, struct
object_config *obj_config)
struct hw_context *
gen9_enc_hw_context_init(VADriverContextP ctx, struct object_config
*obj_config)
{
-if (obj_config->profile == VAProfileJPEGBaseline)
+if (obj_config->profile == VAProfileHEVCMain) {
+return intel_enc_hw_context_init(ctx, obj_config,
gen9_vme_context_init, gen9_hcpe_context_init);
+} else if (obj_config->profile == VAProfileJPEGBaseline)
return intel_enc_hw_context_init(ctx, obj_config,
gen8_vme_context_init, gen8_mfc_context_init);
else
return intel_enc_hw_context_init(ctx, obj_config,
gen9_vme_context_init, gen9_mfc_context_init);
--
1.9.1
___
Libva mailing list
Libva@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/libva
[Libva] [PATCH V4 6/7] HEVC ENC:Added HEVC support in API function
Signed-off-by: Qu,Pengfei
---
src/i965_device_info.c | 1 +
src/i965_drv_video.c | 112 -
2 files changed, 94 insertions(+), 19 deletions(-)
diff --git a/src/i965_device_info.c b/src/i965_device_info.c
index d03aceb..9ccc85e 100755
--- a/src/i965_device_info.c
+++ b/src/i965_device_info.c
@@ -347,6 +347,7 @@ static struct hw_codec_info skl_hw_codec_info = {
.has_blending = 1,
.has_h264_mvc_encoding = 1,
.has_hevc_decoding = 1,
+.has_hevc_encoding = 1,
.num_filters = 5,
.filters = {
diff --git a/src/i965_drv_video.c b/src/i965_drv_video.c
index 74895da..88738cb 100644
--- a/src/i965_drv_video.c
+++ b/src/i965_drv_video.c
@@ -1,5 +1,5 @@
/*
- * Copyright ? 2009 Intel Corporation
+ * Copyright ?2009 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
@@ -104,6 +104,9 @@
#define HAS_HEVC_DECODING(ctx) ((ctx)->codec_info->has_hevc_decoding
&& \
(ctx)->intel.has_bsd)
+#define HAS_HEVC_ENCODING(ctx) ((ctx)->codec_info->has_hevc_encoding
&& \
+ (ctx)->intel.has_bsd)
+
static int get_sampling_from_fourcc(unsigned int fourcc);
/* Check whether we are rendering to X11 (VA/X11 or VA/GLX API) */
@@ -376,7 +379,10 @@ is_image_busy(struct i965_driver_data *i965, struct
object_image *obj_image)
}
#define I965_PACKED_HEADER_BASE 0
-#define I965_PACKED_MISC_HEADER_BASE3
+#define I965_SEQ_PACKED_HEADER_BASE 0
+#define I965_SEQ_PACKED_HEADER_END 2
+#define I965_PIC_PACKED_HEADER_BASE 2
+#define I965_PACKED_MISC_HEADER_BASE4
int
va_enc_packed_type_to_idx(int packed_type)
@@ -393,15 +399,15 @@ va_enc_packed_type_to_idx(int packed_type)
switch (packed_type) {
case VAEncPackedHeaderSequence:
-idx = I965_PACKED_HEADER_BASE + 0;
+idx = I965_SEQ_PACKED_HEADER_BASE + 0;
break;
case VAEncPackedHeaderPicture:
-idx = I965_PACKED_HEADER_BASE + 1;
+idx = I965_PIC_PACKED_HEADER_BASE + 0;
break;
case VAEncPackedHeaderSlice:
-idx = I965_PACKED_HEADER_BASE + 2;
+idx = I965_PIC_PACKED_HEADER_BASE + 1;
break;
default:
@@ -411,7 +417,7 @@ va_enc_packed_type_to_idx(int packed_type)
}
}
-ASSERT_RET(idx < 4, 0);
+ASSERT_RET(idx < 5, 0);
return idx;
}
@@ -465,7 +471,8 @@ i965_QueryConfigProfiles(VADriverContextP ctx,
profile_list[i++] = VAProfileH264StereoHigh;
}
-if (HAS_HEVC_DECODING(i965)) {
+if (HAS_HEVC_DECODING(i965)||
+HAS_HEVC_ENCODING(i965)) {
profile_list[i++] = VAProfileHEVCMain;
}
@@ -548,6 +555,9 @@ i965_QueryConfigEntrypoints(VADriverContextP ctx,
if (HAS_HEVC_DECODING(i965))
entrypoint_list[n++] = VAEntrypointVLD;
+if (HAS_HEVC_ENCODING(i965))
+entrypoint_list[n++] = VAEntrypointEncSlice;
+
break;
default:
@@ -639,7 +649,8 @@ i965_validate_config(VADriverContextP ctx, VAProfile
profile,
break;
case VAProfileHEVCMain:
-if (HAS_HEVC_DECODING(i965) && (entrypoint == VAEntrypointVLD))
+if ((HAS_HEVC_DECODING(i965) && (entrypoint == VAEntrypointVLD))||
+(HAS_HEVC_ENCODING(i965) && (entrypoint == VAEntrypointEncSlice)))
va_status = VA_STATUS_SUCCESS;
else
va_status = VA_STATUS_ERROR_UNSUPPORTED_ENTRYPOINT;
@@ -729,7 +740,8 @@ i965_GetConfigAttributes(VADriverContextP ctx,
profile == VAProfileH264Main ||
profile == VAProfileH264High ||
profile == VAProfileH264StereoHigh ||
-profile == VAProfileH264MultiviewHigh) {
+profile == VAProfileH264MultiviewHigh ||
+profile == VAProfileHEVCMain) {
attrib_list[i].value |= (VA_ENC_PACKED_HEADER_RAW_DATA |
VA_ENC_PACKED_HEADER_SLICE);
}
@@ -1894,6 +1906,8 @@ i965_CreateContext(VADriverContextP ctx,
obj_context->codec_state.encode.slice_header_index =
calloc(obj_context->codec_state.encode.max_slice_num,
sizeof(int));
+obj_context->codec_state.encode.vps_sps_seq_index = 0;
+
obj_context->codec_state.encode.slice_index = 0;
packed_attrib = i965_lookup_config_attribute(obj_config,
VAConfigAttribEncPackedHeaders);
if (packed_attrib)
@@ -1980,6 +1994,20 @@ i965_create_buffer_internal(VADriverContextP ctx,
struct object_buffer *obj_buffer = NULL;
struct buffer_store *buffer_store = NULL;
int bufferID;
+struct obje
[Libva] [PATCH V4 7/7] Just Style alignment
Signed-off-by: Qu,Pengfei
---
src/gen6_mfc_common.c | 464 -
src/gen9_vme.c | 444 +++---
src/i965_device_info.c | 16 +-
src/i965_drv_video.c | 32 ++--
4 files changed, 478 insertions(+), 478 deletions(-)
diff --git a/src/gen6_mfc_common.c b/src/gen6_mfc_common.c
index 6a5f720..cc1b0e6 100644
--- a/src/gen6_mfc_common.c
+++ b/src/gen6_mfc_common.c
@@ -631,8 +631,8 @@ VAStatus intel_mfc_avc_prepare(VADriverContextP ctx,
int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
if (IS_GEN6(i965->intel.device_info)) {
- /* On the SNB it should be fixed to 128 for the DMV buffer */
- width_in_mbs = 128;
+/* On the SNB it should be fixed to 128 for the DMV buffer */
+width_in_mbs = 128;
}
for (j = 0; j < encode_state->num_slice_params_ext && enable_avc_ildb ==
0; j++) {
@@ -735,7 +735,7 @@ VAStatus intel_mfc_avc_prepare(VADriverContextP ctx,
break;
}
}
-
+
mfc_context->uncompressed_picture_source.bo =
encode_state->input_yuv_object->bo;
dri_bo_reference(mfc_context->uncompressed_picture_source.bo);
@@ -807,7 +807,7 @@ int intel_format_lutvalue(int value, int max)
if (temp1 > temp2)
ret = max;
return ret;
-
+
}
@@ -842,40 +842,40 @@ void intel_vme_update_mbmv_cost(VADriverContextP ctx,
if (encoder_context->rate_control_mode == VA_RC_CQP)
- qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
+qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
else
- qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
-
+qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
+
if (vme_state_message == NULL)
- return;
-
+return;
+
assert(qp <= QP_MAX);
lambda = intel_lambda_qp(qp);
if (slice_type == SLICE_TYPE_I) {
- vme_state_message[MODE_INTRA_16X16] = 0;
- m_cost = lambda * 4;
- vme_state_message[MODE_INTRA_8X8] = intel_format_lutvalue(m_cost, 0x8f);
- m_cost = lambda * 16;
- vme_state_message[MODE_INTRA_4X4] = intel_format_lutvalue(m_cost, 0x8f);
- m_cost = lambda * 3;
- vme_state_message[MODE_INTRA_NONPRED] = intel_format_lutvalue(m_cost,
0x6f);
+vme_state_message[MODE_INTRA_16X16] = 0;
+m_cost = lambda * 4;
+vme_state_message[MODE_INTRA_8X8] = intel_format_lutvalue(m_cost,
0x8f);
+m_cost = lambda * 16;
+vme_state_message[MODE_INTRA_4X4] = intel_format_lutvalue(m_cost,
0x8f);
+m_cost = lambda * 3;
+vme_state_message[MODE_INTRA_NONPRED] = intel_format_lutvalue(m_cost,
0x6f);
} else {
- m_cost = 0;
- vme_state_message[MODE_INTER_MV0] = intel_format_lutvalue(m_cost, 0x6f);
- for (j = 1; j < 3; j++) {
+m_cost = 0;
+vme_state_message[MODE_INTER_MV0] = intel_format_lutvalue(m_cost,
0x6f);
+for (j = 1; j < 3; j++) {
m_costf = (log2f((float)(j + 1)) + 1.718f) * lambda;
m_cost = (int)m_costf;
vme_state_message[MODE_INTER_MV0 + j] =
intel_format_lutvalue(m_cost, 0x6f);
- }
- mv_count = 3;
- for (j = 4; j <= 64; j *= 2) {
+}
+mv_count = 3;
+for (j = 4; j <= 64; j *= 2) {
m_costf = (log2f((float)(j + 1)) + 1.718f) * lambda;
m_cost = (int)m_costf;
vme_state_message[MODE_INTER_MV0 + mv_count] =
intel_format_lutvalue(m_cost, 0x6f);
mv_count++;
- }
+}
- if (qp <= 25) {
+if (qp <= 25) {
vme_state_message[MODE_INTRA_16X16] = 0x4a;
vme_state_message[MODE_INTRA_8X8] = 0x4a;
vme_state_message[MODE_INTRA_4X4] = 0x4a;
@@ -887,17 +887,17 @@ void intel_vme_update_mbmv_cost(VADriverContextP ctx,
vme_state_message[MODE_INTER_4X4] = 0x4a;
vme_state_message[MODE_INTER_BWD] = 0x2a;
return;
- }
- m_costf = lambda * 10;
- vme_state_message[MODE_INTRA_16X16] = intel_format_lutvalue(m_cost,
0x8f);
- m_cost = lambda * 14;
- vme_state_message[MODE_INTRA_8X8] = intel_format_lutvalue(m_cost, 0x8f);
- m_cost = lambda * 24;
- vme_state_message[MODE_INTRA_4X4] = intel_format_lutvalue(m_cost, 0x8f);
- m_costf = lambda * 3.5;
- m_cost = m_costf;
- vme_state_message[MODE_INTRA_NONPRED] = intel_format_lutvalue(m_cost,
0x6f);
- if (slice_type == SLICE_TYPE_P) {
+}
+m_costf = lambda * 10;
+vme_state_message[MODE_INTRA_16X16] = intel_format_lutvalue(m_cost,
0x8f);
+m_cost = lambda * 14;
+vme_state_message[MODE_INTRA_8X8] = intel_format_lutvalue(m_cost,
0x8f);
+m_cost = lambda * 24;
+vme_state_message[MODE_INTRA_4X4] = intel_for
[Libva] [PATCH V4 3/7] HEVC ENC:Added PAK pipeline
Signed-off-by: Qu,Pengfei
---
src/Makefile.am |1 +
src/gen9_mfc.h | 51 +
src/gen9_mfc_hevc.c | 2631 +++
3 files changed, 2683 insertions(+)
create mode 100644 src/gen9_mfc_hevc.c
diff --git a/src/Makefile.am b/src/Makefile.am
index 3f43809..880d386 100755
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -64,6 +64,7 @@ source_c = \
gen8_vme.c \
gen9_vme.c \
gen9_mfc.c \
+ gen9_mfc_hevc.c \
gen9_mfd.c \
gen75_picture_process.c \
gen75_vme.c \
diff --git a/src/gen9_mfc.h b/src/gen9_mfc.h
index 5db24ce..51155fe 100644
--- a/src/gen9_mfc.h
+++ b/src/gen9_mfc.h
@@ -234,4 +234,55 @@ struct gen9_hcpe_context {
unsigned long surface_state_offset);
};
+VAStatus gen9_hcpe_pipeline(VADriverContextP ctx,
+VAProfile profile,
+struct encode_state *encode_state,
+struct intel_encoder_context *encoder_context);
+
+/* HEVC BRC */
+extern int intel_hcpe_update_hrd(struct encode_state *encode_state,
+ struct gen9_hcpe_context *hcpe_context,
+ int frame_bits);
+
+extern int intel_hcpe_brc_postpack(struct encode_state *encode_state,
+ struct gen9_hcpe_context *hcpe_context,
+ int frame_bits);
+
+extern void intel_hcpe_hrd_context_update(struct encode_state *encode_state,
+struct gen9_hcpe_context *hcpe_context);
+
+extern int intel_hcpe_interlace_check(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context
*encoder_context);
+
+extern void intel_hcpe_brc_prepare(struct encode_state *encode_state,
+ struct intel_encoder_context
*encoder_context);
+
+/* HEVC HCP pipeline */
+extern void intel_hcpe_hevc_pipeline_header_programing(VADriverContextP ctx,
+struct encode_state *encode_state,
+struct intel_encoder_context *encoder_context,
+struct intel_batchbuffer *slice_batch);
+
+extern VAStatus intel_hcpe_hevc_prepare(VADriverContextP ctx,
+struct encode_state *encode_state,
+struct intel_encoder_context
*encoder_context);
+
+extern void
+intel_hcpe_hevc_ref_idx_state(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context);
+
+extern void
+intel_hevc_slice_insert_packed_data(VADriverContextP ctx,
+struct encode_state *encode_state,
+struct intel_encoder_context
*encoder_context,
+int slice_index,
+struct intel_batchbuffer *slice_batch);
+
+extern
+Bool gen9_hcpe_context_init(VADriverContextP ctx, struct intel_encoder_context
*encoder_context);
+
+void gen9_hcpe_context_destroy(void *context);
+
#endif /* _GEN9_MFC_H_ */
diff --git a/src/gen9_mfc_hevc.c b/src/gen9_mfc_hevc.c
new file mode 100644
index 000..7957d93
--- /dev/null
+++ b/src/gen9_mfc_hevc.c
@@ -0,0 +1,2631 @@
+/*
+ * Copyright ?? 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *Qu Pengfei
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "intel_batchbuffer.h"
+#include "i965_defines.h"
+#include "i965_structs.h"
+#include "i965_drv_video.h"
+#include "i965_encoder.h"
+#include "i965_encoder_util
[Libva] [PATCH V4 1/7] HEVC ENC:Added PAK context for HEVC
Signed-off-by: Qu,Pengfei
---
src/Makefile.am | 1 +
src/gen9_mfc.h | 237
2 files changed, 238 insertions(+)
create mode 100644 src/gen9_mfc.h
diff --git a/src/Makefile.am b/src/Makefile.am
index 9e54fd5..3f43809 100755
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -107,6 +107,7 @@ source_h = \
gen75_vpp_vebox.h \
gen8_post_processing.h \
gen9_mfd.h \
+ gen9_mfc.h \
i965_avc_bsd.h \
i965_avc_hw_scoreboard.h\
i965_avc_ildb.h \
diff --git a/src/gen9_mfc.h b/src/gen9_mfc.h
new file mode 100644
index 000..5db24ce
--- /dev/null
+++ b/src/gen9_mfc.h
@@ -0,0 +1,237 @@
+/*
+ * Copyright ?? 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *Qu Pengfei
+ *
+ */
+
+#ifndef _GEN9_MFC_H_
+#define _GEN9_MFC_H_
+
+#include
+#include
+#include
+
+#include "i965_gpe_utils.h"
+
+struct encode_state;
+
+#define MAX_HCP_REFERENCE_SURFACES 8
+#define NUM_HCP_CURRENT_COLLOCATED_MV_TEMPORAL_BUFFERS 9
+
+#define INTRA_MB_FLAG_MASK 0x2000
+
+/* The space required for slice header SLICE_STATE + header.
+ * Is it enough? */
+#define SLICE_HEADER80
+
+/* the space required for slice tail. */
+#define SLICE_TAIL 16
+
+#define __SOFTWARE__0
+
+#define HCP_BATCHBUFFER_HEVC_INTRA 0
+#define HCP_BATCHBUFFER_HEVC_INTER 1
+#define NUM_HCP_KERNEL 2
+
+#define BIND_IDX_VME_OUTPUT 0
+#define BIND_IDX_HCP_SLICE_HEADER 1
+#define BIND_IDX_HCP_BATCHBUFFER2
+
+#define CMD_LEN_IN_OWORD4
+
+struct gen9_hcpe_context {
+struct {
+unsigned int width;
+unsigned int height;
+unsigned int w_pitch;
+unsigned int h_pitch;
+} surface_state;
+
+//HCP_PIPE_BUF_ADDR_STATE
+
+struct {
+dri_bo *bo;
+} deblocking_filter_line_buffer;//OUTPUT: reconstructed
picture with deblocked
+
+struct {
+dri_bo *bo;
+} deblocking_filter_tile_line_buffer; //OUTPUT: reconstructed
picture with deblocked
+
+struct {
+dri_bo *bo;
+} deblocking_filter_tile_column_buffer; //OUTPUT: reconstructed
picture with deblocked
+
+struct {
+dri_bo *bo;
+} uncompressed_picture_source; //INPUT: original compressed
image
+
+struct {
+dri_bo *bo;
+} metadata_line_buffer; //INTERNAL:metadata
+
+struct {
+dri_bo *bo;
+} metadata_tile_line_buffer;//INTERNAL:metadata
+
+struct {
+dri_bo *bo;
+} metadata_tile_column_buffer; //INTERNAL:metadata
+
+struct {
+dri_bo *bo;
+} sao_line_buffer; //INTERNAL:SAO not used in skylake
+
+struct {
+dri_bo *bo;
+} sao_tile_line_buffer;//INTERNAL:SAO not used in skylake
+
+struct {
+dri_bo *bo;
+} sao_tile_column_buffer; //INTERNAL:SAO not used in skylake
+
+struct {
+dri_bo *bo;
+}
current_collocated_mv_temporal_buffer[NUM_HCP_CURRENT_COLLOCATED_MV_TEMPORAL_BUFFERS];
//
+
+struct {
+dri_bo *bo;
+} reference_surfaces[MAX_HCP_REFERENCE_SURFACES]; //INTERNAL: refrence
surfaces
+
+//HCP_IND_OBJ_BASE_ADDR_STATE
+struct {
+dri_bo *bo;
+} hcp_indirect_cu_object; //INPUT: the cu' mv info
+
+struct {
+dri_bo *bo;
+int offset;
+int end_offset;
+} hcp_indirect_pak_bse_object; //OUTPUT: the compressed bitstream
+
+//Bit rate tracking context
+struct {
+unsigned int QpPrimeY;
+unsigned int MaxQpNegModifier;
+unsigned int MaxQpPosModifier;
+unsigned ch
[Libva] [PATCH V3 5/7] HEVC ENC:Added pipeline init
Signed-off-by: Qu,Pengfei
---
src/i965_encoder.c | 74 +-
1 file changed, 73 insertions(+), 1 deletion(-)
diff --git a/src/i965_encoder.c b/src/i965_encoder.c
index d924f5a..c9ff2ec 100644
--- a/src/i965_encoder.c
+++ b/src/i965_encoder.c
@@ -39,10 +39,12 @@
#include "i965_encoder.h"
#include "gen6_vme.h"
#include "gen6_mfc.h"
+#include "gen9_mfc.h"
extern Bool gen6_mfc_context_init(VADriverContextP ctx, struct
intel_encoder_context *encoder_context);
extern Bool gen6_vme_context_init(VADriverContextP ctx, struct
intel_encoder_context *encoder_context);
extern Bool gen7_mfc_context_init(VADriverContextP ctx, struct
intel_encoder_context *encoder_context);
+extern Bool gen9_hcpe_context_init(VADriverContextP ctx, struct
intel_encoder_context *encoder_context);
static VAStatus
intel_encoder_check_yuv_surface(VADriverContextP ctx,
@@ -422,6 +424,63 @@ error:
}
static VAStatus
+intel_encoder_check_hevc_parameter(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context
*encoder_context)
+{
+struct i965_driver_data *i965 = i965_driver_data(ctx);
+struct object_surface *obj_surface;
+struct object_buffer *obj_buffer;
+VAEncPictureParameterBufferHEVC *pic_param =
(VAEncPictureParameterBufferHEVC *)encode_state->pic_param_ext->buffer;
+int i;
+
+assert(!(pic_param->decoded_curr_pic.flags & VA_PICTURE_HEVC_INVALID));
+
+if (pic_param->decoded_curr_pic.flags & VA_PICTURE_HEVC_INVALID)
+goto error;
+
+obj_surface = SURFACE(pic_param->decoded_curr_pic.picture_id);
+assert(obj_surface); /* It is possible the store buffer isn't allocated
yet */
+
+if (!obj_surface)
+goto error;
+
+encode_state->reconstructed_object = obj_surface;
+obj_buffer = BUFFER(pic_param->coded_buf);
+assert(obj_buffer && obj_buffer->buffer_store &&
obj_buffer->buffer_store->bo);
+
+if (!obj_buffer || !obj_buffer->buffer_store ||
!obj_buffer->buffer_store->bo)
+goto error;
+
+encode_state->coded_buf_object = obj_buffer;
+
+for (i = 0; i < 15; i++) {
+if (pic_param->reference_frames[i].flags & VA_PICTURE_HEVC_INVALID ||
+pic_param->reference_frames[i].picture_id == VA_INVALID_SURFACE)
+break;
+else {
+obj_surface = SURFACE(pic_param->reference_frames[i].picture_id);
+assert(obj_surface);
+
+if (!obj_surface)
+goto error;
+
+if (obj_surface->bo)
+encode_state->reference_objects[i] = obj_surface;
+else
+encode_state->reference_objects[i] = NULL; /* FIXME: Warning
or Error ??? */
+}
+}
+
+for ( ; i < 15; i++)
+encode_state->reference_objects[i] = NULL;
+
+return VA_STATUS_SUCCESS;
+
+error:
+return VA_STATUS_ERROR_INVALID_PARAMETER;
+}
+static VAStatus
intel_encoder_sanity_check_input(VADriverContextP ctx,
VAProfile profile,
struct encode_state *encode_state,
@@ -459,6 +518,13 @@ intel_encoder_sanity_check_input(VADriverContextP ctx,
break;
}
+case VAProfileHEVCMain: {
+vaStatus = intel_encoder_check_hevc_parameter(ctx, encode_state,
encoder_context);
+if (vaStatus != VA_STATUS_SUCCESS)
+goto out;
+vaStatus = intel_encoder_check_yuv_surface(ctx, profile, encode_state,
encoder_context);
+break;
+}
default:
vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
break;
@@ -554,6 +620,10 @@ intel_enc_hw_context_init(VADriverContextP ctx,
encoder_context->codec = CODEC_JPEG;
break;
+case VAProfileHEVCMain:
+encoder_context->codec = CODEC_HEVC;
+break;
+
default:
/* Never get here */
assert(0);
@@ -617,7 +687,9 @@ gen8_enc_hw_context_init(VADriverContextP ctx, struct
object_config *obj_config)
struct hw_context *
gen9_enc_hw_context_init(VADriverContextP ctx, struct object_config
*obj_config)
{
-if (obj_config->profile == VAProfileJPEGBaseline)
+if (obj_config->profile == VAProfileHEVCMain) {
+return intel_enc_hw_context_init(ctx, obj_config,
gen9_vme_context_init, gen9_hcpe_context_init);
+} else if (obj_config->profile == VAProfileJPEGBaseline)
return intel_enc_hw_context_init(ctx, obj_config,
gen8_vme_context_init, gen8_mfc_context_init);
else
return intel_enc_hw_context_init(ctx, obj_config,
gen9_vme_context_init, gen9_mfc_context_init);
--
1.9.1
___
Libva mailing list
Libva@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/libva
[Libva] [PATCH V3 2/7] HEVC ENC:Added slice header generated internally
Signed-off-by: Qu,Pengfei
---
src/i965_drv_video.h | 15 +-
src/i965_encoder_utils.c | 457 +++
src/i965_encoder_utils.h | 29 +++
3 files changed, 499 insertions(+), 2 deletions(-)
diff --git a/src/i965_drv_video.h b/src/i965_drv_video.h
index cb4e8e8..90a7100 100644
--- a/src/i965_drv_video.h
+++ b/src/i965_drv_video.h
@@ -33,6 +33,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -150,8 +151,8 @@ struct encode_state
/* for ext */
struct buffer_store *seq_param_ext;
struct buffer_store *pic_param_ext;
-struct buffer_store *packed_header_param[4];
-struct buffer_store *packed_header_data[4];
+struct buffer_store *packed_header_param[5];
+struct buffer_store *packed_header_data[5];
struct buffer_store **slice_params_ext;
int max_slice_params_ext;
int num_slice_params_ext;
@@ -171,6 +172,8 @@ struct encode_state
int max_packed_header_data_ext;
int num_packed_header_data_ext;
+/* the index of current vps and sps ,special for HEVC*/
+int vps_sps_seq_index;
/* the index of current slice */
int slice_index;
/* the array is determined by max_slice_params_ext */
@@ -370,6 +373,7 @@ struct hw_codec_info
unsigned int has_vp8_encoding:1;
unsigned int has_h264_mvc_encoding:1;
unsigned int has_hevc_decoding:1;
+unsigned int has_hevc_encoding:1;
unsigned int num_filters;
struct i965_filter filters[VAProcFilterCount];
@@ -454,6 +458,7 @@ va_enc_packed_type_to_idx(int packed_type);
#define CODEC_MPEG2 1
#define CODEC_H264_MVC 2
#define CODEC_JPEG 3
+#define CODEC_HEVC 4
#define H264_DELIMITER0 0x00
#define H264_DELIMITER1 0x00
@@ -467,6 +472,12 @@ va_enc_packed_type_to_idx(int packed_type);
#define MPEG2_DELIMITER30x00
#define MPEG2_DELIMITER40xb0
+#define HEVC_DELIMITER0 0x00
+#define HEVC_DELIMITER1 0x00
+#define HEVC_DELIMITER2 0x00
+#define HEVC_DELIMITER3 0x00
+#define HEVC_DELIMITER4 0x00
+
struct i965_coded_buffer_segment
{
VACodedBufferSegment base;
diff --git a/src/i965_encoder_utils.c b/src/i965_encoder_utils.c
index e59e7fb..3cb624b 100644
--- a/src/i965_encoder_utils.c
+++ b/src/i965_encoder_utils.c
@@ -29,6 +29,7 @@
#include
#include
#include
+#include
#include "i965_encoder_utils.h"
@@ -62,6 +63,17 @@
#define PROFILE_IDC_MAIN77
#define PROFILE_IDC_HIGH100
+/*HEVC*/
+#define VPS_NUT32
+#define SPS_NUT33
+#define PPS_NUT34
+#define IDR_WRADL_NUT 19
+#define IDR_NLP_NUT20
+#define SLICE_TRAIL_N_NUT 0
+#define SLICE_TRAIL_R_NUT 1
+#define PREFIX_SEI_NUT 39
+#define SUFFIX_SEI_NUT 40
+
struct __avc_bitstream {
unsigned int *buffer;
int bit_offset;
@@ -562,3 +574,448 @@
build_avc_mvc_slice_header(VAEncSequenceParameterBufferH264_MVC *mvc_sps_param,
return bs.bit_offset;
}
+
+/* HEVC to do for internal header generated*/
+
+void nal_header_hevc(avc_bitstream *bs, int nal_unit_type, int temporalid)
+{
+/* forbidden_zero_bit: 0 */
+avc_bitstream_put_ui(bs, 0, 1);
+/* nal unit_type */
+avc_bitstream_put_ui(bs, nal_unit_type, 6);
+/* layer_id. currently it is zero */
+avc_bitstream_put_ui(bs, 0, 6);
+/* teporalid + 1 .*/
+avc_bitstream_put_ui(bs, temporalid + 1, 3);
+}
+
+int build_hevc_sei_buffering_period(int init_cpb_removal_delay_length,
+unsigned int init_cpb_removal_delay,
+unsigned int init_cpb_removal_delay_offset,
+unsigned char **sei_buffer)
+{
+unsigned char *byte_buf;
+int bp_byte_size, i;
+//unsigned int cpb_removal_delay;
+
+avc_bitstream nal_bs;
+avc_bitstream sei_bp_bs;
+
+avc_bitstream_start(&sei_bp_bs);
+avc_bitstream_put_ue(&sei_bp_bs, 0); /*seq_parameter_set_id*/
+/* SEI buffer period info */
+/* NALHrdBpPresentFlag == 1 */
+avc_bitstream_put_ui(&sei_bp_bs,
init_cpb_removal_delay,init_cpb_removal_delay_length);
+avc_bitstream_put_ui(&sei_bp_bs,
init_cpb_removal_delay_offset,init_cpb_removal_delay_length);
+if ( sei_bp_bs.bit_offset & 0x7) {
+avc_bitstream_put_ui(&sei_bp_bs, 1, 1);
+}
+avc_bitstream_end(&sei_bp_bs);
+bp_byte_size = (sei_bp_bs.bit_offset + 7) / 8;
+
+avc_bitstream_start(&nal_bs);
+nal_start_code_prefix(&nal_bs);
+nal_header_hevc(&nal_bs, PREFIX_SEI_NUT ,0);
+
+/* Write the SEI buffer period data */
+avc_bitstream_put_ui(&nal_bs, 0, 8);
+avc_bitstream_put_ui(&nal_bs, bp_byte_size, 8);
+
+byte_buf = (unsigned char *)sei_bp_bs.buffer;
+for(i = 0; i < bp_byte_size; i++) {
+avc_bitstream_put_ui(&nal_bs, byte_buf[i], 8);
+}
+free(byte_buf);
+
+avc_rbsp_trailing_bits(&nal_bs);
+avc_bitstream_end(&na
[Libva] [PATCH V3 7/7] Just Style alignment
Signed-off-by: Qu,Pengfei
---
src/gen6_mfc_common.c | 464 -
src/gen9_vme.c | 444 +++---
src/i965_device_info.c | 16 +-
src/i965_drv_video.c | 32 ++--
4 files changed, 478 insertions(+), 478 deletions(-)
diff --git a/src/gen6_mfc_common.c b/src/gen6_mfc_common.c
index 6a5f720..cc1b0e6 100644
--- a/src/gen6_mfc_common.c
+++ b/src/gen6_mfc_common.c
@@ -631,8 +631,8 @@ VAStatus intel_mfc_avc_prepare(VADriverContextP ctx,
int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
if (IS_GEN6(i965->intel.device_info)) {
- /* On the SNB it should be fixed to 128 for the DMV buffer */
- width_in_mbs = 128;
+/* On the SNB it should be fixed to 128 for the DMV buffer */
+width_in_mbs = 128;
}
for (j = 0; j < encode_state->num_slice_params_ext && enable_avc_ildb ==
0; j++) {
@@ -735,7 +735,7 @@ VAStatus intel_mfc_avc_prepare(VADriverContextP ctx,
break;
}
}
-
+
mfc_context->uncompressed_picture_source.bo =
encode_state->input_yuv_object->bo;
dri_bo_reference(mfc_context->uncompressed_picture_source.bo);
@@ -807,7 +807,7 @@ int intel_format_lutvalue(int value, int max)
if (temp1 > temp2)
ret = max;
return ret;
-
+
}
@@ -842,40 +842,40 @@ void intel_vme_update_mbmv_cost(VADriverContextP ctx,
if (encoder_context->rate_control_mode == VA_RC_CQP)
- qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
+qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
else
- qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
-
+qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
+
if (vme_state_message == NULL)
- return;
-
+return;
+
assert(qp <= QP_MAX);
lambda = intel_lambda_qp(qp);
if (slice_type == SLICE_TYPE_I) {
- vme_state_message[MODE_INTRA_16X16] = 0;
- m_cost = lambda * 4;
- vme_state_message[MODE_INTRA_8X8] = intel_format_lutvalue(m_cost, 0x8f);
- m_cost = lambda * 16;
- vme_state_message[MODE_INTRA_4X4] = intel_format_lutvalue(m_cost, 0x8f);
- m_cost = lambda * 3;
- vme_state_message[MODE_INTRA_NONPRED] = intel_format_lutvalue(m_cost,
0x6f);
+vme_state_message[MODE_INTRA_16X16] = 0;
+m_cost = lambda * 4;
+vme_state_message[MODE_INTRA_8X8] = intel_format_lutvalue(m_cost,
0x8f);
+m_cost = lambda * 16;
+vme_state_message[MODE_INTRA_4X4] = intel_format_lutvalue(m_cost,
0x8f);
+m_cost = lambda * 3;
+vme_state_message[MODE_INTRA_NONPRED] = intel_format_lutvalue(m_cost,
0x6f);
} else {
- m_cost = 0;
- vme_state_message[MODE_INTER_MV0] = intel_format_lutvalue(m_cost, 0x6f);
- for (j = 1; j < 3; j++) {
+m_cost = 0;
+vme_state_message[MODE_INTER_MV0] = intel_format_lutvalue(m_cost,
0x6f);
+for (j = 1; j < 3; j++) {
m_costf = (log2f((float)(j + 1)) + 1.718f) * lambda;
m_cost = (int)m_costf;
vme_state_message[MODE_INTER_MV0 + j] =
intel_format_lutvalue(m_cost, 0x6f);
- }
- mv_count = 3;
- for (j = 4; j <= 64; j *= 2) {
+}
+mv_count = 3;
+for (j = 4; j <= 64; j *= 2) {
m_costf = (log2f((float)(j + 1)) + 1.718f) * lambda;
m_cost = (int)m_costf;
vme_state_message[MODE_INTER_MV0 + mv_count] =
intel_format_lutvalue(m_cost, 0x6f);
mv_count++;
- }
+}
- if (qp <= 25) {
+if (qp <= 25) {
vme_state_message[MODE_INTRA_16X16] = 0x4a;
vme_state_message[MODE_INTRA_8X8] = 0x4a;
vme_state_message[MODE_INTRA_4X4] = 0x4a;
@@ -887,17 +887,17 @@ void intel_vme_update_mbmv_cost(VADriverContextP ctx,
vme_state_message[MODE_INTER_4X4] = 0x4a;
vme_state_message[MODE_INTER_BWD] = 0x2a;
return;
- }
- m_costf = lambda * 10;
- vme_state_message[MODE_INTRA_16X16] = intel_format_lutvalue(m_cost,
0x8f);
- m_cost = lambda * 14;
- vme_state_message[MODE_INTRA_8X8] = intel_format_lutvalue(m_cost, 0x8f);
- m_cost = lambda * 24;
- vme_state_message[MODE_INTRA_4X4] = intel_format_lutvalue(m_cost, 0x8f);
- m_costf = lambda * 3.5;
- m_cost = m_costf;
- vme_state_message[MODE_INTRA_NONPRED] = intel_format_lutvalue(m_cost,
0x6f);
- if (slice_type == SLICE_TYPE_P) {
+}
+m_costf = lambda * 10;
+vme_state_message[MODE_INTRA_16X16] = intel_format_lutvalue(m_cost,
0x8f);
+m_cost = lambda * 14;
+vme_state_message[MODE_INTRA_8X8] = intel_format_lutvalue(m_cost,
0x8f);
+m_cost = lambda * 24;
+vme_state_message[MODE_INTRA_4X4] = intel_for
[Libva] [PATCH V3 3/7] HEVC ENC:Added PAK pipeline
Signed-off-by: Qu,Pengfei
---
src/Makefile.am |1 +
src/gen9_mfc_hevc.c | 2628 +++
2 files changed, 2629 insertions(+)
create mode 100644 src/gen9_mfc_hevc.c
diff --git a/src/Makefile.am b/src/Makefile.am
index 3f43809..880d386 100755
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -64,6 +64,7 @@ source_c = \
gen8_vme.c \
gen9_vme.c \
gen9_mfc.c \
+ gen9_mfc_hevc.c \
gen9_mfd.c \
gen75_picture_process.c \
gen75_vme.c \
diff --git a/src/gen9_mfc_hevc.c b/src/gen9_mfc_hevc.c
new file mode 100644
index 000..480fe1c
--- /dev/null
+++ b/src/gen9_mfc_hevc.c
@@ -0,0 +1,2628 @@
+/*
+ * Copyright ?? 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *Qu Pengfei
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "intel_batchbuffer.h"
+#include "i965_defines.h"
+#include "i965_structs.h"
+#include "i965_drv_video.h"
+#include "i965_encoder.h"
+#include "i965_encoder_utils.h"
+#include "gen9_mfc.h"
+#include "gen6_vme.h"
+#include "intel_media.h"
+
+typedef enum _gen6_brc_status {
+BRC_NO_HRD_VIOLATION = 0,
+BRC_UNDERFLOW = 1,
+BRC_OVERFLOW = 2,
+BRC_UNDERFLOW_WITH_MAX_QP = 3,
+BRC_OVERFLOW_WITH_MIN_QP = 4,
+} gen6_brc_status;
+
+/* BRC define */
+#define BRC_CLIP(x, min, max) \
+{ \
+x = ((x > (max)) ? (max) : ((x < (min)) ? (min) : x)); \
+}
+
+#define BRC_P_B_QP_DIFF 4
+#define BRC_I_P_QP_DIFF 2
+#define BRC_I_B_QP_DIFF (BRC_I_P_QP_DIFF + BRC_P_B_QP_DIFF)
+
+#define BRC_PWEIGHT 0.6 /* weight if P slice with comparison to I slice */
+#define BRC_BWEIGHT 0.25 /* weight if B slice with comparison to I slice */
+
+#define BRC_QP_MAX_CHANGE 5 /* maximum qp modification */
+#define BRC_CY 0.1 /* weight for */
+#define BRC_CX_UNDERFLOW 5.
+#define BRC_CX_OVERFLOW -4.
+
+#define BRC_PI_0_5 1.5707963267948966192313216916398
+
+/* intel buffer write */
+#define ALLOC_ENCODER_BUFFER(gen_buffer, string, size) do { \
+dri_bo_unreference(gen_buffer->bo); \
+gen_buffer->bo = dri_bo_alloc(i965->intel.bufmgr, \
+ string, \
+ size, \
+ 0x1000); \
+assert(gen_buffer->bo); \
+} while (0);
+
+
+#define OUT_BUFFER_X(buf_bo, is_target, ma) do { \
+if (buf_bo) { \
+OUT_BCS_RELOC(batch,\
+ buf_bo, \
+ I915_GEM_DOMAIN_INSTRUCTION, \
+ is_target ? I915_GEM_DOMAIN_INSTRUCTION : 0, \
+ 0); \
+} else {\
+OUT_BCS_BATCH(batch, 0);\
+} \
+OUT_BCS_BATCH(batch, 0);\
+if (ma) \
+OUT_BCS_BATCH(batch, 0);\
+} while (0)
+
+#define OUT_BUFFER_MA_TARGET(buf_bo) OUT_BUFFER_X(buf_bo, 1, 1)
+#define OUT_BUFFER_MA_REFERENCE(buf_bo)OUT_BUFFER
[Libva] [PATCH V3 6/7] HEVC ENC:Added HEVC support in API function
Signed-off-by: Qu,Pengfei
---
src/i965_device_info.c | 1 +
src/i965_drv_video.c | 121 +
2 files changed, 103 insertions(+), 19 deletions(-)
diff --git a/src/i965_device_info.c b/src/i965_device_info.c
index d03aceb..9ccc85e 100755
--- a/src/i965_device_info.c
+++ b/src/i965_device_info.c
@@ -347,6 +347,7 @@ static struct hw_codec_info skl_hw_codec_info = {
.has_blending = 1,
.has_h264_mvc_encoding = 1,
.has_hevc_decoding = 1,
+.has_hevc_encoding = 1,
.num_filters = 5,
.filters = {
diff --git a/src/i965_drv_video.c b/src/i965_drv_video.c
index 74895da..ca9703b 100644
--- a/src/i965_drv_video.c
+++ b/src/i965_drv_video.c
@@ -104,6 +104,9 @@
#define HAS_HEVC_DECODING(ctx) ((ctx)->codec_info->has_hevc_decoding
&& \
(ctx)->intel.has_bsd)
+#define HAS_HEVC_ENCODING(ctx) ((ctx)->codec_info->has_hevc_encoding
&& \
+ (ctx)->intel.has_bsd)
+
static int get_sampling_from_fourcc(unsigned int fourcc);
/* Check whether we are rendering to X11 (VA/X11 or VA/GLX API) */
@@ -376,7 +379,10 @@ is_image_busy(struct i965_driver_data *i965, struct
object_image *obj_image)
}
#define I965_PACKED_HEADER_BASE 0
-#define I965_PACKED_MISC_HEADER_BASE3
+#define I965_SEQ_PACKED_HEADER_BASE 0
+#define I965_SEQ_PACKED_HEADER_END 2
+#define I965_PIC_PACKED_HEADER_BASE 2
+#define I965_PACKED_MISC_HEADER_BASE4
int
va_enc_packed_type_to_idx(int packed_type)
@@ -393,15 +399,15 @@ va_enc_packed_type_to_idx(int packed_type)
switch (packed_type) {
case VAEncPackedHeaderSequence:
-idx = I965_PACKED_HEADER_BASE + 0;
+idx = I965_SEQ_PACKED_HEADER_BASE + 0;
break;
case VAEncPackedHeaderPicture:
-idx = I965_PACKED_HEADER_BASE + 1;
+idx = I965_PIC_PACKED_HEADER_BASE + 0;
break;
case VAEncPackedHeaderSlice:
-idx = I965_PACKED_HEADER_BASE + 2;
+idx = I965_PIC_PACKED_HEADER_BASE + 1;
break;
default:
@@ -411,7 +417,7 @@ va_enc_packed_type_to_idx(int packed_type)
}
}
-ASSERT_RET(idx < 4, 0);
+ASSERT_RET(idx < 5, 0);
return idx;
}
@@ -465,7 +471,8 @@ i965_QueryConfigProfiles(VADriverContextP ctx,
profile_list[i++] = VAProfileH264StereoHigh;
}
-if (HAS_HEVC_DECODING(i965)) {
+if (HAS_HEVC_DECODING(i965)||
+HAS_HEVC_ENCODING(i965)) {
profile_list[i++] = VAProfileHEVCMain;
}
@@ -548,6 +555,9 @@ i965_QueryConfigEntrypoints(VADriverContextP ctx,
if (HAS_HEVC_DECODING(i965))
entrypoint_list[n++] = VAEntrypointVLD;
+if (HAS_HEVC_ENCODING(i965))
+entrypoint_list[n++] = VAEntrypointEncSlice;
+
break;
default:
@@ -639,7 +649,8 @@ i965_validate_config(VADriverContextP ctx, VAProfile
profile,
break;
case VAProfileHEVCMain:
-if (HAS_HEVC_DECODING(i965) && (entrypoint == VAEntrypointVLD))
+if ((HAS_HEVC_DECODING(i965) && (entrypoint == VAEntrypointVLD))||
+(HAS_HEVC_ENCODING(i965) && (entrypoint == VAEntrypointEncSlice)))
va_status = VA_STATUS_SUCCESS;
else
va_status = VA_STATUS_ERROR_UNSUPPORTED_ENTRYPOINT;
@@ -729,7 +740,8 @@ i965_GetConfigAttributes(VADriverContextP ctx,
profile == VAProfileH264Main ||
profile == VAProfileH264High ||
profile == VAProfileH264StereoHigh ||
-profile == VAProfileH264MultiviewHigh) {
+profile == VAProfileH264MultiviewHigh ||
+profile == VAProfileHEVCMain) {
attrib_list[i].value |= (VA_ENC_PACKED_HEADER_RAW_DATA |
VA_ENC_PACKED_HEADER_SLICE);
}
@@ -1894,6 +1906,8 @@ i965_CreateContext(VADriverContextP ctx,
obj_context->codec_state.encode.slice_header_index =
calloc(obj_context->codec_state.encode.max_slice_num,
sizeof(int));
+obj_context->codec_state.encode.vps_sps_seq_index = 0;
+
obj_context->codec_state.encode.slice_index = 0;
packed_attrib = i965_lookup_config_attribute(obj_config,
VAConfigAttribEncPackedHeaders);
if (packed_attrib)
@@ -1980,6 +1994,20 @@ i965_create_buffer_internal(VADriverContextP ctx,
struct object_buffer *obj_buffer = NULL;
struct buffer_store *buffer_store = NULL;
int bufferID;
+struct object_context *obj_context = NULL;
+struct object_config *obj_config = NULL;
+VAStatus vaStatus = VA_STATUS_ERROR_UNKNOWN;
+
+if (i965->current_context_id == VA_INVALID_ID)
+return vaStatus;
+
+obj_context = CONTE
[Libva] [PATCH V3 0/7] HEVC encoder summary
V1-->V2: 1.add the style alignment patch 2.seperate the files into different patch and ensure building successfully. V2-->V3: 1.re-order the PATCH to ensure HEVC entrypoint/profile query in the last commit. 2.seperate file src/i965_encoder.c from the"VME pipeline" patch and as an independent patch. HEVC enc feature??? 1.LCU size is 16x16 only 2.Min CU size is 16x16 only 3.Transform size 16x16~8x8 4.I/P/B frame enabled. 5.Constant QP only Qu,Pengfei (7): HEVC ENC:Added PAK context for HEVC HEVC ENC:Added slice header generated internally HEVC ENC:Added PAK pipeline HEVC ENC:Added VME pipeline HEVC ENC:Added pipeline init HEVC ENC:Added HEVC support in API function Just Style alignment src/Makefile.am |2 + src/gen6_mfc_common.c| 686 src/gen6_vme.h | 19 + src/gen9_mfc.h | 288 + src/gen9_mfc_hevc.c | 2628 ++ src/gen9_vme.c | 928 src/i965_device_info.c | 17 +- src/i965_drv_video.c | 151 ++- src/i965_drv_video.h | 15 +- src/i965_encoder.c | 74 +- src/i965_encoder_utils.c | 457 src/i965_encoder_utils.h | 29 + 12 files changed, 4795 insertions(+), 499 deletions(-) create mode 100644 src/gen9_mfc.h create mode 100644 src/gen9_mfc_hevc.c -- 1.9.1 ___ Libva mailing list Libva@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/libva
[Libva] [PATCH V3 4/7] HEVC ENC:Added VME pipeline
Signed-off-by: Qu,Pengfei
---
src/gen6_mfc_common.c | 222 +++
src/gen6_vme.h| 19 ++
src/gen9_vme.c| 484 ++
3 files changed, 725 insertions(+)
diff --git a/src/gen6_mfc_common.c b/src/gen6_mfc_common.c
index fe41dac..6a5f720 100644
--- a/src/gen6_mfc_common.c
+++ b/src/gen6_mfc_common.c
@@ -1652,3 +1652,225 @@ void
intel_avc_slice_insert_packed_data(VADriverContextP ctx,
return;
}
+/* HEVC */
+static int
+hevc_temporal_find_surface(VAPictureHEVC *curr_pic,
+ VAPictureHEVC *ref_list,
+ int num_pictures,
+ int dir)
+{
+int i, found = -1, min = 0x7FFF;
+
+for (i = 0; i < num_pictures; i++) {
+int tmp;
+
+if ((ref_list[i].flags & VA_PICTURE_HEVC_INVALID) ||
+(ref_list[i].picture_id == VA_INVALID_SURFACE))
+break;
+
+tmp = curr_pic->pic_order_cnt - ref_list[i].pic_order_cnt;
+
+if (dir)
+tmp = -tmp;
+
+if (tmp > 0 && tmp < min) {
+min = tmp;
+found = i;
+}
+}
+
+return found;
+}
+void
+intel_hevc_vme_reference_state(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context,
+ int list_index,
+ int surface_index,
+ void (* vme_source_surface_state)(
+ VADriverContextP ctx,
+ int index,
+ struct object_surface *obj_surface,
+ struct intel_encoder_context
*encoder_context))
+{
+struct gen6_vme_context *vme_context = encoder_context->vme_context;
+struct object_surface *obj_surface = NULL;
+struct i965_driver_data *i965 = i965_driver_data(ctx);
+VASurfaceID ref_surface_id;
+VAEncPictureParameterBufferHEVC *pic_param =
(VAEncPictureParameterBufferHEVC *)encode_state->pic_param_ext->buffer;
+VAEncSliceParameterBufferHEVC *slice_param =
(VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[0]->buffer;
+int max_num_references;
+VAPictureHEVC *curr_pic;
+VAPictureHEVC *ref_list;
+int ref_idx;
+
+if (list_index == 0) {
+max_num_references = pic_param->num_ref_idx_l0_default_active_minus1 +
1;
+ref_list = slice_param->ref_pic_list0;
+} else {
+max_num_references = pic_param->num_ref_idx_l1_default_active_minus1 +
1;
+ref_list = slice_param->ref_pic_list1;
+}
+
+if (max_num_references == 1) {
+if (list_index == 0) {
+ref_surface_id = slice_param->ref_pic_list0[0].picture_id;
+vme_context->used_references[0] = &slice_param->ref_pic_list0[0];
+} else {
+ref_surface_id = slice_param->ref_pic_list1[0].picture_id;
+vme_context->used_references[1] = &slice_param->ref_pic_list1[0];
+}
+
+if (ref_surface_id != VA_INVALID_SURFACE)
+obj_surface = SURFACE(ref_surface_id);
+
+if (!obj_surface ||
+!obj_surface->bo) {
+obj_surface = encode_state->reference_objects[list_index];
+vme_context->used_references[list_index] =
&pic_param->reference_frames[list_index];
+}
+
+ref_idx = 0;
+} else {
+curr_pic = &pic_param->decoded_curr_pic;
+
+/* select the reference frame in temporal space */
+ref_idx = hevc_temporal_find_surface(curr_pic, ref_list,
max_num_references, list_index == 1);
+ref_surface_id = ref_list[ref_idx].picture_id;
+
+if (ref_surface_id != VA_INVALID_SURFACE) /* otherwise warning later */
+obj_surface = SURFACE(ref_surface_id);
+
+vme_context->used_reference_objects[list_index] = obj_surface;
+vme_context->used_references[list_index] = &ref_list[ref_idx];
+}
+
+if (obj_surface &&
+obj_surface->bo) {
+assert(ref_idx >= 0);
+vme_context->used_reference_objects[list_index] = obj_surface;
+vme_source_surface_state(ctx, surface_index, obj_surface,
encoder_context);
+vme_context->ref_index_in_mb[list_index] = (ref_idx << 24 |
+ref_idx << 16 |
+ref_idx << 8 |
+ref_idx);
+} else {
+vme_context->used_reference_objects[list_index] = NULL;
+vme_context->used_references[list_index] = NULL;
+vme_context->ref_index_in_mb[list_index] = 0;
+}
+}
+
+void intel_vme_hevc_update_mbmv_cost(VADriverContextP ctx,
+ struct encode_state *encode_state,
+
[Libva] [PATCH V3 1/7] HEVC ENC:Added PAK context for HEVC
Signed-off-by: Qu,Pengfei
---
src/Makefile.am | 1 +
src/gen9_mfc.h | 288
2 files changed, 289 insertions(+)
create mode 100644 src/gen9_mfc.h
diff --git a/src/Makefile.am b/src/Makefile.am
index 9e54fd5..3f43809 100755
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -107,6 +107,7 @@ source_h = \
gen75_vpp_vebox.h \
gen8_post_processing.h \
gen9_mfd.h \
+ gen9_mfc.h \
i965_avc_bsd.h \
i965_avc_hw_scoreboard.h\
i965_avc_ildb.h \
diff --git a/src/gen9_mfc.h b/src/gen9_mfc.h
new file mode 100644
index 000..9630039
--- /dev/null
+++ b/src/gen9_mfc.h
@@ -0,0 +1,288 @@
+/*
+ * Copyright ?? 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *Qu Pengfei
+ *
+ */
+
+#ifndef _GEN9_HCP_H_
+#define _GEN9_HCP_H_
+
+#include
+#include
+#include
+
+#include "i965_gpe_utils.h"
+
+struct encode_state;
+
+#define MAX_HCP_REFERENCE_SURFACES 8
+#define NUM_HCP_CURRENT_COLLOCATED_MV_TEMPORAL_BUFFERS 9
+
+#define INTRA_MB_FLAG_MASK 0x2000
+
+/* The space required for slice header SLICE_STATE + header.
+ * Is it enough? */
+#define SLICE_HEADER80
+
+/* the space required for slice tail. */
+#define SLICE_TAIL 16
+
+#define __SOFTWARE__0
+
+#define HCP_BATCHBUFFER_HEVC_INTRA 0
+#define HCP_BATCHBUFFER_HEVC_INTER 1
+#define NUM_HCP_KERNEL 2
+
+#define BIND_IDX_VME_OUTPUT 0
+#define BIND_IDX_HCP_SLICE_HEADER 1
+#define BIND_IDX_HCP_BATCHBUFFER2
+
+#define CMD_LEN_IN_OWORD4
+
+struct gen9_hcpe_context {
+struct {
+unsigned int width;
+unsigned int height;
+unsigned int w_pitch;
+unsigned int h_pitch;
+} surface_state;
+
+//HCP_PIPE_BUF_ADDR_STATE
+
+struct {
+dri_bo *bo;
+} deblocking_filter_line_buffer;//OUTPUT: reconstructed
picture with deblocked
+
+struct {
+dri_bo *bo;
+} deblocking_filter_tile_line_buffer; //OUTPUT: reconstructed
picture with deblocked
+
+struct {
+dri_bo *bo;
+} deblocking_filter_tile_column_buffer; //OUTPUT: reconstructed
picture with deblocked
+
+struct {
+dri_bo *bo;
+} uncompressed_picture_source; //INPUT: original compressed
image
+
+struct {
+dri_bo *bo;
+} metadata_line_buffer; //INTERNAL:metadata
+
+struct {
+dri_bo *bo;
+} metadata_tile_line_buffer;//INTERNAL:metadata
+
+struct {
+dri_bo *bo;
+} metadata_tile_column_buffer; //INTERNAL:metadata
+
+struct {
+dri_bo *bo;
+} sao_line_buffer; //INTERNAL:SAO not used in skylake
+
+struct {
+dri_bo *bo;
+} sao_tile_line_buffer;//INTERNAL:SAO not used in skylake
+
+struct {
+dri_bo *bo;
+} sao_tile_column_buffer; //INTERNAL:SAO not used in skylake
+
+struct {
+dri_bo *bo;
+}
current_collocated_mv_temporal_buffer[NUM_HCP_CURRENT_COLLOCATED_MV_TEMPORAL_BUFFERS];
//
+
+struct {
+dri_bo *bo;
+} reference_surfaces[MAX_HCP_REFERENCE_SURFACES]; //INTERNAL: refrence
surfaces
+
+//HCP_IND_OBJ_BASE_ADDR_STATE
+struct {
+dri_bo *bo;
+} hcp_indirect_cu_object; //INPUT: the cu' mv info
+
+struct {
+dri_bo *bo;
+int offset;
+int end_offset;
+} hcp_indirect_pak_bse_object; //OUTPUT: the compressed bitstream
+
+//Bit rate tracking context
+struct {
+unsigned int QpPrimeY;
+unsigned int MaxQpNegModifier;
+unsigned int MaxQpPosModifier;
+unsigned ch
Re: [Libva] [PATCH V2 1/6] HEVC ENC:Added PAK context for HEVC
I will not change this patch.
-Original Message-
From: Zhao, Yakui
Sent: Wednesday, January 7, 2015 9:11 AM
To: Qu, Pengfei
Cc: libva@lists.freedesktop.org
Subject: Re: [Libva] [PATCH V2 1/6] HEVC ENC:Added PAK context for HEVC
On Tue, 2015-01-06 at 01:57 -0700, Qu,Pengfei wrote:
> Signed-off-by: Qu,Pengfei
> ---
> src/Makefile.am | 1 +
> src/gen9_mfc.h | 288
>
> 2 files changed, 289 insertions(+)
> create mode 100644 src/gen9_mfc.h
>
> diff --git a/src/Makefile.am b/src/Makefile.am index 9e54fd5..3f43809
> 100755
> --- a/src/Makefile.am
> +++ b/src/Makefile.am
> @@ -107,6 +107,7 @@ source_h = \
> gen75_vpp_vebox.h \
> gen8_post_processing.h \
> gen9_mfd.h \
> + gen9_mfc.h \
> i965_avc_bsd.h \
> i965_avc_hw_scoreboard.h\
> i965_avc_ildb.h \
> diff --git a/src/gen9_mfc.h b/src/gen9_mfc.h new file mode 100644
> index 000..9630039
> --- /dev/null
> +++ b/src/gen9_mfc.h
> @@ -0,0 +1,288 @@
> +/*
> + * Copyright © 2014 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person
> +obtaining a
> + * copy of this software and associated documentation files (the
> + * "Software"), to deal in the Software without restriction,
> +including
> + * without limitation the rights to use, copy, modify, merge,
> +publish,
> + * distribute, sub license, and/or sell copies of the Software, and
> +to
> + * permit persons to whom the Software is furnished to do so, subject
> +to
> + * the following conditions:
> + *
> + * The above copyright notice and this permission notice (including
> +the
> + * next paragraph) shall be included in all copies or substantial
> +portions
> + * of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> +EXPRESS
> + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
> + * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE
> +FOR
> + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
> +CONTRACT,
> + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
> + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
> + *
> + * Authors:
> + *Qu Pengfei
> + *
> + */
> +
> +#ifndef _GEN9_HCP_H_
> +#define _GEN9_HCP_H_
> +
> +#include
> +#include
> +#include
> +
> +#include "i965_gpe_utils.h"
> +
> +struct encode_state;
> +
> +#define MAX_HCP_REFERENCE_SURFACES 8
> +#define NUM_HCP_CURRENT_COLLOCATED_MV_TEMPORAL_BUFFERS 9
> +
> +#define INTRA_MB_FLAG_MASK 0x2000
> +
> +/* The space required for slice header SLICE_STATE + header.
> + * Is it enough? */
> +#define SLICE_HEADER80
> +
> +/* the space required for slice tail. */
> +#define SLICE_TAIL 16
> +
> +#define __SOFTWARE__0
> +
> +#define HCP_BATCHBUFFER_HEVC_INTRA 0
> +#define HCP_BATCHBUFFER_HEVC_INTER 1
> +#define NUM_HCP_KERNEL 2
> +
> +#define BIND_IDX_VME_OUTPUT 0
> +#define BIND_IDX_HCP_SLICE_HEADER 1
> +#define BIND_IDX_HCP_BATCHBUFFER2
> +
> +#define CMD_LEN_IN_OWORD4
> +
> +struct gen9_hcpe_context {
> +struct {
> +unsigned int width;
> +unsigned int height;
> +unsigned int w_pitch;
> +unsigned int h_pitch;
> +} surface_state;
> +
> +//HCP_PIPE_BUF_ADDR_STATE
> +
> +struct {
> +dri_bo *bo;
> +} deblocking_filter_line_buffer;//OUTPUT: reconstructed
> picture with deblocked
> +
> +struct {
> +dri_bo *bo;
> +} deblocking_filter_tile_line_buffer; //OUTPUT: reconstructed
> picture with deblocked
> +
> +struct {
> +dri_bo *bo;
> +} deblocking_filter_tile_column_buffer; //OUTPUT: reconstructed
> picture with deblocked
> +
> +struct {
> +dri_bo *bo;
> +} uncompressed_picture_source; //INPUT: original compressed
> image
> +
> +struct {
> +dri_bo *bo;
> +} metadata_line_buffer; //INTERNAL:metadata
> +
> +struct {
> +dri_bo *bo;
> +} metadata_tile_line_buffer;//INTERNAL:metadata
> +
> +struct {
> +dri_bo *bo;
> +} metadata_tile_column_buffer; //INTERNAL:metadata
> +
> +struct {
> +dri_bo *bo;
> +} sao_line_buffer;
Re: [Libva] [PATCH V2 3/6] HEVC ENC:Added HEVC support in API function
Sure, I will try to adjust the patch order again.
-Original Message-
From: Zhao, Yakui
Sent: Wednesday, January 7, 2015 9:21 AM
To: Qu, Pengfei
Cc: libva@lists.freedesktop.org
Subject: Re: [Libva] [PATCH V2 3/6] HEVC ENC:Added HEVC support in API function
On Tue, 2015-01-06 at 01:57 -0700, Qu,Pengfei wrote:
Not sure whether the HEVC encoding profile is exported earlier than the
low-level implementation?
If the subsequent patches are not applied, maybe user-space app queries the
entrypoint for HEVC encoding and then try to use it. In such case it doesn't
work at all.
How about exporting the HEVC encoding profile/entrypoint after the low-level
implementations are already added?
> Signed-off-by: Qu,Pengfei
> ---
> src/i965_device_info.c | 1 +
> src/i965_drv_video.c | 121
> +
> 2 files changed, 103 insertions(+), 19 deletions(-)
>
> diff --git a/src/i965_device_info.c b/src/i965_device_info.c index
> d03aceb..9ccc85e 100755
> --- a/src/i965_device_info.c
> +++ b/src/i965_device_info.c
> @@ -347,6 +347,7 @@ static struct hw_codec_info skl_hw_codec_info = {
> .has_blending = 1,
> .has_h264_mvc_encoding = 1,
> .has_hevc_decoding = 1,
> +.has_hevc_encoding = 1,
>
> .num_filters = 5,
> .filters = {
> diff --git a/src/i965_drv_video.c b/src/i965_drv_video.c index
> 74895da..ca9703b 100644
> --- a/src/i965_drv_video.c
> +++ b/src/i965_drv_video.c
> @@ -104,6 +104,9 @@
> #define HAS_HEVC_DECODING(ctx)
> ((ctx)->codec_info->has_hevc_decoding && \
> (ctx)->intel.has_bsd)
>
> +#define HAS_HEVC_ENCODING(ctx)
> ((ctx)->codec_info->has_hevc_encoding && \
> + (ctx)->intel.has_bsd)
> +
> static int get_sampling_from_fourcc(unsigned int fourcc);
>
> /* Check whether we are rendering to X11 (VA/X11 or VA/GLX API) */ @@
> -376,7 +379,10 @@ is_image_busy(struct i965_driver_data *i965, struct
> object_image *obj_image) }
>
> #define I965_PACKED_HEADER_BASE 0
> -#define I965_PACKED_MISC_HEADER_BASE3
> +#define I965_SEQ_PACKED_HEADER_BASE 0
> +#define I965_SEQ_PACKED_HEADER_END 2
> +#define I965_PIC_PACKED_HEADER_BASE 2
> +#define I965_PACKED_MISC_HEADER_BASE4
>
> int
> va_enc_packed_type_to_idx(int packed_type) @@ -393,15 +399,15 @@
> va_enc_packed_type_to_idx(int packed_type)
>
> switch (packed_type) {
> case VAEncPackedHeaderSequence:
> -idx = I965_PACKED_HEADER_BASE + 0;
> +idx = I965_SEQ_PACKED_HEADER_BASE + 0;
> break;
>
> case VAEncPackedHeaderPicture:
> -idx = I965_PACKED_HEADER_BASE + 1;
> +idx = I965_PIC_PACKED_HEADER_BASE + 0;
> break;
>
> case VAEncPackedHeaderSlice:
> -idx = I965_PACKED_HEADER_BASE + 2;
> +idx = I965_PIC_PACKED_HEADER_BASE + 1;
> break;
>
> default:
> @@ -411,7 +417,7 @@ va_enc_packed_type_to_idx(int packed_type)
> }
> }
>
> -ASSERT_RET(idx < 4, 0);
> +ASSERT_RET(idx < 5, 0);
> return idx;
> }
>
> @@ -465,7 +471,8 @@ i965_QueryConfigProfiles(VADriverContextP ctx,
> profile_list[i++] = VAProfileH264StereoHigh;
> }
>
> -if (HAS_HEVC_DECODING(i965)) {
> +if (HAS_HEVC_DECODING(i965)||
> +HAS_HEVC_ENCODING(i965)) {
> profile_list[i++] = VAProfileHEVCMain;
> }
>
> @@ -548,6 +555,9 @@ i965_QueryConfigEntrypoints(VADriverContextP ctx,
> if (HAS_HEVC_DECODING(i965))
> entrypoint_list[n++] = VAEntrypointVLD;
>
> +if (HAS_HEVC_ENCODING(i965))
> +entrypoint_list[n++] = VAEntrypointEncSlice;
> +
> break;
>
> default:
> @@ -639,7 +649,8 @@ i965_validate_config(VADriverContextP ctx, VAProfile
> profile,
> break;
>
> case VAProfileHEVCMain:
> -if (HAS_HEVC_DECODING(i965) && (entrypoint == VAEntrypointVLD))
> +if ((HAS_HEVC_DECODING(i965) && (entrypoint == VAEntrypointVLD))||
> +(HAS_HEVC_ENCODING(i965) && (entrypoint ==
> + VAEntrypointEncSlice)))
> va_status = VA_STATUS_SUCCESS;
> else
> va_status = VA_STATUS_ERROR_UNSUPPORTED_ENTRYPOINT;
> @@ -729,7 +740,8 @@ i965_GetConfigAttributes(VADriverContextP ctx,
> profile == VAProfileH264Main ||
> profile == VAProfileH264High ||
> profile == VAProfileH264StereoHigh ||
&
Re: [Libva] [PATCH V2 5/6] HEVC ENC:Added VME pipeline
Sure, I will put src/i965_encoder.c into an independent patch.
-Original Message-
From: Zhao, Yakui
Sent: Wednesday, January 7, 2015 9:16 AM
To: Qu, Pengfei
Cc: libva@lists.freedesktop.org
Subject: Re: [Libva] [PATCH V2 5/6] HEVC ENC:Added VME pipeline
On Tue, 2015-01-06 at 01:57 -0700, Qu,Pengfei wrote:
It seems that this patch also mixes the VME pipeline setting up and
initialization of intel_enc_hw_context_init together.
Can it be split into two patches?
> Signed-off-by: Qu,Pengfei
> ---
> src/gen6_mfc_common.c | 222 +++
> src/gen6_vme.h| 19 ++
> src/gen9_vme.c| 484
> ++
> src/i965_encoder.c| 74 +++-
> 4 files changed, 798 insertions(+), 1 deletion(-)
>
> diff --git a/src/gen6_mfc_common.c b/src/gen6_mfc_common.c index
> fe41dac..6a5f720 100644
> --- a/src/gen6_mfc_common.c
> +++ b/src/gen6_mfc_common.c
> @@ -1652,3 +1652,225 @@ void
> intel_avc_slice_insert_packed_data(VADriverContextP ctx,
> return;
> }
>
> +/* HEVC */
> +static int
> +hevc_temporal_find_surface(VAPictureHEVC *curr_pic,
> + VAPictureHEVC *ref_list,
> + int num_pictures,
> + int dir)
> +{
> +int i, found = -1, min = 0x7FFF;
> +
> +for (i = 0; i < num_pictures; i++) {
> +int tmp;
> +
> +if ((ref_list[i].flags & VA_PICTURE_HEVC_INVALID) ||
> +(ref_list[i].picture_id == VA_INVALID_SURFACE))
> +break;
> +
> +tmp = curr_pic->pic_order_cnt - ref_list[i].pic_order_cnt;
> +
> +if (dir)
> +tmp = -tmp;
> +
> +if (tmp > 0 && tmp < min) {
> +min = tmp;
> +found = i;
> +}
> +}
> +
> +return found;
> +}
> +void
> +intel_hevc_vme_reference_state(VADriverContextP ctx,
> + struct encode_state *encode_state,
> + struct intel_encoder_context *encoder_context,
> + int list_index,
> + int surface_index,
> + void (* vme_source_surface_state)(
> + VADriverContextP ctx,
> + int index,
> + struct object_surface *obj_surface,
> + struct intel_encoder_context
> +*encoder_context)) {
> +struct gen6_vme_context *vme_context = encoder_context->vme_context;
> +struct object_surface *obj_surface = NULL;
> +struct i965_driver_data *i965 = i965_driver_data(ctx);
> +VASurfaceID ref_surface_id;
> +VAEncPictureParameterBufferHEVC *pic_param =
> (VAEncPictureParameterBufferHEVC *)encode_state->pic_param_ext->buffer;
> +VAEncSliceParameterBufferHEVC *slice_param =
> (VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[0]->buffer;
> +int max_num_references;
> +VAPictureHEVC *curr_pic;
> +VAPictureHEVC *ref_list;
> +int ref_idx;
> +
> +if (list_index == 0) {
> +max_num_references = pic_param->num_ref_idx_l0_default_active_minus1
> + 1;
> +ref_list = slice_param->ref_pic_list0;
> +} else {
> +max_num_references = pic_param->num_ref_idx_l1_default_active_minus1
> + 1;
> +ref_list = slice_param->ref_pic_list1;
> +}
> +
> +if (max_num_references == 1) {
> +if (list_index == 0) {
> +ref_surface_id = slice_param->ref_pic_list0[0].picture_id;
> +vme_context->used_references[0] = &slice_param->ref_pic_list0[0];
> +} else {
> +ref_surface_id = slice_param->ref_pic_list1[0].picture_id;
> +vme_context->used_references[1] = &slice_param->ref_pic_list1[0];
> +}
> +
> +if (ref_surface_id != VA_INVALID_SURFACE)
> +obj_surface = SURFACE(ref_surface_id);
> +
> +if (!obj_surface ||
> +!obj_surface->bo) {
> +obj_surface = encode_state->reference_objects[list_index];
> +vme_context->used_references[list_index] =
> &pic_param->reference_frames[list_index];
> +}
> +
> +ref_idx = 0;
> +} else {
> +curr_pic = &pic_param->decoded_curr_pic;
> +
> +/* select the reference frame in temporal space */
> +ref_idx = hevc_temporal_find_surface(curr_pic, ref_list,
> max_num_references, list_index == 1);
> +ref_surface_id = ref_list[ref_idx].picture_id;
> +
> +if (ref
[Libva] [PATCH V2 4/6] HEVC ENC:Added PAK pipeline
Signed-off-by: Qu,Pengfei
---
src/Makefile.am |1 +
src/gen9_mfc_hevc.c | 2628 +++
2 files changed, 2629 insertions(+)
create mode 100644 src/gen9_mfc_hevc.c
diff --git a/src/Makefile.am b/src/Makefile.am
index 3f43809..880d386 100755
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -64,6 +64,7 @@ source_c = \
gen8_vme.c \
gen9_vme.c \
gen9_mfc.c \
+ gen9_mfc_hevc.c \
gen9_mfd.c \
gen75_picture_process.c \
gen75_vme.c \
diff --git a/src/gen9_mfc_hevc.c b/src/gen9_mfc_hevc.c
new file mode 100644
index 000..480fe1c
--- /dev/null
+++ b/src/gen9_mfc_hevc.c
@@ -0,0 +1,2628 @@
+/*
+ * Copyright ?? 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *Qu Pengfei
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "intel_batchbuffer.h"
+#include "i965_defines.h"
+#include "i965_structs.h"
+#include "i965_drv_video.h"
+#include "i965_encoder.h"
+#include "i965_encoder_utils.h"
+#include "gen9_mfc.h"
+#include "gen6_vme.h"
+#include "intel_media.h"
+
+typedef enum _gen6_brc_status {
+BRC_NO_HRD_VIOLATION = 0,
+BRC_UNDERFLOW = 1,
+BRC_OVERFLOW = 2,
+BRC_UNDERFLOW_WITH_MAX_QP = 3,
+BRC_OVERFLOW_WITH_MIN_QP = 4,
+} gen6_brc_status;
+
+/* BRC define */
+#define BRC_CLIP(x, min, max) \
+{ \
+x = ((x > (max)) ? (max) : ((x < (min)) ? (min) : x)); \
+}
+
+#define BRC_P_B_QP_DIFF 4
+#define BRC_I_P_QP_DIFF 2
+#define BRC_I_B_QP_DIFF (BRC_I_P_QP_DIFF + BRC_P_B_QP_DIFF)
+
+#define BRC_PWEIGHT 0.6 /* weight if P slice with comparison to I slice */
+#define BRC_BWEIGHT 0.25 /* weight if B slice with comparison to I slice */
+
+#define BRC_QP_MAX_CHANGE 5 /* maximum qp modification */
+#define BRC_CY 0.1 /* weight for */
+#define BRC_CX_UNDERFLOW 5.
+#define BRC_CX_OVERFLOW -4.
+
+#define BRC_PI_0_5 1.5707963267948966192313216916398
+
+/* intel buffer write */
+#define ALLOC_ENCODER_BUFFER(gen_buffer, string, size) do { \
+dri_bo_unreference(gen_buffer->bo); \
+gen_buffer->bo = dri_bo_alloc(i965->intel.bufmgr, \
+ string, \
+ size, \
+ 0x1000); \
+assert(gen_buffer->bo); \
+} while (0);
+
+
+#define OUT_BUFFER_X(buf_bo, is_target, ma) do { \
+if (buf_bo) { \
+OUT_BCS_RELOC(batch,\
+ buf_bo, \
+ I915_GEM_DOMAIN_INSTRUCTION, \
+ is_target ? I915_GEM_DOMAIN_INSTRUCTION : 0, \
+ 0); \
+} else {\
+OUT_BCS_BATCH(batch, 0);\
+} \
+OUT_BCS_BATCH(batch, 0);\
+if (ma) \
+OUT_BCS_BATCH(batch, 0);\
+} while (0)
+
+#define OUT_BUFFER_MA_TARGET(buf_bo) OUT_BUFFER_X(buf_bo, 1, 1)
+#define OUT_BUFFER_MA_REFERENCE(buf_bo)OUT_BUFFER
[Libva] [PATCH V2 1/6] HEVC ENC:Added PAK context for HEVC
Signed-off-by: Qu,Pengfei
---
src/Makefile.am | 1 +
src/gen9_mfc.h | 288
2 files changed, 289 insertions(+)
create mode 100644 src/gen9_mfc.h
diff --git a/src/Makefile.am b/src/Makefile.am
index 9e54fd5..3f43809 100755
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -107,6 +107,7 @@ source_h = \
gen75_vpp_vebox.h \
gen8_post_processing.h \
gen9_mfd.h \
+ gen9_mfc.h \
i965_avc_bsd.h \
i965_avc_hw_scoreboard.h\
i965_avc_ildb.h \
diff --git a/src/gen9_mfc.h b/src/gen9_mfc.h
new file mode 100644
index 000..9630039
--- /dev/null
+++ b/src/gen9_mfc.h
@@ -0,0 +1,288 @@
+/*
+ * Copyright ?? 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *Qu Pengfei
+ *
+ */
+
+#ifndef _GEN9_HCP_H_
+#define _GEN9_HCP_H_
+
+#include
+#include
+#include
+
+#include "i965_gpe_utils.h"
+
+struct encode_state;
+
+#define MAX_HCP_REFERENCE_SURFACES 8
+#define NUM_HCP_CURRENT_COLLOCATED_MV_TEMPORAL_BUFFERS 9
+
+#define INTRA_MB_FLAG_MASK 0x2000
+
+/* The space required for slice header SLICE_STATE + header.
+ * Is it enough? */
+#define SLICE_HEADER80
+
+/* the space required for slice tail. */
+#define SLICE_TAIL 16
+
+#define __SOFTWARE__0
+
+#define HCP_BATCHBUFFER_HEVC_INTRA 0
+#define HCP_BATCHBUFFER_HEVC_INTER 1
+#define NUM_HCP_KERNEL 2
+
+#define BIND_IDX_VME_OUTPUT 0
+#define BIND_IDX_HCP_SLICE_HEADER 1
+#define BIND_IDX_HCP_BATCHBUFFER2
+
+#define CMD_LEN_IN_OWORD4
+
+struct gen9_hcpe_context {
+struct {
+unsigned int width;
+unsigned int height;
+unsigned int w_pitch;
+unsigned int h_pitch;
+} surface_state;
+
+//HCP_PIPE_BUF_ADDR_STATE
+
+struct {
+dri_bo *bo;
+} deblocking_filter_line_buffer;//OUTPUT: reconstructed
picture with deblocked
+
+struct {
+dri_bo *bo;
+} deblocking_filter_tile_line_buffer; //OUTPUT: reconstructed
picture with deblocked
+
+struct {
+dri_bo *bo;
+} deblocking_filter_tile_column_buffer; //OUTPUT: reconstructed
picture with deblocked
+
+struct {
+dri_bo *bo;
+} uncompressed_picture_source; //INPUT: original compressed
image
+
+struct {
+dri_bo *bo;
+} metadata_line_buffer; //INTERNAL:metadata
+
+struct {
+dri_bo *bo;
+} metadata_tile_line_buffer;//INTERNAL:metadata
+
+struct {
+dri_bo *bo;
+} metadata_tile_column_buffer; //INTERNAL:metadata
+
+struct {
+dri_bo *bo;
+} sao_line_buffer; //INTERNAL:SAO not used in skylake
+
+struct {
+dri_bo *bo;
+} sao_tile_line_buffer;//INTERNAL:SAO not used in skylake
+
+struct {
+dri_bo *bo;
+} sao_tile_column_buffer; //INTERNAL:SAO not used in skylake
+
+struct {
+dri_bo *bo;
+}
current_collocated_mv_temporal_buffer[NUM_HCP_CURRENT_COLLOCATED_MV_TEMPORAL_BUFFERS];
//
+
+struct {
+dri_bo *bo;
+} reference_surfaces[MAX_HCP_REFERENCE_SURFACES]; //INTERNAL: refrence
surfaces
+
+//HCP_IND_OBJ_BASE_ADDR_STATE
+struct {
+dri_bo *bo;
+} hcp_indirect_cu_object; //INPUT: the cu' mv info
+
+struct {
+dri_bo *bo;
+int offset;
+int end_offset;
+} hcp_indirect_pak_bse_object; //OUTPUT: the compressed bitstream
+
+//Bit rate tracking context
+struct {
+unsigned int QpPrimeY;
+unsigned int MaxQpNegModifier;
+unsigned int MaxQpPosModifier;
+unsigned ch
[Libva] [PATCH V2 6/6] it is just style alignment
Signed-off-by: Qu,Pengfei
---
src/gen6_mfc_common.c | 464 -
src/gen9_vme.c | 444 +++---
src/i965_device_info.c | 16 +-
src/i965_drv_video.c | 32 ++--
4 files changed, 478 insertions(+), 478 deletions(-)
diff --git a/src/gen6_mfc_common.c b/src/gen6_mfc_common.c
index 6a5f720..cc1b0e6 100644
--- a/src/gen6_mfc_common.c
+++ b/src/gen6_mfc_common.c
@@ -631,8 +631,8 @@ VAStatus intel_mfc_avc_prepare(VADriverContextP ctx,
int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
if (IS_GEN6(i965->intel.device_info)) {
- /* On the SNB it should be fixed to 128 for the DMV buffer */
- width_in_mbs = 128;
+/* On the SNB it should be fixed to 128 for the DMV buffer */
+width_in_mbs = 128;
}
for (j = 0; j < encode_state->num_slice_params_ext && enable_avc_ildb ==
0; j++) {
@@ -735,7 +735,7 @@ VAStatus intel_mfc_avc_prepare(VADriverContextP ctx,
break;
}
}
-
+
mfc_context->uncompressed_picture_source.bo =
encode_state->input_yuv_object->bo;
dri_bo_reference(mfc_context->uncompressed_picture_source.bo);
@@ -807,7 +807,7 @@ int intel_format_lutvalue(int value, int max)
if (temp1 > temp2)
ret = max;
return ret;
-
+
}
@@ -842,40 +842,40 @@ void intel_vme_update_mbmv_cost(VADriverContextP ctx,
if (encoder_context->rate_control_mode == VA_RC_CQP)
- qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
+qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
else
- qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
-
+qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
+
if (vme_state_message == NULL)
- return;
-
+return;
+
assert(qp <= QP_MAX);
lambda = intel_lambda_qp(qp);
if (slice_type == SLICE_TYPE_I) {
- vme_state_message[MODE_INTRA_16X16] = 0;
- m_cost = lambda * 4;
- vme_state_message[MODE_INTRA_8X8] = intel_format_lutvalue(m_cost, 0x8f);
- m_cost = lambda * 16;
- vme_state_message[MODE_INTRA_4X4] = intel_format_lutvalue(m_cost, 0x8f);
- m_cost = lambda * 3;
- vme_state_message[MODE_INTRA_NONPRED] = intel_format_lutvalue(m_cost,
0x6f);
+vme_state_message[MODE_INTRA_16X16] = 0;
+m_cost = lambda * 4;
+vme_state_message[MODE_INTRA_8X8] = intel_format_lutvalue(m_cost,
0x8f);
+m_cost = lambda * 16;
+vme_state_message[MODE_INTRA_4X4] = intel_format_lutvalue(m_cost,
0x8f);
+m_cost = lambda * 3;
+vme_state_message[MODE_INTRA_NONPRED] = intel_format_lutvalue(m_cost,
0x6f);
} else {
- m_cost = 0;
- vme_state_message[MODE_INTER_MV0] = intel_format_lutvalue(m_cost, 0x6f);
- for (j = 1; j < 3; j++) {
+m_cost = 0;
+vme_state_message[MODE_INTER_MV0] = intel_format_lutvalue(m_cost,
0x6f);
+for (j = 1; j < 3; j++) {
m_costf = (log2f((float)(j + 1)) + 1.718f) * lambda;
m_cost = (int)m_costf;
vme_state_message[MODE_INTER_MV0 + j] =
intel_format_lutvalue(m_cost, 0x6f);
- }
- mv_count = 3;
- for (j = 4; j <= 64; j *= 2) {
+}
+mv_count = 3;
+for (j = 4; j <= 64; j *= 2) {
m_costf = (log2f((float)(j + 1)) + 1.718f) * lambda;
m_cost = (int)m_costf;
vme_state_message[MODE_INTER_MV0 + mv_count] =
intel_format_lutvalue(m_cost, 0x6f);
mv_count++;
- }
+}
- if (qp <= 25) {
+if (qp <= 25) {
vme_state_message[MODE_INTRA_16X16] = 0x4a;
vme_state_message[MODE_INTRA_8X8] = 0x4a;
vme_state_message[MODE_INTRA_4X4] = 0x4a;
@@ -887,17 +887,17 @@ void intel_vme_update_mbmv_cost(VADriverContextP ctx,
vme_state_message[MODE_INTER_4X4] = 0x4a;
vme_state_message[MODE_INTER_BWD] = 0x2a;
return;
- }
- m_costf = lambda * 10;
- vme_state_message[MODE_INTRA_16X16] = intel_format_lutvalue(m_cost,
0x8f);
- m_cost = lambda * 14;
- vme_state_message[MODE_INTRA_8X8] = intel_format_lutvalue(m_cost, 0x8f);
- m_cost = lambda * 24;
- vme_state_message[MODE_INTRA_4X4] = intel_format_lutvalue(m_cost, 0x8f);
- m_costf = lambda * 3.5;
- m_cost = m_costf;
- vme_state_message[MODE_INTRA_NONPRED] = intel_format_lutvalue(m_cost,
0x6f);
- if (slice_type == SLICE_TYPE_P) {
+}
+m_costf = lambda * 10;
+vme_state_message[MODE_INTRA_16X16] = intel_format_lutvalue(m_cost,
0x8f);
+m_cost = lambda * 14;
+vme_state_message[MODE_INTRA_8X8] = intel_format_lutvalue(m_cost,
0x8f);
+m_cost = lambda * 24;
+vme_state_message[MODE_INTRA_4X4] = intel_for
[Libva] [PATCH V2 5/6] HEVC ENC:Added VME pipeline
Signed-off-by: Qu,Pengfei
---
src/gen6_mfc_common.c | 222 +++
src/gen6_vme.h| 19 ++
src/gen9_vme.c| 484 ++
src/i965_encoder.c| 74 +++-
4 files changed, 798 insertions(+), 1 deletion(-)
diff --git a/src/gen6_mfc_common.c b/src/gen6_mfc_common.c
index fe41dac..6a5f720 100644
--- a/src/gen6_mfc_common.c
+++ b/src/gen6_mfc_common.c
@@ -1652,3 +1652,225 @@ void
intel_avc_slice_insert_packed_data(VADriverContextP ctx,
return;
}
+/* HEVC */
+static int
+hevc_temporal_find_surface(VAPictureHEVC *curr_pic,
+ VAPictureHEVC *ref_list,
+ int num_pictures,
+ int dir)
+{
+int i, found = -1, min = 0x7FFF;
+
+for (i = 0; i < num_pictures; i++) {
+int tmp;
+
+if ((ref_list[i].flags & VA_PICTURE_HEVC_INVALID) ||
+(ref_list[i].picture_id == VA_INVALID_SURFACE))
+break;
+
+tmp = curr_pic->pic_order_cnt - ref_list[i].pic_order_cnt;
+
+if (dir)
+tmp = -tmp;
+
+if (tmp > 0 && tmp < min) {
+min = tmp;
+found = i;
+}
+}
+
+return found;
+}
+void
+intel_hevc_vme_reference_state(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context,
+ int list_index,
+ int surface_index,
+ void (* vme_source_surface_state)(
+ VADriverContextP ctx,
+ int index,
+ struct object_surface *obj_surface,
+ struct intel_encoder_context
*encoder_context))
+{
+struct gen6_vme_context *vme_context = encoder_context->vme_context;
+struct object_surface *obj_surface = NULL;
+struct i965_driver_data *i965 = i965_driver_data(ctx);
+VASurfaceID ref_surface_id;
+VAEncPictureParameterBufferHEVC *pic_param =
(VAEncPictureParameterBufferHEVC *)encode_state->pic_param_ext->buffer;
+VAEncSliceParameterBufferHEVC *slice_param =
(VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[0]->buffer;
+int max_num_references;
+VAPictureHEVC *curr_pic;
+VAPictureHEVC *ref_list;
+int ref_idx;
+
+if (list_index == 0) {
+max_num_references = pic_param->num_ref_idx_l0_default_active_minus1 +
1;
+ref_list = slice_param->ref_pic_list0;
+} else {
+max_num_references = pic_param->num_ref_idx_l1_default_active_minus1 +
1;
+ref_list = slice_param->ref_pic_list1;
+}
+
+if (max_num_references == 1) {
+if (list_index == 0) {
+ref_surface_id = slice_param->ref_pic_list0[0].picture_id;
+vme_context->used_references[0] = &slice_param->ref_pic_list0[0];
+} else {
+ref_surface_id = slice_param->ref_pic_list1[0].picture_id;
+vme_context->used_references[1] = &slice_param->ref_pic_list1[0];
+}
+
+if (ref_surface_id != VA_INVALID_SURFACE)
+obj_surface = SURFACE(ref_surface_id);
+
+if (!obj_surface ||
+!obj_surface->bo) {
+obj_surface = encode_state->reference_objects[list_index];
+vme_context->used_references[list_index] =
&pic_param->reference_frames[list_index];
+}
+
+ref_idx = 0;
+} else {
+curr_pic = &pic_param->decoded_curr_pic;
+
+/* select the reference frame in temporal space */
+ref_idx = hevc_temporal_find_surface(curr_pic, ref_list,
max_num_references, list_index == 1);
+ref_surface_id = ref_list[ref_idx].picture_id;
+
+if (ref_surface_id != VA_INVALID_SURFACE) /* otherwise warning later */
+obj_surface = SURFACE(ref_surface_id);
+
+vme_context->used_reference_objects[list_index] = obj_surface;
+vme_context->used_references[list_index] = &ref_list[ref_idx];
+}
+
+if (obj_surface &&
+obj_surface->bo) {
+assert(ref_idx >= 0);
+vme_context->used_reference_objects[list_index] = obj_surface;
+vme_source_surface_state(ctx, surface_index, obj_surface,
encoder_context);
+vme_context->ref_index_in_mb[list_index] = (ref_idx << 24 |
+ref_idx << 16 |
+ref_idx << 8 |
+ref_idx);
+} else {
+vme_context->used_reference_objects[list_index] = NULL;
+vme_context->used_references[list_index] = NULL;
+vme_context->ref_index_in_mb[list_index] = 0;
+}
+}
+
+void intel_vme_hevc_update_mbmv_cost(VADriverContextP ctx,
+ struct enc
[Libva] [PATCH V2 2/6] HEVC ENC:Added slice header generated internally
Signed-off-by: Qu,Pengfei
---
src/i965_drv_video.h | 15 +-
src/i965_encoder_utils.c | 457 +++
src/i965_encoder_utils.h | 29 +++
3 files changed, 499 insertions(+), 2 deletions(-)
diff --git a/src/i965_drv_video.h b/src/i965_drv_video.h
index cb4e8e8..90a7100 100644
--- a/src/i965_drv_video.h
+++ b/src/i965_drv_video.h
@@ -33,6 +33,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -150,8 +151,8 @@ struct encode_state
/* for ext */
struct buffer_store *seq_param_ext;
struct buffer_store *pic_param_ext;
-struct buffer_store *packed_header_param[4];
-struct buffer_store *packed_header_data[4];
+struct buffer_store *packed_header_param[5];
+struct buffer_store *packed_header_data[5];
struct buffer_store **slice_params_ext;
int max_slice_params_ext;
int num_slice_params_ext;
@@ -171,6 +172,8 @@ struct encode_state
int max_packed_header_data_ext;
int num_packed_header_data_ext;
+/* the index of current vps and sps ,special for HEVC*/
+int vps_sps_seq_index;
/* the index of current slice */
int slice_index;
/* the array is determined by max_slice_params_ext */
@@ -370,6 +373,7 @@ struct hw_codec_info
unsigned int has_vp8_encoding:1;
unsigned int has_h264_mvc_encoding:1;
unsigned int has_hevc_decoding:1;
+unsigned int has_hevc_encoding:1;
unsigned int num_filters;
struct i965_filter filters[VAProcFilterCount];
@@ -454,6 +458,7 @@ va_enc_packed_type_to_idx(int packed_type);
#define CODEC_MPEG2 1
#define CODEC_H264_MVC 2
#define CODEC_JPEG 3
+#define CODEC_HEVC 4
#define H264_DELIMITER0 0x00
#define H264_DELIMITER1 0x00
@@ -467,6 +472,12 @@ va_enc_packed_type_to_idx(int packed_type);
#define MPEG2_DELIMITER30x00
#define MPEG2_DELIMITER40xb0
+#define HEVC_DELIMITER0 0x00
+#define HEVC_DELIMITER1 0x00
+#define HEVC_DELIMITER2 0x00
+#define HEVC_DELIMITER3 0x00
+#define HEVC_DELIMITER4 0x00
+
struct i965_coded_buffer_segment
{
VACodedBufferSegment base;
diff --git a/src/i965_encoder_utils.c b/src/i965_encoder_utils.c
index e59e7fb..3cb624b 100644
--- a/src/i965_encoder_utils.c
+++ b/src/i965_encoder_utils.c
@@ -29,6 +29,7 @@
#include
#include
#include
+#include
#include "i965_encoder_utils.h"
@@ -62,6 +63,17 @@
#define PROFILE_IDC_MAIN77
#define PROFILE_IDC_HIGH100
+/*HEVC*/
+#define VPS_NUT32
+#define SPS_NUT33
+#define PPS_NUT34
+#define IDR_WRADL_NUT 19
+#define IDR_NLP_NUT20
+#define SLICE_TRAIL_N_NUT 0
+#define SLICE_TRAIL_R_NUT 1
+#define PREFIX_SEI_NUT 39
+#define SUFFIX_SEI_NUT 40
+
struct __avc_bitstream {
unsigned int *buffer;
int bit_offset;
@@ -562,3 +574,448 @@
build_avc_mvc_slice_header(VAEncSequenceParameterBufferH264_MVC *mvc_sps_param,
return bs.bit_offset;
}
+
+/* HEVC to do for internal header generated*/
+
+void nal_header_hevc(avc_bitstream *bs, int nal_unit_type, int temporalid)
+{
+/* forbidden_zero_bit: 0 */
+avc_bitstream_put_ui(bs, 0, 1);
+/* nal unit_type */
+avc_bitstream_put_ui(bs, nal_unit_type, 6);
+/* layer_id. currently it is zero */
+avc_bitstream_put_ui(bs, 0, 6);
+/* teporalid + 1 .*/
+avc_bitstream_put_ui(bs, temporalid + 1, 3);
+}
+
+int build_hevc_sei_buffering_period(int init_cpb_removal_delay_length,
+unsigned int init_cpb_removal_delay,
+unsigned int init_cpb_removal_delay_offset,
+unsigned char **sei_buffer)
+{
+unsigned char *byte_buf;
+int bp_byte_size, i;
+//unsigned int cpb_removal_delay;
+
+avc_bitstream nal_bs;
+avc_bitstream sei_bp_bs;
+
+avc_bitstream_start(&sei_bp_bs);
+avc_bitstream_put_ue(&sei_bp_bs, 0); /*seq_parameter_set_id*/
+/* SEI buffer period info */
+/* NALHrdBpPresentFlag == 1 */
+avc_bitstream_put_ui(&sei_bp_bs,
init_cpb_removal_delay,init_cpb_removal_delay_length);
+avc_bitstream_put_ui(&sei_bp_bs,
init_cpb_removal_delay_offset,init_cpb_removal_delay_length);
+if ( sei_bp_bs.bit_offset & 0x7) {
+avc_bitstream_put_ui(&sei_bp_bs, 1, 1);
+}
+avc_bitstream_end(&sei_bp_bs);
+bp_byte_size = (sei_bp_bs.bit_offset + 7) / 8;
+
+avc_bitstream_start(&nal_bs);
+nal_start_code_prefix(&nal_bs);
+nal_header_hevc(&nal_bs, PREFIX_SEI_NUT ,0);
+
+/* Write the SEI buffer period data */
+avc_bitstream_put_ui(&nal_bs, 0, 8);
+avc_bitstream_put_ui(&nal_bs, bp_byte_size, 8);
+
+byte_buf = (unsigned char *)sei_bp_bs.buffer;
+for(i = 0; i < bp_byte_size; i++) {
+avc_bitstream_put_ui(&nal_bs, byte_buf[i], 8);
+}
+free(byte_buf);
+
+avc_rbsp_trailing_bits(&nal_bs);
+avc_bitstream_end(&na
[Libva] [PATCH V2 3/6] HEVC ENC:Added HEVC support in API function
Signed-off-by: Qu,Pengfei
---
src/i965_device_info.c | 1 +
src/i965_drv_video.c | 121 +
2 files changed, 103 insertions(+), 19 deletions(-)
diff --git a/src/i965_device_info.c b/src/i965_device_info.c
index d03aceb..9ccc85e 100755
--- a/src/i965_device_info.c
+++ b/src/i965_device_info.c
@@ -347,6 +347,7 @@ static struct hw_codec_info skl_hw_codec_info = {
.has_blending = 1,
.has_h264_mvc_encoding = 1,
.has_hevc_decoding = 1,
+.has_hevc_encoding = 1,
.num_filters = 5,
.filters = {
diff --git a/src/i965_drv_video.c b/src/i965_drv_video.c
index 74895da..ca9703b 100644
--- a/src/i965_drv_video.c
+++ b/src/i965_drv_video.c
@@ -104,6 +104,9 @@
#define HAS_HEVC_DECODING(ctx) ((ctx)->codec_info->has_hevc_decoding
&& \
(ctx)->intel.has_bsd)
+#define HAS_HEVC_ENCODING(ctx) ((ctx)->codec_info->has_hevc_encoding
&& \
+ (ctx)->intel.has_bsd)
+
static int get_sampling_from_fourcc(unsigned int fourcc);
/* Check whether we are rendering to X11 (VA/X11 or VA/GLX API) */
@@ -376,7 +379,10 @@ is_image_busy(struct i965_driver_data *i965, struct
object_image *obj_image)
}
#define I965_PACKED_HEADER_BASE 0
-#define I965_PACKED_MISC_HEADER_BASE3
+#define I965_SEQ_PACKED_HEADER_BASE 0
+#define I965_SEQ_PACKED_HEADER_END 2
+#define I965_PIC_PACKED_HEADER_BASE 2
+#define I965_PACKED_MISC_HEADER_BASE4
int
va_enc_packed_type_to_idx(int packed_type)
@@ -393,15 +399,15 @@ va_enc_packed_type_to_idx(int packed_type)
switch (packed_type) {
case VAEncPackedHeaderSequence:
-idx = I965_PACKED_HEADER_BASE + 0;
+idx = I965_SEQ_PACKED_HEADER_BASE + 0;
break;
case VAEncPackedHeaderPicture:
-idx = I965_PACKED_HEADER_BASE + 1;
+idx = I965_PIC_PACKED_HEADER_BASE + 0;
break;
case VAEncPackedHeaderSlice:
-idx = I965_PACKED_HEADER_BASE + 2;
+idx = I965_PIC_PACKED_HEADER_BASE + 1;
break;
default:
@@ -411,7 +417,7 @@ va_enc_packed_type_to_idx(int packed_type)
}
}
-ASSERT_RET(idx < 4, 0);
+ASSERT_RET(idx < 5, 0);
return idx;
}
@@ -465,7 +471,8 @@ i965_QueryConfigProfiles(VADriverContextP ctx,
profile_list[i++] = VAProfileH264StereoHigh;
}
-if (HAS_HEVC_DECODING(i965)) {
+if (HAS_HEVC_DECODING(i965)||
+HAS_HEVC_ENCODING(i965)) {
profile_list[i++] = VAProfileHEVCMain;
}
@@ -548,6 +555,9 @@ i965_QueryConfigEntrypoints(VADriverContextP ctx,
if (HAS_HEVC_DECODING(i965))
entrypoint_list[n++] = VAEntrypointVLD;
+if (HAS_HEVC_ENCODING(i965))
+entrypoint_list[n++] = VAEntrypointEncSlice;
+
break;
default:
@@ -639,7 +649,8 @@ i965_validate_config(VADriverContextP ctx, VAProfile
profile,
break;
case VAProfileHEVCMain:
-if (HAS_HEVC_DECODING(i965) && (entrypoint == VAEntrypointVLD))
+if ((HAS_HEVC_DECODING(i965) && (entrypoint == VAEntrypointVLD))||
+(HAS_HEVC_ENCODING(i965) && (entrypoint == VAEntrypointEncSlice)))
va_status = VA_STATUS_SUCCESS;
else
va_status = VA_STATUS_ERROR_UNSUPPORTED_ENTRYPOINT;
@@ -729,7 +740,8 @@ i965_GetConfigAttributes(VADriverContextP ctx,
profile == VAProfileH264Main ||
profile == VAProfileH264High ||
profile == VAProfileH264StereoHigh ||
-profile == VAProfileH264MultiviewHigh) {
+profile == VAProfileH264MultiviewHigh ||
+profile == VAProfileHEVCMain) {
attrib_list[i].value |= (VA_ENC_PACKED_HEADER_RAW_DATA |
VA_ENC_PACKED_HEADER_SLICE);
}
@@ -1894,6 +1906,8 @@ i965_CreateContext(VADriverContextP ctx,
obj_context->codec_state.encode.slice_header_index =
calloc(obj_context->codec_state.encode.max_slice_num,
sizeof(int));
+obj_context->codec_state.encode.vps_sps_seq_index = 0;
+
obj_context->codec_state.encode.slice_index = 0;
packed_attrib = i965_lookup_config_attribute(obj_config,
VAConfigAttribEncPackedHeaders);
if (packed_attrib)
@@ -1980,6 +1994,20 @@ i965_create_buffer_internal(VADriverContextP ctx,
struct object_buffer *obj_buffer = NULL;
struct buffer_store *buffer_store = NULL;
int bufferID;
+struct object_context *obj_context = NULL;
+struct object_config *obj_config = NULL;
+VAStatus vaStatus = VA_STATUS_ERROR_UNKNOWN;
+
+if (i965->current_context_id == VA_INVALID_ID)
+return vaStatus;
+
+obj_context = CONTE
[Libva] [PATCH V2 0/6] HEVC Encoder summary
V1-->V2: 1.add the style alignment patch 2.seperate the files into different patch and ensure building successfully. HEVC enc feature??? 1.LCU size is 16x16 only 2.Min CU size is 16x16 only 3.Transform size 16x16~8x8 4.I/P/B frame enabled. 5.Constant QP only Qu,Pengfei (6): HEVC ENC:Added PAK context for HEVC HEVC ENC:Added slice header generated internally HEVC ENC:Added HEVC support in API function HEVC ENC:Added PAK pipeline HEVC ENC:Added VME pipeline it is just style alignment src/Makefile.am |2 + src/gen6_mfc_common.c| 686 src/gen6_vme.h | 19 + src/gen9_mfc.h | 288 + src/gen9_mfc_hevc.c | 2628 ++ src/gen9_vme.c | 928 src/i965_device_info.c | 17 +- src/i965_drv_video.c | 151 ++- src/i965_drv_video.h | 15 +- src/i965_encoder.c | 74 +- src/i965_encoder_utils.c | 457 src/i965_encoder_utils.h | 29 + 12 files changed, 4795 insertions(+), 499 deletions(-) create mode 100644 src/gen9_mfc.h create mode 100644 src/gen9_mfc_hevc.c -- 1.9.1 ___ Libva mailing list Libva@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/libva
[Libva] [PATCH 0/6] HEVC ENCODER Summary
HEVC encoder feature: 1. LCU size is 16x16 only 2. Min CU size is 16x16 only 3. Transform size 16x16~8x8 4. I/P/B frame enabled. 5. Constant QP only Qu,Pengfei (6): HEVC ENC:Added PAK context for HEVC HEVC ENC:Added slice header generated internally HEVC ENC:Added HEVC support in API function HEVC ENC:Added PAK pipeline HEVC ENC:Added VME pipeline it is just style alignment src/Makefile.am |2 + src/gen6_mfc_common.c| 686 src/gen6_vme.h | 19 + src/gen9_mfc.h | 288 + src/gen9_mfc_hevc.c | 2628 ++ src/gen9_vme.c | 928 src/i965_device_info.c | 17 +- src/i965_drv_video.c | 151 ++- src/i965_drv_video.h | 15 +- src/i965_encoder.c | 74 +- src/i965_encoder_utils.c | 457 src/i965_encoder_utils.h | 29 + 12 files changed, 4795 insertions(+), 499 deletions(-) create mode 100644 src/gen9_mfc.h create mode 100644 src/gen9_mfc_hevc.c -- 1.9.1 ___ Libva mailing list Libva@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/libva
[Libva] [PATCH 6/6] it is just style alignment
Signed-off-by: Qu,Pengfei
---
src/gen6_mfc_common.c | 464 -
src/gen9_vme.c | 444 +++---
src/i965_device_info.c | 16 +-
src/i965_drv_video.c | 32 ++--
4 files changed, 478 insertions(+), 478 deletions(-)
diff --git a/src/gen6_mfc_common.c b/src/gen6_mfc_common.c
index 6a5f720..cc1b0e6 100644
--- a/src/gen6_mfc_common.c
+++ b/src/gen6_mfc_common.c
@@ -631,8 +631,8 @@ VAStatus intel_mfc_avc_prepare(VADriverContextP ctx,
int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
if (IS_GEN6(i965->intel.device_info)) {
- /* On the SNB it should be fixed to 128 for the DMV buffer */
- width_in_mbs = 128;
+/* On the SNB it should be fixed to 128 for the DMV buffer */
+width_in_mbs = 128;
}
for (j = 0; j < encode_state->num_slice_params_ext && enable_avc_ildb ==
0; j++) {
@@ -735,7 +735,7 @@ VAStatus intel_mfc_avc_prepare(VADriverContextP ctx,
break;
}
}
-
+
mfc_context->uncompressed_picture_source.bo =
encode_state->input_yuv_object->bo;
dri_bo_reference(mfc_context->uncompressed_picture_source.bo);
@@ -807,7 +807,7 @@ int intel_format_lutvalue(int value, int max)
if (temp1 > temp2)
ret = max;
return ret;
-
+
}
@@ -842,40 +842,40 @@ void intel_vme_update_mbmv_cost(VADriverContextP ctx,
if (encoder_context->rate_control_mode == VA_RC_CQP)
- qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
+qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
else
- qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
-
+qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
+
if (vme_state_message == NULL)
- return;
-
+return;
+
assert(qp <= QP_MAX);
lambda = intel_lambda_qp(qp);
if (slice_type == SLICE_TYPE_I) {
- vme_state_message[MODE_INTRA_16X16] = 0;
- m_cost = lambda * 4;
- vme_state_message[MODE_INTRA_8X8] = intel_format_lutvalue(m_cost, 0x8f);
- m_cost = lambda * 16;
- vme_state_message[MODE_INTRA_4X4] = intel_format_lutvalue(m_cost, 0x8f);
- m_cost = lambda * 3;
- vme_state_message[MODE_INTRA_NONPRED] = intel_format_lutvalue(m_cost,
0x6f);
+vme_state_message[MODE_INTRA_16X16] = 0;
+m_cost = lambda * 4;
+vme_state_message[MODE_INTRA_8X8] = intel_format_lutvalue(m_cost,
0x8f);
+m_cost = lambda * 16;
+vme_state_message[MODE_INTRA_4X4] = intel_format_lutvalue(m_cost,
0x8f);
+m_cost = lambda * 3;
+vme_state_message[MODE_INTRA_NONPRED] = intel_format_lutvalue(m_cost,
0x6f);
} else {
- m_cost = 0;
- vme_state_message[MODE_INTER_MV0] = intel_format_lutvalue(m_cost, 0x6f);
- for (j = 1; j < 3; j++) {
+m_cost = 0;
+vme_state_message[MODE_INTER_MV0] = intel_format_lutvalue(m_cost,
0x6f);
+for (j = 1; j < 3; j++) {
m_costf = (log2f((float)(j + 1)) + 1.718f) * lambda;
m_cost = (int)m_costf;
vme_state_message[MODE_INTER_MV0 + j] =
intel_format_lutvalue(m_cost, 0x6f);
- }
- mv_count = 3;
- for (j = 4; j <= 64; j *= 2) {
+}
+mv_count = 3;
+for (j = 4; j <= 64; j *= 2) {
m_costf = (log2f((float)(j + 1)) + 1.718f) * lambda;
m_cost = (int)m_costf;
vme_state_message[MODE_INTER_MV0 + mv_count] =
intel_format_lutvalue(m_cost, 0x6f);
mv_count++;
- }
+}
- if (qp <= 25) {
+if (qp <= 25) {
vme_state_message[MODE_INTRA_16X16] = 0x4a;
vme_state_message[MODE_INTRA_8X8] = 0x4a;
vme_state_message[MODE_INTRA_4X4] = 0x4a;
@@ -887,17 +887,17 @@ void intel_vme_update_mbmv_cost(VADriverContextP ctx,
vme_state_message[MODE_INTER_4X4] = 0x4a;
vme_state_message[MODE_INTER_BWD] = 0x2a;
return;
- }
- m_costf = lambda * 10;
- vme_state_message[MODE_INTRA_16X16] = intel_format_lutvalue(m_cost,
0x8f);
- m_cost = lambda * 14;
- vme_state_message[MODE_INTRA_8X8] = intel_format_lutvalue(m_cost, 0x8f);
- m_cost = lambda * 24;
- vme_state_message[MODE_INTRA_4X4] = intel_format_lutvalue(m_cost, 0x8f);
- m_costf = lambda * 3.5;
- m_cost = m_costf;
- vme_state_message[MODE_INTRA_NONPRED] = intel_format_lutvalue(m_cost,
0x6f);
- if (slice_type == SLICE_TYPE_P) {
+}
+m_costf = lambda * 10;
+vme_state_message[MODE_INTRA_16X16] = intel_format_lutvalue(m_cost,
0x8f);
+m_cost = lambda * 14;
+vme_state_message[MODE_INTRA_8X8] = intel_format_lutvalue(m_cost,
0x8f);
+m_cost = lambda * 24;
+vme_state_message[MODE_INTRA_4X4] = intel_for
[Libva] [PATCH 4/6] HEVC ENC:Added PAK pipeline
Signed-off-by: Qu,Pengfei
---
src/Makefile.am |1 +
src/gen9_mfc_hevc.c | 2628 +++
2 files changed, 2629 insertions(+)
create mode 100644 src/gen9_mfc_hevc.c
diff --git a/src/Makefile.am b/src/Makefile.am
index 3f43809..880d386 100755
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -64,6 +64,7 @@ source_c = \
gen8_vme.c \
gen9_vme.c \
gen9_mfc.c \
+ gen9_mfc_hevc.c \
gen9_mfd.c \
gen75_picture_process.c \
gen75_vme.c \
diff --git a/src/gen9_mfc_hevc.c b/src/gen9_mfc_hevc.c
new file mode 100644
index 000..480fe1c
--- /dev/null
+++ b/src/gen9_mfc_hevc.c
@@ -0,0 +1,2628 @@
+/*
+ * Copyright ?? 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *Qu Pengfei
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "intel_batchbuffer.h"
+#include "i965_defines.h"
+#include "i965_structs.h"
+#include "i965_drv_video.h"
+#include "i965_encoder.h"
+#include "i965_encoder_utils.h"
+#include "gen9_mfc.h"
+#include "gen6_vme.h"
+#include "intel_media.h"
+
+typedef enum _gen6_brc_status {
+BRC_NO_HRD_VIOLATION = 0,
+BRC_UNDERFLOW = 1,
+BRC_OVERFLOW = 2,
+BRC_UNDERFLOW_WITH_MAX_QP = 3,
+BRC_OVERFLOW_WITH_MIN_QP = 4,
+} gen6_brc_status;
+
+/* BRC define */
+#define BRC_CLIP(x, min, max) \
+{ \
+x = ((x > (max)) ? (max) : ((x < (min)) ? (min) : x)); \
+}
+
+#define BRC_P_B_QP_DIFF 4
+#define BRC_I_P_QP_DIFF 2
+#define BRC_I_B_QP_DIFF (BRC_I_P_QP_DIFF + BRC_P_B_QP_DIFF)
+
+#define BRC_PWEIGHT 0.6 /* weight if P slice with comparison to I slice */
+#define BRC_BWEIGHT 0.25 /* weight if B slice with comparison to I slice */
+
+#define BRC_QP_MAX_CHANGE 5 /* maximum qp modification */
+#define BRC_CY 0.1 /* weight for */
+#define BRC_CX_UNDERFLOW 5.
+#define BRC_CX_OVERFLOW -4.
+
+#define BRC_PI_0_5 1.5707963267948966192313216916398
+
+/* intel buffer write */
+#define ALLOC_ENCODER_BUFFER(gen_buffer, string, size) do { \
+dri_bo_unreference(gen_buffer->bo); \
+gen_buffer->bo = dri_bo_alloc(i965->intel.bufmgr, \
+ string, \
+ size, \
+ 0x1000); \
+assert(gen_buffer->bo); \
+} while (0);
+
+
+#define OUT_BUFFER_X(buf_bo, is_target, ma) do { \
+if (buf_bo) { \
+OUT_BCS_RELOC(batch,\
+ buf_bo, \
+ I915_GEM_DOMAIN_INSTRUCTION, \
+ is_target ? I915_GEM_DOMAIN_INSTRUCTION : 0, \
+ 0); \
+} else {\
+OUT_BCS_BATCH(batch, 0);\
+} \
+OUT_BCS_BATCH(batch, 0);\
+if (ma) \
+OUT_BCS_BATCH(batch, 0);\
+} while (0)
+
+#define OUT_BUFFER_MA_TARGET(buf_bo) OUT_BUFFER_X(buf_bo, 1, 1)
+#define OUT_BUFFER_MA_REFERENCE(buf_bo)OUT_BUFFER
[Libva] [PATCH 2/6] HEVC ENC:Added slice header generated internally
Signed-off-by: Qu,Pengfei
---
src/i965_drv_video.h | 15 +-
src/i965_encoder_utils.c | 457 +++
src/i965_encoder_utils.h | 29 +++
3 files changed, 499 insertions(+), 2 deletions(-)
diff --git a/src/i965_drv_video.h b/src/i965_drv_video.h
index cb4e8e8..90a7100 100644
--- a/src/i965_drv_video.h
+++ b/src/i965_drv_video.h
@@ -33,6 +33,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -150,8 +151,8 @@ struct encode_state
/* for ext */
struct buffer_store *seq_param_ext;
struct buffer_store *pic_param_ext;
-struct buffer_store *packed_header_param[4];
-struct buffer_store *packed_header_data[4];
+struct buffer_store *packed_header_param[5];
+struct buffer_store *packed_header_data[5];
struct buffer_store **slice_params_ext;
int max_slice_params_ext;
int num_slice_params_ext;
@@ -171,6 +172,8 @@ struct encode_state
int max_packed_header_data_ext;
int num_packed_header_data_ext;
+/* the index of current vps and sps ,special for HEVC*/
+int vps_sps_seq_index;
/* the index of current slice */
int slice_index;
/* the array is determined by max_slice_params_ext */
@@ -370,6 +373,7 @@ struct hw_codec_info
unsigned int has_vp8_encoding:1;
unsigned int has_h264_mvc_encoding:1;
unsigned int has_hevc_decoding:1;
+unsigned int has_hevc_encoding:1;
unsigned int num_filters;
struct i965_filter filters[VAProcFilterCount];
@@ -454,6 +458,7 @@ va_enc_packed_type_to_idx(int packed_type);
#define CODEC_MPEG2 1
#define CODEC_H264_MVC 2
#define CODEC_JPEG 3
+#define CODEC_HEVC 4
#define H264_DELIMITER0 0x00
#define H264_DELIMITER1 0x00
@@ -467,6 +472,12 @@ va_enc_packed_type_to_idx(int packed_type);
#define MPEG2_DELIMITER30x00
#define MPEG2_DELIMITER40xb0
+#define HEVC_DELIMITER0 0x00
+#define HEVC_DELIMITER1 0x00
+#define HEVC_DELIMITER2 0x00
+#define HEVC_DELIMITER3 0x00
+#define HEVC_DELIMITER4 0x00
+
struct i965_coded_buffer_segment
{
VACodedBufferSegment base;
diff --git a/src/i965_encoder_utils.c b/src/i965_encoder_utils.c
index e59e7fb..3cb624b 100644
--- a/src/i965_encoder_utils.c
+++ b/src/i965_encoder_utils.c
@@ -29,6 +29,7 @@
#include
#include
#include
+#include
#include "i965_encoder_utils.h"
@@ -62,6 +63,17 @@
#define PROFILE_IDC_MAIN77
#define PROFILE_IDC_HIGH100
+/*HEVC*/
+#define VPS_NUT32
+#define SPS_NUT33
+#define PPS_NUT34
+#define IDR_WRADL_NUT 19
+#define IDR_NLP_NUT20
+#define SLICE_TRAIL_N_NUT 0
+#define SLICE_TRAIL_R_NUT 1
+#define PREFIX_SEI_NUT 39
+#define SUFFIX_SEI_NUT 40
+
struct __avc_bitstream {
unsigned int *buffer;
int bit_offset;
@@ -562,3 +574,448 @@
build_avc_mvc_slice_header(VAEncSequenceParameterBufferH264_MVC *mvc_sps_param,
return bs.bit_offset;
}
+
+/* HEVC to do for internal header generated*/
+
+void nal_header_hevc(avc_bitstream *bs, int nal_unit_type, int temporalid)
+{
+/* forbidden_zero_bit: 0 */
+avc_bitstream_put_ui(bs, 0, 1);
+/* nal unit_type */
+avc_bitstream_put_ui(bs, nal_unit_type, 6);
+/* layer_id. currently it is zero */
+avc_bitstream_put_ui(bs, 0, 6);
+/* teporalid + 1 .*/
+avc_bitstream_put_ui(bs, temporalid + 1, 3);
+}
+
+int build_hevc_sei_buffering_period(int init_cpb_removal_delay_length,
+unsigned int init_cpb_removal_delay,
+unsigned int init_cpb_removal_delay_offset,
+unsigned char **sei_buffer)
+{
+unsigned char *byte_buf;
+int bp_byte_size, i;
+//unsigned int cpb_removal_delay;
+
+avc_bitstream nal_bs;
+avc_bitstream sei_bp_bs;
+
+avc_bitstream_start(&sei_bp_bs);
+avc_bitstream_put_ue(&sei_bp_bs, 0); /*seq_parameter_set_id*/
+/* SEI buffer period info */
+/* NALHrdBpPresentFlag == 1 */
+avc_bitstream_put_ui(&sei_bp_bs,
init_cpb_removal_delay,init_cpb_removal_delay_length);
+avc_bitstream_put_ui(&sei_bp_bs,
init_cpb_removal_delay_offset,init_cpb_removal_delay_length);
+if ( sei_bp_bs.bit_offset & 0x7) {
+avc_bitstream_put_ui(&sei_bp_bs, 1, 1);
+}
+avc_bitstream_end(&sei_bp_bs);
+bp_byte_size = (sei_bp_bs.bit_offset + 7) / 8;
+
+avc_bitstream_start(&nal_bs);
+nal_start_code_prefix(&nal_bs);
+nal_header_hevc(&nal_bs, PREFIX_SEI_NUT ,0);
+
+/* Write the SEI buffer period data */
+avc_bitstream_put_ui(&nal_bs, 0, 8);
+avc_bitstream_put_ui(&nal_bs, bp_byte_size, 8);
+
+byte_buf = (unsigned char *)sei_bp_bs.buffer;
+for(i = 0; i < bp_byte_size; i++) {
+avc_bitstream_put_ui(&nal_bs, byte_buf[i], 8);
+}
+free(byte_buf);
+
+avc_rbsp_trailing_bits(&nal_bs);
+avc_bitstream_end(&na
[Libva] [PATCH 1/6] HEVC ENC:Added PAK context for HEVC
Signed-off-by: Qu,Pengfei
---
src/Makefile.am | 1 +
src/gen9_mfc.h | 288
2 files changed, 289 insertions(+)
create mode 100644 src/gen9_mfc.h
diff --git a/src/Makefile.am b/src/Makefile.am
index 9e54fd5..3f43809 100755
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -107,6 +107,7 @@ source_h = \
gen75_vpp_vebox.h \
gen8_post_processing.h \
gen9_mfd.h \
+ gen9_mfc.h \
i965_avc_bsd.h \
i965_avc_hw_scoreboard.h\
i965_avc_ildb.h \
diff --git a/src/gen9_mfc.h b/src/gen9_mfc.h
new file mode 100644
index 000..9630039
--- /dev/null
+++ b/src/gen9_mfc.h
@@ -0,0 +1,288 @@
+/*
+ * Copyright ?? 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *Qu Pengfei
+ *
+ */
+
+#ifndef _GEN9_HCP_H_
+#define _GEN9_HCP_H_
+
+#include
+#include
+#include
+
+#include "i965_gpe_utils.h"
+
+struct encode_state;
+
+#define MAX_HCP_REFERENCE_SURFACES 8
+#define NUM_HCP_CURRENT_COLLOCATED_MV_TEMPORAL_BUFFERS 9
+
+#define INTRA_MB_FLAG_MASK 0x2000
+
+/* The space required for slice header SLICE_STATE + header.
+ * Is it enough? */
+#define SLICE_HEADER80
+
+/* the space required for slice tail. */
+#define SLICE_TAIL 16
+
+#define __SOFTWARE__0
+
+#define HCP_BATCHBUFFER_HEVC_INTRA 0
+#define HCP_BATCHBUFFER_HEVC_INTER 1
+#define NUM_HCP_KERNEL 2
+
+#define BIND_IDX_VME_OUTPUT 0
+#define BIND_IDX_HCP_SLICE_HEADER 1
+#define BIND_IDX_HCP_BATCHBUFFER2
+
+#define CMD_LEN_IN_OWORD4
+
+struct gen9_hcpe_context {
+struct {
+unsigned int width;
+unsigned int height;
+unsigned int w_pitch;
+unsigned int h_pitch;
+} surface_state;
+
+//HCP_PIPE_BUF_ADDR_STATE
+
+struct {
+dri_bo *bo;
+} deblocking_filter_line_buffer;//OUTPUT: reconstructed
picture with deblocked
+
+struct {
+dri_bo *bo;
+} deblocking_filter_tile_line_buffer; //OUTPUT: reconstructed
picture with deblocked
+
+struct {
+dri_bo *bo;
+} deblocking_filter_tile_column_buffer; //OUTPUT: reconstructed
picture with deblocked
+
+struct {
+dri_bo *bo;
+} uncompressed_picture_source; //INPUT: original compressed
image
+
+struct {
+dri_bo *bo;
+} metadata_line_buffer; //INTERNAL:metadata
+
+struct {
+dri_bo *bo;
+} metadata_tile_line_buffer;//INTERNAL:metadata
+
+struct {
+dri_bo *bo;
+} metadata_tile_column_buffer; //INTERNAL:metadata
+
+struct {
+dri_bo *bo;
+} sao_line_buffer; //INTERNAL:SAO not used in skylake
+
+struct {
+dri_bo *bo;
+} sao_tile_line_buffer;//INTERNAL:SAO not used in skylake
+
+struct {
+dri_bo *bo;
+} sao_tile_column_buffer; //INTERNAL:SAO not used in skylake
+
+struct {
+dri_bo *bo;
+}
current_collocated_mv_temporal_buffer[NUM_HCP_CURRENT_COLLOCATED_MV_TEMPORAL_BUFFERS];
//
+
+struct {
+dri_bo *bo;
+} reference_surfaces[MAX_HCP_REFERENCE_SURFACES]; //INTERNAL: refrence
surfaces
+
+//HCP_IND_OBJ_BASE_ADDR_STATE
+struct {
+dri_bo *bo;
+} hcp_indirect_cu_object; //INPUT: the cu' mv info
+
+struct {
+dri_bo *bo;
+int offset;
+int end_offset;
+} hcp_indirect_pak_bse_object; //OUTPUT: the compressed bitstream
+
+//Bit rate tracking context
+struct {
+unsigned int QpPrimeY;
+unsigned int MaxQpNegModifier;
+unsigned int MaxQpPosModifier;
+unsigned ch
[Libva] [PATCH 3/6] HEVC ENC:Added HEVC support in API function
Signed-off-by: Qu,Pengfei
---
src/i965_device_info.c | 1 +
src/i965_drv_video.c | 121 +
2 files changed, 103 insertions(+), 19 deletions(-)
diff --git a/src/i965_device_info.c b/src/i965_device_info.c
index d03aceb..9ccc85e 100755
--- a/src/i965_device_info.c
+++ b/src/i965_device_info.c
@@ -347,6 +347,7 @@ static struct hw_codec_info skl_hw_codec_info = {
.has_blending = 1,
.has_h264_mvc_encoding = 1,
.has_hevc_decoding = 1,
+.has_hevc_encoding = 1,
.num_filters = 5,
.filters = {
diff --git a/src/i965_drv_video.c b/src/i965_drv_video.c
index 74895da..ca9703b 100644
--- a/src/i965_drv_video.c
+++ b/src/i965_drv_video.c
@@ -104,6 +104,9 @@
#define HAS_HEVC_DECODING(ctx) ((ctx)->codec_info->has_hevc_decoding
&& \
(ctx)->intel.has_bsd)
+#define HAS_HEVC_ENCODING(ctx) ((ctx)->codec_info->has_hevc_encoding
&& \
+ (ctx)->intel.has_bsd)
+
static int get_sampling_from_fourcc(unsigned int fourcc);
/* Check whether we are rendering to X11 (VA/X11 or VA/GLX API) */
@@ -376,7 +379,10 @@ is_image_busy(struct i965_driver_data *i965, struct
object_image *obj_image)
}
#define I965_PACKED_HEADER_BASE 0
-#define I965_PACKED_MISC_HEADER_BASE3
+#define I965_SEQ_PACKED_HEADER_BASE 0
+#define I965_SEQ_PACKED_HEADER_END 2
+#define I965_PIC_PACKED_HEADER_BASE 2
+#define I965_PACKED_MISC_HEADER_BASE4
int
va_enc_packed_type_to_idx(int packed_type)
@@ -393,15 +399,15 @@ va_enc_packed_type_to_idx(int packed_type)
switch (packed_type) {
case VAEncPackedHeaderSequence:
-idx = I965_PACKED_HEADER_BASE + 0;
+idx = I965_SEQ_PACKED_HEADER_BASE + 0;
break;
case VAEncPackedHeaderPicture:
-idx = I965_PACKED_HEADER_BASE + 1;
+idx = I965_PIC_PACKED_HEADER_BASE + 0;
break;
case VAEncPackedHeaderSlice:
-idx = I965_PACKED_HEADER_BASE + 2;
+idx = I965_PIC_PACKED_HEADER_BASE + 1;
break;
default:
@@ -411,7 +417,7 @@ va_enc_packed_type_to_idx(int packed_type)
}
}
-ASSERT_RET(idx < 4, 0);
+ASSERT_RET(idx < 5, 0);
return idx;
}
@@ -465,7 +471,8 @@ i965_QueryConfigProfiles(VADriverContextP ctx,
profile_list[i++] = VAProfileH264StereoHigh;
}
-if (HAS_HEVC_DECODING(i965)) {
+if (HAS_HEVC_DECODING(i965)||
+HAS_HEVC_ENCODING(i965)) {
profile_list[i++] = VAProfileHEVCMain;
}
@@ -548,6 +555,9 @@ i965_QueryConfigEntrypoints(VADriverContextP ctx,
if (HAS_HEVC_DECODING(i965))
entrypoint_list[n++] = VAEntrypointVLD;
+if (HAS_HEVC_ENCODING(i965))
+entrypoint_list[n++] = VAEntrypointEncSlice;
+
break;
default:
@@ -639,7 +649,8 @@ i965_validate_config(VADriverContextP ctx, VAProfile
profile,
break;
case VAProfileHEVCMain:
-if (HAS_HEVC_DECODING(i965) && (entrypoint == VAEntrypointVLD))
+if ((HAS_HEVC_DECODING(i965) && (entrypoint == VAEntrypointVLD))||
+(HAS_HEVC_ENCODING(i965) && (entrypoint == VAEntrypointEncSlice)))
va_status = VA_STATUS_SUCCESS;
else
va_status = VA_STATUS_ERROR_UNSUPPORTED_ENTRYPOINT;
@@ -729,7 +740,8 @@ i965_GetConfigAttributes(VADriverContextP ctx,
profile == VAProfileH264Main ||
profile == VAProfileH264High ||
profile == VAProfileH264StereoHigh ||
-profile == VAProfileH264MultiviewHigh) {
+profile == VAProfileH264MultiviewHigh ||
+profile == VAProfileHEVCMain) {
attrib_list[i].value |= (VA_ENC_PACKED_HEADER_RAW_DATA |
VA_ENC_PACKED_HEADER_SLICE);
}
@@ -1894,6 +1906,8 @@ i965_CreateContext(VADriverContextP ctx,
obj_context->codec_state.encode.slice_header_index =
calloc(obj_context->codec_state.encode.max_slice_num,
sizeof(int));
+obj_context->codec_state.encode.vps_sps_seq_index = 0;
+
obj_context->codec_state.encode.slice_index = 0;
packed_attrib = i965_lookup_config_attribute(obj_config,
VAConfigAttribEncPackedHeaders);
if (packed_attrib)
@@ -1980,6 +1994,20 @@ i965_create_buffer_internal(VADriverContextP ctx,
struct object_buffer *obj_buffer = NULL;
struct buffer_store *buffer_store = NULL;
int bufferID;
+struct object_context *obj_context = NULL;
+struct object_config *obj_config = NULL;
+VAStatus vaStatus = VA_STATUS_ERROR_UNKNOWN;
+
+if (i965->current_context_id == VA_INVALID_ID)
+return vaStatus;
+
+obj_context = CONTE
[Libva] [PATCH 5/6] HEVC ENC:Added VME pipeline
Signed-off-by: Qu,Pengfei
---
src/gen6_mfc_common.c | 222 +++
src/gen6_vme.h| 19 ++
src/gen9_vme.c| 484 ++
src/i965_encoder.c| 74 +++-
4 files changed, 798 insertions(+), 1 deletion(-)
diff --git a/src/gen6_mfc_common.c b/src/gen6_mfc_common.c
index fe41dac..6a5f720 100644
--- a/src/gen6_mfc_common.c
+++ b/src/gen6_mfc_common.c
@@ -1652,3 +1652,225 @@ void
intel_avc_slice_insert_packed_data(VADriverContextP ctx,
return;
}
+/* HEVC */
+static int
+hevc_temporal_find_surface(VAPictureHEVC *curr_pic,
+ VAPictureHEVC *ref_list,
+ int num_pictures,
+ int dir)
+{
+int i, found = -1, min = 0x7FFF;
+
+for (i = 0; i < num_pictures; i++) {
+int tmp;
+
+if ((ref_list[i].flags & VA_PICTURE_HEVC_INVALID) ||
+(ref_list[i].picture_id == VA_INVALID_SURFACE))
+break;
+
+tmp = curr_pic->pic_order_cnt - ref_list[i].pic_order_cnt;
+
+if (dir)
+tmp = -tmp;
+
+if (tmp > 0 && tmp < min) {
+min = tmp;
+found = i;
+}
+}
+
+return found;
+}
+void
+intel_hevc_vme_reference_state(VADriverContextP ctx,
+ struct encode_state *encode_state,
+ struct intel_encoder_context *encoder_context,
+ int list_index,
+ int surface_index,
+ void (* vme_source_surface_state)(
+ VADriverContextP ctx,
+ int index,
+ struct object_surface *obj_surface,
+ struct intel_encoder_context
*encoder_context))
+{
+struct gen6_vme_context *vme_context = encoder_context->vme_context;
+struct object_surface *obj_surface = NULL;
+struct i965_driver_data *i965 = i965_driver_data(ctx);
+VASurfaceID ref_surface_id;
+VAEncPictureParameterBufferHEVC *pic_param =
(VAEncPictureParameterBufferHEVC *)encode_state->pic_param_ext->buffer;
+VAEncSliceParameterBufferHEVC *slice_param =
(VAEncSliceParameterBufferHEVC *)encode_state->slice_params_ext[0]->buffer;
+int max_num_references;
+VAPictureHEVC *curr_pic;
+VAPictureHEVC *ref_list;
+int ref_idx;
+
+if (list_index == 0) {
+max_num_references = pic_param->num_ref_idx_l0_default_active_minus1 +
1;
+ref_list = slice_param->ref_pic_list0;
+} else {
+max_num_references = pic_param->num_ref_idx_l1_default_active_minus1 +
1;
+ref_list = slice_param->ref_pic_list1;
+}
+
+if (max_num_references == 1) {
+if (list_index == 0) {
+ref_surface_id = slice_param->ref_pic_list0[0].picture_id;
+vme_context->used_references[0] = &slice_param->ref_pic_list0[0];
+} else {
+ref_surface_id = slice_param->ref_pic_list1[0].picture_id;
+vme_context->used_references[1] = &slice_param->ref_pic_list1[0];
+}
+
+if (ref_surface_id != VA_INVALID_SURFACE)
+obj_surface = SURFACE(ref_surface_id);
+
+if (!obj_surface ||
+!obj_surface->bo) {
+obj_surface = encode_state->reference_objects[list_index];
+vme_context->used_references[list_index] =
&pic_param->reference_frames[list_index];
+}
+
+ref_idx = 0;
+} else {
+curr_pic = &pic_param->decoded_curr_pic;
+
+/* select the reference frame in temporal space */
+ref_idx = hevc_temporal_find_surface(curr_pic, ref_list,
max_num_references, list_index == 1);
+ref_surface_id = ref_list[ref_idx].picture_id;
+
+if (ref_surface_id != VA_INVALID_SURFACE) /* otherwise warning later */
+obj_surface = SURFACE(ref_surface_id);
+
+vme_context->used_reference_objects[list_index] = obj_surface;
+vme_context->used_references[list_index] = &ref_list[ref_idx];
+}
+
+if (obj_surface &&
+obj_surface->bo) {
+assert(ref_idx >= 0);
+vme_context->used_reference_objects[list_index] = obj_surface;
+vme_source_surface_state(ctx, surface_index, obj_surface,
encoder_context);
+vme_context->ref_index_in_mb[list_index] = (ref_idx << 24 |
+ref_idx << 16 |
+ref_idx << 8 |
+ref_idx);
+} else {
+vme_context->used_reference_objects[list_index] = NULL;
+vme_context->used_references[list_index] = NULL;
+vme_context->ref_index_in_mb[list_index] = 0;
+}
+}
+
+void intel_vme_hevc_update_mbmv_cost(VADriverContextP ctx,
+ struct enc
[Libva] [PATCH 5/5] Added HEVC silce header generated internally
Signed-off-by: Qu,Pengfei
---
src/i965_encoder_utils.c | 475 ++-
src/i965_encoder_utils.h | 43 -
2 files changed, 502 insertions(+), 16 deletions(-)
diff --git a/src/i965_encoder_utils.c b/src/i965_encoder_utils.c
index e59e7fb..a21e65b 100644
--- a/src/i965_encoder_utils.c
+++ b/src/i965_encoder_utils.c
@@ -29,6 +29,7 @@
#include
#include
#include
+#include
#include "i965_encoder_utils.h"
@@ -62,6 +63,17 @@
#define PROFILE_IDC_MAIN77
#define PROFILE_IDC_HIGH100
+/*HEVC*/
+#define VPS_NUT32
+#define SPS_NUT33
+#define PPS_NUT34
+#define IDR_WRADL_NUT 19
+#define IDR_NLP_NUT20
+#define SLICE_TRAIL_N_NUT 0
+#define SLICE_TRAIL_R_NUT 1
+#define PREFIX_SEI_NUT 39
+#define SUFFIX_SEI_NUT 40
+
struct __avc_bitstream {
unsigned int *buffer;
int bit_offset;
@@ -439,13 +451,13 @@ build_avc_sei_pic_timing(unsigned int cpb_removal_length,
unsigned int cpb_remov
int
build_avc_sei_buffer_timing(unsigned int init_cpb_removal_length,
- unsigned int init_cpb_removal_delay,
- unsigned int init_cpb_removal_delay_offset,
- unsigned int cpb_removal_length,
- unsigned int cpb_removal_delay,
- unsigned int dpb_output_length,
- unsigned int dpb_output_delay,
- unsigned char **sei_buffer)
+unsigned int init_cpb_removal_delay,
+unsigned int init_cpb_removal_delay_offset,
+unsigned int cpb_removal_length,
+unsigned int cpb_removal_delay,
+unsigned int dpb_output_length,
+unsigned int dpb_output_delay,
+unsigned char **sei_buffer)
{
unsigned char *byte_buf;
int bp_byte_size, i, pic_byte_size;
@@ -476,7 +488,7 @@ build_avc_sei_buffer_timing(unsigned int
init_cpb_removal_length,
nal_start_code_prefix(&nal_bs);
nal_header(&nal_bs, NAL_REF_IDC_NONE, NAL_SEI);
- /* Write the SEI buffer period data */
+/* Write the SEI buffer period data */
avc_bitstream_put_ui(&nal_bs, 0, 8);
avc_bitstream_put_ui(&nal_bs, bp_byte_size, 8);
@@ -485,7 +497,7 @@ build_avc_sei_buffer_timing(unsigned int
init_cpb_removal_length,
avc_bitstream_put_ui(&nal_bs, byte_buf[i], 8);
}
free(byte_buf);
- /* write the SEI timing data */
+/* write the SEI timing data */
avc_bitstream_put_ui(&nal_bs, 0x01, 8);
avc_bitstream_put_ui(&nal_bs, pic_byte_size, 8);
@@ -562,3 +574,448 @@
build_avc_mvc_slice_header(VAEncSequenceParameterBufferH264_MVC *mvc_sps_param,
return bs.bit_offset;
}
+
+/* HEVC to do for internal header generated*/
+
+void nal_header_hevc(avc_bitstream *bs, int nal_unit_type, int temporalid)
+{
+/* forbidden_zero_bit: 0 */
+avc_bitstream_put_ui(bs, 0, 1);
+/* nal unit_type */
+avc_bitstream_put_ui(bs, nal_unit_type, 6);
+/* layer_id. currently it is zero */
+avc_bitstream_put_ui(bs, 0, 6);
+/* teporalid + 1 .*/
+avc_bitstream_put_ui(bs, temporalid + 1, 3);
+}
+
+int build_hevc_sei_buffering_period(int init_cpb_removal_delay_length,
+unsigned int init_cpb_removal_delay,
+unsigned int init_cpb_removal_delay_offset,
+unsigned char **sei_buffer)
+{
+unsigned char *byte_buf;
+int bp_byte_size, i;
+//unsigned int cpb_removal_delay;
+
+avc_bitstream nal_bs;
+avc_bitstream sei_bp_bs;
+
+avc_bitstream_start(&sei_bp_bs);
+avc_bitstream_put_ue(&sei_bp_bs, 0); /*seq_parameter_set_id*/
+/* SEI buffer period info */
+/* NALHrdBpPresentFlag == 1 */
+avc_bitstream_put_ui(&sei_bp_bs,
init_cpb_removal_delay,init_cpb_removal_delay_length);
+avc_bitstream_put_ui(&sei_bp_bs,
init_cpb_removal_delay_offset,init_cpb_removal_delay_length);
+if ( sei_bp_bs.bit_offset & 0x7) {
+avc_bitstream_put_ui(&sei_bp_bs, 1, 1);
+}
+avc_bitstream_end(&sei_bp_bs);
+bp_byte_size = (sei_bp_bs.bit_offset + 7) / 8;
+
+avc_bitstream_start(&nal_bs);
+nal_start_code_prefix(&nal_bs);
+nal_header_hevc(&nal_bs, PREFIX_SEI_NUT ,0);
+
+/* Write the SEI buffer period data */
+avc_bitstream_put_ui(&nal_bs, 0, 8);
+avc_bitstream_put_ui(&nal_bs, bp_byte_size, 8);
+
+byte_buf = (unsigned char *)sei_bp_bs.buffer;
+for(i = 0; i < bp_byte_size; i++) {
+avc_bitstream_put_ui(&nal_bs, byte_buf[i], 8);
+}
+free(byte_buf);
+
+avc_rbsp_trailing_bits(&nal_bs);
+avc_bitstream_end(&nal_bs);
+
+*sei_buffer = (unsigned char *)nal_bs.buffer;
+
+return nal_
[Libva] [PATCH 4/5] Added HEVC PAK pipeline
Signed-off-by: Qu,Pengfei
---
src/gen9_mfc_hevc.c | 2636 +++
1 file changed, 2636 insertions(+)
create mode 100644 src/gen9_mfc_hevc.c
diff --git a/src/gen9_mfc_hevc.c b/src/gen9_mfc_hevc.c
new file mode 100644
index 000..76e13b3
--- /dev/null
+++ b/src/gen9_mfc_hevc.c
@@ -0,0 +1,2636 @@
+/*
+ * Copyright ?? 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *Qu Pengfei
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "intel_batchbuffer.h"
+#include "i965_defines.h"
+#include "i965_structs.h"
+#include "i965_drv_video.h"
+#include "i965_encoder.h"
+#include "i965_encoder_utils.h"
+#include "gen9_mfc.h"
+#include "gen6_vme.h"
+#include "intel_media.h"
+
+typedef enum _gen6_brc_status {
+BRC_NO_HRD_VIOLATION = 0,
+BRC_UNDERFLOW = 1,
+BRC_OVERFLOW = 2,
+BRC_UNDERFLOW_WITH_MAX_QP = 3,
+BRC_OVERFLOW_WITH_MIN_QP = 4,
+} gen6_brc_status;
+
+/* BRC define */
+#define BRC_CLIP(x, min, max) \
+{ \
+x = ((x > (max)) ? (max) : ((x < (min)) ? (min) : x)); \
+}
+
+#define BRC_P_B_QP_DIFF 4
+#define BRC_I_P_QP_DIFF 2
+#define BRC_I_B_QP_DIFF (BRC_I_P_QP_DIFF + BRC_P_B_QP_DIFF)
+
+#define BRC_PWEIGHT 0.6 /* weight if P slice with comparison to I slice */
+#define BRC_BWEIGHT 0.25 /* weight if B slice with comparison to I slice */
+
+#define BRC_QP_MAX_CHANGE 5 /* maximum qp modification */
+#define BRC_CY 0.1 /* weight for */
+#define BRC_CX_UNDERFLOW 5.
+#define BRC_CX_OVERFLOW -4.
+
+#define BRC_PI_0_5 1.5707963267948966192313216916398
+
+/* intel buffer write */
+#define ALLOC_ENCODER_BUFFER(gen_buffer, string, size) do { \
+dri_bo_unreference(gen_buffer->bo); \
+gen_buffer->bo = dri_bo_alloc(i965->intel.bufmgr, \
+ string, \
+ size, \
+ 0x1000); \
+assert(gen_buffer->bo); \
+} while (0);
+
+
+#define OUT_BUFFER_X(buf_bo, is_target, ma) do { \
+if (buf_bo) { \
+OUT_BCS_RELOC(batch,\
+ buf_bo, \
+ I915_GEM_DOMAIN_INSTRUCTION, \
+ is_target ? I915_GEM_DOMAIN_INSTRUCTION : 0, \
+ 0); \
+} else {\
+OUT_BCS_BATCH(batch, 0);\
+} \
+OUT_BCS_BATCH(batch, 0);\
+if (ma) \
+OUT_BCS_BATCH(batch, 0);\
+} while (0)
+
+#define OUT_BUFFER_MA_TARGET(buf_bo) OUT_BUFFER_X(buf_bo, 1, 1)
+#define OUT_BUFFER_MA_REFERENCE(buf_bo)OUT_BUFFER_X(buf_bo, 0, 1)
+#define OUT_BUFFER_NMA_TARGET(buf_bo) OUT_BUFFER_X(buf_bo, 1, 0)
+#define OUT_BUFFER_NMA_REFERENCE(buf_bo) OUT_BUFFER_X(buf_bo, 0, 0)
+
+
+#define SURFACE_STATE_PADDED_SIZE SURFACE_STATE_PADDED_SIZE_GEN8
+#define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE *
index)
+#define BINDING_TABLE_OFFSET(index)
(SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GE
[Libva] [PATCH 1/5] VME pipeline for HEVC
Signed-off-by: Qu,Pengfei
---
src/gen6_mfc_common.c | 688 -
src/gen6_vme.h| 19 ++
src/gen9_vme.c| 928 ++
3 files changed, 1180 insertions(+), 455 deletions(-)
diff --git a/src/gen6_mfc_common.c b/src/gen6_mfc_common.c
index fe41dac..a69f00a 100644
--- a/src/gen6_mfc_common.c
+++ b/src/gen6_mfc_common.c
@@ -631,8 +631,8 @@ VAStatus intel_mfc_avc_prepare(VADriverContextP ctx,
int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
if (IS_GEN6(i965->intel.device_info)) {
- /* On the SNB it should be fixed to 128 for the DMV buffer */
- width_in_mbs = 128;
+/* On the SNB it should be fixed to 128 for the DMV buffer */
+width_in_mbs = 128;
}
for (j = 0; j < encode_state->num_slice_params_ext && enable_avc_ildb ==
0; j++) {
@@ -735,7 +735,7 @@ VAStatus intel_mfc_avc_prepare(VADriverContextP ctx,
break;
}
}
-
+
mfc_context->uncompressed_picture_source.bo =
encode_state->input_yuv_object->bo;
dri_bo_reference(mfc_context->uncompressed_picture_source.bo);
@@ -807,7 +807,7 @@ int intel_format_lutvalue(int value, int max)
if (temp1 > temp2)
ret = max;
return ret;
-
+
}
@@ -842,40 +842,40 @@ void intel_vme_update_mbmv_cost(VADriverContextP ctx,
if (encoder_context->rate_control_mode == VA_RC_CQP)
- qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
+qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
else
- qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
-
+qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
+
if (vme_state_message == NULL)
- return;
-
+return;
+
assert(qp <= QP_MAX);
lambda = intel_lambda_qp(qp);
if (slice_type == SLICE_TYPE_I) {
- vme_state_message[MODE_INTRA_16X16] = 0;
- m_cost = lambda * 4;
- vme_state_message[MODE_INTRA_8X8] = intel_format_lutvalue(m_cost, 0x8f);
- m_cost = lambda * 16;
- vme_state_message[MODE_INTRA_4X4] = intel_format_lutvalue(m_cost, 0x8f);
- m_cost = lambda * 3;
- vme_state_message[MODE_INTRA_NONPRED] = intel_format_lutvalue(m_cost,
0x6f);
+vme_state_message[MODE_INTRA_16X16] = 0;
+m_cost = lambda * 4;
+vme_state_message[MODE_INTRA_8X8] = intel_format_lutvalue(m_cost,
0x8f);
+m_cost = lambda * 16;
+vme_state_message[MODE_INTRA_4X4] = intel_format_lutvalue(m_cost,
0x8f);
+m_cost = lambda * 3;
+vme_state_message[MODE_INTRA_NONPRED] = intel_format_lutvalue(m_cost,
0x6f);
} else {
- m_cost = 0;
- vme_state_message[MODE_INTER_MV0] = intel_format_lutvalue(m_cost, 0x6f);
- for (j = 1; j < 3; j++) {
+m_cost = 0;
+vme_state_message[MODE_INTER_MV0] = intel_format_lutvalue(m_cost,
0x6f);
+for (j = 1; j < 3; j++) {
m_costf = (log2f((float)(j + 1)) + 1.718f) * lambda;
m_cost = (int)m_costf;
vme_state_message[MODE_INTER_MV0 + j] =
intel_format_lutvalue(m_cost, 0x6f);
- }
- mv_count = 3;
- for (j = 4; j <= 64; j *= 2) {
+}
+mv_count = 3;
+for (j = 4; j <= 64; j *= 2) {
m_costf = (log2f((float)(j + 1)) + 1.718f) * lambda;
m_cost = (int)m_costf;
vme_state_message[MODE_INTER_MV0 + mv_count] =
intel_format_lutvalue(m_cost, 0x6f);
mv_count++;
- }
+}
- if (qp <= 25) {
+if (qp <= 25) {
vme_state_message[MODE_INTRA_16X16] = 0x4a;
vme_state_message[MODE_INTRA_8X8] = 0x4a;
vme_state_message[MODE_INTRA_4X4] = 0x4a;
@@ -887,17 +887,17 @@ void intel_vme_update_mbmv_cost(VADriverContextP ctx,
vme_state_message[MODE_INTER_4X4] = 0x4a;
vme_state_message[MODE_INTER_BWD] = 0x2a;
return;
- }
- m_costf = lambda * 10;
- vme_state_message[MODE_INTRA_16X16] = intel_format_lutvalue(m_cost,
0x8f);
- m_cost = lambda * 14;
- vme_state_message[MODE_INTRA_8X8] = intel_format_lutvalue(m_cost, 0x8f);
- m_cost = lambda * 24;
- vme_state_message[MODE_INTRA_4X4] = intel_format_lutvalue(m_cost, 0x8f);
- m_costf = lambda * 3.5;
- m_cost = m_costf;
- vme_state_message[MODE_INTRA_NONPRED] = intel_format_lutvalue(m_cost,
0x6f);
- if (slice_type == SLICE_TYPE_P) {
+}
+m_costf = lambda * 10;
+vme_state_message[MODE_INTRA_16X16] = intel_format_lutvalue(m_cost,
0x8f);
+m_cost = lambda * 14;
+vme_state_message[MODE_INTRA_8X8] = intel_format_lutvalue(m_cost,
0x8f);
+m_cost = lambda * 24;
+vme_state_message[MODE_INTRA_4X4] = intel_format_lutvalue(m_cost,
0x8f);
+
[Libva] [PATCH] Added HEVC encoder. summary
Signed-off-by: Qu,Pengfei --- feature: 1. LCU size is 16x16 only 2. Min CU size is 16x16 only 3. Transform size 16x16~8x8 4. I/P/B frame enabled. 5. Constant QP only --- src/Makefile.am |2 + src/gen6_mfc_common.c| 688 src/gen6_vme.h | 19 + src/gen9_mfc.h | 288 + src/gen9_mfc_hevc.c | 2636 ++ src/gen9_vme.c | 928 src/i965_device_info.c | 17 +- src/i965_drv_video.c | 153 ++- src/i965_drv_video.h | 15 +- src/i965_encoder.c | 74 +- src/i965_encoder_utils.c | 475 - src/i965_encoder_utils.h | 43 +- 12 files changed, 4821 insertions(+), 517 deletions(-) create mode 100644 src/gen9_mfc.h create mode 100644 src/gen9_mfc_hevc.c diff --git a/src/Makefile.am b/src/Makefile.am index 566a7ae..cb88cca 100755 --- a/src/Makefile.am +++ b/src/Makefile.am @@ -64,6 +64,7 @@ source_c = \ gen8_vme.c \ gen9_vme.c \ gen9_mfc.c \ + gen9_mfc_hevc.c \ gen9_mfd.c \ gen75_picture_process.c \ gen75_vme.c \ @@ -106,6 +107,7 @@ source_h = \ gen75_vpp_vebox.h \ gen8_post_processing.h \ gen9_mfd.h \ + gen9_mfc.h \ i965_avc_bsd.h \ i965_avc_hw_scoreboard.h\ i965_avc_ildb.h \ ___ Libva mailing list Libva@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/libva
[Libva] [PATCH 3/5] Added to support HEVC related to intel driver API
Signed-off-by: Qu,Pengfei
---
src/i965_device_info.c | 17 +++---
src/i965_drv_video.c | 153 ++---
src/i965_drv_video.h | 15 -
src/i965_encoder.c | 74 +++-
4 files changed, 213 insertions(+), 46 deletions(-)
diff --git a/src/i965_device_info.c b/src/i965_device_info.c
index ac5031a..e400b3f 100755
--- a/src/i965_device_info.c
+++ b/src/i965_device_info.c
@@ -347,6 +347,7 @@ static struct hw_codec_info skl_hw_codec_info = {
.has_blending = 1,
.has_h264_mvc_encoding = 1,
.has_hevc_decoding = 1,
+.has_hevc_encoding = 1,
.num_filters = 5,
.filters = {
@@ -502,7 +503,7 @@ static void cpuid(unsigned int op,
uint32_t *eax, uint32_t *ebx,
uint32_t *ecx, uint32_t *edx)
{
- __cpuid_count(op, 0, *eax, *ebx, *ecx, *edx);
+__cpuid_count(op, 0, *eax, *ebx, *ecx, *edx);
}
/*
@@ -523,7 +524,7 @@ static int intel_driver_detect_cpustring(char *model_id)
/* If the max extended CPUID info is less than 0x8004, fail */
if (rdata[0] < 0x8004)
- return -EINVAL;
+return -EINVAL;
/* obtain the CPUID string */
cpuid(0x8002, &rdata[0], &rdata[1], &rdata[2], &rdata[3]);
@@ -585,18 +586,18 @@ static void hsw_hw_codec_preinit(VADriverContextP ctx,
struct hw_codec_info *cod
model_ptr = (char *)hsw_cpu_hook_list[i];
if (strlen(model_ptr) != model_len)
- continue;
+continue;
if (strncasecmp(model_string, model_ptr, model_len) == 0) {
found = true;
break;
- }
+}
}
if (found) {
- codec_info->has_h264_encoding = 0;
- codec_info->has_h264_mvc_encoding = 0;
- codec_info->has_mpeg2_encoding = 0;
+codec_info->has_h264_encoding = 0;
+codec_info->has_h264_mvc_encoding = 0;
+codec_info->has_mpeg2_encoding = 0;
}
return;
}
@@ -713,7 +714,7 @@ static void gen7_hw_codec_preinit(VADriverContextP ctx,
struct hw_codec_info *co
if (strncasecmp(model_string, model_ptr, model_len) == 0) {
found = true;
break;
- }
+}
}
if (found) {
diff --git a/src/i965_drv_video.c b/src/i965_drv_video.c
index 034ff20..ccae568 100644
--- a/src/i965_drv_video.c
+++ b/src/i965_drv_video.c
@@ -1,5 +1,5 @@
/*
- * Copyright ? 2009 Intel Corporation
+ * Copyright ?2009 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
@@ -104,6 +104,9 @@
#define HAS_HEVC_DECODING(ctx) ((ctx)->codec_info->has_hevc_decoding
&& \
(ctx)->intel.has_bsd)
+#define HAS_HEVC_ENCODING(ctx) ((ctx)->codec_info->has_hevc_encoding
&& \
+ (ctx)->intel.has_bsd)
+
static int get_sampling_from_fourcc(unsigned int fourcc);
/* Check whether we are rendering to X11 (VA/X11 or VA/GLX API) */
@@ -376,7 +379,10 @@ is_image_busy(struct i965_driver_data *i965, struct
object_image *obj_image)
}
#define I965_PACKED_HEADER_BASE 0
-#define I965_PACKED_MISC_HEADER_BASE3
+#define I965_SEQ_PACKED_HEADER_BASE 0
+#define I965_SEQ_PACKED_HEADER_END 2
+#define I965_PIC_PACKED_HEADER_BASE 2
+#define I965_PACKED_MISC_HEADER_BASE4
int
va_enc_packed_type_to_idx(int packed_type)
@@ -393,15 +399,15 @@ va_enc_packed_type_to_idx(int packed_type)
switch (packed_type) {
case VAEncPackedHeaderSequence:
-idx = I965_PACKED_HEADER_BASE + 0;
+idx = I965_SEQ_PACKED_HEADER_BASE + 0;
break;
case VAEncPackedHeaderPicture:
-idx = I965_PACKED_HEADER_BASE + 1;
+idx = I965_PIC_PACKED_HEADER_BASE + 0;
break;
case VAEncPackedHeaderSlice:
-idx = I965_PACKED_HEADER_BASE + 2;
+idx = I965_PIC_PACKED_HEADER_BASE + 1;
break;
default:
@@ -411,7 +417,7 @@ va_enc_packed_type_to_idx(int packed_type)
}
}
-ASSERT_RET(idx < 4, 0);
+ASSERT_RET(idx < 5, 0);
return idx;
}
@@ -465,7 +471,8 @@ i965_QueryConfigProfiles(VADriverContextP ctx,
profile_list[i++] = VAProfileH264StereoHigh;
}
-if (HAS_HEVC_DECODING(i965)) {
+if (HAS_HEVC_DECODING(i965)||
+HAS_HEVC_ENCODING(i965)) {
profile_list[i++] = VAProfileHEVCMain;
}
@@ -548,6 +555,9 @@ i965_QueryConfigEntrypoints(VADriverContextP ctx,
if (HAS_HEVC_DECODING(i965))
entrypoint_list[n++] = VAEntrypointVLD;
+if (HAS_HEVC_ENCODING(i965))
+entrypoint_list[n++] = VAEntrypointEncSlice;
+
break;
default:
@@ -639,7 +649,8 @@ i965_validate_config(VADriverCo
[Libva] [PATCH 2/5] Added HEVC PAK context
Signed-off-by: Qu,Pengfei
---
src/Makefile.am | 2 +
src/gen9_mfc.h | 288
2 files changed, 290 insertions(+)
create mode 100644 src/gen9_mfc.h
diff --git a/src/Makefile.am b/src/Makefile.am
index 566a7ae..cb88cca 100755
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -64,6 +64,7 @@ source_c = \
gen8_vme.c \
gen9_vme.c \
gen9_mfc.c \
+ gen9_mfc_hevc.c \
gen9_mfd.c \
gen75_picture_process.c \
gen75_vme.c \
@@ -106,6 +107,7 @@ source_h = \
gen75_vpp_vebox.h \
gen8_post_processing.h \
gen9_mfd.h \
+ gen9_mfc.h \
i965_avc_bsd.h \
i965_avc_hw_scoreboard.h\
i965_avc_ildb.h \
diff --git a/src/gen9_mfc.h b/src/gen9_mfc.h
new file mode 100644
index 000..dbbb152
--- /dev/null
+++ b/src/gen9_mfc.h
@@ -0,0 +1,288 @@
+/*
+ * Copyright ?? 2010 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *Qu Pengfei
+ *
+ */
+
+#ifndef _GEN9_HCP_H_
+#define _GEN9_HCP_H_
+
+#include
+#include
+#include
+
+#include "i965_gpe_utils.h"
+
+struct encode_state;
+
+#define MAX_HCP_REFERENCE_SURFACES 8
+#define NUM_HCP_CURRENT_COLLOCATED_MV_TEMPORAL_BUFFERS 9
+
+#define INTRA_MB_FLAG_MASK 0x2000
+
+/* The space required for slice header SLICE_STATE + header.
+ * Is it enough? */
+#define SLICE_HEADER80
+
+/* the space required for slice tail. */
+#define SLICE_TAIL 16
+
+#define __SOFTWARE__0
+
+#define HCP_BATCHBUFFER_HEVC_INTRA 0
+#define HCP_BATCHBUFFER_HEVC_INTER 1
+#define NUM_HCP_KERNEL 2
+
+#define BIND_IDX_VME_OUTPUT 0
+#define BIND_IDX_HCP_SLICE_HEADER 1
+#define BIND_IDX_HCP_BATCHBUFFER2
+
+#define CMD_LEN_IN_OWORD4
+
+struct gen9_hcpe_context {
+struct {
+unsigned int width;
+unsigned int height;
+unsigned int w_pitch;
+unsigned int h_pitch;
+} surface_state;
+
+//HCP_PIPE_BUF_ADDR_STATE
+
+struct {
+dri_bo *bo;
+} deblocking_filter_line_buffer;//OUTPUT: reconstructed
picture with deblocked
+
+struct {
+dri_bo *bo;
+} deblocking_filter_tile_line_buffer; //OUTPUT: reconstructed
picture with deblocked
+
+struct {
+dri_bo *bo;
+} deblocking_filter_tile_column_buffer; //OUTPUT: reconstructed
picture with deblocked
+
+struct {
+dri_bo *bo;
+} uncompressed_picture_source; //INPUT: original compressed
image
+
+struct {
+dri_bo *bo;
+} metadata_line_buffer; //INTERNAL:metadata
+
+struct {
+dri_bo *bo;
+} metadata_tile_line_buffer;//INTERNAL:metadata
+
+struct {
+dri_bo *bo;
+} metadata_tile_column_buffer; //INTERNAL:metadata
+
+struct {
+dri_bo *bo;
+} sao_line_buffer; //INTERNAL:SAO not used in skylake
+
+struct {
+dri_bo *bo;
+} sao_tile_line_buffer;//INTERNAL:SAO not used in skylake
+
+struct {
+dri_bo *bo;
+} sao_tile_column_buffer; //INTERNAL:SAO not used in skylake
+
+struct {
+dri_bo *bo;
+}
current_collocated_mv_temporal_buffer[NUM_HCP_CURRENT_COLLOCATED_MV_TEMPORAL_BUFFERS];
//
+
+struct {
+dri_bo *bo;
+} reference_surfaces[MAX_HCP_REFERENCE_SURFACES]; //INTERNAL: refrence
surfaces
+
+//HCP_IND_OBJ_BASE_ADDR_STATE
+struct {
+dri_bo *bo;
+} hcp_indirect_cu_object; //INPUT: the cu' mv info
+
+struct {
+dri_bo *bo;
+
[Libva] [PATCH] Added HEVC encoder. summary
Signed-off-by: Qu,Pengfei --- feature: 1. LCU size is 16x16 only 2. Min CU size is 16x16 only 3. Transform size 16x16~8x8 4. I/P/B frame enabled. 5. Constant QP only --- src/Makefile.am |2 + src/gen6_mfc_common.c| 688 src/gen6_vme.h | 19 + src/gen9_mfc.h | 288 + src/gen9_mfc_hevc.c | 2636 ++ src/gen9_vme.c | 928 src/i965_device_info.c | 17 +- src/i965_drv_video.c | 153 ++- src/i965_drv_video.h | 15 +- src/i965_encoder.c | 74 +- src/i965_encoder_utils.c | 475 - src/i965_encoder_utils.h | 43 +- 12 files changed, 4821 insertions(+), 517 deletions(-) create mode 100644 src/gen9_mfc.h create mode 100644 src/gen9_mfc_hevc.c diff --git a/src/Makefile.am b/src/Makefile.am index 566a7ae..cb88cca 100755 --- a/src/Makefile.am +++ b/src/Makefile.am @@ -64,6 +64,7 @@ source_c = \ gen8_vme.c \ gen9_vme.c \ gen9_mfc.c \ + gen9_mfc_hevc.c \ gen9_mfd.c \ gen75_picture_process.c \ gen75_vme.c \ @@ -106,6 +107,7 @@ source_h = \ gen75_vpp_vebox.h \ gen8_post_processing.h \ gen9_mfd.h \ + gen9_mfc.h \ i965_avc_bsd.h \ i965_avc_hw_scoreboard.h\ i965_avc_ildb.h \ ___ Libva mailing list Libva@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/libva
[Libva] [PATCH 1/5] VME pipeline for HEVC
Signed-off-by: Qu,Pengfei
---
src/gen6_mfc_common.c | 688 -
src/gen6_vme.h| 19 ++
src/gen9_vme.c| 928 ++
3 files changed, 1180 insertions(+), 455 deletions(-)
diff --git a/src/gen6_mfc_common.c b/src/gen6_mfc_common.c
index fe41dac..a69f00a 100644
--- a/src/gen6_mfc_common.c
+++ b/src/gen6_mfc_common.c
@@ -631,8 +631,8 @@ VAStatus intel_mfc_avc_prepare(VADriverContextP ctx,
int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
if (IS_GEN6(i965->intel.device_info)) {
- /* On the SNB it should be fixed to 128 for the DMV buffer */
- width_in_mbs = 128;
+/* On the SNB it should be fixed to 128 for the DMV buffer */
+width_in_mbs = 128;
}
for (j = 0; j < encode_state->num_slice_params_ext && enable_avc_ildb ==
0; j++) {
@@ -735,7 +735,7 @@ VAStatus intel_mfc_avc_prepare(VADriverContextP ctx,
break;
}
}
-
+
mfc_context->uncompressed_picture_source.bo =
encode_state->input_yuv_object->bo;
dri_bo_reference(mfc_context->uncompressed_picture_source.bo);
@@ -807,7 +807,7 @@ int intel_format_lutvalue(int value, int max)
if (temp1 > temp2)
ret = max;
return ret;
-
+
}
@@ -842,40 +842,40 @@ void intel_vme_update_mbmv_cost(VADriverContextP ctx,
if (encoder_context->rate_control_mode == VA_RC_CQP)
- qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
+qp = pic_param->pic_init_qp + slice_param->slice_qp_delta;
else
- qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
-
+qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
+
if (vme_state_message == NULL)
- return;
-
+return;
+
assert(qp <= QP_MAX);
lambda = intel_lambda_qp(qp);
if (slice_type == SLICE_TYPE_I) {
- vme_state_message[MODE_INTRA_16X16] = 0;
- m_cost = lambda * 4;
- vme_state_message[MODE_INTRA_8X8] = intel_format_lutvalue(m_cost, 0x8f);
- m_cost = lambda * 16;
- vme_state_message[MODE_INTRA_4X4] = intel_format_lutvalue(m_cost, 0x8f);
- m_cost = lambda * 3;
- vme_state_message[MODE_INTRA_NONPRED] = intel_format_lutvalue(m_cost,
0x6f);
+vme_state_message[MODE_INTRA_16X16] = 0;
+m_cost = lambda * 4;
+vme_state_message[MODE_INTRA_8X8] = intel_format_lutvalue(m_cost,
0x8f);
+m_cost = lambda * 16;
+vme_state_message[MODE_INTRA_4X4] = intel_format_lutvalue(m_cost,
0x8f);
+m_cost = lambda * 3;
+vme_state_message[MODE_INTRA_NONPRED] = intel_format_lutvalue(m_cost,
0x6f);
} else {
- m_cost = 0;
- vme_state_message[MODE_INTER_MV0] = intel_format_lutvalue(m_cost, 0x6f);
- for (j = 1; j < 3; j++) {
+m_cost = 0;
+vme_state_message[MODE_INTER_MV0] = intel_format_lutvalue(m_cost,
0x6f);
+for (j = 1; j < 3; j++) {
m_costf = (log2f((float)(j + 1)) + 1.718f) * lambda;
m_cost = (int)m_costf;
vme_state_message[MODE_INTER_MV0 + j] =
intel_format_lutvalue(m_cost, 0x6f);
- }
- mv_count = 3;
- for (j = 4; j <= 64; j *= 2) {
+}
+mv_count = 3;
+for (j = 4; j <= 64; j *= 2) {
m_costf = (log2f((float)(j + 1)) + 1.718f) * lambda;
m_cost = (int)m_costf;
vme_state_message[MODE_INTER_MV0 + mv_count] =
intel_format_lutvalue(m_cost, 0x6f);
mv_count++;
- }
+}
- if (qp <= 25) {
+if (qp <= 25) {
vme_state_message[MODE_INTRA_16X16] = 0x4a;
vme_state_message[MODE_INTRA_8X8] = 0x4a;
vme_state_message[MODE_INTRA_4X4] = 0x4a;
@@ -887,17 +887,17 @@ void intel_vme_update_mbmv_cost(VADriverContextP ctx,
vme_state_message[MODE_INTER_4X4] = 0x4a;
vme_state_message[MODE_INTER_BWD] = 0x2a;
return;
- }
- m_costf = lambda * 10;
- vme_state_message[MODE_INTRA_16X16] = intel_format_lutvalue(m_cost,
0x8f);
- m_cost = lambda * 14;
- vme_state_message[MODE_INTRA_8X8] = intel_format_lutvalue(m_cost, 0x8f);
- m_cost = lambda * 24;
- vme_state_message[MODE_INTRA_4X4] = intel_format_lutvalue(m_cost, 0x8f);
- m_costf = lambda * 3.5;
- m_cost = m_costf;
- vme_state_message[MODE_INTRA_NONPRED] = intel_format_lutvalue(m_cost,
0x6f);
- if (slice_type == SLICE_TYPE_P) {
+}
+m_costf = lambda * 10;
+vme_state_message[MODE_INTRA_16X16] = intel_format_lutvalue(m_cost,
0x8f);
+m_cost = lambda * 14;
+vme_state_message[MODE_INTRA_8X8] = intel_format_lutvalue(m_cost,
0x8f);
+m_cost = lambda * 24;
+vme_state_message[MODE_INTRA_4X4] = intel_format_lutvalue(m_cost,
0x8f);
+
[Libva] [PATCH 4/5] Added HEVC PAK pipeline
Signed-off-by: Qu,Pengfei
---
src/gen9_mfc_hevc.c | 2636 +++
1 file changed, 2636 insertions(+)
create mode 100644 src/gen9_mfc_hevc.c
diff --git a/src/gen9_mfc_hevc.c b/src/gen9_mfc_hevc.c
new file mode 100644
index 000..76e13b3
--- /dev/null
+++ b/src/gen9_mfc_hevc.c
@@ -0,0 +1,2636 @@
+/*
+ * Copyright ?? 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *Qu Pengfei
+ *
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "intel_batchbuffer.h"
+#include "i965_defines.h"
+#include "i965_structs.h"
+#include "i965_drv_video.h"
+#include "i965_encoder.h"
+#include "i965_encoder_utils.h"
+#include "gen9_mfc.h"
+#include "gen6_vme.h"
+#include "intel_media.h"
+
+typedef enum _gen6_brc_status {
+BRC_NO_HRD_VIOLATION = 0,
+BRC_UNDERFLOW = 1,
+BRC_OVERFLOW = 2,
+BRC_UNDERFLOW_WITH_MAX_QP = 3,
+BRC_OVERFLOW_WITH_MIN_QP = 4,
+} gen6_brc_status;
+
+/* BRC define */
+#define BRC_CLIP(x, min, max) \
+{ \
+x = ((x > (max)) ? (max) : ((x < (min)) ? (min) : x)); \
+}
+
+#define BRC_P_B_QP_DIFF 4
+#define BRC_I_P_QP_DIFF 2
+#define BRC_I_B_QP_DIFF (BRC_I_P_QP_DIFF + BRC_P_B_QP_DIFF)
+
+#define BRC_PWEIGHT 0.6 /* weight if P slice with comparison to I slice */
+#define BRC_BWEIGHT 0.25 /* weight if B slice with comparison to I slice */
+
+#define BRC_QP_MAX_CHANGE 5 /* maximum qp modification */
+#define BRC_CY 0.1 /* weight for */
+#define BRC_CX_UNDERFLOW 5.
+#define BRC_CX_OVERFLOW -4.
+
+#define BRC_PI_0_5 1.5707963267948966192313216916398
+
+/* intel buffer write */
+#define ALLOC_ENCODER_BUFFER(gen_buffer, string, size) do { \
+dri_bo_unreference(gen_buffer->bo); \
+gen_buffer->bo = dri_bo_alloc(i965->intel.bufmgr, \
+ string, \
+ size, \
+ 0x1000); \
+assert(gen_buffer->bo); \
+} while (0);
+
+
+#define OUT_BUFFER_X(buf_bo, is_target, ma) do { \
+if (buf_bo) { \
+OUT_BCS_RELOC(batch,\
+ buf_bo, \
+ I915_GEM_DOMAIN_INSTRUCTION, \
+ is_target ? I915_GEM_DOMAIN_INSTRUCTION : 0, \
+ 0); \
+} else {\
+OUT_BCS_BATCH(batch, 0);\
+} \
+OUT_BCS_BATCH(batch, 0);\
+if (ma) \
+OUT_BCS_BATCH(batch, 0);\
+} while (0)
+
+#define OUT_BUFFER_MA_TARGET(buf_bo) OUT_BUFFER_X(buf_bo, 1, 1)
+#define OUT_BUFFER_MA_REFERENCE(buf_bo)OUT_BUFFER_X(buf_bo, 0, 1)
+#define OUT_BUFFER_NMA_TARGET(buf_bo) OUT_BUFFER_X(buf_bo, 1, 0)
+#define OUT_BUFFER_NMA_REFERENCE(buf_bo) OUT_BUFFER_X(buf_bo, 0, 0)
+
+
+#define SURFACE_STATE_PADDED_SIZE SURFACE_STATE_PADDED_SIZE_GEN8
+#define SURFACE_STATE_OFFSET(index) (SURFACE_STATE_PADDED_SIZE *
index)
+#define BINDING_TABLE_OFFSET(index)
(SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GE
[Libva] [PATCH 2/5] Added HEVC PAK context
Signed-off-by: Qu,Pengfei
---
src/Makefile.am | 2 +
src/gen9_mfc.h | 288
2 files changed, 290 insertions(+)
create mode 100644 src/gen9_mfc.h
diff --git a/src/Makefile.am b/src/Makefile.am
index 566a7ae..cb88cca 100755
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -64,6 +64,7 @@ source_c = \
gen8_vme.c \
gen9_vme.c \
gen9_mfc.c \
+ gen9_mfc_hevc.c \
gen9_mfd.c \
gen75_picture_process.c \
gen75_vme.c \
@@ -106,6 +107,7 @@ source_h = \
gen75_vpp_vebox.h \
gen8_post_processing.h \
gen9_mfd.h \
+ gen9_mfc.h \
i965_avc_bsd.h \
i965_avc_hw_scoreboard.h\
i965_avc_ildb.h \
diff --git a/src/gen9_mfc.h b/src/gen9_mfc.h
new file mode 100644
index 000..dbbb152
--- /dev/null
+++ b/src/gen9_mfc.h
@@ -0,0 +1,288 @@
+/*
+ * Copyright ?? 2010 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *Qu Pengfei
+ *
+ */
+
+#ifndef _GEN9_HCP_H_
+#define _GEN9_HCP_H_
+
+#include
+#include
+#include
+
+#include "i965_gpe_utils.h"
+
+struct encode_state;
+
+#define MAX_HCP_REFERENCE_SURFACES 8
+#define NUM_HCP_CURRENT_COLLOCATED_MV_TEMPORAL_BUFFERS 9
+
+#define INTRA_MB_FLAG_MASK 0x2000
+
+/* The space required for slice header SLICE_STATE + header.
+ * Is it enough? */
+#define SLICE_HEADER80
+
+/* the space required for slice tail. */
+#define SLICE_TAIL 16
+
+#define __SOFTWARE__0
+
+#define HCP_BATCHBUFFER_HEVC_INTRA 0
+#define HCP_BATCHBUFFER_HEVC_INTER 1
+#define NUM_HCP_KERNEL 2
+
+#define BIND_IDX_VME_OUTPUT 0
+#define BIND_IDX_HCP_SLICE_HEADER 1
+#define BIND_IDX_HCP_BATCHBUFFER2
+
+#define CMD_LEN_IN_OWORD4
+
+struct gen9_hcpe_context {
+struct {
+unsigned int width;
+unsigned int height;
+unsigned int w_pitch;
+unsigned int h_pitch;
+} surface_state;
+
+//HCP_PIPE_BUF_ADDR_STATE
+
+struct {
+dri_bo *bo;
+} deblocking_filter_line_buffer;//OUTPUT: reconstructed
picture with deblocked
+
+struct {
+dri_bo *bo;
+} deblocking_filter_tile_line_buffer; //OUTPUT: reconstructed
picture with deblocked
+
+struct {
+dri_bo *bo;
+} deblocking_filter_tile_column_buffer; //OUTPUT: reconstructed
picture with deblocked
+
+struct {
+dri_bo *bo;
+} uncompressed_picture_source; //INPUT: original compressed
image
+
+struct {
+dri_bo *bo;
+} metadata_line_buffer; //INTERNAL:metadata
+
+struct {
+dri_bo *bo;
+} metadata_tile_line_buffer;//INTERNAL:metadata
+
+struct {
+dri_bo *bo;
+} metadata_tile_column_buffer; //INTERNAL:metadata
+
+struct {
+dri_bo *bo;
+} sao_line_buffer; //INTERNAL:SAO not used in skylake
+
+struct {
+dri_bo *bo;
+} sao_tile_line_buffer;//INTERNAL:SAO not used in skylake
+
+struct {
+dri_bo *bo;
+} sao_tile_column_buffer; //INTERNAL:SAO not used in skylake
+
+struct {
+dri_bo *bo;
+}
current_collocated_mv_temporal_buffer[NUM_HCP_CURRENT_COLLOCATED_MV_TEMPORAL_BUFFERS];
//
+
+struct {
+dri_bo *bo;
+} reference_surfaces[MAX_HCP_REFERENCE_SURFACES]; //INTERNAL: refrence
surfaces
+
+//HCP_IND_OBJ_BASE_ADDR_STATE
+struct {
+dri_bo *bo;
+} hcp_indirect_cu_object; //INPUT: the cu' mv info
+
+struct {
+dri_bo *bo;
+
[Libva] [PATCH 5/5] Added HEVC silce header generated internally
Signed-off-by: Qu,Pengfei
---
src/i965_encoder_utils.c | 475 ++-
src/i965_encoder_utils.h | 43 -
2 files changed, 502 insertions(+), 16 deletions(-)
diff --git a/src/i965_encoder_utils.c b/src/i965_encoder_utils.c
index e59e7fb..a21e65b 100644
--- a/src/i965_encoder_utils.c
+++ b/src/i965_encoder_utils.c
@@ -29,6 +29,7 @@
#include
#include
#include
+#include
#include "i965_encoder_utils.h"
@@ -62,6 +63,17 @@
#define PROFILE_IDC_MAIN77
#define PROFILE_IDC_HIGH100
+/*HEVC*/
+#define VPS_NUT32
+#define SPS_NUT33
+#define PPS_NUT34
+#define IDR_WRADL_NUT 19
+#define IDR_NLP_NUT20
+#define SLICE_TRAIL_N_NUT 0
+#define SLICE_TRAIL_R_NUT 1
+#define PREFIX_SEI_NUT 39
+#define SUFFIX_SEI_NUT 40
+
struct __avc_bitstream {
unsigned int *buffer;
int bit_offset;
@@ -439,13 +451,13 @@ build_avc_sei_pic_timing(unsigned int cpb_removal_length,
unsigned int cpb_remov
int
build_avc_sei_buffer_timing(unsigned int init_cpb_removal_length,
- unsigned int init_cpb_removal_delay,
- unsigned int init_cpb_removal_delay_offset,
- unsigned int cpb_removal_length,
- unsigned int cpb_removal_delay,
- unsigned int dpb_output_length,
- unsigned int dpb_output_delay,
- unsigned char **sei_buffer)
+unsigned int init_cpb_removal_delay,
+unsigned int init_cpb_removal_delay_offset,
+unsigned int cpb_removal_length,
+unsigned int cpb_removal_delay,
+unsigned int dpb_output_length,
+unsigned int dpb_output_delay,
+unsigned char **sei_buffer)
{
unsigned char *byte_buf;
int bp_byte_size, i, pic_byte_size;
@@ -476,7 +488,7 @@ build_avc_sei_buffer_timing(unsigned int
init_cpb_removal_length,
nal_start_code_prefix(&nal_bs);
nal_header(&nal_bs, NAL_REF_IDC_NONE, NAL_SEI);
- /* Write the SEI buffer period data */
+/* Write the SEI buffer period data */
avc_bitstream_put_ui(&nal_bs, 0, 8);
avc_bitstream_put_ui(&nal_bs, bp_byte_size, 8);
@@ -485,7 +497,7 @@ build_avc_sei_buffer_timing(unsigned int
init_cpb_removal_length,
avc_bitstream_put_ui(&nal_bs, byte_buf[i], 8);
}
free(byte_buf);
- /* write the SEI timing data */
+/* write the SEI timing data */
avc_bitstream_put_ui(&nal_bs, 0x01, 8);
avc_bitstream_put_ui(&nal_bs, pic_byte_size, 8);
@@ -562,3 +574,448 @@
build_avc_mvc_slice_header(VAEncSequenceParameterBufferH264_MVC *mvc_sps_param,
return bs.bit_offset;
}
+
+/* HEVC to do for internal header generated*/
+
+void nal_header_hevc(avc_bitstream *bs, int nal_unit_type, int temporalid)
+{
+/* forbidden_zero_bit: 0 */
+avc_bitstream_put_ui(bs, 0, 1);
+/* nal unit_type */
+avc_bitstream_put_ui(bs, nal_unit_type, 6);
+/* layer_id. currently it is zero */
+avc_bitstream_put_ui(bs, 0, 6);
+/* teporalid + 1 .*/
+avc_bitstream_put_ui(bs, temporalid + 1, 3);
+}
+
+int build_hevc_sei_buffering_period(int init_cpb_removal_delay_length,
+unsigned int init_cpb_removal_delay,
+unsigned int init_cpb_removal_delay_offset,
+unsigned char **sei_buffer)
+{
+unsigned char *byte_buf;
+int bp_byte_size, i;
+//unsigned int cpb_removal_delay;
+
+avc_bitstream nal_bs;
+avc_bitstream sei_bp_bs;
+
+avc_bitstream_start(&sei_bp_bs);
+avc_bitstream_put_ue(&sei_bp_bs, 0); /*seq_parameter_set_id*/
+/* SEI buffer period info */
+/* NALHrdBpPresentFlag == 1 */
+avc_bitstream_put_ui(&sei_bp_bs,
init_cpb_removal_delay,init_cpb_removal_delay_length);
+avc_bitstream_put_ui(&sei_bp_bs,
init_cpb_removal_delay_offset,init_cpb_removal_delay_length);
+if ( sei_bp_bs.bit_offset & 0x7) {
+avc_bitstream_put_ui(&sei_bp_bs, 1, 1);
+}
+avc_bitstream_end(&sei_bp_bs);
+bp_byte_size = (sei_bp_bs.bit_offset + 7) / 8;
+
+avc_bitstream_start(&nal_bs);
+nal_start_code_prefix(&nal_bs);
+nal_header_hevc(&nal_bs, PREFIX_SEI_NUT ,0);
+
+/* Write the SEI buffer period data */
+avc_bitstream_put_ui(&nal_bs, 0, 8);
+avc_bitstream_put_ui(&nal_bs, bp_byte_size, 8);
+
+byte_buf = (unsigned char *)sei_bp_bs.buffer;
+for(i = 0; i < bp_byte_size; i++) {
+avc_bitstream_put_ui(&nal_bs, byte_buf[i], 8);
+}
+free(byte_buf);
+
+avc_rbsp_trailing_bits(&nal_bs);
+avc_bitstream_end(&nal_bs);
+
+*sei_buffer = (unsigned char *)nal_bs.buffer;
+
+return nal_
[Libva] [PATCH 3/5] Added to support HEVC related to intel driver API
Signed-off-by: Qu,Pengfei
---
src/i965_device_info.c | 17 +++---
src/i965_drv_video.c | 153 ++---
src/i965_drv_video.h | 15 -
src/i965_encoder.c | 74 +++-
4 files changed, 213 insertions(+), 46 deletions(-)
diff --git a/src/i965_device_info.c b/src/i965_device_info.c
index ac5031a..e400b3f 100755
--- a/src/i965_device_info.c
+++ b/src/i965_device_info.c
@@ -347,6 +347,7 @@ static struct hw_codec_info skl_hw_codec_info = {
.has_blending = 1,
.has_h264_mvc_encoding = 1,
.has_hevc_decoding = 1,
+.has_hevc_encoding = 1,
.num_filters = 5,
.filters = {
@@ -502,7 +503,7 @@ static void cpuid(unsigned int op,
uint32_t *eax, uint32_t *ebx,
uint32_t *ecx, uint32_t *edx)
{
- __cpuid_count(op, 0, *eax, *ebx, *ecx, *edx);
+__cpuid_count(op, 0, *eax, *ebx, *ecx, *edx);
}
/*
@@ -523,7 +524,7 @@ static int intel_driver_detect_cpustring(char *model_id)
/* If the max extended CPUID info is less than 0x8004, fail */
if (rdata[0] < 0x8004)
- return -EINVAL;
+return -EINVAL;
/* obtain the CPUID string */
cpuid(0x8002, &rdata[0], &rdata[1], &rdata[2], &rdata[3]);
@@ -585,18 +586,18 @@ static void hsw_hw_codec_preinit(VADriverContextP ctx,
struct hw_codec_info *cod
model_ptr = (char *)hsw_cpu_hook_list[i];
if (strlen(model_ptr) != model_len)
- continue;
+continue;
if (strncasecmp(model_string, model_ptr, model_len) == 0) {
found = true;
break;
- }
+}
}
if (found) {
- codec_info->has_h264_encoding = 0;
- codec_info->has_h264_mvc_encoding = 0;
- codec_info->has_mpeg2_encoding = 0;
+codec_info->has_h264_encoding = 0;
+codec_info->has_h264_mvc_encoding = 0;
+codec_info->has_mpeg2_encoding = 0;
}
return;
}
@@ -713,7 +714,7 @@ static void gen7_hw_codec_preinit(VADriverContextP ctx,
struct hw_codec_info *co
if (strncasecmp(model_string, model_ptr, model_len) == 0) {
found = true;
break;
- }
+}
}
if (found) {
diff --git a/src/i965_drv_video.c b/src/i965_drv_video.c
index 034ff20..ccae568 100644
--- a/src/i965_drv_video.c
+++ b/src/i965_drv_video.c
@@ -1,5 +1,5 @@
/*
- * Copyright ? 2009 Intel Corporation
+ * Copyright ?2009 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
@@ -104,6 +104,9 @@
#define HAS_HEVC_DECODING(ctx) ((ctx)->codec_info->has_hevc_decoding
&& \
(ctx)->intel.has_bsd)
+#define HAS_HEVC_ENCODING(ctx) ((ctx)->codec_info->has_hevc_encoding
&& \
+ (ctx)->intel.has_bsd)
+
static int get_sampling_from_fourcc(unsigned int fourcc);
/* Check whether we are rendering to X11 (VA/X11 or VA/GLX API) */
@@ -376,7 +379,10 @@ is_image_busy(struct i965_driver_data *i965, struct
object_image *obj_image)
}
#define I965_PACKED_HEADER_BASE 0
-#define I965_PACKED_MISC_HEADER_BASE3
+#define I965_SEQ_PACKED_HEADER_BASE 0
+#define I965_SEQ_PACKED_HEADER_END 2
+#define I965_PIC_PACKED_HEADER_BASE 2
+#define I965_PACKED_MISC_HEADER_BASE4
int
va_enc_packed_type_to_idx(int packed_type)
@@ -393,15 +399,15 @@ va_enc_packed_type_to_idx(int packed_type)
switch (packed_type) {
case VAEncPackedHeaderSequence:
-idx = I965_PACKED_HEADER_BASE + 0;
+idx = I965_SEQ_PACKED_HEADER_BASE + 0;
break;
case VAEncPackedHeaderPicture:
-idx = I965_PACKED_HEADER_BASE + 1;
+idx = I965_PIC_PACKED_HEADER_BASE + 0;
break;
case VAEncPackedHeaderSlice:
-idx = I965_PACKED_HEADER_BASE + 2;
+idx = I965_PIC_PACKED_HEADER_BASE + 1;
break;
default:
@@ -411,7 +417,7 @@ va_enc_packed_type_to_idx(int packed_type)
}
}
-ASSERT_RET(idx < 4, 0);
+ASSERT_RET(idx < 5, 0);
return idx;
}
@@ -465,7 +471,8 @@ i965_QueryConfigProfiles(VADriverContextP ctx,
profile_list[i++] = VAProfileH264StereoHigh;
}
-if (HAS_HEVC_DECODING(i965)) {
+if (HAS_HEVC_DECODING(i965)||
+HAS_HEVC_ENCODING(i965)) {
profile_list[i++] = VAProfileHEVCMain;
}
@@ -548,6 +555,9 @@ i965_QueryConfigEntrypoints(VADriverContextP ctx,
if (HAS_HEVC_DECODING(i965))
entrypoint_list[n++] = VAEntrypointVLD;
+if (HAS_HEVC_ENCODING(i965))
+entrypoint_list[n++] = VAEntrypointEncSlice;
+
break;
default:
@@ -639,7 +649,8 @@ i965_validate_config(VADriverCo
Re: [Libva] [PATCH] MADI: Reject reference surfaces in the wrong format
Hi,Gwenole,
Thanks for your code review and comments.
>>This looks OK as a last resort solution, but it should be completed with an
>>earlier check in vaQueryVideoProcPipelineCaps(). This is the function used to
>>validate the filter chain somehow.
It sounds good idea. vaQueryVideoProcPipelineCaps() just offer the interface to
get the supported image format capability(such as NV12, etc) by application and
then the application (such as gstreamer) will be responsible for the final
image format negociation/validation. Is it correct? This will change the
structure VAProcPipelineParameterBuffer to support this.
>>Besides, I believe we should probably return
>>VA_STATUS_ERROR_INVALID_IMAGE_FORMAT or any other
>>VA_STATUS_ERROR_INVALID_SURFACE_FORMAT that yields the same error code?
Yes, you are right. It should be changed as your comments.
Thanks,
Pengfei
-Original Message-
From: Gwenole Beauchesne [mailto:gb.de...@gmail.com]
Sent: Wednesday, August 27, 2014 12:00 PM
To: Qu, Pengfei
Cc: libva@lists.freedesktop.org
Subject: Re: [Libva] [PATCH] MADI: Reject reference surfaces in the wrong format
Hi,
2014-08-14 13:04 GMT+02:00 Qu, Pengfei :
>
> From b62ef279566e8d2548b519f5b62abceede1042c7 Mon Sep 17 00:00:00 2001
> From: Simon Farnsworth
> Date: Thu, 29 May 2014 10:21:03 +0100
> Subject: [PATCH] MADI: Reject reference surfaces in the wrong format
>
> SNB and IVB DNDI only work with NV12 surfaces. Reject anything else.
>
> Signed-off-by: Simon Farnsworth
> ---
> src/i965_post_processing.c | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git a/src/i965_post_processing.c b/src/i965_post_processing.c
> index 5f5a508..44ba3e0 100755
> --- a/src/i965_post_processing.c
> +++ b/src/i965_post_processing.c
> @@ -3106,6 +3106,11 @@ pp_nv12_dndi_initialize(VADriverContextP ctx, struct
> i965_post_processing_contex
> return VA_STATUS_ERROR_UNIMPLEMENTED;
> }
>
> +if (previous_in_obj_surface && previous_in_obj_surface->fourcc !=
> VA_FOURCC_NV12) {
> +WARN_ONCE("Forward temporal reference must be NV12\n");
> +return VA_STATUS_ERROR_INVALID_PARAMETER;
> +}
> +
> /* source (temporal reference) YUV surface index 5 */
> orig_w = previous_in_obj_surface->orig_width;
> orig_h = previous_in_obj_surface->orig_height;
> @@ -3605,6 +3610,11 @@ gen7_pp_nv12_dndi_initialize(VADriverContextP ctx,
> struct i965_post_processing_c
> return VA_STATUS_ERROR_UNIMPLEMENTED;
> }
>
> +if (previous_in_obj_surface && previous_in_obj_surface->fourcc !=
> VA_FOURCC_NV12) {
> +WARN_ONCE("Forward temporal reference must be NV12\n");
> +return VA_STATUS_ERROR_INVALID_PARAMETER;
> +}
> +
> /* source (temporal reference) YUV surface index 4 */
> orig_w = previous_in_obj_surface->orig_width;
> orig_h = previous_in_obj_surface->orig_height;
> --
> 1.9.0
> ___
> Libva mailing list
> Libva@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/libva
This looks OK as a last resort solution, but it should be completed with an
earlier check in vaQueryVideoProcPipelineCaps(). This is the function used to
validate the filter chain somehow.
Besides, I believe we should probably return
VA_STATUS_ERROR_INVALID_IMAGE_FORMAT or any other
VA_STATUS_ERROR_INVALID_SURFACE_FORMAT that yields the same error code?
Thanks,
--
Gwenole Beauchesne
Intel Corporation SAS / 2 rue de Paris, 92196 Meudon Cedex, France Registration
Number (RCS): Nanterre B 302 456 199
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[Libva] [PATCH] MADI: Reject reference surfaces in the wrong format
>From b62ef279566e8d2548b519f5b62abceede1042c7 Mon Sep 17 00:00:00 2001
From: Simon Farnsworth
Date: Thu, 29 May 2014 10:21:03 +0100
Subject: [PATCH] MADI: Reject reference surfaces in the wrong format
SNB and IVB DNDI only work with NV12 surfaces. Reject anything else.
Signed-off-by: Simon Farnsworth
---
src/i965_post_processing.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/src/i965_post_processing.c b/src/i965_post_processing.c index
5f5a508..44ba3e0 100755
--- a/src/i965_post_processing.c
+++ b/src/i965_post_processing.c
@@ -3106,6 +3106,11 @@ pp_nv12_dndi_initialize(VADriverContextP ctx, struct
i965_post_processing_contex
return VA_STATUS_ERROR_UNIMPLEMENTED;
}
+if (previous_in_obj_surface && previous_in_obj_surface->fourcc !=
VA_FOURCC_NV12) {
+WARN_ONCE("Forward temporal reference must be NV12\n");
+return VA_STATUS_ERROR_INVALID_PARAMETER;
+}
+
/* source (temporal reference) YUV surface index 5 */
orig_w = previous_in_obj_surface->orig_width;
orig_h = previous_in_obj_surface->orig_height;
@@ -3605,6 +3610,11 @@ gen7_pp_nv12_dndi_initialize(VADriverContextP ctx,
struct i965_post_processing_c
return VA_STATUS_ERROR_UNIMPLEMENTED;
}
+if (previous_in_obj_surface && previous_in_obj_surface->fourcc !=
VA_FOURCC_NV12) {
+WARN_ONCE("Forward temporal reference must be NV12\n");
+return VA_STATUS_ERROR_INVALID_PARAMETER;
+}
+
/* source (temporal reference) YUV surface index 4 */
orig_w = previous_in_obj_surface->orig_width;
orig_h = previous_in_obj_surface->orig_height;
--
1.9.0
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