Re: int64_t definition conflict on Aarch64
On 1 January 2013 16:55, Arnd Bergmann a...@arndb.de wrote: On Monday 31 December 2012, Riku Voipio wrote: http://sourceforge.net/mailarchive/forum.php?thread_name=CAAqcGH%3D-xM_a%3DR0o4cWoLqh7wKRLbiuHa_qPtrOBT2watYq_HA%40mail.gmail.comamp;forum_name=fuse-devel No response back yet, The patch basically reverts back to the previous state from a few years ago. I think that is fine, but you seem to be missing the #include statement in the #else path. There is nothing sys/types.h that the header file needs, that's why I didn't include it in the patch. I verified that #else path still compiles by compiling fuse on freebsd. Riku ___ linaro-dev mailing list linaro-dev@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-dev
Re: [U-Boot] [PATCH v3 2/3] EXYNOS: EXYNOS4X12: Add clock structure for EXYNOS4X12
On 26/12/12 15:13, Minkyu Kang wrote: From: Chander Kashyap chander.kash...@linaro.org This patch adds clock structure for Exynos4x12. Signed-off-by: Chander Kashyap chander.kash...@linaro.org Signed-off-by: Minkyu Kang mk7.k...@samsung.com --- Changes since v2: - None arch/arm/include/asm/arch-exynos/clock.h | 276 ++ 1 file changed, 276 insertions(+) applied to u-boot-samsung/master. Thanks, Minkyu Kang. ___ linaro-dev mailing list linaro-dev@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-dev
Re: [U-Boot] [PATCH v3 3/3] EXYNOS: EXYNOS4X12: Add gpio structure for EXYNOS4X12
On 26/12/12 15:13, Minkyu Kang wrote: From: Chander Kashyap chander.kash...@linaro.org This patch adds gpio structure for Exynos4x12. Signed-off-by: Chander Kashyap chander.kash...@linaro.org Signed-off-by: Minkyu Kang mk7.k...@samsung.com --- Changes since v2: - None arch/arm/include/asm/arch-exynos/gpio.h | 85 +++ 1 file changed, 85 insertions(+) applied to u-boot-samsung/master. Thanks, Minkyu Kang. ___ linaro-dev mailing list linaro-dev@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-dev
[PATCH v3 1/3] EXYNOS: EXYNOS4X12: Populate Exynos4x12 register addresses
From: Chander Kashyap chander.kash...@linaro.org
This patch populates base addresses of Exynos4x12 registers.
Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Minkyu Kang mk7.k...@samsung.com
---
Changes since v2:
- rebased, add SPI and I2S addresses.
arch/arm/include/asm/arch-exynos/cpu.h | 48
1 file changed, 42 insertions(+), 6 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h
b/arch/arm/include/asm/arch-exynos/cpu.h
index f06af2e..eb34422 100644
--- a/arch/arm/include/asm/arch-exynos/cpu.h
+++ b/arch/arm/include/asm/arch-exynos/cpu.h
@@ -27,7 +27,7 @@
#define EXYNOS_CPU_NAMEExynos
#define EXYNOS4_ADDR_BASE 0x1000
-/* EXYNOS4 */
+/* EXYNOS4 Common*/
#define EXYNOS4_I2C_SPACING0x1
#define EXYNOS4_GPIO_PART3_BASE0x0386
@@ -63,7 +63,40 @@
#define EXYNOS4_DP_BASEDEVICE_NOT_AVAILABLE
#define EXYNOS4_SPI_ISP_BASE DEVICE_NOT_AVAILABLE
-/* EXYNOS5 */
+/* EXYNOS4X12 */
+#define EXYNOS4X12_GPIO_PART3_BASE 0x0386
+#define EXYNOS4X12_PRO_ID 0x1000
+#define EXYNOS4X12_SYSREG_BASE 0x1001
+#define EXYNOS4X12_POWER_BASE 0x1002
+#define EXYNOS4X12_SWRESET 0x10020400
+#define EXYNOS4X12_USBPHY_CONTROL 0x10020704
+#define EXYNOS4X12_CLOCK_BASE 0x1003
+#define EXYNOS4X12_SYSTIMER_BASE 0x1005
+#define EXYNOS4X12_WATCHDOG_BASE 0x1006
+#define EXYNOS4X12_DMC0_BASE 0x1060
+#define EXYNOS4X12_DMC1_BASE 0x1061
+#define EXYNOS4X12_GPIO_PART4_BASE 0x106E
+#define EXYNOS4X12_GPIO_PART2_BASE 0x1100
+#define EXYNOS4X12_GPIO_PART1_BASE 0x1140
+#define EXYNOS4X12_FIMD_BASE 0x11C0
+#define EXYNOS4X12_MIPI_DSIM_BASE 0x11C8
+#define EXYNOS4X12_USBOTG_BASE 0x1248
+#define EXYNOS4X12_MMC_BASE0x1251
+#define EXYNOS4X12_SROMC_BASE 0x1257
+#define EXYNOS4X12_USB_HOST_EHCI_BASE 0x1258
+#define EXYNOS4X12_USBPHY_BASE 0x125B
+#define EXYNOS4X12_UART_BASE 0x1380
+#define EXYNOS4X12_I2C_BASE0x1386
+#define EXYNOS4X12_PWMTIMER_BASE 0x139D
+
+#define EXYNOS4X12_ADC_BASEDEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_DP_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_MODEM_BASE DEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_I2S_BASEDEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_SPI_BASEDEVICE_NOT_AVAILABLE
+#define EXYNOS4X12_SPI_ISP_BASEDEVICE_NOT_AVAILABLE
+
+/* EXYNOS5 Common*/
#define EXYNOS5_I2C_SPACING0x1
#define EXYNOS5_GPIO_PART4_BASE0x0386
@@ -154,17 +187,20 @@ static inline int proid_is_##type(void)
\
}
IS_EXYNOS_TYPE(exynos4210, 0x4210)
+IS_EXYNOS_TYPE(exynos4412, 0x4412)
IS_EXYNOS_TYPE(exynos5250, 0x5250)
#define SAMSUNG_BASE(device, base) \
static inline unsigned int samsung_get_base_##device(void) \
{ \
- if (cpu_is_exynos4()) \
+ if (cpu_is_exynos4()) { \
+ if (proid_is_exynos4412()) \
+ return EXYNOS4X12_##base; \
return EXYNOS4_##base; \
- else if (cpu_is_exynos5()) \
+ } else if (cpu_is_exynos5()) { \
return EXYNOS5_##base; \
- else\
- return 0; \
+ } \
+ return 0; \
}
SAMSUNG_BASE(adc, ADC_BASE)
--
1.7.9.5
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Re: [U-Boot] [PATCH v3 1/3] EXYNOS: EXYNOS4X12: Populate Exynos4x12 register addresses
On 26/12/12 15:13, Minkyu Kang wrote: From: Chander Kashyap chander.kash...@linaro.org This patch populates base addresses of Exynos4x12 registers. Signed-off-by: Chander Kashyap chander.kash...@linaro.org Signed-off-by: Minkyu Kang mk7.k...@samsung.com --- Changes since v2: - rebased, add SPI and I2S addresses. arch/arm/include/asm/arch-exynos/cpu.h | 48 1 file changed, 42 insertions(+), 6 deletions(-) applied to u-boot-samsung/master. Thanks, Minkyu Kang. ___ linaro-dev mailing list linaro-dev@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-dev
[PATCH v3 3/3] EXYNOS: EXYNOS4X12: Add gpio structure for EXYNOS4X12
From: Chander Kashyap chander.kash...@linaro.org
This patch adds gpio structure for Exynos4x12.
Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Minkyu Kang mk7.k...@samsung.com
---
Changes since v2:
- None
arch/arm/include/asm/arch-exynos/gpio.h | 85 +++
1 file changed, 85 insertions(+)
diff --git a/arch/arm/include/asm/arch-exynos/gpio.h
b/arch/arm/include/asm/arch-exynos/gpio.h
index 4db8fd6..cfe1024 100644
--- a/arch/arm/include/asm/arch-exynos/gpio.h
+++ b/arch/arm/include/asm/arch-exynos/gpio.h
@@ -79,6 +79,67 @@ struct exynos4_gpio_part3 {
struct s5p_gpio_bank z;
};
+struct exynos4x12_gpio_part1 {
+ struct s5p_gpio_bank a0;
+ struct s5p_gpio_bank a1;
+ struct s5p_gpio_bank b;
+ struct s5p_gpio_bank c0;
+ struct s5p_gpio_bank c1;
+ struct s5p_gpio_bank d0;
+ struct s5p_gpio_bank d1;
+ struct s5p_gpio_bank res1[0x5];
+ struct s5p_gpio_bank f0;
+ struct s5p_gpio_bank f1;
+ struct s5p_gpio_bank f2;
+ struct s5p_gpio_bank f3;
+ struct s5p_gpio_bank res2[0x2];
+ struct s5p_gpio_bank j0;
+ struct s5p_gpio_bank j1;
+};
+
+struct exynos4x12_gpio_part2 {
+ struct s5p_gpio_bank res1[0x2];
+ struct s5p_gpio_bank k0;
+ struct s5p_gpio_bank k1;
+ struct s5p_gpio_bank k2;
+ struct s5p_gpio_bank k3;
+ struct s5p_gpio_bank l0;
+ struct s5p_gpio_bank l1;
+ struct s5p_gpio_bank l2;
+ struct s5p_gpio_bank y0;
+ struct s5p_gpio_bank y1;
+ struct s5p_gpio_bank y2;
+ struct s5p_gpio_bank y3;
+ struct s5p_gpio_bank y4;
+ struct s5p_gpio_bank y5;
+ struct s5p_gpio_bank y6;
+ struct s5p_gpio_bank res2[0x3];
+ struct s5p_gpio_bank m0;
+ struct s5p_gpio_bank m1;
+ struct s5p_gpio_bank m2;
+ struct s5p_gpio_bank m3;
+ struct s5p_gpio_bank m4;
+ struct s5p_gpio_bank res3[0x48];
+ struct s5p_gpio_bank x0;
+ struct s5p_gpio_bank x1;
+ struct s5p_gpio_bank x2;
+ struct s5p_gpio_bank x3;
+};
+
+struct exynos4x12_gpio_part3 {
+ struct s5p_gpio_bank z;
+};
+
+struct exynos4x12_gpio_part4 {
+ struct s5p_gpio_bank v0;
+ struct s5p_gpio_bank v1;
+ struct s5p_gpio_bank res1[0x1];
+ struct s5p_gpio_bank v2;
+ struct s5p_gpio_bank v3;
+ struct s5p_gpio_bank res2[0x1];
+ struct s5p_gpio_bank v4;
+};
+
struct exynos5_gpio_part1 {
struct s5p_gpio_bank a0;
struct s5p_gpio_bank a1;
@@ -163,6 +224,30 @@ void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int
gpio, int mode);
- EXYNOS4_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
* GPIO_PER_BANK) + pin) + EXYNOS4_GPIO_PART1_MAX)
+#define exynos4x12_gpio_part1_get_nr(bank, pin) \
+ ((unsigned int) (((struct exynos4x12_gpio_part1 *) \
+ EXYNOS4X12_GPIO_PART1_BASE)-bank)) \
+ - EXYNOS4X12_GPIO_PART1_BASE) / sizeof(struct s5p_gpio_bank)) \
+ * GPIO_PER_BANK) + pin)
+
+#define EXYNOS4X12_GPIO_PART1_MAX ((sizeof(struct exynos4x12_gpio_part1) \
+ / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
+
+#define exynos4x12_gpio_part2_get_nr(bank, pin) \
+ (((unsigned int) (((struct exynos4x12_gpio_part2 *) \
+ EXYNOS4X12_GPIO_PART2_BASE)-bank)) \
+ - EXYNOS4X12_GPIO_PART2_BASE) / sizeof(struct s5p_gpio_bank)) \
+ * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART1_MAX)
+
+#define EXYNOS4X12_GPIO_PART2_MAX ((sizeof(struct exynos4x12_gpio_part2) \
+ / sizeof(struct s5p_gpio_bank)) * GPIO_PER_BANK)
+
+#define exynos4x12_gpio_part3_get_nr(bank, pin) \
+ (((unsigned int) (((struct exynos4x12_gpio_part3 *) \
+ EXYNOS4X12_GPIO_PART3_BASE)-bank)) \
+ - EXYNOS4X12_GPIO_PART3_BASE) / sizeof(struct s5p_gpio_bank)) \
+ * GPIO_PER_BANK) + pin) + EXYNOS4X12_GPIO_PART2_MAX)
+
#define exynos5_gpio_part1_get_nr(bank, pin) \
((unsigned int) (((struct exynos5_gpio_part1 *) \
EXYNOS5_GPIO_PART1_BASE)-bank)) \
--
1.7.9.5
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[PATCH v3 2/3] EXYNOS: EXYNOS4X12: Add clock structure for EXYNOS4X12
From: Chander Kashyap chander.kash...@linaro.org
This patch adds clock structure for Exynos4x12.
Signed-off-by: Chander Kashyap chander.kash...@linaro.org
Signed-off-by: Minkyu Kang mk7.k...@samsung.com
---
Changes since v2:
- None
arch/arm/include/asm/arch-exynos/clock.h | 276 ++
1 file changed, 276 insertions(+)
diff --git a/arch/arm/include/asm/arch-exynos/clock.h
b/arch/arm/include/asm/arch-exynos/clock.h
index ff6781a..9b56b4e 100644
--- a/arch/arm/include/asm/arch-exynos/clock.h
+++ b/arch/arm/include/asm/arch-exynos/clock.h
@@ -251,6 +251,282 @@ struct exynos4_clock {
unsigned intdiv_iem_l1;
};
+struct exynos4x12_clock {
+ unsigned char res1[0x4200];
+ unsigned intsrc_leftbus;
+ unsigned char res2[0x1fc];
+ unsigned intmux_stat_leftbus;
+ unsigned char res3[0xfc];
+ unsigned intdiv_leftbus;
+ unsigned char res4[0xfc];
+ unsigned intdiv_stat_leftbus;
+ unsigned char res5[0x1fc];
+ unsigned intgate_ip_leftbus;
+ unsigned char res6[0x12c];
+ unsigned intgate_ip_image;
+ unsigned char res7[0xcc];
+ unsigned intclkout_leftbus;
+ unsigned intclkout_leftbus_div_stat;
+ unsigned char res8[0x37f8];
+ unsigned intsrc_rightbus;
+ unsigned char res9[0x1fc];
+ unsigned intmux_stat_rightbus;
+ unsigned char res10[0xfc];
+ unsigned intdiv_rightbus;
+ unsigned char res11[0xfc];
+ unsigned intdiv_stat_rightbus;
+ unsigned char res12[0x1fc];
+ unsigned intgate_ip_rightbus;
+ unsigned char res13[0x15c];
+ unsigned intgate_ip_perir;
+ unsigned char res14[0x9c];
+ unsigned intclkout_rightbus;
+ unsigned intclkout_rightbus_div_stat;
+ unsigned char res15[0x3608];
+ unsigned intepll_lock;
+ unsigned char res16[0xc];
+ unsigned intvpll_lock;
+ unsigned char res17[0xec];
+ unsigned intepll_con0;
+ unsigned intepll_con1;
+ unsigned intepll_con2;
+ unsigned char res18[0x4];
+ unsigned intvpll_con0;
+ unsigned intvpll_con1;
+ unsigned intvpll_con2;
+ unsigned char res19[0xe4];
+ unsigned intsrc_top0;
+ unsigned intsrc_top1;
+ unsigned char res20[0x8];
+ unsigned intsrc_cam;
+ unsigned intsrc_tv;
+ unsigned intsrc_mfc;
+ unsigned intsrc_g3d;
+ unsigned char res21[0x4];
+ unsigned intsrc_lcd;
+ unsigned intsrc_isp;
+ unsigned intsrc_maudio;
+ unsigned intsrc_fsys;
+ unsigned char res22[0xc];
+ unsigned intsrc_peril0;
+ unsigned intsrc_peril1;
+ unsigned intsrc_cam1;
+ unsigned char res23[0xb4];
+ unsigned intsrc_mask_top;
+ unsigned char res24[0xc];
+ unsigned intsrc_mask_cam;
+ unsigned intsrc_mask_tv;
+ unsigned char res25[0xc];
+ unsigned intsrc_mask_lcd;
+ unsigned intsrc_mask_isp;
+ unsigned intsrc_mask_maudio;
+ unsigned intsrc_mask_fsys;
+ unsigned char res26[0xc];
+ unsigned intsrc_mask_peril0;
+ unsigned intsrc_mask_peril1;
+ unsigned char res27[0xb8];
+ unsigned intmux_stat_top0;
+ unsigned intmux_stat_top1;
+ unsigned char res28[0x10];
+ unsigned intmux_stat_mfc;
+ unsigned intmux_stat_g3d;
+ unsigned char res29[0x28];
+ unsigned intmux_stat_cam1;
+ unsigned char res30[0xb4];
+ unsigned intdiv_top;
+ unsigned char res31[0xc];
+ unsigned intdiv_cam;
+ unsigned intdiv_tv;
+ unsigned intdiv_mfc;
+ unsigned intdiv_g3d;
+ unsigned char res32[0x4];
+ unsigned intdiv_lcd;
+ unsigned intdiv_isp;
+ unsigned intdiv_maudio;
+ unsigned intdiv_fsys0;
+ unsigned intdiv_fsys1;
+ unsigned intdiv_fsys2;
+ unsigned intdiv_fsys3;
+ unsigned intdiv_peril0;
+ unsigned intdiv_peril1;
+ unsigned intdiv_peril2;
+ unsigned intdiv_peril3;
+ unsigned intdiv_peril4;
+ unsigned intdiv_peril5;
+ unsigned intdiv_cam1;
+ unsigned char res33[0x14];
+ unsigned intdiv2_ratio;
+ unsigned char res34[0x8c];
+ unsigned intdiv_stat_top;
+ unsigned char res35[0xc];
+ unsigned intdiv_stat_cam;
+ unsigned intdiv_stat_tv;
+ unsigned intdiv_stat_mfc;
+ unsigned intdiv_stat_g3d;
+ unsigned char res36[0x4];
+ unsigned intdiv_stat_lcd;
+ unsigned intdiv_stat_isp;
+ unsigned intdiv_stat_maudio;
+ unsigned intdiv_stat_fsys0;
+ unsigned
Re: sched: Consequences of integrating the Per Entity Load Tracking Metric into the Load Balancer
On Wed, 2013-01-02 at 09:52 +0530, Preeti U Murthy wrote: Hi everyone, I have been looking at how different workloads react when the per entity load tracking metric is integrated into the load balancer and what are the possible reasons for it. I had posted the integration patch earlier: https://lkml.org/lkml/2012/11/15/391 Essentially what I am doing is: 1.I have disabled CONFIG_FAIR_GROUP_SCHED to make the analysis simple 2.I have replaced cfs_rq-load.weight in weighted_cpuload() with cfs.runnable_load_avg,the active load tracking metric. 3.I have replaced se.load.weight in task_h_load() with se.load.avg.contrib,the per entity load tracking metric. 4.The load balancer will end up using these metrics. After conducting experiments on several workloads I found out that the performance of the workloads with the above integration would neither improve nor deteriorate.And this observation was consistent. Ideally the performance should have improved considering,that the metric does better tracking of load. Let me explain with a simple example as to why we should see a performance improvement ideally:Consider 2 80% tasks and 1 40% task. With integration: 40% 80%40% cpu1 cpu2 The above will be the scenario when the tasks fork initially.And this is a perfectly balanced system,hence no more load balancing.And proper distribution of loads on the cpu. Without integration --- 40% 40% 80%40% 80%40% cpu1 cpu2OR cpu1 cpu2 Because the view is that all the tasks as having the same load.The load balancer could ping pong tasks between these two situations. When I performed this experiment,I did not see an improvement in the performance though in the former case.On further observation I found that the following was actually happening. With integration Initially 40% task sleeps 40% task wakes up and select_idle_sibling() decides to wake it up on cpu1 40% - - 40% 80%40%80%40% 80% 40% cpu1 cpu2cpu1 cpu2 cpu1 cpu2 This makes load balance trigger movement of 40% from cpu1 back to cpu2.Hence the stability that the load balancer was trying to achieve is gone.Hence the culprit boils down to select_idle_sibling.How is it the culprit and how is it hindering performance of the workloads? *What is the way ahead with the per entity load tracking metric in the load balancer then?* select_idle_sibling() is all about dynamic, lowering latency and cranking up cores during ramp-up to boost throughput. If you want the system to achieve a stable state with periodic balancing, you need to turn select_idle_sibling() the heck off. Once you've gotten the box mostly committed, it's just an overhead/bounce source anyway. In replies to a post by Paul in https://lkml.org/lkml/2012/12/6/105, he mentions the following: It is my intuition that the greatest carnage here is actually caused by wake-up load-balancing getting in the way of periodic in establishing a steady state. I suspect more mileage would result from reducing the interference wake-up load-balancing has with steady state. The whole point of using blocked load is so that you can converge on a steady state where you don't NEED to move tasks. What disrupts this is we naturally prefer idle cpus on wake-up balance to reduce wake-up latency. I think the better answer is making these two processes load balancing() and select_idle_sibling() more co-operative. The down-side of steady state seeking via load tracking being that you want to take N% average load tasks, and stack them on top of each other, which does nothing good for those tasks when they overlap in execution. Long term balance looks all pretty, but if one or more of them could have slipped into an idle shared cache, it's still a latency hit and utilization loss. You are at odds with select_idle_sibling()'s mission. It cares about the here and now, while load tracking cares about fuzzy long-term averages. I had not realised how this would happen until I saw it happening in the above experiment. select_idle_sibling()'s job is to be annoying as hell.. and it does that very well :) Based on what Paul explained above let us use the runnable load + the blocked load for calculating the load on a cfs runqueue rather than just the runnable load(which is what i am doing now) and see its consequence. Initially: 40% task sleeps 40% 80%40% - 80% 40% cpu1 cpu2 cpu1 cpu2 So initially the load on cpu1 is say 80 and on cpu2 also it is 80.Balanced.Now when 40% task sleeps,the total load on cpu2=runnable load+blocked load.which is still 80. As a consequence,firstly,during periodic load
Re: HMP patches v2
On 2 January 2013 06:28, Viresh Kumar viresh.ku...@linaro.org wrote: On 20 December 2012 13:41, Vincent Guittot vincent.guit...@linaro.org wrote: On 19 December 2012 11:57, Morten Rasmussen morten.rasmus...@arm.com wrote: If I understand the new version of sched: secure access to other CPU statistics correctly, the effect of the patch is: Without the patch the cpu will appear to be busy if sum/period are not coherent (sumperiod). The same is true with the patch except in the case where nr_running is 0. In this particular case the cpu will appear not to be busy. I assume there is good reason why this particular case is important? Sorry for this late reply. It's not really more important than other but it's one case we can safely detect to prevent spurious spread of tasks. In addition, The incoherency occurs if both value are close so nr_running == 0 was the only condition that left to be tested In any case the patch is fine by me. Hmm... I am still confused :( We have two patches from ARM, do let me know if i can drop these: I think you can drop them as they don't apply anymore for V2. Morten, do you confirm ? Vincent commit 3f1dff11ac95eda2772bef577e368bc124bfe087 Author: Morten Rasmussen morten.rasmus...@arm.com Date: Fri Nov 16 18:32:40 2012 + ARM: TC2: Re-enable SD_SHARE_POWERLINE Re-enable SD_SHARE_POWERLINE to reflect the power domains of TC2. arch/arm/kernel/topology.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) commit e8cceacd3913e3a3e955614bacc1bc81866bc243 Author: Liviu Dudau liviu.du...@arm.com Date: Fri Nov 16 18:32:38 2012 + Revert sched: secure access to other CPU statistics This reverts commit 2aa14d0379cc54bc0ec44adb7a2e0ad02ae293d0. The way this functionality is implemented is under review and the current implementation is considered not safe. Signed-of-by: Liviu Dudau liviu.du...@arm.com kernel/sched/fair.c | 19 ++- 1 file changed, 2 insertions(+), 17 deletions(-) ___ linaro-dev mailing list linaro-dev@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-dev
booting an exynos
Hi All, happy new year ! I am trying to boot my exynos board for the first time but I have no console output (the line shows offline). I used a serial-usb with minicom and screen. The web site origenboard.org is down, so I have no information available. Is there a trick I missed ? Did anyone face this problem ? Thanks -- Daniel -- http://www.linaro.org/ Linaro.org │ Open source software for ARM SoCs Follow Linaro: http://www.facebook.com/pages/Linaro Facebook | http://twitter.com/#!/linaroorg Twitter | http://www.linaro.org/linaro-blog/ Blog ___ linaro-dev mailing list linaro-dev@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-dev
raring ringtail test rebuild
A test rebuild of raring ringtail started in 2012 for the amd64, i386 and armhf architectures is now finished for all components on armhf. The amd64 and i386 rebuilds will hopefully finish in a few days. Results can be seen at http://people.ubuntuwire.org/~wgrant/rebuild-ftbfs-test/test-rebuild-20121221-raring.html The archive for the test rebuild is https://launchpad.net/ubuntu/+archive/test-rebuild-20121221/ Some common build failures are: - not finding pyconfig.h, installed into a multiarch include dir - eglibc-2.16 changes (puts). Please help fixing the build failures for the final release. Matthias PS: For those interested, a second test rebuild using a snapshot of GCC-4.8 is going on. Status at http://people.ubuntuwire.org/~wgrant/rebuild-ftbfs-test/test-rebuild-20121221-4.8-raring.html ___ linaro-dev mailing list linaro-dev@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-dev
Re: raring ringtail test rebuild
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 W dniu 02.01.2013 16:58, Matthias Klose pisze: A test rebuild of raring ringtail started in 2012 for the amd64, i386 and armhf architectures is now finished for all components on armhf. The amd64 and i386 rebuilds will hopefully finish in a few days. I think this is the first time that I recall, where arm finished before any intel-like parts :-) Was the rebuild for arm smaller or just started earlier? Thanks ZK -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.11 (GNU/Linux) Comment: Using GnuPG with undefined - http://www.enigmail.net/ iQIcBAEBAgAGBQJQ5GClAAoJEOvx/vtfL8ZX2ooQAJ4GDkDh2hKz5Jn9quEHcfQq pdVt6SlPLptZVPLKToTpymKFpzrxim6WLa8CikZBP7ckO6GvCMKLHTCK2qtmA7WM iAR9fEiXvFL8/V0gCyJcy6mReZ5OzdXgI/wxjFbDTrWVju4ygEe7B9ZTXAx2mIuM glzq4yk39xYG33jtygaFEs63WF/huOqRKGWma+pSS/i2cgj/WvoV9nz6serRx/Vw gEFIf3rMPoS880cwJK2+H0fcxlxLHYLwDZ7Zwk877uGScQp9+mUl7FcT5jbJPHYj xmcEcm5pZ8voXbRx1eTN3hbc5+an3cs209Lx8Z4SDf/9uqP3Sht17R1J7/l9lhJ6 /+nMu02vIXNivxlQIdnp6DNaGxvvYe51axLi5DnTKNpwso1r0enSwNHRNZp3MPw6 gWgCVvdLbP2i7EnCTORf0etkYdT3zDDS7EWpeWTqMoLhvXFf77ozyBGVWhPFinqd FtHATi1FeyyqKQf0vYXV9ROZoCfPWHP4G51q/q+uPDVwqBtBMWKuqy28Uy5SMLih WKg/+3wzi2Zi3wycPWEp1MF17GPn8xfeglNFscbMTRvFho8NOZzD2gaAVqGiH1HZ Dtcd3bYWTayuYsBlZpkFg3Q3JQe2IVX5n3nmuIPy5vPsMC/fv3Y0xjwumkkkge9V nNQcZIkqtMQryZ+PLmlZ =cEiU -END PGP SIGNATURE- ___ linaro-dev mailing list linaro-dev@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-dev
Re: HMP patches v2
On 02/01/13 10:29, Vincent Guittot wrote: On 2 January 2013 06:28, Viresh Kumar viresh.ku...@linaro.org wrote: On 20 December 2012 13:41, Vincent Guittot vincent.guit...@linaro.org wrote: On 19 December 2012 11:57, Morten Rasmussen morten.rasmus...@arm.com wrote: If I understand the new version of sched: secure access to other CPU statistics correctly, the effect of the patch is: Without the patch the cpu will appear to be busy if sum/period are not coherent (sumperiod). The same is true with the patch except in the case where nr_running is 0. In this particular case the cpu will appear not to be busy. I assume there is good reason why this particular case is important? Sorry for this late reply. It's not really more important than other but it's one case we can safely detect to prevent spurious spread of tasks. In addition, The incoherency occurs if both value are close so nr_running == 0 was the only condition that left to be tested In any case the patch is fine by me. Hmm... I am still confused :( We have two patches from ARM, do let me know if i can drop these: I think you can drop them as they don't apply anymore for V2. Morten, do you confirm ? Confirmed. I don't see any problems with the v2 patch. The overhead of the check should be minimal. Morten Vincent commit 3f1dff11ac95eda2772bef577e368bc124bfe087 Author: Morten Rasmussen morten.rasmus...@arm.com Date: Fri Nov 16 18:32:40 2012 + ARM: TC2: Re-enable SD_SHARE_POWERLINE Re-enable SD_SHARE_POWERLINE to reflect the power domains of TC2. arch/arm/kernel/topology.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) commit e8cceacd3913e3a3e955614bacc1bc81866bc243 Author: Liviu Dudau liviu.du...@arm.com Date: Fri Nov 16 18:32:38 2012 + Revert sched: secure access to other CPU statistics This reverts commit 2aa14d0379cc54bc0ec44adb7a2e0ad02ae293d0. The way this functionality is implemented is under review and the current implementation is considered not safe. Signed-of-by: Liviu Dudau liviu.du...@arm.com kernel/sched/fair.c | 19 ++- 1 file changed, 2 insertions(+), 17 deletions(-) -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ___ linaro-dev mailing list linaro-dev@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-dev
Re: booting an exynos
On 2 January 2013 03:32, Daniel Lezcano daniel.lezc...@linaro.org wrote: Hi All, happy new year ! I am trying to boot my exynos board for the first time but I have no console output (the line shows offline). I used a serial-usb with minicom and screen. The web site origenboard.org is down, so I have no information available. Is there a trick I missed ? Did anyone face this problem ? Make sure console port is set as 2 (CONFIG_S3C_LOWLEVEL_UART_PORT). If this still does not help, please let me know the Exynos processor on the board (Exynos4210 or Exynos4412) and the mainline kernel version you are using. Thanks, Thomas. Thanks -- Daniel -- http://www.linaro.org/ Linaro.org │ Open source software for ARM SoCs Follow Linaro: http://www.facebook.com/pages/Linaro Facebook | http://twitter.com/#!/linaroorg Twitter | http://www.linaro.org/linaro-blog/ Blog ___ linaro-dev mailing list linaro-dev@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-dev ___ linaro-dev mailing list linaro-dev@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-dev
Re: [PATCH 1/3] cpufreq: Manage only online cpus
On Wednesday, January 02, 2013 11:59:57 AM Viresh Kumar wrote: On 16 December 2012 19:07, Viresh Kumar viresh.ku...@linaro.org wrote: On 16 December 2012 18:34, Rafael J. Wysocki r...@sisk.pl wrote: Well, this series makes sense to me, but I'd like to hear what the other people think. That sounds great :) Some more information for others about how i reached to these issues is present here: https://lkml.org/lkml/2012/12/10/44 Hmm.. I don't know, if we are going to get any feedback from others :( Surely somebody cares except for us two? BTW, i consider them as fixes and so would make sense to get them in next rc. What do you think? Yes, if somebody tells me yes, this fixes a problem for me. Otherwise, I don't quite see the reason. Thanks, Rafael -- I speak only for myself. Rafael J. Wysocki, Intel Open Source Technology Center. ___ linaro-dev mailing list linaro-dev@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-dev
Re: [PATCH 1/3] cpufreq: Manage only online cpus
On 3 January 2013 06:43, Rafael J. Wysocki r...@sisk.pl wrote: BTW, i consider them as fixes and so would make sense to get them in next rc. What do you think? Yes, if somebody tells me yes, this fixes a problem for me. Otherwise, I don't quite see the reason. I don't know how much people test HOTPLUG, but there are clear bugs related to hotplug of cpus on a multiple cpu system :) ___ linaro-dev mailing list linaro-dev@lists.linaro.org http://lists.linaro.org/mailman/listinfo/linaro-dev
