[ACTIVITY] week ending 8 Jan 2023
* A couple of attempts at minimizing arm per-cpu init work. I've posted a short/medium-term solution for the lookup issue, so that we can re-apply Alex's CPUState unrealize patch. * TCG patch queue flushed, including call abi reorg. - Rebase TCGv_i128 patch set - Rebase goto_tb race condition patch set r~ ___ linaro-toolchain mailing list -- linaro-toolchain@lists.linaro.org To unsubscribe send an email to linaro-toolchain-le...@lists.linaro.org
Virt meeting 2022-11-01
Hi guys,
I will attempt to join today, but we've been finding that connectivity is dependent on the
number of rain drops and/or hail in between here and the mast. So I'm not overly hopeful
for later this evening.
Status report:
- Fixed a failure in my x86 TARGET_TB_PCREL patches, which caused
non-booting of some images (in today's tcg PR).
- Revised the TCGv_i128 patch set (not yet posted).
- Lots of work on accel/tcg/{cputlb,user-exec}.c, to honor
atomicity requirements of FEAT_LSE2.
Next up: Adding qemu_ld/st helpers and patterns for i128.
r~
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qemu meeting status
Hi guys. I just realized that today's meeting will be right in the middle of dinner plans. I'll organize better next week. Anyway, here's my status: - Fourth SME patch set -- parts merged, and some bugs fixed. - Base/arm-compat portion of semihosting rewrite now upstream. Target-specific bits for m68k, mips, nios2, xtensa outstanding. - Almost done with FEAT_HAFDBS (hardware access/dirty updates). Big changes to ptw.c to make that work: 50+ patches. The reorg should make FEAT_RME easier though. r~ ___ linaro-toolchain mailing list -- linaro-toolchain@lists.linaro.org To unsubscribe send an email to linaro-toolchain-le...@lists.linaro.org
Re: [TCWG CI] 456.hmmer grew in size by 9% after llvm: Extend the `uwtable` attribute with unwind table kind
On 3/28/22 10:46, Momchil Velikov wrote: Your patch seems to significantly increase code-size of several benchmarks — by up to 9%. Would you please investigate whether this can be avoided? Could you, please, confirm if the size increase is due to having bigger `.eh_frame`/`.debug_frame` sections? It looks like the reason is generating a bunch of non-sensical unwind info entries for outlined functions, e.g.: 00bc 0010 00c0 FDE cie= pc=0c34..0c3c DW_CFA_nop DW_CFA_nop DW_CFA_nop That's not nonsensical, that just means the entire unwind for this pc range is contained in the CIE description. The nops are for the alignment of the next record. I'm working on a patch to not emit .cfi_startproc/.cfi_endproc if a function does not contain any CFI instructions. Be very careful about what "no cfi" really means for leaf functions, when fasynchronous-unwind-tables is in use or to the debugger. r~ ___ linaro-toolchain mailing list -- linaro-toolchain@lists.linaro.org To unsubscribe send an email to linaro-toolchain-le...@lists.linaro.org
On holiday through 22 Jan
Hi Peter, Welcome back, hope you had a good Christmas break. I'm off oh holiday myself for the next two weeks, so this would be an ideal time to pass back merge control to you. The board is mostly green now, with occasional allowed failures for centos-stream and freebsd for upstream package manager failures. See yall in a couple of weeks. r~ ___ linaro-toolchain mailing list -- linaro-toolchain@lists.linaro.org To unsubscribe send an email to linaro-toolchain-le...@lists.linaro.org
[ACTIVITY] week ending 9 Jan 2022
[UM-2] * Re-greening of gitlab-ci. - There are continuing issues with cross-i386-tci. Occasionally I see *really* long test times: https://gitlab.com/qemu-project/qemu/-/jobs/1941996332 with qtest-aarch64/qom-test taking 1738s, or 28 of the 60 minute budget. More often it's merely slow: https://gitlab.com/qemu-project/qemu/-/jobs/1954634840 with qtest-aarch64/qom-test taking 538s. Note that locally this test runs in about 100s, and I have been unable to determine why it runs so much slower on gitlab. - Worked on a ppc64-softmmu slowdown leading to timeouts. - Fixes for meson regressions affecting testing. * Refresh tcg unaligned user patch sets. r~ ___ linaro-toolchain mailing list -- linaro-toolchain@lists.linaro.org To unsubscribe send an email to linaro-toolchain-le...@lists.linaro.org
[ACTIVITY] week ending 21 Nov 2021
[UM-2] * release work * revived some 6month old ppc fpu fixes * reviews: loongarch, riscv, watchpoints, gdbstub. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 29 Aug 2021
(PSA: On holiday through 11 September.) [ UM-2 ] * Some patch review * Revise riscv tcg_constant cleanup * Cleanup tcg/optimize.c * Optimize repeat sign-extensions. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 11 Jul 2021
[ UM-2 ] * Sent v2 vdso + signal page patch set. * Fix #457 (tb_phys_invalidate_cont) * Fix #187 (arm on s390x) * Sent new rev for i386 fcs:fip patch set. * Sent v3 translator_use_goto_tb patch set. * Sent bswap cleanup. * Sent tcg_constant cleanups: alpha, hppa, openrisc, riscv. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
toolchain+qemu regression testing
Hey, Maxim, You recently mentioned we have such a setup working, yes? Is there an easy way to point the qemu portion to a custom branch? I'm currently working on adding vdso support to qemu, and want to make sure that the unwind info that I've written works correctly with libgcc and llvm's libunwind. Also, what arm CPU models are being used? My edge cases are v4, v4t, m0 (which is not really linux-user, but I think Christophe Lyon had made work). r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
Re: Binutils help? Aarch64 PE/COFF support to enable UEFI Secure Boot
On 6/29/21 7:32 AM, Steve McIntyre wrote: Hi Adhemerval, On Mon, Jun 28, 2021 at 04:37:34PM -0300, Adhemerval Zanella wrote: Peter Jones from Red Hat (pjo...@redhat.com ) seems to working on adding support for aarch64, by the last common on the thread. His work seems to be quite recent (6th may), so we might want to check with him if he is planning to finish this work. AIUI Peter started hacking on this a while back, but he told me he was definitely looking for somebody to restart or pick it up. It's not really his area of expertise. I've added him in CC here... Another option might to check lld, we have it working on llvm for windows on aarch64. It might be ready available or require less adjustment than add the full binutils support. Ideally it would be nice to have more than just objcopy/ld. At the moment debugging builds is awkward; objdump refuses to do anything useful with our binaries, for example. Basic format support would include objdump. The second level of support would be ld with elf input and pecoff output. Third level would be pecoff assemble+link. It shouldn't be difficult to get basic pecoff-arm64 support, which sounds like the level that you require for uefi. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 20 Jun 2021
[UM-2] * Version 2 of signal trampolines, * Version 1 of vdso, * RFC patch set for #360 (unaligned mmio), * Beginning on #404 (breakpoint slowdown), - convert cris, nios2, avr to translator loop. - translator_use_goto_tb Both of these, working toward improving the recognition of pc's with bp's, and avoiding the need for any tb flushing at all. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 13 Jun 2021
[UM-2] Upstream bugs: #390, fix posted #403, fix posted #360, lots of investigation, and work on updating a patch from 2017. I have a workable change, which ought to be improved. Reorg for tcg bswap opcode. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 6 June 2021
[UM-2] * Refresh tci patch set. * Review: - target/s390 vector enhancements - arm refactor * Knocked up a tcg patch for Peter's MVE work. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 16 May 2021
3 day week. [UM-2 # QEMU Upstream] * Refresh target/i386 translate user/sysemu cleanup. * Pull request for half of my softfloat reorg. * Tiny pull request for collected tcg patches. [QEMU-349 # SVE2] * Processing Peter's review comments. Another 3 day week this week. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 2 May 2021
[um-2] Patch review: power10, arm. Fixes for Alex's new signals.c test: sparc, s390. [qemu-349] Refreshed sve2 patch set. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 11 Apr 2021
[UM-2] * Patch review. Lots. [QEMU-389 # Bfloat16 ] * Implemented. Will post patches next week. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
qemu bfloat16 branch
https://gitlab.com/rth7680/qemu/-/commits/tgt-arm-bf16 It isn't a large extension, so all done. I added aarch64 simd, aarch32 neon, and sve support all at once. I've tested it via risu vs FVP. I've based this on my SVE2 branch, since there are some cleanups that made that easier. I'll post patches to qemu-devel next week. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 28 Mar 2021
[UM-2] * Fix exec-vary.c vs gcc -flto. * Fix ppc tb->flags usage. * Patch review: - v11 of claudio's arm accel work - hexagon stuff - arm pcmr settings r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 14 Mar 2021
[UM-2] * Clean up tcg code_gen_buffer mapping. * Clean up ppc tb->flags madness. * Rebase tci clean up. * Random patch review. [VIRT-349] * Send v4 of sve2 patch set. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 7 Mar 2021
[VIRT-349 # QEMU SVE2 Support ] I have a working FVP SVE2 install! I used a new FVP version (11.13.36) from the last time that I tried (11.13.21 on Jan 27). I used a debian-testing snapshot from 1-MAR, which has linux 5.10 bundled, and fvp revc dtb installed. I used https://git.linaro.org/landing-teams/working/arm/arm-reference-platforms.git/ (which is linked to by one of the howtos that Peter forwarded) and chose the "pre-built uefi" version. I need to report a bug on this build script -- the "build from source" option does not work on a system that has all python3 and no python2. I've rebuilt all of the risu trace files for vq=4 (512-bit). I'm now refreshing my qemu branch to test. [UM-61 # TCG Core Maintainership ] PR for patch queue; aa64 fixes, tci fixes, tb_lookup cleanups. [UM-2 # Upstream Maintainership ] Patch review, mostly v8.1m board stuff. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
Re: What does suffix ' ... isra.0' mean in compiled symbols in GCC 10.2?
On 3/5/21 12:37 AM, Guodong Xu wrote: Thanks to John Stultz, now I know that this may relate to the new improvements about IPA-SRA in GCC 10. Refer to [1], which states: "Inter-procedural optimization improvements: The inter-procedural scalar replacement of aggregates (IPA-SRA) pass was re-implemented to work at link-time and can now also remove computing and returning unused return values." However, such a change of symbol names negatively impacts the tracing tools commonly used in kernel debugging. Such as bcc/eBPF, who __hardcoded__ function names (without the .isra.0 suffix) into their scripts. You can add __noclone to prevent such. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 28 Feb 2021
[UM-2 # QEMU Upstream Work] * A lot of patch review. * Some target/i386 cleanup, as followup to said patch review. * Collecting patches for tcg-next. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 21 Feb 2021
* After proving that the aarch64 host problem with booting s390x with virtio was lack of barriers for the guest memory model, I've spent some time working on a ld-acq/st-rel optimizer for tcg. * Minor rev of tci rewrite. * Some patch review on claudio's kvm/tcg split. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 24 Jan 2021
[UM-61 TCG Maint] 3 different attempts at fixing the out-of-temps failure produced by the tcg-constant patch set. The last, longjmp to restart w/ a smaller tb, seems unlikely to have unanticipated side effects. [UM-2 QEMU Maint] Refresh two patches toward cortex-a76. Misc patch review. Partial fix for target/ppc mis-use of tb->flags. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 17 Jan 2021
[UM-61 TCG Maint] Refresh tcg backend constraints. Pull request for tcg constants. -- which caused reported failures. [UM-2 QEMU Maint] Refresh sve pred_desc fixes. Refresh arm alignment fixes. Misc review. [QEMU-344 ARMv8.5-MemTag] Refresh mte user-only patch set. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] 2 weeks ending 27 Dec 2020
(or the 10 days preceding Christmas) [UM-61 TCG Maint] New version of tcg constants patch set. TCG backend constraints cleanup. ARM NEON host patch set. [UM-2 QEMU Maint] Fixed tcg gvec bug vs hosts without vector support. Rebase and re-send pauth impdef algorithm. Patch review: mips, riscv. gdbstub. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 13 Dec 2020
[UM-2] New revision on arm alignment patch set. Patch review: mips and i386 cleanups. [UM-61] New revision on splitwx patch set. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 6 Dec 2020
[UM-59] More work on softfloat rem; f128 still needs work. [UM-2] Patch review, notably v8.1m, mips cleanups, arc port. Revisions to arm alignment patch set. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 22 Nov 2020
[UM-59 # FPU Emulation Maintainership ] Lots more work converting to FloatParts. Almost all floatx80 now converted. Still to do are log2 and rem/mod for full conversion. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 8 Nov 2020
[VIRT-327 # Richard's upstream QEMU work ] * Fix neon register offsets big-endian hosts. * Fix neon register offsets for VTBL. * Working through a 4th revision of float128_muladd. * Random patch review and bug fixes. [UM-61 # TCG Core Maintainership ] * Two revisions of split w^x patch set. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 25 Oct 2020
[VIRT-327 # Richard's upstream QEMU work ] More time than I expected on float128_muladd, adjusting the codebase to share code with float64_muladd. [VIRT-339 # ARMv8.5-BTI, Branch Target Identification ] Posted v12, adjusting one of the smoke tests vs a distro linker bug (fixed in mainline). r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 11 Oct 2020
[VIRT-327 # Richard's upstream QEMU work ] Completed capstone update. Flushed tcg patch queue. Fixed a decodetree issue for pmm. [VIRT-339 # ARMv8.5-BTI, Branch Target Identification ] Refreshed BTI linux-user patch set. [VIRT-344 # ARMv8.5-MemTag, Memory Tagging Extension ] Fixed a couple of MTE bugs reported by Arm. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 28 Sep 2020
[VIRT-327 # Richard's upstream QEMU work ] Capstone patch set v4. Implement float128_muladd. Some patch review. Note, on holiday next week. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 20 Sep 2020
[VIRT-349 # QEMU SVE2 Support ] Posted v3, now tested vs armie. [VIRT-327 # Richard's upstream QEMU work ] Another round of capstone patches, still needs review. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 14 Sep 2020
[ Sorry it's a bit late. ] [VIRT-327 # Richard's upstream QEMU work ] Send out tcg patch queue. Prototype a disassembler using llvm. Not ideal. If we proceed with this further, we should probably schedule time for it, because the job is not small. Updating the capstone submodule; a couple of rounds converting that to meson. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 6 Sep 2020
[VIRT-349 # QEMU SVE2 Support ] Continuing the testing vs armie. [VIRT-327 # Richard's upstream QEMU work ] * More microblaze cleanup, including a check-acceptance regression fix from the first pull. Ho hum. * Patch review, queue is empty again. * Old patch queue cleanup, Fixed some gvec bugs affecting 32-bit x86; testing vs aa32 risu. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] 2 weeks ending 30 Aug 2020
[VIRT-349 # QEMU SVE2 Support ] Rebased on accepted patches, a few bits of cleanup per review. [VIRT-327 # Richard's upstream QEMU work ] Patch review: * mttcg for microblaze * aa32 vfp fp16 * aa32 neon fp16 * hexagon v3 * riscv vector v4 Posted microblaze conversion to translator + decodetree. Posted v2 of crypto/cipher cleanup. Posted pr for softfloat. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 16 Aug 2020
[VIRT-327 # Richard's upstream QEMU work ] Patch review, all over the place. Patches for pauth impdef algorithm. Patches for mte WnR bit. Patches for crypto/cipher cleanup. [VIRT-349 # QEMU SVE2 Support ] Split out 20 patches from the SVE2 patch set. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] two weeks ending 9 Aug 2020
[VIRT-327 # Richard's upstream QEMU work ] Patch review -- lots of riscv vector stuff. Fix for PAUTH error indication. Diagnosed an MTE KASAN problem -- my theory is a guest os thread error. Investigation into PAUTH slowdown. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 26 Jul 2020
[VIRT-327 # Richard's upstream QEMU work ] Misc patch review. - Largest bit is half of riscv 0.9 vector patch set. Fix arm E2 bug in ptw_translate. Fix arm E3 buts in direct kernel startup. Fix linux-user chroot failure. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 19 Jul 2020
[VIRT-327 # Richard's upstream QEMU work ] Misc patch review. [GCC] I looked into Adhemerval's libgomp-scalability patch set. The code looks good, and I can't see anything wrong. The cancel-parallel-2 test that's reported to regress, does, sometimes. It never fails for me on qemu-test (aarch64, tx1). It *only* fails under the dejagnu test harness on x86_64 and ppc64le. When run by hand it succeeds, always. I cannot explain that at all. I've run the testsuite with OMP_DEBUG_ENV=verbose and see that the dejagnu environment is as expected. Anyway, I can't make forward progress because I can't reproduce the problem under controlled conditions. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 12 Jul 2020
[VIRT-339 # ARMv8.5-BTI, Branch Target Identification ] [VIRT-344 # ARMv8.5-MemTag, Memory Tagging Extension ] Rebase and update linux-user for comments. [VIRT-327 # Richard's upstream QEMU work ] Patch review. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
Re: [ACTIVITY] week ending 5 Jul 2020
On 7/7/20 8:06 AM, Peter Maydell wrote: > On Tue, 7 Jul 2020 at 16:02, Richard Henderson > wrote: >> >> 4 day week. >> >> [VIRT-327 # Richard's upstream QEMU work ] >> >> Bug hunting vs aa32 ldrex/strex. I had hoped it would be relatively easy to >> reproduce -- just run something from the .NET testsuite -- but even getting >> that far wasn't obvious. So I put that aside; let's see if Peter's request >> for >> an actual reproducer gets results. > > er, I didn't request a reproducer; I merely suggested that you > could request a reproducer... Ah, right. Will do. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 5 Jul 2020
4 day week. [VIRT-327 # Richard's upstream QEMU work ] Bug hunting vs aa32 ldrex/strex. I had hoped it would be relatively easy to reproduce -- just run something from the .NET testsuite -- but even getting that far wasn't obvious. So I put that aside; let's see if Peter's request for an actual reproducer gets results. Bug hunting vs aa64 gcc sync-4.c as reported by clyon. I determined that it's not the fault of the null-pointer dereference, and that something goes wrong somewhere in libgcc's exception unwind prior to the c++ throw. But it doesn't fail all of the time. And worse, the problem vanishes when randomize_va_space is disabled. So I can neither get a "good" vs "bad" trace without needless differences nor produce a failure under gdb. I should try again with rr and see if that works... r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] three weeks ending 28 Jun 2020
[VIRT-344 # ARMv8.5-MemTag, Memory Tagging Extension ] Lots of work here, finally merging MTE system support. [VIRT-349 # QEMU SVE2 Support ] Posted v2, all 100 patches. [VIRT-327 # Richard's upstream QEMU work ] A fair amount of patch review. Merged the decodetree exclusive groups feature. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 7 Jun 2020
[VIRT-344 # ARMv8.5-MemTag, Memory Tagging Extension ] Posted v7 of system mode Posted v2 of user mode vs in-progress kernel abi. Some bug fixing for Stephen and Szabolcs. [VIRT-349 # QEMU SVE2 Support ] Started reviewing Stephen's sve2 risu patches. [VIRT-327 # Richard's upstream QEMU work ] A fair amount of patch review New version of decodetree exclusive groups. Some work on clang 10 werrors. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[INACTIVITY] week ending 31 May 2020
Holidays! I worked on nothing but my tan. ;-) r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 24 May 2020
[VIRT-339 # ARMv8.5-BTI, Branch Target Identification ] Updated to match the latest kernel for-next/bti-user branch; I hope this is going to be merged for 5.7. Posted v9 for review. [VIRT-349 # QEMU SVE2 Supprt ] More RISU work to improve support for SVE. Stephen Long has posted some sve2 risu patterns that need reviewing, and I plan to test all of that next week vs ArmIE. I had a start on rebasing my current sve2 patch set on master, with lots of prereqs merged. But stopped in the middle because I realized that I wanted to get all of the RISU work done first, so that I can test each patch as it is updated. r~ PS: Out all next week on holiday. ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 17 May 2020
[VIRT-344 # ARMv8.5-MemTag, Memory Tagging Extension ] Some prerequisites merged upstream. [VIRT-349 # QEMU SVE2 Support ] Some prerequisites merged upstream. Work on risu to compress sve output files. Split out the crypto conversion to gvec. [VIRT-327 # Richard's upstream QEMU work ] Posted some softfloat cleanups. Some patch review. Support non-overlapping regions for decodetree. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 10 May 2020
... and apologies for tomorrow's meeting. [VIRT-344 # ARMv8.5-MemTag, Memory Tagging Extension ] Updated the branch, both system and user. There's a report of an assertion failure in system mode, but no testcase to go with it. I need to ping for a devel branch with which to play. [VIRT-349 # QEMU SVE2 Support ] Some prerequisites merged upstream. [VIRT-327 # Richard's upstream QEMU work ] Review of risc-v risu patches. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 3 May 2020
[VIRT-349 # QEMU SVE2 Support ] More progress on insn implementation; just about done with all of the indexed multiply. Perhaps 10 insns remaining. Assad mentioned on irc that he has fixed the Armie bug that prevented RISU from running properly, so I hope to start doing some testing soon. [VIRT-327 # Richard's upstream QEMU work ] Reviewed Peter's decodetree conversion. Posted some extracts from my sve2 branch that may be relevant and helpful. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 26 Apr 2020
[VIRT-349 # QEMU SVE2 Support ] More progress on insn implementation. More patches from Stephen Long merged. More good review from Laurent Desnogues. Down to perhaps 30 insns remaining, and then figuring out some miscomparisons reported by Laurent, but not diagnosed. [VIRT-344 # ARMv8.5-MemTag ] Fixed an exception return bug vs PSTATE.TCO. [VIRT-327 # Richard's upstream QEMU work ] Posted some tcg patch sets for 5.1. Worked on the sparc regression Alex reported vs TEMP_CONST. I've set that aside for now; I need to come up with a new scheme to debug that one. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] 2 weeks ending 19 Apr 2020
Short weeks around Easter. [VIRT-349 # QEMU SVE2 Support ] Lots of progress on insn implementation. Several patches from Stephen Long merged. He's coming up to speed nicely. Some good review from Laurent Desnogues. Spent some time writing a version of strspn for Arm optimized-routines, as a way of testing the NMATCH instruction. Found bugs in the tcg optimizer instead. Still in the process of rebasing the branch upon those fixes, and upon patch review from Peter. [VIRT-327 # Richard's upstream QEMU work ] Couple of patches for 5.0. [GCC] Posted v4 of aarch64 cmpti patch set. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 5 Apr 2020
[VIRT-349 # QEMU SVE2 Support ] Met with Qualcomm on Friday to discuss sharing the development work, and help start bringing their new-hire, Stephen Long, up to speed on qemu. Gave Stephen generic qemu development pointers, and a simple set of SVE2 instruction on which to wet his feet. [VIRT-327 # Richard's upstream QEMU work ] Better constant propagation and allocation for TCG. Worked on probe_guest_base as a follow-up to some of the work Alex was doing wrt init_guest_space. Misc patch review for 5.0. [GCC] Posted v3 of aarch64 cmpti patch set. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 29 Mar 2020
[VIRT-349 # QEMU SVE2 Support ] Posted the first incremental patch set for review, as requested by Qualcomm. [VIRT-327 # Richard's upstream QEMU work ] Patch review, much of it 5.0 related, but also v6 of the riscv vector patch set. Revise the PIE and linkage patch set. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 22 Mar 2020
Progress: [VIRT-349 # QEMU SVE2 Support ] 10 of N insn groups implemented. Annoyingly, there doesn't seem to be a summary of new insns, so confirming that all of the insns have been implemented. [VIRT-327 # Richard's upstream QEMU work ] Patch review. Mostly Phil's arm --disable-tcg set. Cleanup for some of the new Coverity reports. Flush tcg patch queue. [GCC] Two revisions improving TImode comparisons for aarch64 (PR94174). https://gcc.gnu.org/pipermail/gcc-patches/2020-March/542447.html [Kernel] Follow-up on a discussion a few weeks ago re __range_ok. The gcc cmpti patch set is in support of that, but I also found a much better solution for constant sized checks. http://lists.infradead.org/pipermail/linux-arm-kernel/2020-March/719754.html r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] 2 weeks ending 15 May 2020
[VIRT-344 # ARMv8.5-MemTag, Memory Tagging Extension ] Reorg sve load/stores w/probe_access_flags. Posted v6, now including support for sve. [VIRT-327 # Richard's upstream QEMU work ] Posted v3 of tbi cleanups. Updated a forgotten patch vs sve fmla/fcmla. Oodles of patch review. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 1 Mar 2020
[VIRT-344 # ARMv8.5-MemTag, Memory Tagging Extension ] Lots of work, including an arch update. The system-mode patch set is much changed, but still not quite ready. [VIRT-349 # QEMU SVE2 Supprt ] [VIRT-327 # Richard's upstream QEMU work ] TBI fixes, 2 rounds. HCR fixes, 2 rounds. TCG patch queue flushed. Some patch review. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 23 Feb 2020
Four day week. [VIRT-344 # ARMv8.5-MemTag, Memory Tagging Extension ] Lots of work here. Noticed that our TBI handling is wrong for system mode, such that the FAR_ELx register gets the wrong contents. Noticed that SVE isn't handling TBI at all, much less being prepared for MTE. Noticed that even AdvSIMD would not quite produce the correct results for LD*/ST* (multiple structures). Rearranging the actual MTE check from the ground up. Found an odd case with DC_ZVA that threw a wrench into that planning. [VIRT-327 # Richard's upstream QEMU work ] Honor more HCR_EL2 trap bits. HPPA patch queue flushed. Patch review for ppc "hardfloat" patch. Patch review for memory_region_allocate_system_memory. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 16 Feb 2020
[VIRT-262 # ARMv8.1-PAN ] [VIRT-273 # ARMv8.2-ATS1E1 ] [VIRT-276 # ARMv8.2-UAO ] All three now merged. [VIRT-349 # QEMU SVE2 Support ] Refreshed an old patch set tidying up pmul. [VIRT-327 # Richard's upstream QEMU work ] Patch review: - ARMv8.1-PMU - riscv vector extension, partial - cpu_exec_step_atomic race Refresh x86_64 vsyscall implementation Refresh aa64_va_parameter optimization Refresh vfp feature and decodetree cleanup Refresh tcg/arm epilogue expansion Refresh arm vector improvements Pass sve fmla arguments by value. Fix some advsimd vs sve extension errors r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 9 Feb 2020
[ Linux on ARM mini-conference ] 2 days. Some interesting stuff in the future hardware directions talks. Helped out a bit with ABI history in the toolchain breakout session. Some good hallway discussion, especially re record-replay on aarch64. I should make time this weekend to produce a more complete trip report. [VIRT-263 # ARMv8.1-VHE Virtual Host Extensions ] Posted v7 -- merged! [VIRT-262 # ARMv8.1-PAN ] [VIRT-273 # ARMv8.2-ATS1E1 ] [VIRT-276 # ARMv8.2-UAO ] Posted v3. [VIRT-327 # Richard's upstream QEMU work ] Random patch review. Updated some aa32 vfp cleanup patches; still need to re-test and post. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 0202-2020
[VIRT-263 # ARMv8.1-VHE Virtual Host Extensions ]
Posted v5 & v6.
{
[VIRT-262 # ARMv8.1-PAN Privileged Access Never]
[VIRT-273 # ARMv8.2-ATS1E1 ]
[VIRT-276 # ARMv8.2-UAO ]
Posted v2.
}
[VIRT-327 # Richard's upstream QEMU work ]
Addressed a performance regression, of sorts,
for ppc32, caused by one of my cputlb reorgs.
r~
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[ACTIVITY] week ending 26 Jan 2020
[VIRT-327 # Richard's upstream QEMU work ] * tcg patch queue flush, including some VHE prereqs. * target/hppa patch queue flushing. * combined the two in-flight avr patch sets, hoping to move that project to completion. * patch review. * target/s390x local variable "leak" fix, to satisfy a static analyzer. [VIRT-263 # ARMv8.1-VHE Virtual Host Extensions ] * started rebasing, and addressing the collected comments from v4 in December. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 19 Jan 2020
[VIRT-327 # Richard's upstream QEMU work ] * Implement x86_64-linux-user vsyscall page, which should keep Peter's pre-merge testing working. * Another tcg queue pull without the bits that depend on the vsyscall implementation above. * Posted v2 of some fixes to -accel option processing. * Posted v2 of some fixes to target/arm syn data syndrome bits. * Wrote some test cases for a target/arm pauth sbox fix. * Investigated a fix for memory layout of -static-pie binaries. * Random patch review. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 12 Jan 2020
[VIRT-327 # Richard's upstream QEMU work ] * TCG patch queue flush, including phase 1 increase for number of mmu_idx, on which VHE is dependent. * Random patch review. * Capstone update. * cputlb cleanup in prep for modeling ASIDs. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 22 Dec 2019
* Patch set cleaning up PIE/non-PIE linking - Add new support for static pie. * Another revision removing MMU_MODE_SUFFIX. * Random patch review. * Planning for Linux on ARM summit in Cambridge in February. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 15 Dec 2019
[VIRT-327 # Richard's upstream QEMU work ] Following up on the feedback from last week on VHE and PAN, posted a patch set eliminating MMU_MODE*_SUFFIX, and the current limit of NB_MMU_IDX <= 12 that went with that. Some patch review. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] 2 weeks ending 1 Dec 2019
7 working days, then Thanksgiving. [VIRT-262 # ARMv8.1-PAN Privileged Access Never] Finished, still need to post. [VIRT-273 # ARMv8.2-ATS1E1, AT S1E1R and AT S1E1W instruction variants ] Finished, still need to post. [VIRT-276 # ARMv8.2-UAO, PSTATE override of Unprivileged Load/Store ] Finished, still need to post. [VIRT-263 # ARMv8.1-VHE Virtual Host Extensions ] FIXED! Welsh sprint with AJB; found and fixed two bugs. Final bug causing guest kernel crash while booting fixed upstream by Marc Zyngier vs ptrauth. Will do some more thorough testing during rc4 and post once the development phase opens up again. [VIRT-327 # Richard's upstream QEMU work ] Review of target/hexagon skeleton. Review of arm dcpop patch set for beata. Fixed a couple of arm translator bug for clyon. Some investigation into a reported hppa-linux-user bug. While I can reproduce locally, so far I have not tracked down anything that I can prove is a translation bug. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 17 Nov 2019
[VIRT-262 # ARMv8.1-PAN Privileged Access Never] Started, based on VHE patch set due to mmu_idx reorg therein. Needs some minor re-work to handle Secure EL1. [VIRT-273 # ARMv8.2-ATS1E1, AT S1E1R and AT S1E1W instruction variants ] Started. [VIRT-327 # Richard's upstream QEMU work ] Some soft-freeze bug fixing of stuff that I broke this cycle. Some patch review. [Kernel] Posted v7 of the ARMv8.5-RNG patch set. There's some significant mis-communication going on between me and Mark Rutland; I have no idea what he wants at this point... [GCC] Committed the base asm-flags patch set. Posted a follow-up to un-break thumb1, and add tests for it. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 10 Nov 2019
[VIRT-263 # ARMv8.1-VHE Virtual Host Extensions ] Reworked the timer redirection. Now the EL2 and EL0 redirection is unified, which is a bit easier to understand. Still no joy working out where the unwanted interrupt is coming from. As far as I can tell everything is plumbed correctly... I'll shelve this until PMM is not swamped with release work. It must wait for 5.0 for merging anyway. [VIRT-327 # Richard's upstream QEMU work ] Assorted patch review. [Kernel] Posted two more rounds of ARMv8.5-RNG for review. Seems I'd misunderstood one of Mark's previous suggestions, and Ard changed his mind about how RNDR vs RNDRRS should be used in the context of the shared resource across host*CORES + virt*VCPUS. [GCC] Posted an implementation of asm-flag-output for AArch32+AArch64. I should have done this years ago. There are two potential users within the kernel, and one is access_ok() which has thousands of uses. (Oh, and RNG, which has like 3 uses. :-P) Reviewed some arm simd patches that caught my eye. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
Re: VHE status
On 10/31/19 2:30 PM, Peter Maydell wrote:
> HCR_EL2.{VI,VF} aren't set by the CPU, they're set by software
> (ie the hypervisor running in QEMU). They're for the situation where
> the hypervisor wants to cause a VIRQ or VFIQ to occur directly
> (ie not because the hypervisor has programmed the GIC and the
> GIC is injecting a VIRQ/VFIQ). I have a feeling Linux doesn't use
> them and always uses the GIC.
This seems to be the case.
> What I had in mind for 'a' was the implementation of the bit of
> the spec that says "When executing at EL2 or Non-secure EL0, any
> physical interrupt that is configured to be taken at EL2 is
> subject to the Process state interrupt mask. If the mask bit is set,
> then the corresponding interrupt will not be taken. If the mask bit is
> not set, then the corresponding interrupt will be taken." (ie handling
> of PSTATE.[AIF] when HCR_EL2.{E2H, TGE} == {1, 1}.)
As far as I can see this is all correct.
In particular, the manipulations to HCR_{AMO,FMO,IMO} that are done by
arm_hcr_el2_eff based on HCR_{E2H,TGE} means that arm_excp_unmasked and
arm_phys_excp_target_el are correct as-is.
The case I'm trying to debug, guest EL1 timer, TGE == 0 && IMO == 1. Which,
according to D1-10 routes to EL2, and according to D1-13 is not masked by
PSTATE.
I really don't understand how this is supposed to work.
The only thing I can imagine is that the guest EL1 timer is not really supposed
to generate a real interrupt, but to silently generate a virq, but I don't see
anything in section D11 (Generic Timer in AArch64 State) that validates that
hypothesis.
r~
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VHE status
Tree:
https://github.com/rth7680/qemu.git tgt-arm-vhe-5
Testcase:
qemu-test:~rth/linux/initramfs-min.cpio.gz
The host kernel could be anything, but I've been using
the same Image.gz that is inside the cpio archive.
./aarch64-softmmu/qemu-system-aarch64 -m 4G \
-M virt,virtualization=on,gic-version=max -cpu max \
-kernel Image.gz -initrd initramfs-min.cpio.gz
At the shell prompt, ./test will run a guest kernel with kvm.
As momentarily discussed with PMM in the hallway:
As soon as the guest kernel enables interrupts,
arch_timer_starting_cpu
enable_percpu_irq
irq_percpu_enable
gic_unmask_irq
-- Incorrect exception delivery.
the GTIMER_PHYS interrupt is delivered to EL2 (seems to be ok), the host kernel
does something (haven't dug into what exactly, bug presumably setting bits that
are supposed to pass the virq to the guest), and immediately another interrupt
is delivered to EL2. Repeat.
Whether this is incorrect routing of the virq interrupt, or incorrect
masking/acking of the hard irq interrupt at EL2, I do not yet know.
PMM: I don't know the answer to either (a) or (b) as asked on hangouts. I
think (b) is correct, but I can't be sure. I'm trying to understand how (a) is
supposed to work now. In particular, I can't find any code that sets
HCR_EL2.{VI,VF}, only tests them.
r~
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[ACTIVITY] week ending 20 Oct 2019
Progress: [VIRT-344 # ARMv8.5-MemTag, Memory Tagging Extension ] Updates for user-only. Merge bug fixes from eugeni.stepa...@gmail.com. [VIRT-349 # QEMU SVE2 Supprt ] Convert neon pmul helpers to a form that will be usable for sve2. [VIRT-327 # Richard's upstream QEMU work ] Pull for tcg-next. Review plugins v5. Update for capstone submodule. Started reviewing multi-phase reset v5. [Kernel] Hacked up a patch for ARMv8.5-RNG. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 13 Oct 2019
[VIRT-263 # ARMv8.1-VHE Virtual Host Extensions ] Still need to think of more test cases... [VIRT-344 # ARMv8.5-MemTag, Memory Tagging Extension ] Posted v5 of the system-only patch set, with testing help from Alex. [VIRT-327 # Richard's upstream QEMU work ] Catching up on patch review - arm semihosting - tcg profiler - ptimer transactions - s390 mvcl interrupt - started on v2 of dave martin's bti kernel patch set. Posted v6 of my arm hflags patch set. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 6 Oct 2019
[VIRT-263 # ARMv8.1-VHE Virtual Host Extensions ] Lots of work with Alex trying to produce a reduced test case. We are now unit testing entry and exit from EL0 (EL2&0), EL1 and EL0-in-EL1 (EL1&0). Next would be to test the various memory access faults. [VIRT-327 # Richard's upstream QEMU work ] Patch review for SVE in KVM, S390 interrupt handling during MVCL. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 22 Sep 2019
[VIRT-327 # Richard's upstream QEMU work ] Convert notdirty and rom handling to cputlb; lots of cleanup around that area. Version 3 is the first version that worked; two previous RFCs took quite a bit of effort to work out why they didn't work. [GCC] Committed the lse out-of-line patch set. Posted patches for two follow-on bugs affecting aarch64-elf. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 15 Sep 2019
[VIRT-327 # Richard's upstream QEMU work ] Posted v2 of fixing tlb bswap. Fixed a regression in arm SMLAL* Reviewed v2 of risc-v vector extension (ugh). Created pull for Sven's target/hppa fixes. [GNU Cauldron] * Project Ranger: New extensible representation for value ranges. * Lightning talks, a new gdbserver. - too short to have enough details to be useful. - incomplete enough that no demo possible. - maybe look back at this when it's more developed. * Register allocation BOF * ARM BOF - MTE is alive! In that there are now RFC patches for glibc and gcc. It's probably time to revive my MTE patch set, at least for system mode. I spent quite a long time talking with Richard Earnshaw about the current state of affairs. I'm hoping that we can get the kernel folk to agree on some fundamentals of the userland ABI, even perhaps before the final support is in the kernel, so that we can implement the linux-user side, which would probably be most helpful for glibc+gcc work. * GCC Steering Committee * Rethinking GCC development process + continuous testing * Truly interprocedural IPA-SRA * Lightning talks, - EmBench - Combined elimination for -Os. * RISC-V BOF r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
Out Monday
Hi guys. Due to unfortunate baggage handling, I don't have my laptop and won't be able to log in Monday. I should be back online Tuesday, all going well. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 1 Sep 2019
[VIRT-327 # Richard's upstream QEMU work ] Fix two ppc fp launchpad bugs. Resurect patches for openrisc v1.3 Once-over review of risc-v vector extension. Posted v3 of a32 coversion to decodetree. Started poking at neon conversion to decodetree, as a prerequisite to a32 support for fp16. Some cleanups to watchpoints. Generic stuff now queued to tcg-next. DavidH is taking care of target/s390x updates, but there are some changes wanted within target/arm SVE code. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 25 Aug 2019
[VIRT-263 # ARMv8.1-VHE Virtual Host Extensions ] Reorg ARMMMUIdx again; this time, do not overlap EL1&0 and EL2&0 mmu_idx. This makes debugging a bit easier. Fix one more bug in EL2&0 selection. This was not the last, because a nested kernel does not yet boot. [VIRT-327 # Richard's upstream QEMU work ] Another round of aa32 decodetree patches. Another round of arm hflags patches. Review of and some patches for cpu watchpoints. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 11 Aug 2019
[VIRT-327 # Richard's upstream QEMU work ] Posted v4 of arm hflags reorg. Split out 3 minor patch sets from the larger aa32 decodetree set. Reviewed v6 of invert-endian tlb patch set. Reviewed ajb's fpu header reorg. Posted an RFC vs Andrew Jones' SVE-in-KVM patch set. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 4 Aug 2019
[VIRT-263 # ARMv8.1-VHE Virtual Host Extensions ] Posted a couple of revisions. Good feedback between this and MemTag, both of which need to adjust the set of TLBs. [VIRT-339 # ARMv8.5-BTI, Branch Target Identification ] Posted v7. [VIRT-344 # ARMv8.5-MemTag, Memory Tagging Extension ] Rebased upon current VHE+BTI work. Updated from beta manuals to the ARM ARM issue E.a manual. [VIRT-327 # Richard's upstream QEMU work ] Reviewed v1 x86 gen_sse rewrite. Reviewed Alex's v4 plugin patchset. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 28 July 2019
[VIRT-263 # ARMv8.1-VHE Virtual Host Extensions ] Merged some fixes from Alex. Starting to test kvm-inside-tcg. [VIRT-327 # Richard's upstream QEMU work ] Posted v1 of aa32 base isa conversion to decodetree. Reviewed v5 of the sparc64 invert endian tlb bit patches. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 21 July 2019
[VIRT-263 # ARMv8.1-VHE Virtual Host Extensions ] Posted v1. [VIRT-327 # Richard's upstream QEMU work ] Finished GSoC risugen review. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 14 July 2019
[VIRT-263 # ARMv8.1-VHE Virtual Host Extensions ] Got to "kvm enabled with vhe" kernel message, but then the kernel hangs there. Irritatingly works with the kernel I built myself, but not a distro supplied kernel. Need to track down the config difference so I can continue using gdbstub. [VIRT-344 # ARMv8.5-MemTag, Memory Tagging Extension ] Regenerated an mte+linux-user branch for Google engineers to use to develop llvm. This is code previously posted, but my current branch striped out linux-user for ease of review of the system code. [VIRT-327 # Richard's upstream QEMU work ] Fixed mmap assert, signal handler method. Fixed constant folding of extract2. Fixed aarch64 host output of extract2. Posted pull request for those. Started reviewing the GSoC risugen patches, v3 for avx. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 7 July 2019
Short week; 3 days. [VIRT-263 # ARMv8.1-VHE Virtual Host Extensions ] Fixed 3 bugs: * SVE length calculation, * PNX bit while in EL2&0 regime, * Interrupt routing w/ TGE bit. A bare 5.2 kernel boots to root file system not found. A 4.19 kernel hangs during boot somewhere. Now doing a fedora30 install, which I believe has a 5.x kernel... [VIRT-327 # Richard's upstream QEMU work ] Patch review: * GSoC x86 risugen, * arm semihost cleanups. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 30 June 2019
[VIRT-263 # ARMv8.1-VHE Virtual Host Extensions ] Rebased on master. Now trying to remember the incantation that produced a minimum number of insns before the kernel actually tries to use this. At present things seem to be crashing before I even get that far, as if I've misconfigured something. [VIRT-327 # Richard's upstream QEMU work ] Fixed a couple of bugs in my tcg/ppc host vector patch set. Reviewed qemu kvm sve patches. Reviewed target/ppc altivec optimization patches. Reviewed GSoC risugen x86 patches. Other misc upstream review. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 16 June, plus 2 days
Week ending 23 June is very short. * Patch review - target/ppc vsr cleanup - target/tricore translator loop conversion - target/arm vfp decodetree cleanup - cortex-strings strrchr fix - continuing on the plugin api * Xilinx meeting * Fix qemu assert for clyon - Found two other bugs in the process. * Debugging my own USHR/SSHR patch vs aa32. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 9 Jun 2019
[VIRT-339 # ARMv8.5-BTI, Branch Target Identification ] Posted v6. Some review from Dave Martin; will need at least one further revision, and to wait til the kernel patches land. [VIRT-327 # Richard's upstream QEMU work ] Fix a reported bug in pauth Auth results. Fix a reported bug in vector variable shift. Review Peter's vfp decodetree patch set. Review of v18 of target/rx. Never-ending, it seems... Review of some target/ppc vector patches. Posted v4 of CPUNegativeOffsetState. This looks ready to pull. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 2 Jun 2019
Four day week. [VIRT-327 # Richard's upstream QEMU work ] Reviewed s390 fp vector patch set. Posted v16 rx. This seemed so close to being ready last week, but now I don't know. I think I should quit pushing it myself and let Yoshinori do more of the lifting here. Reviewed avr v20 patch set. Reviewed Alex's testing patch set. Submitted patches to constify upstream capstone (500k from .data to .rodata). r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 26 May 2019
[VIRT-343 # ARMv8.5-RNG, Random Number Generator ] Merged! [VIRT-263 # ARMv8.1-VHE Virtual Host Extensions ] Started dusting off and rebasing wip. [VIRT-339 # ARMv8.5-BTI, Branch Target Identification ] Started reviewing the kernel patch set for this feature. [VIRT-327 # Richard's upstream QEMU work ] PR for tcg gvec work. PR for Sato-san's RX target. Patch set to update capstone and enable s390x. GSOC: Review v3 of Jan's enable risu for x86 patch set. [Other] Travel arrangements for Xilinx meeting in San Jose, June 13. Will need to pick Peter's brain re m-profile before then. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 19 May 2019
[VIRT-343 # ARMv8.5-RNG, Random Number Generator ] Posted v7 and v8. I think this is now ready for merge, but I said that last week as well. :-P [VIRT-327 # Richard's upstream QEMU work ] More gvec work, some of which applies to target/arm, and some to tcg/aarch64/, but all of which is in support of David's target/s390x work. Should be coming to a close on that soon. Posted v7 of my do_syscall split. Reviewed v13 of the RX target, adjusted it slightly for my tlb_fill changes. I think this now ready to merge. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 12 May 2019
[VIRT-343 # ARMv8.5-RNG, Random Number Generator ] Posted v4, v5, v6. I think this is now ready for merge. [VIRT-327 # Richard's upstream QEMU work ] Posted v3 of the CPUNegativeOffset patch set. Posted v2, v3, and a pull request for the tlb_fill patch set. Debugged one more fix for Sparc testthreads. Reposted some long dormant linux-user fixes. Started reviving the do_syscall split patch set, since Laurent asked after it. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 5 May 2019
[VIRT-327 # Richard's upstream QEMU work ] Review Mark's target/ppc getVSR patch set. Two rounds of "tcg vector improvments"; hopefully that's ready to go in on Monday. More work on "bit select" and "compare select" primitives. I can now vectorize Neon VSHL/VSHR variable shift (where positive values are left shift and negative values are right shift). Waiting on posting this while previous tcg vector patch set is still in flight. Review Alex's demacrofy v5. Wrote a boot.S for Alpha. Review David's latest target/s390 vector patch set. Review Sato-san's target/rx v8. Played around with a few disassembler improvements, but I'll not confuse the review process by posting them now. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 28 Apr 2019
[VIRT-327 # Richard's upstream QEMU work ] Another round on launchpad 1824853, TB overflow. This time handling relocation overflow. Which would not be seen on an x86 host (2GB displacement), but would affect some of the risc hosts. Reviewed Peter's v7m fpu patches. Another round on util/path.c, fixing the startup loop that we get into for using a full chroot for -L. Poked my nose into Alex's cputlb demacrofy patch set. Hopefully the feedback was helpful... First two pull requests for 4.1. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 21 Apr 2019
[VIRT-327 # Richard's upstream QEMU work ] Fix TranslationBlock overflow, launchpad 1824853. Investigated launchpad 1824768, i386 emulation on arm32. But works-for-me. A bunch of work on new gvec primitives. Primarily to support David Hildebrand's target/s390 conversion, but it does enable more vectorization in target/arm as well. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 31 Mar 2019
[VIRT-263 # ARMv8.1-VHE Virtual Host Extensions ] More progress, but still crashing early. Crashes on first memory access after swapping ttbr1. Debugging kernel on guest and qemu on host simultaneously. So far, all the numbers look right but still boom. [VIRT-339 # ARMv8.5-BTI, Branch Target Identification ] Posted a v4 using the PT_NOTE, but still RFC-ish due to missing abi for new mmap flag. [VIRT-327 # Richard's upstream QEMU work ] Posted v1+v2 of CPUNegativeOffsetState. Posted v1 of a cleanup of target/riscv wrt decodetree. [Other] Upgraded the laptop from fedora 27 (out of support now), to ubuntu 18.04 lts. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
Re: Cross compiling QEMU for aarch64
On 3/28/19 11:40 AM, Rohit Khanna wrote: > > > rokhanna@rokhanna-dev ~/dev/qemu.git $ ./configure > --target-list=aarch64-softmmu --enable-kvm --enable-vhost-net > --cross-prefix=aarch64-linux-gnu- > > ERROR: glib-2.40 gthread-2.0 is required to compile QEMU > > > I have installed libglib2.0-0 using apt-get but I cant find libglib2.4. Any > ideas how I can install that. Thanks in advance. I'm fairly certain that you have installed libglib for the host, x86_64, but not the cross-compiled libraries for aarch64. This is what I meant when I said: > Third, you're going to need a *lot* of aarch64 libraries in order to build > QEMU. This is where OS support for cross-toolchains is key. Try the following as root: dpkg --add-architecture arm64 apt-get update apt-get install build-essential apt-get install libcairo2-dev:arm64 See https://wiki.debian.org/Multiarch/HOWTO for more details. r~ ___ linaro-toolchain mailing list linaro-toolchain@lists.linaro.org https://lists.linaro.org/mailman/listinfo/linaro-toolchain
[ACTIVITY] week ending 24 Mar 2019
[VIRT-263 # ARMv8.1-VHE Virtual Host Extensions ]
Picked up my partial patch set and started on it again.
It is improved by having done the pauth/bti/mte work.
But still a work in progress.
[VIRT-327 # Richard's upstream QEMU work ]
Version 3 of tcg/ppc vector instructions.
Reviewed target/rx v4.
Fixed thread=single expansion of casp after Alex did all the
hard work tracking down the kernel failure, and writing me a
test case.
Looking into the size of the softmmu tlb expansion. Current
thinking is to move tlb out of CPUArchState into a new struct
that precedes env, so that the tlb is at small negative offsets
from env, so that {mask, table} is loadable with LDP/LDRD.
r~
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