Re: CPU Arch Security [was: Re: Probably the first published shel l code]
On Mon, 11 Nov 2002, Post, Mark K wrote: > Linas, > > No. Either your storage key matches, or it doesn't. If it matches, you get > read and write access, if it doesn't match, you get neither. (You _do_ get > a S0C4 abend.) > A better source;-) http://doclib.ucs.indiana.edu/cgi-bin/bookmgr/bookmgr.exe/BOOKS/DZ9AR007/3.3 A storage key is associated with each 4K-byte block of storage that is available in the configuration. The storage key has the following format: _ _ _ |ACC |F|R|C| ||_|_|_| 0 46 The bit positions in the storage key are allocated as follows: Access-Control Bits (ACC): If a reference is subject to key-controlled protection, the four access-control bits, bits 0-3, are matched with the four-bit access key when information is stored, or when information is fetched from a location that is protected against fetching. Fetch-Protection Bit (F): If a reference is subject to key-controlled protection, the fetch-protection bit, bit 4, controls whether key-controlled protection applies to fetch-type references: a zero indicates that only store-type references are monitored and that fetching with any access key is permitted; a one indicates that key-controlled protection applies to both fetching and storing. No distinction is made between the fetching of instructions and of operands. Reference Bit (R): The reference bit, bit 5, normally is set to one each time a location in the corresponding storage block is referred to either for storing or for fetching of information. Change Bit (C): The change bit, bit 6, is set to one each time information is stored at a location in the corresponding storage block. Storage keys are not part of addressable storage. The entire storage key is set by SET STORAGE KEY EXTENDED and inspected by INSERT STORAGE KEY EXTENDED. Additionally, the instruction RESET REFERENCE BIT EXTENDED provides a means of inspecting the reference and change bits and of setting the reference bit to zero. Bits 0-4 of the storage key are inspected by the INSERT VIRTUAL STORAGE KEY instruction. The contents of the storage key are unpredictable during and after the execution of the usability test of the TEST BLOCK instruction. > Mark Post > > -Original Message- > From: Linas Vepstas [mailto:linas@;linas.org] > Sent: Monday, November 11, 2002 12:57 PM > To: [EMAIL PROTECTED] > Subject: Re: CPU Arch Security [was: Re: Probably the first published > shell code] > > > -snip- > It has been years since I last looked at the 390 instruction set. Can't one > set a read-only mode for selected PSW keys? > -- Cheers John. Please, no off-list mail. You will fall foul of my spam treatment. Join the "Linux Support by Small Businesses" list at http://mail.computerdatasafe.com.au/mailman/listinfo/lssb
Re: CPU Arch Security [was: Re: Probably the first published shel l code]
On Mon, 11 Nov 2002, Post, Mark K wrote: > Linas, > > No. Either your storage key matches, or it doesn't. If it matches, you get > read and write access, if it doesn't match, you get neither. (You _do_ get > a S0C4 abend.) > I am looking at http://www.share.org/proceedings/SH98/data/S2826.PDF The stroage key is 7 bits. 0-3 Protect key, 0-15 4 F Fetch 5 R 6 C A program may fetch if its PDW key matches, or the F bit is zero. I'm having difficulty reading it; it's a slide presentation, landscape format and Mozilla's running xpdf inside the browser window. I turned the image round, but it's cropped. Actually, gets cropped both ways;-( My recollection, from over 20 years ago, that the page can be ro and it can be changed, but I don't see how that fits R. > Mark Post > > -Original Message- > From: Linas Vepstas [mailto:linas@;linas.org] > Sent: Monday, November 11, 2002 12:57 PM > To: [EMAIL PROTECTED] > Subject: Re: CPU Arch Security [was: Re: Probably the first published > shell code] > > > -snip- > It has been years since I last looked at the 390 instruction set. Can't one > set a read-only mode for selected PSW keys? > -- Cheers John. Please, no off-list mail. You will fall foul of my spam treatment. Join the "Linux Support by Small Businesses" list at http://mail.computerdatasafe.com.au/mailman/listinfo/lssb
Re: CPU Arch Security [was: Re: Probably the first published shel l code]
The keys don't have to match if the fetch pretection bit is 0. See from z/900 PofO: 3.3 Storage Key A storage key is associated with each 4K-byte block of storage that is available in the configuration. The storage key has the following format: ACC FRC 0 46 Fetch-Protection Bit (F): If a reference is subject to key-controlled protection, the fetch-protection bit, bit 4, controls whether key-controlled protection applies to fetch-type references:a zero indicates that only store-type references are monitored and that fetching with any access key is permitted; a one indicates that key-controlled protection applies to both fetching and storing. No distinction is made between the fetching of instructions and of operands. To: [EMAIL PROTECTED] "Post, Mark K" cc: (bcc: Michael Short/Towers Perrin) <[EMAIL PROTECTED]Subject: Re: CPU Arch Security [was: Re: Probably the first published shel l m>code] Sent by: Linux on 390 Port <[EMAIL PROTECTED] IST.EDU> 11/11/2002 02:27 PM Please respond to Linux on 390 Port Linas, No. Either your storage key matches, or it doesn't. If it matches, you get read and write access, if it doesn't match, you get neither. (You _do_ get a S0C4 abend.) Mark Post -Original Message- From: Linas Vepstas [mailto:linas@;linas.org] Sent: Monday, November 11, 2002 12:57 PM To: [EMAIL PROTECTED] Subject: Re: CPU Arch Security [was: Re: Probably the first published shell code] -snip- It has been years since I last looked at the 390 instruction set. Can't one set a read-only mode for selected PSW keys?
Re: CPU Arch Security [was: Re: Probably the first published shel l code]
> -Original Message- > From: Post, Mark K [mailto:mark.post@;eds.com] > Sent: Monday, November 11, 2002 1:28 PM > To: [EMAIL PROTECTED] > Subject: Re: CPU Arch Security [was: Re: Probably the first > published shel l code] > > > Linas, > > No. Either your storage key matches, or it doesn't. If it > matches, you get > read and write access, if it doesn't match, you get neither. > (You _do_ get > a S0C4 abend.) > > Mark Post > Not entirely true, but it can be a bit complicated. If the PSW key is zero, then it can fetch from any page and store into any page except: addresses 0-511 if "low address protection" is turned on. (and bytes 4096-4607 in zArchitecture mode as well) The page table entry for the address is marked as "read only". If the PSW key is not zero and matches the key of the piece of storage, it can store into the page unless the page table entry is marked as "read only". It can always fetch the contents of the page. If the PSW key is not zero and does not match the key in storage, it cannot store into the page under any conditions. (Well, this is a lie, but even more complicated due to "subspace groups" which are not used in Linux/390). It can fetch from the page if the "fetch protect" bit is *not* on. If the "fetch protect" bit is on, then it will get an interrupt code 4. -- John McKown Senior Technical Specialist UICI Insurance Center Applications & Solutions Team +1.817.255.3225
Re: CPU Arch Security [was: Re: Probably the first published shel l code]
Linas, No. Either your storage key matches, or it doesn't. If it matches, you get read and write access, if it doesn't match, you get neither. (You _do_ get a S0C4 abend.) Mark Post -Original Message- From: Linas Vepstas [mailto:linas@;linas.org] Sent: Monday, November 11, 2002 12:57 PM To: [EMAIL PROTECTED] Subject: Re: CPU Arch Security [was: Re: Probably the first published shell code] -snip- It has been years since I last looked at the 390 instruction set. Can't one set a read-only mode for selected PSW keys?
Re: CPU Arch Security [was: Re: Probably the first published shel l code]
Folks, This is known territory, both in implementation and literature. Both Multics and MTS implemented a similar architecture to what Linus V. is describing, and Apollo did an implementation with distributed memory in NCS. I'd suggest doing some reading before you go off to design a CPU -- we've solved this problem several times before. -- db David Boyes Sine Nomine Associates
