The latest (-04) level of the Principles of Operations manual is now
out.
See: http://publibz.boulder.ibm.com/epubs/pdf/a2278324.pdf
Some of the gems:
- Fullword immediate instructions:
The extended-immediate facility may be available on
models implementing z/Architecture. The facility provides
32-bit immediate-operand versions of the following
instructions:
ADD IMMEDIATE
ADD LOGICAL IMMEDIATE
AND IMMEDIATE
COMPARE IMMEDIATE
COMPARE LOGICAL IMMEDIATE
EXCLUSIVE OR IMMEDIATE
INSERT IMMEDIATE
LOAD IMMEDIATE
LOAD LOGICAL IMMEDIATE
OR IMMEDIATE
SUBTRACT LOGICAL IMMEDIATE
Other new instructions added as a part of the
extended-immediate facility include the following:
FIND LEFTMOST ONE
LOAD AND TEST (32-bit and 64-bit RXY format)
LOAD BYTE (RRE format)
LOAD HALFWORD (RRE format)
LOAD LOGICAL CHARACTER (64-bit RRE format,
and 32-bit RXY and RRE formats)
LOAD LOGICAL HALFWORD (64-bit RRE format,
and 32-bit RXY and RRE formats)
- Server-time-protocol facility:
The server-time-protocol facility may be available on a model
implementing z/Architecture. The facility provides the means
by which the time-of-day (TOD) clocks in various systems can
be synchronized using message links. STP operates in conjunct-
ion with the TOD-clock-steering facility, providing a new tim-
ing mode, new timing states, a new STP-timing-alert
external interruption, nd a new STP-sync-check machine-check
conditions.
- TOD clock steering facility
The TOD-clock-steering facility may be available on a
model implementing z/Architecture. The facility provides
a means by which apparent stepping rate of the
time-of-day clock may be altered without changing
the physical hardware oscillator which steps the
physical clock. The facility adds the semiprivileged
PERFORM TIMING FACILITY FUNCTION (PTFF)
instruction which provides the means by which the
program can query various timing-related parameters,
and, optionally, the means by which an authorized
timing-control program can influence certain of
these parameters.
- DAT Enhancement Facility 2
The DAT-enhancement facility 2 may be available on
a model implementing z/Architecture. When the DAT
enhancement facility 2 is installed, the LOAD PAGETABLE-
ENTRY ADDRESS instruction is available.
Given a virtual address, the LOAD PAGE-TABLEENTRY
ADDRESS instruction returns the 64-bit real
address of the corresponding page-table entry. The
address-space-control mode used by the dynamic address-
translation process is specified in the M4
field of the instruction.
- Extended translate facility improvements (e.g. TROO now no longer have
to check a comparison character)
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