Re: [RFC v1 PATCH 6/6] drivers: rtc: Add support for Qualcomm PMIC8058 RTC
Hi Alessandro, On 11/10/2010 6:18 PM, Trilok Soni wrote: From: Anirudh Ghayal agha...@codeaurora.org PMIC8058 is Qualcomm's power management IC. A 32-bit RTC is housed inside this PMIC. The RTC driver uses SSBI to communicate with the RTC module. Cc: Alessandro Zummo a.zu...@towertech.it Signed-off-by: Anirudh Ghayal agha...@codeaurora.org Please review this driver. Thanks. ---Trilok Soni -- Sent by a consultant of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum. -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 1/2] msm: gpio: Add v2 gpio support to MSM SoCs.
Beginning with the MSM8x60, the hardware block responsible for gpio
support changes. Provide gpiolib support for the new v2 architecture.
Signed-off-by: Gregory Bean gb...@codeaurora.org
---
arch/arm/mach-msm/Makefile |4 +-
arch/arm/mach-msm/gpio-v2.c | 180 +++
2 files changed, 183 insertions(+), 1 deletions(-)
create mode 100644 arch/arm/mach-msm/gpio-v2.c
diff --git a/arch/arm/mach-msm/Makefile b/arch/arm/mach-msm/Makefile
index b5a7b07..4a1a7ea 100644
--- a/arch/arm/mach-msm/Makefile
+++ b/arch/arm/mach-msm/Makefile
@@ -28,6 +28,8 @@ obj-$(CONFIG_ARCH_MSM8X60) += board-msm8x60.o
obj-$(CONFIG_ARCH_MSM7X30) += gpiomux-7x30.o gpiomux-v1.o gpiomux.o
obj-$(CONFIG_ARCH_QSD8X50) += gpiomux-8x50.o gpiomux-v1.o gpiomux.o
obj-$(CONFIG_ARCH_MSM8X60) += gpiomux-8x60.o gpiomux-v2.o gpiomux.o
-ifndef CONFIG_MSM_V2_TLMM
+ifdef CONFIG_MSM_V2_TLMM
+obj-y += gpio-v2.o
+else
obj-y += gpio.o
endif
diff --git a/arch/arm/mach-msm/gpio-v2.c b/arch/arm/mach-msm/gpio-v2.c
new file mode 100644
index 000..5d31a7c
--- /dev/null
+++ b/arch/arm/mach-msm/gpio-v2.c
@@ -0,0 +1,180 @@
+/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA.
+ *
+ */
+#include linux/gpio.h
+#include linux/io.h
+#include linux/irq.h
+#include linux/module.h
+#include linux/platform_device.h
+#include linux/spinlock.h
+#include mach/msm_iomap.h
+#include gpiomux.h
+
+/* Bits of interest in the GPIO_IN_OUT register.
+ */
+enum {
+ GPIO_IN_BIT = 0,
+ GPIO_OUT_BIT = 1
+};
+
+/* Bits of interest in the GPIO_CFG register.
+ */
+enum {
+ GPIO_OE_BIT = 9,
+};
+
+#define GPIO_CONFIG(gpio) (MSM_TLMM_BASE + 0x1000 + (0x10 * (gpio)))
+#define GPIO_IN_OUT(gpio) (MSM_TLMM_BASE + 0x1004 + (0x10 * (gpio)))
+
+struct msm_gpio_dev {
+ struct gpio_chip gpio_chip;
+};
+
+static DEFINE_SPINLOCK(tlmm_lock);
+
+static inline struct msm_gpio_dev *to_msm_gpio_dev(struct gpio_chip *chip)
+{
+ return container_of(chip, struct msm_gpio_dev, gpio_chip);
+}
+
+static inline void set_gpio_bits(unsigned n, void __iomem *reg)
+{
+ writel(readl(reg) | n, reg);
+}
+
+static inline void clr_gpio_bits(unsigned n, void __iomem *reg)
+{
+ writel(readl(reg) ~n, reg);
+}
+
+static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
+{
+ return readl(GPIO_IN_OUT(offset)) BIT(GPIO_IN_BIT);
+}
+
+static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int val)
+{
+ writel(val ? BIT(GPIO_OUT_BIT) : 0, GPIO_IN_OUT(offset));
+}
+
+static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
+{
+ unsigned long irq_flags;
+
+ spin_lock_irqsave(tlmm_lock, irq_flags);
+ clr_gpio_bits(BIT(GPIO_OE_BIT), GPIO_CONFIG(offset));
+ spin_unlock_irqrestore(tlmm_lock, irq_flags);
+ return 0;
+}
+
+static int msm_gpio_direction_output(struct gpio_chip *chip,
+ unsigned offset,
+ int val)
+{
+ unsigned long irq_flags;
+
+ spin_lock_irqsave(tlmm_lock, irq_flags);
+ msm_gpio_set(chip, offset, val);
+ set_gpio_bits(BIT(GPIO_OE_BIT), GPIO_CONFIG(offset));
+ spin_unlock_irqrestore(tlmm_lock, irq_flags);
+ return 0;
+}
+
+static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
+{
+ return msm_gpiomux_get(chip-base + offset);
+}
+
+static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
+{
+ msm_gpiomux_put(chip-base + offset);
+}
+
+static struct msm_gpio_dev msm_gpio = {
+ .gpio_chip = {
+ .base = 0,
+ .ngpio= NR_GPIO_IRQS,
+ .direction_input = msm_gpio_direction_input,
+ .direction_output = msm_gpio_direction_output,
+ .get = msm_gpio_get,
+ .set = msm_gpio_set,
+ .request = msm_gpio_request,
+ .free = msm_gpio_free,
+ },
+};
+
+static int __devinit msm_gpio_probe(struct platform_device *dev)
+{
+ int ret;
+
+ spin_lock_init(tlmm_lock);
+ msm_gpio.gpio_chip.label = dev-name;
+ ret = gpiochip_add(msm_gpio.gpio_chip);
+
+ return ret;
+}
+
+static int __devexit msm_gpio_remove(struct
Re: [RFC v1 PATCH 4/6] input: pmic8058_pwrkey: Add support for power key
On Fri, Nov 12, 2010 at 02:26:28PM +0530, Trilok Soni wrote: Hi Dmitry, On 11/12/2010 6:27 AM, Dmitry Torokhov wrote: On Thu, Nov 11, 2010 at 05:30:21PM +0530, Trilok Soni wrote: Hi Dmitry, On 11/11/2010 12:51 PM, Dmitry Torokhov wrote: Hi Trilkok, On Wed, Nov 10, 2010 at 06:17:59PM +0530, Trilok Soni wrote: Add support for PMIC8058 power key driven over dedicated KYPD_PWR_N pin. It allows the user to specify the amount of time by which the power key reporting can be delayed. Why do we need to delay KEY_POWER reporting? Do we need to use high resolution timers or regular timers would do as well? KEY_END appears to be abused (you don't want to move your cursor to the end of line, do you?). Also I wonder if header file should reside in linux/mfd with the rest of pmic8058 components. Most of the time Mobile devices come with single physical key for POWER, which if pressed for less than 500ms (configurable) then it will only report KEY_END (which say locks the screen on mobile) and if it pressed more than 500ms then it will also report KEY_POWER event too, which will say display menu on your mobile for asking you to suspend/switch off/etc, operations. I see,. If you would have used KEY_SCREENLOCK iinstead of KEY_END I would likely not ask this question ;) KEY_SCRENNLOCK looks good, let me analyze the impact on userspace framework which I have. I will come back on this in a day. For the timers I can move from hrtimers to regular timers. For the header file, I can move them to include/linux/mfd too. No problem on that. I am not even sure we need to keep them in separate header files, but it is up to you. Do you suggest that all the MFD sub-devices's platform data structures should come from single header file? It is an option, depends on how many external headers are needed, etc. When I looked at this particular file I got the feeling that it could be folded together with the rest. I expect that the board code that will specify platform resources will include every one of this sub-files anyway. But maybe if I was presented with the combined header I'd say wow, thats too big... Like I said, it is up to you. -- Dmitry -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 08/14] msm: iommu: Don't flush page tables if no devices attached
Don't flush the page tables on an IOMMU domain if there are
no IOMMU devices attached to the domain. The act of
attaching to the domain will cause an implicit flush of
those areas if the page tables are configured to not be L2
cacheable.
Signed-off-by: Stepan Moskovchenko step...@codeaurora.org
---
arch/arm/mach-msm/iommu.c | 15 +--
1 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-msm/iommu.c b/arch/arm/mach-msm/iommu.c
index 134add7..74f2157 100644
--- a/arch/arm/mach-msm/iommu.c
+++ b/arch/arm/mach-msm/iommu.c
@@ -50,13 +50,16 @@ static void __flush_iotlb(struct iommu_domain *domain)
unsigned long *fl_table = priv-pgtable;
int i;
- dmac_flush_range(fl_table, fl_table + SZ_16K);
+ if (!list_empty(priv-list_attached)) {
+ dmac_flush_range(fl_table, fl_table + SZ_16K);
- for (i = 0; i NUM_FL_PTE; i++)
- if ((fl_table[i] 0x03) == FL_TYPE_TABLE) {
- void *sl_table = __va(fl_table[i] FL_BASE_MASK);
- dmac_flush_range(sl_table, sl_table + SZ_4K);
- }
+ for (i = 0; i NUM_FL_PTE; i++)
+ if ((fl_table[i] 0x03) == FL_TYPE_TABLE) {
+ void *sl_table = __va(fl_table[i]
+ FL_BASE_MASK);
+ dmac_flush_range(sl_table, sl_table + SZ_4K);
+ }
+ }
#endif
list_for_each_entry(ctx_drvdata, priv-list_attached, attached_elm) {
--
1.7.0.2
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[PATCH 04/14] msm: iommu: Revise GFX3D IOMMU contexts and M2V mappings
Update the platform data for the 3D core's IOMMU based on
the revised usage model. Remove unused contexts and rename
the remaining contexts based on their new function. Add the
new M2VCBMT mappings for the updated contexts.
Signed-off-by: Stepan Moskovchenko step...@codeaurora.org
---
arch/arm/mach-msm/devices-msm8x60-iommu.c | 45 +---
1 files changed, 15 insertions(+), 30 deletions(-)
diff --git a/arch/arm/mach-msm/devices-msm8x60-iommu.c
b/arch/arm/mach-msm/devices-msm8x60-iommu.c
index 9e657e0..22d0c7c 100644
--- a/arch/arm/mach-msm/devices-msm8x60-iommu.c
+++ b/arch/arm/mach-msm/devices-msm8x60-iommu.c
@@ -519,22 +519,17 @@ static struct msm_iommu_ctx_dev vcodec_b_mm2_ctx = {
.mids = {0, 1, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
};
-static struct msm_iommu_ctx_dev gfx3d_rbpa_ctx = {
- .name = gfx3d_rbpa,
+static struct msm_iommu_ctx_dev gfx3d_user_ctx = {
+ .name = gfx3d_user,
.num = 0,
- .mids = {-1}
+ .mids = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, -1}
};
-static struct msm_iommu_ctx_dev gfx3d_cpvgttc_ctx = {
- .name = gfx3d_cpvgttc,
+static struct msm_iommu_ctx_dev gfx3d_priv_ctx = {
+ .name = gfx3d_priv,
.num = 1,
- .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1}
-};
-
-static struct msm_iommu_ctx_dev gfx3d_smmu_ctx = {
- .name = gfx3d_smmu,
- .num = 2,
- .mids = {8, 9, 10, 11, 12, -1}
+ .mids = {16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30,
+31, -1}
};
static struct msm_iommu_ctx_dev gfx2d0_pixv1_ctx = {
@@ -685,7 +680,7 @@ static struct platform_device msm_device_vcodec_b_mm2_ctx =
{
},
};
-static struct platform_device msm_device_gfx3d_rbpa_ctx = {
+static struct platform_device msm_device_gfx3d_user_ctx = {
.name = msm_iommu_ctx,
.id = 17,
.dev = {
@@ -693,7 +688,7 @@ static struct platform_device msm_device_gfx3d_rbpa_ctx = {
},
};
-static struct platform_device msm_device_gfx3d_cpvgttc_ctx = {
+static struct platform_device msm_device_gfx3d_priv_ctx = {
.name = msm_iommu_ctx,
.id = 18,
.dev = {
@@ -701,17 +696,9 @@ static struct platform_device msm_device_gfx3d_cpvgttc_ctx
= {
},
};
-static struct platform_device msm_device_gfx3d_smmu_ctx = {
- .name = msm_iommu_ctx,
- .id = 19,
- .dev = {
- .parent = msm_device_iommu_gfx3d.dev,
- },
-};
-
static struct platform_device msm_device_gfx2d0_pixv1_ctx = {
.name = msm_iommu_ctx,
- .id = 20,
+ .id = 19,
.dev = {
.parent = msm_device_iommu_gfx2d0.dev,
},
@@ -719,7 +706,7 @@ static struct platform_device msm_device_gfx2d0_pixv1_ctx =
{
static struct platform_device msm_device_gfx2d0_texv3_ctx = {
.name = msm_iommu_ctx,
- .id = 21,
+ .id = 20,
.dev = {
.parent = msm_device_iommu_gfx2d0.dev,
},
@@ -771,9 +758,8 @@ static struct platform_device *msm_iommu_ctx_devs[] = {
msm_device_vcodec_a_stream_ctx,
msm_device_vcodec_a_mm1_ctx,
msm_device_vcodec_b_mm2_ctx,
- msm_device_gfx3d_rbpa_ctx,
- msm_device_gfx3d_cpvgttc_ctx,
- msm_device_gfx3d_smmu_ctx,
+ msm_device_gfx3d_user_ctx,
+ msm_device_gfx3d_priv_ctx,
msm_device_gfx2d0_pixv1_ctx,
msm_device_gfx2d0_texv3_ctx,
};
@@ -796,9 +782,8 @@ static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = {
vcodec_a_stream_ctx,
vcodec_a_mm1_ctx,
vcodec_b_mm2_ctx,
- gfx3d_rbpa_ctx,
- gfx3d_cpvgttc_ctx,
- gfx3d_smmu_ctx,
+ gfx3d_user_ctx,
+ gfx3d_priv_ctx,
gfx2d0_pixv1_ctx,
gfx2d0_texv3_ctx,
};
--
1.7.0.2
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[PATCH 14/14] msm: iommu: Miscellaneous code cleanup
Remove some unneeded assignments and messages, restructure
a failure path in iova_to_phys, and make __flush_iotlb
return int in preparation for adding IOMMU clock control.
Signed-off-by: Stepan Moskovchenko step...@codeaurora.org
---
arch/arm/mach-msm/iommu.c | 29 +
1 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/arch/arm/mach-msm/iommu.c b/arch/arm/mach-msm/iommu.c
index 935025e..932728c 100644
--- a/arch/arm/mach-msm/iommu.c
+++ b/arch/arm/mach-msm/iommu.c
@@ -50,12 +50,12 @@ struct msm_priv {
struct list_head list_attached;
};
-static void __flush_iotlb(struct iommu_domain *domain)
+static int __flush_iotlb(struct iommu_domain *domain)
{
struct msm_priv *priv = domain-priv;
struct msm_iommu_drvdata *iommu_drvdata;
struct msm_iommu_ctx_drvdata *ctx_drvdata;
-
+ int ret = 0;
#ifndef CONFIG_IOMMU_PGTABLES_L2
unsigned long *fl_table = priv-pgtable;
int i;
@@ -79,6 +79,8 @@ static void __flush_iotlb(struct iommu_domain *domain)
iommu_drvdata = dev_get_drvdata(ctx_drvdata-pdev-dev.parent);
SET_CTX_TLBIALL(iommu_drvdata-base, ctx_drvdata-num, 0);
}
+
+ return ret;
}
static void __reset_context(void __iomem *base, int ctx)
@@ -267,7 +269,7 @@ static int msm_iommu_attach_dev(struct iommu_domain
*domain, struct device *dev)
__pa(priv-pgtable));
list_add((ctx_drvdata-attached_elm), priv-list_attached);
- __flush_iotlb(domain);
+ ret = __flush_iotlb(domain);
fail:
spin_unlock_irqrestore(msm_iommu_lock, flags);
@@ -282,6 +284,7 @@ static void msm_iommu_detach_dev(struct iommu_domain
*domain,
struct msm_iommu_drvdata *iommu_drvdata;
struct msm_iommu_ctx_drvdata *ctx_drvdata;
unsigned long flags;
+ int ret;
spin_lock_irqsave(msm_iommu_lock, flags);
priv = domain-priv;
@@ -296,7 +299,10 @@ static void msm_iommu_detach_dev(struct iommu_domain
*domain,
if (!iommu_drvdata || !ctx_drvdata || !ctx_dev)
goto fail;
- __flush_iotlb(domain);
+ ret = __flush_iotlb(domain);
+ if (ret)
+ goto fail;
+
__reset_context(iommu_drvdata-base, ctx_dev-num);
list_del_init(ctx_drvdata-attached_elm);
@@ -410,7 +416,7 @@ static int msm_iommu_map(struct iommu_domain *domain,
unsigned long va,
SL_AP1 | SL_SHARED | SL_TYPE_LARGE | pgprot;
}
- __flush_iotlb(domain);
+ ret = __flush_iotlb(domain);
fail:
spin_unlock_irqrestore(msm_iommu_lock, flags);
return ret;
@@ -495,7 +501,7 @@ static int msm_iommu_unmap(struct iommu_domain *domain,
unsigned long va,
}
}
- __flush_iotlb(domain);
+ ret = __flush_iotlb(domain);
fail:
spin_unlock_irqrestore(msm_iommu_lock, flags);
return ret;
@@ -530,9 +536,6 @@ static phys_addr_t msm_iommu_iova_to_phys(struct
iommu_domain *domain,
SET_CTX_TLBIALL(base, ctx, 0);
SET_V2PPR_VA(base, ctx, va V2Pxx_VA_SHIFT);
- if (GET_FAULT(base, ctx))
- goto fail;
-
par = GET_PAR(base, ctx);
/* We are dealing with a supersection */
@@ -541,6 +544,9 @@ static phys_addr_t msm_iommu_iova_to_phys(struct
iommu_domain *domain,
else/* Upper 20 bits from PAR, lower 12 from VA */
ret = (par 0xF000) | (va 0x0FFF);
+ if (GET_FAULT(base, ctx))
+ ret = 0;
+
fail:
spin_unlock_irqrestore(msm_iommu_lock, flags);
return ret;
@@ -583,8 +589,8 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id)
{
struct msm_iommu_drvdata *drvdata = dev_id;
void __iomem *base;
- unsigned int fsr = 0;
- int ncb = 0, i = 0;
+ unsigned int fsr;
+ int ncb, i;
spin_lock(msm_iommu_lock);
@@ -595,7 +601,6 @@ irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id)
base = drvdata-base;
- pr_err(= WOAH! =\n);
pr_err(Unexpected IOMMU page fault!\n);
pr_err(base = %08x\n, (unsigned int) base);
--
1.7.0.2
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[PATCH 13/14] msm: iommu: Support cache-coherent memory access
Add support for allowing IOMMU memory transactions to be
cache coherent, eliminating the need for software cache
management in certain situations. This can lead to
improvements in performance and power usage, assuming the
multimedia core's access pattern exhibits spatial locality
and that its working set fits into the cache.
Signed-off-by: Stepan Moskovchenko step...@codeaurora.org
---
arch/arm/mach-msm/iommu.c | 93 +++-
1 files changed, 82 insertions(+), 11 deletions(-)
diff --git a/arch/arm/mach-msm/iommu.c b/arch/arm/mach-msm/iommu.c
index 67e8f53..935025e 100644
--- a/arch/arm/mach-msm/iommu.c
+++ b/arch/arm/mach-msm/iommu.c
@@ -33,6 +33,16 @@
#include mach/iommu_hw-8xxx.h
#include mach/iommu.h
+#define MRC(reg, processor, op1, crn, crm, op2)
\
+__asm__ __volatile__ ( \
+ mrc #processor , #op1 , %0, #crn , #crm , #op2 \n \
+: =r (reg))
+
+#define RCP15_PRRR(reg)MRC(reg, p15, 0, c10, c2, 0)
+#define RCP15_NMRR(reg)MRC(reg, p15, 0, c10, c2, 1)
+
+static int msm_iommu_tex_class[4];
+
DEFINE_SPINLOCK(msm_iommu_lock);
struct msm_priv {
@@ -98,6 +108,7 @@ static void __reset_context(void __iomem *base, int ctx)
static void __program_context(void __iomem *base, int ctx, phys_addr_t pgtable)
{
+ unsigned int prrr, nmrr;
__reset_context(base, ctx);
/* Set up HTW mode */
@@ -130,11 +141,11 @@ static void __program_context(void __iomem *base, int
ctx, phys_addr_t pgtable)
/* Turn on TEX Remap */
SET_TRE(base, ctx, 1);
- /* Do not configure PRRR / NMRR on the IOMMU for now. We will assume
-* TEX class 0 for everything until attributes are properly worked out
-*/
- SET_PRRR(base, ctx, 0);
- SET_NMRR(base, ctx, 0);
+ /* Set TEX remap attributes */
+ RCP15_PRRR(prrr);
+ RCP15_NMRR(nmrr);
+ SET_PRRR(base, ctx, prrr);
+ SET_NMRR(base, ctx, nmrr);
/* Turn on BFB prefetch */
SET_BFBDFE(base, ctx, 1);
@@ -304,12 +315,21 @@ static int msm_iommu_map(struct iommu_domain *domain,
unsigned long va,
unsigned long *sl_table;
unsigned long *sl_pte;
unsigned long sl_offset;
+ unsigned int pgprot;
size_t len = 0x1000UL order;
- int ret = 0;
+ int ret = 0, tex, sh;
spin_lock_irqsave(msm_iommu_lock, flags);
- priv = domain-priv;
+ sh = (prot MSM_IOMMU_ATTR_SH) ? 1 : 0;
+ tex = msm_iommu_tex_class[prot 0x03];
+
+ if (tex 0 || tex NUM_TEX_CLASS - 1) {
+ ret = -EINVAL;
+ goto fail;
+ }
+
+ priv = domain-priv;
if (!priv) {
ret = -EINVAL;
goto fail;
@@ -330,6 +350,18 @@ static int msm_iommu_map(struct iommu_domain *domain,
unsigned long va,
goto fail;
}
+ if (len == SZ_16M || len == SZ_1M) {
+ pgprot = sh ? FL_SHARED : 0;
+ pgprot |= tex 0x01 ? FL_BUFFERABLE : 0;
+ pgprot |= tex 0x02 ? FL_CACHEABLE : 0;
+ pgprot |= tex 0x04 ? FL_TEX0 : 0;
+ } else {
+ pgprot = sh ? SL_SHARED : 0;
+ pgprot |= tex 0x01 ? SL_BUFFERABLE : 0;
+ pgprot |= tex 0x02 ? SL_CACHEABLE : 0;
+ pgprot |= tex 0x04 ? SL_TEX0 : 0;
+ }
+
fl_offset = FL_OFFSET(va); /* Upper 12 bits */
fl_pte = fl_table + fl_offset; /* int pointers, 4 bytes */
@@ -338,12 +370,12 @@ static int msm_iommu_map(struct iommu_domain *domain,
unsigned long va,
for (i = 0; i 16; i++)
*(fl_pte+i) = (pa 0xFF00) | FL_SUPERSECTION |
FL_AP_READ | FL_AP_WRITE | FL_TYPE_SECT |
- FL_SHARED;
+ FL_SHARED | pgprot;
}
if (len == SZ_1M)
*fl_pte = (pa 0xFFF0) | FL_AP_READ | FL_AP_WRITE |
- FL_TYPE_SECT | FL_SHARED;
+ FL_TYPE_SECT | FL_SHARED | pgprot;
/* Need a 2nd level table */
if ((len == SZ_4K || len == SZ_64K) (*fl_pte) == 0) {
@@ -368,14 +400,14 @@ static int msm_iommu_map(struct iommu_domain *domain,
unsigned long va,
if (len == SZ_4K)
*sl_pte = (pa SL_BASE_MASK_SMALL) | SL_AP0 | SL_AP1 |
- SL_SHARED | SL_TYPE_SMALL;
+ SL_SHARED | SL_TYPE_SMALL | pgprot;
if (len == SZ_64K) {
int i;
for (i = 0; i 16; i++)
*(sl_pte+i) = (pa SL_BASE_MASK_LARGE) | SL_AP0 |
- SL_AP1 | SL_SHARED | SL_TYPE_LARGE;
+ SL_AP1 | SL_SHARED | SL_TYPE_LARGE
[PATCH 02/14] msm: iomap: Addresses and IRQs for 2nd GFX core IOMMU
Add register addresses and IRQ numbers for the IOMMU used for the second 2D graphics core. Signed-off-by: Stepan Moskovchenko step...@codeaurora.org --- arch/arm/mach-msm/include/mach/irqs-8x60.h |7 ++- arch/arm/mach-msm/include/mach/msm_iomap-8x60.h |3 +++ 2 files changed, 9 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-msm/include/mach/irqs-8x60.h b/arch/arm/mach-msm/include/mach/irqs-8x60.h index 36074cf..f65841c 100644 --- a/arch/arm/mach-msm/include/mach/irqs-8x60.h +++ b/arch/arm/mach-msm/include/mach/irqs-8x60.h @@ -237,7 +237,12 @@ #define GSBI11_QUP_IRQ (GIC_SPI_START + 194) #define INT_UART12DM_IRQ (GIC_SPI_START + 195) #define GSBI12_QUP_IRQ (GIC_SPI_START + 196) -/*SPI 197 to 216 arent used in 8x60*/ + +/*SPI 197 to 209 arent used in 8x60*/ +#define SMMU_GFX2D1_CB_SC_SECURE_IRQ(GIC_SPI_START + 210) +#define SMMU_GFX2D1_CB_SC_NON_SECURE_IRQ(GIC_SPI_START + 211) + +/*SPI 212 to 216 arent used in 8x60*/ #define SMPSS_SPARE_1 (GIC_SPI_START + 217) #define SMPSS_SPARE_2 (GIC_SPI_START + 218) #define SMPSS_SPARE_3 (GIC_SPI_START + 219) diff --git a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h index 45bab50..7c43a9b 100644 --- a/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h +++ b/arch/arm/mach-msm/include/mach/msm_iomap-8x60.h @@ -98,4 +98,7 @@ #define MSM_IOMMU_GFX2D0_PHYS 0x07D0 #define MSM_IOMMU_GFX2D0_SIZE SZ_1M +#define MSM_IOMMU_GFX2D1_PHYS 0x07E0 +#define MSM_IOMMU_GFX2D1_SIZE SZ_1M + #endif -- 1.7.0.2 Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum. -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 11/14] msm: iommu: Kconfig dependency for the IOMMU API
Make the IOMMU driver select the IOMMU API in the kernel configuration. Signed-off-by: Stepan Moskovchenko step...@codeaurora.org --- arch/arm/mach-msm/Kconfig |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index 7781920..2f7ca4c 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -44,6 +44,7 @@ config ARCH_MSM8X60 select CPU_V7 select MSM_V2_TLMM select MSM_GPIOMUX + select IOMMU_API endchoice @@ -177,4 +178,7 @@ config MSM_GPIOMUX config MSM_V2_TLMM bool + +config IOMMU_API + bool endif -- 1.7.0.2 Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum. -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 01/14] msm: iommu: Increase maximum MID size to 5 bits
On msm8x60, the MID field on the AXI connection to the IOMMU can be up to five bits wide. Thus, allow the IOMMU context platform data to map up to 32 MIDs. Signed-off-by: Stepan Moskovchenko step...@codeaurora.org --- arch/arm/mach-msm/include/mach/iommu.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/mach-msm/include/mach/iommu.h b/arch/arm/mach-msm/include/mach/iommu.h index 218ef57..17fc79f 100644 --- a/arch/arm/mach-msm/include/mach/iommu.h +++ b/arch/arm/mach-msm/include/mach/iommu.h @@ -26,7 +26,7 @@ * be present. These mappings are typically determined at design time and are * not expected to change at run time. */ -#define MAX_NUM_MIDS 16 +#define MAX_NUM_MIDS 32 /** * struct msm_iommu_dev - a single IOMMU hardware instance -- 1.7.0.2 Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum. -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 05/14] msm: iommu: Revise GFX2D0 IOMMU contexts and M2V mappings
Update the platform data for the 2D core's IOMMU based on
the revised usage model. Merge the two contexts and their
M2VCBMT mappings, adding the previously-missing mappings to
the newly-formed context.
Signed-off-by: Stepan Moskovchenko step...@codeaurora.org
---
arch/arm/mach-msm/devices-msm8x60-iommu.c | 28 ++--
1 files changed, 6 insertions(+), 22 deletions(-)
diff --git a/arch/arm/mach-msm/devices-msm8x60-iommu.c
b/arch/arm/mach-msm/devices-msm8x60-iommu.c
index 22d0c7c..8cccb26 100644
--- a/arch/arm/mach-msm/devices-msm8x60-iommu.c
+++ b/arch/arm/mach-msm/devices-msm8x60-iommu.c
@@ -532,16 +532,10 @@ static struct msm_iommu_ctx_dev gfx3d_priv_ctx = {
31, -1}
};
-static struct msm_iommu_ctx_dev gfx2d0_pixv1_ctx = {
- .name = gfx2d0_pixv1_smmu,
+static struct msm_iommu_ctx_dev gfx2d0_2d0_ctx = {
+ .name = gfx2d0_2d0,
.num = 0,
- .mids = {0, 3, 4, -1}
-};
-
-static struct msm_iommu_ctx_dev gfx2d0_texv3_ctx = {
- .name = gfx2d0_texv3_smmu,
- .num = 1,
- .mids = {1, 6, 7, -1}
+ .mids = {0, 1, 2, 3, 4, 5, 6, 7, -1}
};
static struct platform_device msm_device_jpegd_src_ctx = {
@@ -696,7 +690,7 @@ static struct platform_device msm_device_gfx3d_priv_ctx = {
},
};
-static struct platform_device msm_device_gfx2d0_pixv1_ctx = {
+static struct platform_device msm_device_gfx2d0_2d0_ctx = {
.name = msm_iommu_ctx,
.id = 19,
.dev = {
@@ -704,14 +698,6 @@ static struct platform_device msm_device_gfx2d0_pixv1_ctx
= {
},
};
-static struct platform_device msm_device_gfx2d0_texv3_ctx = {
- .name = msm_iommu_ctx,
- .id = 20,
- .dev = {
- .parent = msm_device_iommu_gfx2d0.dev,
- },
-};
-
static struct platform_device *msm_iommu_devs[] = {
msm_device_iommu_jpegd,
msm_device_iommu_vpe,
@@ -760,8 +746,7 @@ static struct platform_device *msm_iommu_ctx_devs[] = {
msm_device_vcodec_b_mm2_ctx,
msm_device_gfx3d_user_ctx,
msm_device_gfx3d_priv_ctx,
- msm_device_gfx2d0_pixv1_ctx,
- msm_device_gfx2d0_texv3_ctx,
+ msm_device_gfx2d0_2d0_ctx,
};
static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = {
@@ -784,8 +769,7 @@ static struct msm_iommu_ctx_dev *msm_iommu_ctx_data[] = {
vcodec_b_mm2_ctx,
gfx3d_user_ctx,
gfx3d_priv_ctx,
- gfx2d0_pixv1_ctx,
- gfx2d0_texv3_ctx,
+ gfx2d0_2d0_ctx,
};
static int msm8x60_iommu_init(void)
--
1.7.0.2
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The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
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[PATCH 09/14] msm: iommu: Kconfig option for cacheable page tables
Add a Kconfig option to allow the IOMMU page tables to be coherent in the L2 cache. This generally reduces TLB miss latencies, but may lead to cache pollution if the multimedia core's access pattern does not benefit from fast handling of TLB misses. Signed-off-by: Stepan Moskovchenko step...@codeaurora.org --- arch/arm/mach-msm/Kconfig | 15 +++ 1 files changed, 15 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig index dbbcfeb..7781920 100644 --- a/arch/arm/mach-msm/Kconfig +++ b/arch/arm/mach-msm/Kconfig @@ -122,6 +122,21 @@ config MACH_MSM8X60_FFA endmenu +config IOMMU_PGTABLES_L2 + depends on ARCH_MSM8X60 + depends on MMU + depends on CPU_DCACHE_DISABLE=n + depends on SMP + bool Cacheable IOMMU page tables + default y + help + Allows the IOMMU page tables to be brought into the L2 cache. This + improves the TLB miss latency at the expense of potential pollution + of the L2 cache. This option has been shown to improve multimedia + performance in some cases. + + If unsure, say Y here. + config MSM_DEBUG_UART int default 1 if MSM_DEBUG_UART1 -- 1.7.0.2 Sent by an employee of the Qualcomm Innovation Center, Inc. The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum. -- To unsubscribe from this list: send the line unsubscribe linux-arm-msm in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 10/14] msm: iommu: Check if device is already attached
An IOMMU device can only be attached to one IOMMU domain at
any given time. Check whether the device is already
attached to a domain before allowing it to be attached to
another domain. If so, return busy.
Signed-off-by: Stepan Moskovchenko step...@codeaurora.org
---
arch/arm/mach-msm/iommu.c |5 +
1 files changed, 5 insertions(+), 0 deletions(-)
diff --git a/arch/arm/mach-msm/iommu.c b/arch/arm/mach-msm/iommu.c
index 74f2157..67e8f53 100644
--- a/arch/arm/mach-msm/iommu.c
+++ b/arch/arm/mach-msm/iommu.c
@@ -241,6 +241,11 @@ static int msm_iommu_attach_dev(struct iommu_domain
*domain, struct device *dev)
goto fail;
}
+ if (!list_empty(ctx_drvdata-attached_elm)) {
+ ret = -EBUSY;
+ goto fail;
+ }
+
list_for_each_entry(tmp_drvdata, priv-list_attached, attached_elm)
if (tmp_drvdata == ctx_drvdata) {
ret = -EBUSY;
--
1.7.0.2
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The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum.
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