Re: [Patch v9 3/3] phy: Add Qualcomm DWC3 HS/SS PHY driver
Hi, On Saturday 13 September 2014 12:58 AM, Andy Gross wrote: > This patch adds a new driver for the Qualcomm USB 3.0 PHY that exists on some > Qualcomm platforms. This driver uses the generic PHY framework and will > interact with the DWC3 controller. Do you have dt documentation for this driver? > > Signed-off-by: Andy Gross > --- > drivers/phy/Kconfig | 11 + > drivers/phy/Makefile|1 + > drivers/phy/phy-qcom-dwc3.c | 483 > +++ > 3 files changed, 495 insertions(+) > create mode 100644 drivers/phy/phy-qcom-dwc3.c > > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig > index 0dd7427..5d56161 100644 > --- a/drivers/phy/Kconfig > +++ b/drivers/phy/Kconfig > @@ -230,4 +230,15 @@ config PHY_XGENE > help > This option enables support for APM X-Gene SoC multi-purpose PHY. > > +config PHY_QCOM_DWC3 > + tristate "QCOM DWC3 USB PHY support" > + depends on ARCH_QCOM > + depends on HAS_IOMEM > + depends on OF > + select GENERIC_PHY > + help > + This option enables support for the Synopsis PHYs present inside the > + Qualcomm USB3.0 DWC3 controller. This driver supports both HS and SS > + PHY controllers. > + > endmenu > diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile > index 95c69ed..aa16f30 100644 > --- a/drivers/phy/Makefile > +++ b/drivers/phy/Makefile > @@ -28,3 +28,4 @@ obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += > phy-qcom-ipq806x-sata.o > obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o > obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o > obj-$(CONFIG_PHY_XGENE) += phy-xgene.o > +obj-$(CONFIG_PHY_QCOM_DWC3) += phy-qcom-dwc3.o > diff --git a/drivers/phy/phy-qcom-dwc3.c b/drivers/phy/phy-qcom-dwc3.c > new file mode 100644 > index 000..2c7b316 > --- /dev/null > +++ b/drivers/phy/phy-qcom-dwc3.c > @@ -0,0 +1,483 @@ > +/* Copyright (c) 2013-2014, Code Aurora Forum. All rights reserved. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 and > + * only version 2 as published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/** > + * USB QSCRATCH Hardware registers > + */ > +#define QSCRATCH_GENERAL_CFG (0x08) > +#define HSUSB_PHY_CTRL_REG (0x10) > + > +/* PHY_CTRL_REG */ > +#define HSUSB_CTRL_DMSEHV_CLAMP BIT(24) > +#define HSUSB_CTRL_USB2_SUSPEND BIT(23) > +#define HSUSB_CTRL_UTMI_CLK_EN BIT(21) > +#define HSUSB_CTRL_UTMI_OTG_VBUS_VALID BIT(20) alignment went wrong here.. > +#define HSUSB_CTRL_USE_CLKCORE BIT(18) > +#define HSUSB_CTRL_DPSEHV_CLAMP BIT(17) > +#define HSUSB_CTRL_COMMONONN BIT(11) > +#define HSUSB_CTRL_ID_HV_CLAMP BIT(9) > +#define HSUSB_CTRL_OTGSESSVLD_CLAMP BIT(8) > +#define HSUSB_CTRL_CLAMP_EN BIT(7) > +#define HSUSB_CTRL_RETENABLENBIT(1) > +#define HSUSB_CTRL_POR BIT(0) > + > +/* QSCRATCH_GENERAL_CFG */ > +#define HSUSB_GCFG_XHCI_REV BIT(2) > + > +/** > + * USB QSCRATCH Hardware registers > + */ > +#define SSUSB_PHY_CTRL_REG (0x00) > +#define SSUSB_PHY_PARAM_CTRL_1 (0x04) > +#define SSUSB_PHY_PARAM_CTRL_2 (0x08) > +#define CR_PROTOCOL_DATA_IN_REG (0x0c) > +#define CR_PROTOCOL_DATA_OUT_REG (0x10) > +#define CR_PROTOCOL_CAP_ADDR_REG (0x14) > +#define CR_PROTOCOL_CAP_DATA_REG (0x18) > +#define CR_PROTOCOL_READ_REG (0x1c) > +#define CR_PROTOCOL_WRITE_REG(0x20) > + > +/* PHY_CTRL_REG */ > +#define SSUSB_CTRL_REF_USE_PAD BIT(28) > +#define SSUSB_CTRL_TEST_POWERDOWNBIT(27) > +#define SSUSB_CTRL_LANE0_PWR_PRESENT BIT(24) > +#define SSUSB_CTRL_SS_PHY_EN BIT(8) > +#define SSUSB_CTRL_SS_PHY_RESET BIT(7) > + > +/* SSPHY control registers */ > +#define SSPHY_CTRL_RX_OVRD_IN_HI(lane) (0x1006 + 0x100 * lane) > +#define SSPHY_CTRL_TX_OVRD_DRV_LO(lane) (0x1002 + 0x100 * lane) > + > +/* RX OVRD IN HI bits */ > +#define RX_OVRD_IN_HI_RX_RESET_OVRD BIT(13) > +#define RX_OVRD_IN_HI_RX_RX_RESETBIT(12) > +#define RX_OVRD_IN_HI_RX_EQ_OVRD BIT(11) > +#define RX_OVRD_IN_HI_RX_EQ_MASK 0x0700 > +#define RX_OVRD_IN_HI_RX_EQ_SHIFT8 > +#define RX_OVRD_IN_HI_RX_EQ_EN_OVRD BIT(7) > +#define
回复: kexec on APQ8074
Do you pass a initrd to kexec kernel?
i don't see it.
- 发送自我的Sony Xperia™智能手机
Noé RUBINSTEIN编写
2014-09-12 4:02 GMT+02:00 Wang, Yalin :
> What's your @memory parameters in your dtb file?
> And what's your PHYSICAL_OFFSET of your kexec kernel ?
TEXT_OFFSET is 0x8000;
Here's the content of the memory node:
memory {
#address-cells = <0x1>;
#size-cells = <0x1>;
device_type = "memory";
reg = <0x0 0x4000 0x4000 0x4000>;
secure_region {
linux,contiguous-region;
reg = <0x0 0xfc0>;
label = "secure_mem";
linux,phandle = <0x1b>;
phandle = <0x1b>;
};
adsp_region {
linux,contiguous-region;
reg = <0x0 0x2f0>;
label = "adsp_mem";
linux,phandle = <0x1c>;
phandle = <0x1c>;
};
qsecom_region {
linux,contiguous-region;
reg = <0x0 0x110>;
label = "qseecom_mem";
linux,phandle = <0x1d>;
phandle = <0x1d>;
};
};
Thanks a lot,
Noé
Re: [PATCH v2 2/2] DT: iio: vadc: document dt binding
Stanimir Varbanov schrieb, Am 11.09.2014 17:13:
> Document DT binding for Qualcomm SPMI PMIC voltage ADC
> driver.
>
Still one typo left.
> Signed-off-by: Stanimir Varbanov
> Signed-off-by: Ivan T. Ivanov
> ---
> .../devicetree/bindings/iio/adc/qcom,spmi-vadc.txt | 123
>
> 1 files changed, 123 insertions(+), 0 deletions(-)
> create mode 100644
> Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt
> b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt
> new file mode 100644
> index 000..5abb491
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt
> @@ -0,0 +1,123 @@
> +Qualcomm's SPMI PMIC voltage ADC
> +
> +SPMI PMIC voltage ADC (VADC) provides interface to clients to read
> +voltage. A 15 bit ADC is used for voltage measurements. There are multiple
> +peripherals to the VADC and the scope of the driver is to provide interface
> +for the USR peripheral of the VADC.
> +
> +VADC node:
> +
> +- compatible:
> +Usage: required
> +Value type:
> +Definition: Should contain "qcom,spmi-vadc".
> +
> +- reg:
> +Usage: required
> +Value type:
> +Definition: Base address in the SPMI PMIC register map.
> +
> +- address-cells:
> +Usage: required
> +Value type:
> +Definition: Must be one.
> +
> +- size-cells:
> +Usage: required
> +Value type:
> +Definition: Must be zero.
> +
> +- interrupts:
> +Usage: required
> +Value type:
> +Definition: End of convertion interrupt number.
Typo: conversion
> +
> +- qcom,poll-eoc:
> +Usage: optional
> +Value type:
> +Definition: Use polling instead of interrupt for end of conversion
> +completion.
> +
> +Channel node properties:
> +
> +- reg:
> +Usage: required
> +Value type:
> +Definition: AMUX channel number.
> +See include/dt-bindings/iio/qcom,spmi-pmic-vadc.h
> +
> +- qcom,decimation:
> +Usage: optional
> +Value type:
> +Definition: Sampling rate to use for the individual channel measurement.
> +Quicker measurements can be made by reducing decimation ratio.
> +Valid values are 512, 1024, 2048, 4096.
> +If property is not found, default value of 512 will be used.
> +
> +- qcom,pre-scaling:
> +Usage: optional
> +Value type:
> +Definition: Used for scaling the channel input signal before the signal
> is
> +fed to VADC. The configuration for this node is to know the
> +pre-determined ratio and use it for post scaling. Select one from
> +the following options.
> +<1 1>, <1 3>, <1 4>, <1 6>, <1 20>, <1 8>, <10 81>, <1 10>
> +If property is not found default value depending of chip will be
> used.
> +
> +- qcom,ratiometric:
> +Usage: optional
> +Value type:
> +Definition: Channel calibration type. If this property is specified
> +VADC will use the VDD reference(1.8V) and GND for channel
> +calibration. If property is not found, channel will be
> +calibrated with 625mV and 1.25V reference channels.
> +
> +- qcom,hw-settle-time:
> +Usage: optional
> +Value type:
> +Definition: Time between AMUX getting configured and the ADC starting
> +conversion. Delay = 100us * (value) for value < 11, and
> +2ms * (value - 10) otherwise.
> +Valid values are: 0, 100, 200, 300, 400, 500, 600, 700, 800,
> +900 us and 1, 2, 4, 6, 8, 10 ms
> +If property is not found, channel will use 0us.
> +
> +- qcom,avg-samples:
> +Usage: optional
> +Value type:
> +Definition: Number of samples to be used for measurement.
> +Fast averaging provides the option to obtain a single measurement
> +from the ADC that is an average of multiple samples. The value
> +selected is 2^(value).
> +Valid values are: 1, 2, 4, 8, 16, 32, 64, 128, 256, 512
> +If property is not found, 1 sample will be used.
> +
> +NOTE: At least one channel node is required.
> +
> +Example:
> + /* VADC node */
> + pmic_vadc: vadc@3100 {
> + compatible = "qcom,spmi-vadc";
> + reg = <0x3100 0x100>;
> + interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #io-channel-cells = <1>;
> + io-channel-ranges;
> +
> + /* Channel node */
> + usb_id_nopull {
> + reg = ;
> + qcom,decimation = <512>;
> + qcom,ratiometric;
> + qcom,hw-settle-time = <200>;
> + qcom,avg-samples = <1>;
> + qcom,pre-scaling = <1 3>;
> + };
> + };
> +
> + /* IIO client node */
> + usb {
> + io
Re: [PATCH v2 1/2] iio: vadc: Qualcomm SPMI PMIC voltage ADC driver
Stanimir Varbanov schrieb, Am 11.09.2014 17:13: > The voltage ADC is peripheral of Qualcomm SPMI PMIC chips. It has > 15bits resolution and register space inside PMIC accessible across > SPMI bus. > > The vadc driver registers itself through IIO interface. > Looks already pretty good. Things you should consider in regard of common coding style are to use the variable name ret instead of rc, since it is used in almost all adc drivers and thus makes reviewing a bit easier. Besides that, you seem to use unsigned as well as unsigned int, so to be consistent, please stick to one of them. Other comments in line. > Signed-off-by: Stanimir Varbanov > Signed-off-by: Ivan T. Ivanov > --- > drivers/iio/adc/Kconfig | 11 + > drivers/iio/adc/Makefile |1 + > drivers/iio/adc/qcom-spmi-vadc.c | 999 > + > include/dt-bindings/iio/qcom,spmi-pmic-vadc.h | 119 +++ > 4 files changed, 1130 insertions(+), 0 deletions(-) > create mode 100644 drivers/iio/adc/qcom-spmi-vadc.c > create mode 100644 include/dt-bindings/iio/qcom,spmi-pmic-vadc.h > > diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig > index 11b048a..08700d4 100644 > --- a/drivers/iio/adc/Kconfig > +++ b/drivers/iio/adc/Kconfig > @@ -206,6 +206,17 @@ config NAU7802 > To compile this driver as a module, choose M here: the > module will be called nau7802. > > +config QCOM_SPMI_VADC > + tristate "Qualcomm SPMI PMIC voltage ADC" > + depends on SPMI > + help > + Say yes here if you want support for the Qualcomm SPMI PMIC voltage > ADC. > + > + The driver supports reading the HKADC, XOADC through the ADC AMUX > arbiter. > + The VADC includes support for the conversion sequencer. The driver > + supports reading the ADC through the AMUX channels for external > pull-ups > + simultaneously. > + > config TI_ADC081C > tristate "Texas Instruments ADC081C021/027" > depends on I2C > diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile > index ad81b51..d5d18f4 100644 > --- a/drivers/iio/adc/Makefile > +++ b/drivers/iio/adc/Makefile > @@ -22,6 +22,7 @@ obj-$(CONFIG_MCP320X) += mcp320x.o > obj-$(CONFIG_MCP3422) += mcp3422.o > obj-$(CONFIG_MEN_Z188_ADC) += men_z188_adc.o > obj-$(CONFIG_NAU7802) += nau7802.o > +obj-$(CONFIG_QCOM_SPMI_VADC) += qcom-spmi-vadc.o > obj-$(CONFIG_TI_ADC081C) += ti-adc081c.o > obj-$(CONFIG_TI_AM335X_ADC) += ti_am335x_adc.o > obj-$(CONFIG_TWL4030_MADC) += twl4030-madc.o > diff --git a/drivers/iio/adc/qcom-spmi-vadc.c > b/drivers/iio/adc/qcom-spmi-vadc.c > new file mode 100644 > index 000..e30eb04 > --- /dev/null > +++ b/drivers/iio/adc/qcom-spmi-vadc.c > @@ -0,0 +1,999 @@ > +/* > + * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License version 2 and > + * only version 2 as published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#include > + > +/* VADC register and bit definition */ > +#define VADC_REVISION2 0x1 > +#define VADC_REVISION2_SUPPORTED_VADC1 > + > +#define VADC_PERPH_TYPE 0x4 > +#define VADC_PERPH_TYPE_ADC 8 > + > +#define VADC_PERPH_SUBTYPE 0x5 > +#define VADC_PERPH_SUBTYPE_VADC 1 > + > +#define VADC_STATUS1 0x8 > +#define VADC_STATUS1_OP_MODE 4 > +#define VADC_STATUS1_REQ_STS BIT(1) > +#define VADC_STATUS1_EOC BIT(0) > +#define VADC_STATUS1_REQ_STS_EOC_MASK0x3 > + > +#define VADC_MODE_CTL0x40 > +#define VADC_OP_MODE_SHIFT 3 > +#define VADC_OP_MODE_NORMAL 0 > +#define VADC_AMUX_TRIM_ENBIT(1) > +#define VADC_ADC_TRIM_EN BIT(0) > + > +#define VADC_EN_CTL1 0x46 > +#define VADC_EN_CTL1_SET BIT(7) > + > +#define VADC_ADC_CH_SEL_CTL 0x48 > + > +#define VADC_ADC_DIG_PARAM 0x50 > +#define VADC_ADC_DIG_DEC_RATIO_SEL_SHIFT 2 > + > +#define VADC_HW_SETTLE_DELAY 0x51 > + > +#define VADC_CONV_REQ0x52 > +#define VADC_CONV_REQ_SETBIT(7) > + > +#define VADC_FAST_AVG_CTL0x5a > +#define
Re: [Patch v9 2/3] usb: dwc3: Add Qualcomm DWC3 glue layer driver
On 13-09-2014 01:59 AM, Felipe Balbi wrote:
> Hi,
>
> On Sat, Sep 13, 2014 at 01:55:50AM +0530, Pramod Gurav wrote:
> + qdwc = devm_kzalloc(&pdev->dev, sizeof(*qdwc), GFP_KERNEL);
> + if (!qdwc)
> + return -ENOMEM;
> +
> + platform_set_drvdata(pdev, qdwc);
> +
> + qdwc->dev = &pdev->dev;
> +
> + qdwc->core_clk = devm_clk_get(qdwc->dev, "core");
> + if (IS_ERR(qdwc->core_clk)) {
> + dev_err(qdwc->dev, "failed to get core clock\n");
> + return PTR_ERR(qdwc->core_clk);
> + }
> +
> + qdwc->iface_clk = devm_clk_get(qdwc->dev, "iface");
> + if (IS_ERR(qdwc->iface_clk)) {
> + dev_dbg(qdwc->dev, "failed to get optional iface
> clock\n");
> + qdwc->iface_clk = NULL;
> + }
> +
> + qdwc->sleep_clk = devm_clk_get(qdwc->dev, "sleep");
> + if (IS_ERR(qdwc->sleep_clk)) {
> + dev_dbg(qdwc->dev, "failed to get optional sleep
> clock\n");
> + qdwc->sleep_clk = NULL;
> + }
> +
> + ret = clk_prepare_enable(qdwc->core_clk);
> + if (ret) {
> + dev_err(qdwc->dev, "failed to enable core clock\n");
> + goto err_core;
> + }
> +
> + ret = clk_prepare_enable(qdwc->iface_clk);
>
Should not we check if qdwc->iface_clk is valid?
>>>
>>> read the sources luke.
>> Now I read that its initialized to NULL in fail case but should we call
>> prepare_enable at all if its NULL?
>
> now read the source of clk_enable() and clk_prepare() ;-) NULL is a
> valid clock, it just returns 0. This is better than sprinkling IS_ERR()
> all over the place.
Seen that. I was wrong about IS_ERR. Thanks. :)
>
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Re: [Patch v9 2/3] usb: dwc3: Add Qualcomm DWC3 glue layer driver
Hi,
On Sat, Sep 13, 2014 at 01:55:50AM +0530, Pramod Gurav wrote:
> >>> + qdwc = devm_kzalloc(&pdev->dev, sizeof(*qdwc), GFP_KERNEL);
> >>> + if (!qdwc)
> >>> + return -ENOMEM;
> >>> +
> >>> + platform_set_drvdata(pdev, qdwc);
> >>> +
> >>> + qdwc->dev = &pdev->dev;
> >>> +
> >>> + qdwc->core_clk = devm_clk_get(qdwc->dev, "core");
> >>> + if (IS_ERR(qdwc->core_clk)) {
> >>> + dev_err(qdwc->dev, "failed to get core clock\n");
> >>> + return PTR_ERR(qdwc->core_clk);
> >>> + }
> >>> +
> >>> + qdwc->iface_clk = devm_clk_get(qdwc->dev, "iface");
> >>> + if (IS_ERR(qdwc->iface_clk)) {
> >>> + dev_dbg(qdwc->dev, "failed to get optional iface
> >>> clock\n");
> >>> + qdwc->iface_clk = NULL;
> >>> + }
> >>> +
> >>> + qdwc->sleep_clk = devm_clk_get(qdwc->dev, "sleep");
> >>> + if (IS_ERR(qdwc->sleep_clk)) {
> >>> + dev_dbg(qdwc->dev, "failed to get optional sleep
> >>> clock\n");
> >>> + qdwc->sleep_clk = NULL;
> >>> + }
> >>> +
> >>> + ret = clk_prepare_enable(qdwc->core_clk);
> >>> + if (ret) {
> >>> + dev_err(qdwc->dev, "failed to enable core clock\n");
> >>> + goto err_core;
> >>> + }
> >>> +
> >>> + ret = clk_prepare_enable(qdwc->iface_clk);
> >>>
> >> Should not we check if qdwc->iface_clk is valid?
> >
> > read the sources luke.
> Now I read that its initialized to NULL in fail case but should we call
> prepare_enable at all if its NULL?
now read the source of clk_enable() and clk_prepare() ;-) NULL is a
valid clock, it just returns 0. This is better than sprinkling IS_ERR()
all over the place.
--
balbi
signature.asc
Description: Digital signature
Re: [Patch v9 2/3] usb: dwc3: Add Qualcomm DWC3 glue layer driver
Hi Felipe,
On 13-09-2014 01:50 AM, Felipe Balbi wrote:
> On Sat, Sep 13, 2014 at 01:44:25AM +0530, Pramod Gurav wrote:
>> Andy,
>> Couple of minor comments.
>>
>> On Sat, Sep 13, 2014 at 12:58 AM, Andy Gross wrote:
>>
>>> From: "Ivan T. Ivanov"
>>>
>>> DWC3 glue layer is hardware layer around Synopsys DesignWare
>>> USB3 core. Its purpose is to supply Synopsys IP with required
>>> clocks, voltages and interface it with the rest of the SoC.
>>>
>>> Signed-off-by: Ivan T. Ivanov
>>> Signed-off-by: Andy Gross
>>> ---
>>> drivers/usb/dwc3/Kconfig |8 +++
>>> drivers/usb/dwc3/Makefile|1 +
>>> drivers/usb/dwc3/dwc3-qcom.c | 131
>>> ++
>>> 3 files changed, 140 insertions(+)
>>> create mode 100644 drivers/usb/dwc3/dwc3-qcom.c
>>>
>>>
>> <..>
>>
>>
>>> +#include
>>> +
>>> +struct dwc3_qcom {
>>> + struct device *dev;
>>> +
>>>
>> Extra new line here.
>
> that's not an issue however.
>
>>> + struct clk *core_clk;
>>> + struct clk *iface_clk;
>>> + struct clk *sleep_clk;
>>> +};
>>> +
>>> +static int dwc3_qcom_probe(struct platform_device *pdev)
>>> +{
>>> + struct device_node *node = pdev->dev.of_node;
>>> + struct dwc3_qcom *qdwc;
>>> + int ret = 0;
>>>
>> Initialization not required.
>
> I'll fix this one as I'm already applying this patch.
>
>>> +
>>> + qdwc = devm_kzalloc(&pdev->dev, sizeof(*qdwc), GFP_KERNEL);
>>> + if (!qdwc)
>>> + return -ENOMEM;
>>> +
>>> + platform_set_drvdata(pdev, qdwc);
>>> +
>>> + qdwc->dev = &pdev->dev;
>>> +
>>> + qdwc->core_clk = devm_clk_get(qdwc->dev, "core");
>>> + if (IS_ERR(qdwc->core_clk)) {
>>> + dev_err(qdwc->dev, "failed to get core clock\n");
>>> + return PTR_ERR(qdwc->core_clk);
>>> + }
>>> +
>>> + qdwc->iface_clk = devm_clk_get(qdwc->dev, "iface");
>>> + if (IS_ERR(qdwc->iface_clk)) {
>>> + dev_dbg(qdwc->dev, "failed to get optional iface clock\n");
>>> + qdwc->iface_clk = NULL;
>>> + }
>>> +
>>> + qdwc->sleep_clk = devm_clk_get(qdwc->dev, "sleep");
>>> + if (IS_ERR(qdwc->sleep_clk)) {
>>> + dev_dbg(qdwc->dev, "failed to get optional sleep clock\n");
>>> + qdwc->sleep_clk = NULL;
>>> + }
>>> +
>>> + ret = clk_prepare_enable(qdwc->core_clk);
>>> + if (ret) {
>>> + dev_err(qdwc->dev, "failed to enable core clock\n");
>>> + goto err_core;
>>> + }
>>> +
>>> + ret = clk_prepare_enable(qdwc->iface_clk);
>>>
>> Should not we check if qdwc->iface_clk is valid?
>
> read the sources luke.
Now I read that its initialized to NULL in fail case but should we call
prepare_enable at all if its NULL?
>
>>> +err_clks:
>>> + clk_disable_unprepare(qdwc->sleep_clk);
>>>
>> IS_ERR check before above statement not needed as we have continued with
>> probe even after failure og devm_clk_get?
>
> read more carefully, there's a detail which you're missing.
>
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Re: [Patch v9 2/3] usb: dwc3: Add Qualcomm DWC3 glue layer driver
On Sat, Sep 13, 2014 at 01:44:25AM +0530, Pramod Gurav wrote:
> Andy,
> Couple of minor comments.
>
> On Sat, Sep 13, 2014 at 12:58 AM, Andy Gross wrote:
>
> > From: "Ivan T. Ivanov"
> >
> > DWC3 glue layer is hardware layer around Synopsys DesignWare
> > USB3 core. Its purpose is to supply Synopsys IP with required
> > clocks, voltages and interface it with the rest of the SoC.
> >
> > Signed-off-by: Ivan T. Ivanov
> > Signed-off-by: Andy Gross
> > ---
> > drivers/usb/dwc3/Kconfig |8 +++
> > drivers/usb/dwc3/Makefile|1 +
> > drivers/usb/dwc3/dwc3-qcom.c | 131
> > ++
> > 3 files changed, 140 insertions(+)
> > create mode 100644 drivers/usb/dwc3/dwc3-qcom.c
> >
> >
> <..>
>
>
> > +#include
> > +
> > +struct dwc3_qcom {
> > + struct device *dev;
> > +
> >
> Extra new line here.
that's not an issue however.
> > + struct clk *core_clk;
> > + struct clk *iface_clk;
> > + struct clk *sleep_clk;
> > +};
> > +
> > +static int dwc3_qcom_probe(struct platform_device *pdev)
> > +{
> > + struct device_node *node = pdev->dev.of_node;
> > + struct dwc3_qcom *qdwc;
> > + int ret = 0;
> >
> Initialization not required.
I'll fix this one as I'm already applying this patch.
> > +
> > + qdwc = devm_kzalloc(&pdev->dev, sizeof(*qdwc), GFP_KERNEL);
> > + if (!qdwc)
> > + return -ENOMEM;
> > +
> > + platform_set_drvdata(pdev, qdwc);
> > +
> > + qdwc->dev = &pdev->dev;
> > +
> > + qdwc->core_clk = devm_clk_get(qdwc->dev, "core");
> > + if (IS_ERR(qdwc->core_clk)) {
> > + dev_err(qdwc->dev, "failed to get core clock\n");
> > + return PTR_ERR(qdwc->core_clk);
> > + }
> > +
> > + qdwc->iface_clk = devm_clk_get(qdwc->dev, "iface");
> > + if (IS_ERR(qdwc->iface_clk)) {
> > + dev_dbg(qdwc->dev, "failed to get optional iface clock\n");
> > + qdwc->iface_clk = NULL;
> > + }
> > +
> > + qdwc->sleep_clk = devm_clk_get(qdwc->dev, "sleep");
> > + if (IS_ERR(qdwc->sleep_clk)) {
> > + dev_dbg(qdwc->dev, "failed to get optional sleep clock\n");
> > + qdwc->sleep_clk = NULL;
> > + }
> > +
> > + ret = clk_prepare_enable(qdwc->core_clk);
> > + if (ret) {
> > + dev_err(qdwc->dev, "failed to enable core clock\n");
> > + goto err_core;
> > + }
> > +
> > + ret = clk_prepare_enable(qdwc->iface_clk);
> >
> Should not we check if qdwc->iface_clk is valid?
read the sources luke.
> > +err_clks:
> > + clk_disable_unprepare(qdwc->sleep_clk);
> >
> IS_ERR check before above statement not needed as we have continued with
> probe even after failure og devm_clk_get?
read more carefully, there's a detail which you're missing.
--
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[GIT PULL] qcom DT changes for v3.18
The following changes since commit 7d1311b93e58ed55f3a31cc8f94c4b8fe988a2b9: Linux 3.17-rc1 (2014-08-16 10:40:26 -0600) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom.git tags/qcom-dt-for-3.18 for you to fetch changes up to edb81ca3bf586ad526ee67b245cb87f7c7142a87: ARM: DT: QCOM: apq8064: Add dma support for sdcc node (2014-09-11 12:07:40 -0500) Qualcomm ARM Based Device Tree Updates for v3.18 * Added APQ8084 dt support for clocks, serial, pinctrl, and IFC6540 board * Added IPQ8064 dt support for basic SoC and AP148 board * Added APQ8064 dt support for pinctrl, reset, SDHC, and multimedia clocks * Added PMIC 8058 dt support on MSM8660, enables PMIC based power key, keypad, rtc, and vibrator * Added PMIC 8921 dt support on MSM8960, enables PMIC based power key, keypad, and rtc Georgi Djakov (4): ARM: dts: qcom: Add APQ8084 Global Clock Controller DT node ARM: dts: qcom: Add APQ8084 serial port DT node ARM: dts: qcom: Add initial IFC6540 board device tree ARM: dts: qcom: Add TLMM DT node for APQ8084 Kumar Gala (1): ARM: qcom: Add initial IPQ8064 SoC and AP148 device trees Pramod Gurav (2): ARM: DT: APQ8064: Add pinctrl support ARM: DT: APQ8064: Add node for ps_hold function in pinctrl Srinivas Kandagatla (2): ARM: DT: apq8064: Add sdcc support via mcci driver. ARM: DT: QCOM: apq8064: Add dma support for sdcc node Stephen Boyd (3): ARM: dts: msm: Add 8921 PMIC to ssbi bus ARM: dts: msm: Add 8058 PMIC to ssbi bus ARM: dts: qcom: Add 8064 multimedia clock controller node arch/arm/boot/dts/Makefile | 2 + arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 12 +++ arch/arm/boot/dts/qcom-apq8064.dtsi| 103 arch/arm/boot/dts/qcom-apq8084-ifc6540.dts | 23 ++ arch/arm/boot/dts/qcom-apq8084-mtp.dts | 6 ++ arch/arm/boot/dts/qcom-apq8084.dtsi| 51 arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 85 arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi | 1 + arch/arm/boot/dts/qcom-ipq8064.dtsi| 250 ++ arch/arm/boot/dts/qcom-msm8660-surf.dts| 30 +++ arch/arm/boot/dts/qcom-msm8660.dtsi| 42 ++ arch/arm/boot/dts/qcom-msm8960-cdp.dts | 15 arch/arm/boot/dts/qcom-msm8960.dtsi| 37 + arch/arm/mach-qcom/board.c | 2 + 14 files changed, 659 insertions(+) create mode 100644 arch/arm/boot/dts/qcom-apq8084-ifc6540.dts create mode 100644 arch/arm/boot/dts/qcom-ipq8064-ap148.dts create mode 100644 arch/arm/boot/dts/qcom-ipq8064-v1.0.dtsi create mode 100644 arch/arm/boot/dts/qcom-ipq8064.dtsi -- Employee of Qualcomm Innovation Center, Inc. Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[Patch v9 2/3] usb: dwc3: Add Qualcomm DWC3 glue layer driver
From: "Ivan T. Ivanov"
DWC3 glue layer is hardware layer around Synopsys DesignWare
USB3 core. Its purpose is to supply Synopsys IP with required
clocks, voltages and interface it with the rest of the SoC.
Signed-off-by: Ivan T. Ivanov
Signed-off-by: Andy Gross
---
drivers/usb/dwc3/Kconfig |8 +++
drivers/usb/dwc3/Makefile|1 +
drivers/usb/dwc3/dwc3-qcom.c | 131 ++
3 files changed, 140 insertions(+)
create mode 100644 drivers/usb/dwc3/dwc3-qcom.c
diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
index 785510a..a816fe4 100644
--- a/drivers/usb/dwc3/Kconfig
+++ b/drivers/usb/dwc3/Kconfig
@@ -80,6 +80,14 @@ config USB_DWC3_KEYSTONE
Support of USB2/3 functionality in TI Keystone2 platforms.
Say 'Y' or 'M' here if you have one such device
+config USB_DWC3_QCOM
+ tristate "Qualcomm Platforms"
+ depends on ARCH_QCOM || COMPILE_TEST
+ default USB_DWC3
+ help
+ Recent Qualcomm SoCs ship with one DesignWare Core USB3 IP inside,
+ say 'Y' or 'M' if you have one such device.
+
comment "Debugging features"
config USB_DWC3_DEBUG
diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
index 10ac3e7..0da8e75 100644
--- a/drivers/usb/dwc3/Makefile
+++ b/drivers/usb/dwc3/Makefile
@@ -33,3 +33,4 @@ obj-$(CONFIG_USB_DWC3_OMAP) += dwc3-omap.o
obj-$(CONFIG_USB_DWC3_EXYNOS) += dwc3-exynos.o
obj-$(CONFIG_USB_DWC3_PCI) += dwc3-pci.o
obj-$(CONFIG_USB_DWC3_KEYSTONE)+= dwc3-keystone.o
+obj-$(CONFIG_USB_DWC3_QCOM)+= dwc3-qcom.o
diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
new file mode 100644
index 000..f255335
--- /dev/null
+++ b/drivers/usb/dwc3/dwc3-qcom.c
@@ -0,0 +1,131 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct dwc3_qcom {
+ struct device *dev;
+
+ struct clk *core_clk;
+ struct clk *iface_clk;
+ struct clk *sleep_clk;
+};
+
+static int dwc3_qcom_probe(struct platform_device *pdev)
+{
+ struct device_node *node = pdev->dev.of_node;
+ struct dwc3_qcom *qdwc;
+ int ret = 0;
+
+ qdwc = devm_kzalloc(&pdev->dev, sizeof(*qdwc), GFP_KERNEL);
+ if (!qdwc)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, qdwc);
+
+ qdwc->dev = &pdev->dev;
+
+ qdwc->core_clk = devm_clk_get(qdwc->dev, "core");
+ if (IS_ERR(qdwc->core_clk)) {
+ dev_err(qdwc->dev, "failed to get core clock\n");
+ return PTR_ERR(qdwc->core_clk);
+ }
+
+ qdwc->iface_clk = devm_clk_get(qdwc->dev, "iface");
+ if (IS_ERR(qdwc->iface_clk)) {
+ dev_dbg(qdwc->dev, "failed to get optional iface clock\n");
+ qdwc->iface_clk = NULL;
+ }
+
+ qdwc->sleep_clk = devm_clk_get(qdwc->dev, "sleep");
+ if (IS_ERR(qdwc->sleep_clk)) {
+ dev_dbg(qdwc->dev, "failed to get optional sleep clock\n");
+ qdwc->sleep_clk = NULL;
+ }
+
+ ret = clk_prepare_enable(qdwc->core_clk);
+ if (ret) {
+ dev_err(qdwc->dev, "failed to enable core clock\n");
+ goto err_core;
+ }
+
+ ret = clk_prepare_enable(qdwc->iface_clk);
+ if (ret) {
+ dev_err(qdwc->dev, "failed to enable optional iface clock\n");
+ goto err_iface;
+ }
+
+ ret = clk_prepare_enable(qdwc->sleep_clk);
+ if (ret) {
+ dev_err(qdwc->dev, "failed to enable optional sleep clock\n");
+ goto err_sleep;
+ }
+
+ ret = of_platform_populate(node, NULL, NULL, qdwc->dev);
+ if (ret) {
+ dev_err(qdwc->dev, "failed to register core - %d\n", ret);
+ goto err_clks;
+ }
+
+ return 0;
+
+err_clks:
+ clk_disable_unprepare(qdwc->sleep_clk);
+err_sleep:
+ clk_disable_unprepare(qdwc->iface_clk);
+err_iface:
+ clk_disable_unprepare(qdwc->core_clk);
+err_core:
+ return ret;
+}
+
+static int dwc3_qcom_remove(struct platform_device *pdev)
+{
+ struct dwc3_qcom *qdwc = platform_get_drvdata(pdev);
+
+ of_platform_depopulate(&pdev->dev);
+
+ clk_disable_unprepare(qdwc->sleep_clk);
+ clk_disable_unprepare(qdwc->iface_clk);
+ clk_disable_unprepare(qdwc-
[Patch v9 0/3] DWC3 USB support for Qualcomm platform
These patches add basic support for USB3.0 controllers found on MSM platforms. USB3.0 core is based on Synopsys DesignWare SuperSpeed IP. This work was started by Ivan Ivanov and went through a number of iterations. I picked these patches up and did a little rework to get them working. Changes since v8: * Fixed minor comments from reviewers. Changes since v7: * Reworked phy driver to conform to the generic phy framework. * Collapsed HS and SS phy drivers into same source file. * Dropped regulators from the drivers. The only platform where we can utilize this driver has regulators on all the time. Will add regulators back in when they are required. * Added timeouts to the phy register accesses * Put in definitions for the phy specific registers and bitfields * Removed unnecessary workarounds. Changes since v6: * Renamed all MSM references to qcom, including file names * Removed direct TCSR manipulation. This done from new TCSR driver. * Added defines for register bits * XO clk is optional on some platforms. Corrected logic to handle this. * Ignore set_voltage failures. This allows us to support dummy regulators on platforms where there is no voltage control. * Reworked devicetree binding to remove TCSR reg resources Changes since v5: * devicetree bindings descriptions fixes * Fixed NULL pointer dereferences in dev_prink's * Removed extra space in "sleep " clock name Changes since v4: * Substitute references to "wc3" with just "dw" in USB PHY drivers and file names. This is to indicate that the PHY's are DesignWare, but not necessarily related to DWC3 IP core. Changes since v3: * Remove "_clk" suffix from clock names * Clarify required child node for qcom,dwc3 * Fix comments in functions headers * Use dbg instead err in drivers probe functions. Changes since v2: * Several improvements in devicetree bindings description * Disable regulators in glue layer if there is error during ioremap. Changes since first version: * Split devicetree bindings description file to separate patch * Address comments for device bindings description * Fix typo in 'gdsc' requlator name. Andy Gross (1): phy: Add Qualcomm DWC3 HS/SS PHY driver Ivan T. Ivanov (2): usb: dwc3: qcom: Add device tree binding usb: dwc3: Add Qualcomm DWC3 glue layer driver .../devicetree/bindings/phy/qcom-dwc3-usb-phy.txt | 39 ++ .../devicetree/bindings/usb/qcom,dwc3.txt | 66 +++ drivers/phy/Kconfig| 11 + drivers/phy/Makefile |1 + drivers/phy/phy-qcom-dwc3.c| 483 drivers/usb/dwc3/Kconfig |8 + drivers/usb/dwc3/Makefile |1 + drivers/usb/dwc3/dwc3-qcom.c | 131 ++ 8 files changed, 740 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt create mode 100644 Documentation/devicetree/bindings/usb/qcom,dwc3.txt create mode 100644 drivers/phy/phy-qcom-dwc3.c create mode 100644 drivers/usb/dwc3/dwc3-qcom.c -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[Patch v9 1/3] usb: dwc3: qcom: Add device tree binding
From: "Ivan T. Ivanov"
QCOM USB3.0 core wrapper consist of USB3.0 IP from Synopsys
(SNPS) and HS, SS PHY's control and configuration registers.
It could operate in device mode (SS, HS, FS) and host
mode (SS, HS, FS, LS).
Signed-off-by: Ivan T. Ivanov
Signed-off-by: Andy Gross
---
.../devicetree/bindings/phy/qcom-dwc3-usb-phy.txt | 39
.../devicetree/bindings/usb/qcom,dwc3.txt | 66
2 files changed, 105 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt
create mode 100644 Documentation/devicetree/bindings/usb/qcom,dwc3.txt
diff --git a/Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt
b/Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt
new file mode 100644
index 000..86f2dbe
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt
@@ -0,0 +1,39 @@
+Qualcomm DWC3 HS AND SS PHY CONTROLLER
+--
+
+DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer
+controllers. Each DWC3 PHY controller should have its own node.
+
+Required properties:
+- compatible: should contain one of the following:
+ - "qcom,dwc3-hs-usb-phy" for High Speed Synopsis PHY controller
+ - "qcom,dwc3-ss-usb-phy" for Super Speed Synopsis PHY controller
+- reg: offset and length of the DWC3 PHY controller register set
+- #phy-cells: must be zero
+- clocks: a list of phandles and clock-specifier pairs, one for each entry in
+ clock-names.
+- clock-names: Should contain "ref" for the PHY reference clock
+
+Optional clocks:
+ "xo" External reference clock
+
+Example:
+ phy@100f8800 {
+ compatible = "qcom,dwc3-hs-usb-phy";
+ reg = <0x100f8800 0x30>;
+ clocks = <&gcc USB30_0_UTMI_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+
+ status = "ok";
+ };
+
+ phy@100f8830 {
+ compatible = "qcom,dwc3-ss-usb-phy";
+ reg = <0x100f8830 0x30>;
+ clocks = <&gcc USB30_0_MASTER_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+
+ status = "ok";
+ };
diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
new file mode 100644
index 000..ca164e7
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
@@ -0,0 +1,66 @@
+Qualcomm SuperSpeed DWC3 USB SoC controller
+
+Required properties:
+- compatible: should contain "qcom,dwc3"
+- clocks: A list of phandle + clock-specifier pairs for the
+ clocks listed in clock-names
+- clock-names: Should contain the following:
+ "core" Master/Core clock, have to be >= 125 MHz for SS
+ operation and >= 60MHz for HS operation
+
+Optional clocks:
+ "iface" System bus AXI clock. Not present on all platforms
+ "sleep" Sleep clock, used when USB3 core goes into low
+ power mode (U3).
+
+Required child node:
+A child node must exist to represent the core DWC3 IP block. The name of
+the node is not important. The content of the node is defined in dwc3.txt.
+
+Phy documentation is provided in the following places:
+Documentation/devicetree/bindings/phy/qcom,dwc3-usb-phy.txt
+
+Example device nodes:
+
+ hs_phy: phy@100f8800 {
+ compatible = "qcom,dwc3-hs-usb-phy";
+ reg = <0x100f8800 0x30>;
+ clocks = <&gcc USB30_0_UTMI_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+
+ status = "ok";
+ };
+
+ ss_phy: phy@100f8830 {
+ compatible = "qcom,dwc3-ss-usb-phy";
+ reg = <0x100f8830 0x30>;
+ clocks = <&gcc USB30_0_MASTER_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+
+ status = "ok";
+ };
+
+ usb3_0: usb30@0 {
+ compatible = "qcom,dwc3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&gcc USB30_0_MASTER_CLK>;
+ clock-names = "core";
+
+ ranges;
+
+ status = "ok";
+
+ dwc3@1000 {
+ compatible = "snps,dwc3";
+ reg = <0x1000 0xcd00>;
+ interrupts = <0 205 0x4>;
+ phys = <&hs_phy>, <&ss_phy>;
+ phy-names = "usb2-phy", "u
[Patch v9 3/3] phy: Add Qualcomm DWC3 HS/SS PHY driver
This patch adds a new driver for the Qualcomm USB 3.0 PHY that exists on some Qualcomm platforms. This driver uses the generic PHY framework and will interact with the DWC3 controller. Signed-off-by: Andy Gross --- drivers/phy/Kconfig | 11 + drivers/phy/Makefile|1 + drivers/phy/phy-qcom-dwc3.c | 483 +++ 3 files changed, 495 insertions(+) create mode 100644 drivers/phy/phy-qcom-dwc3.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 0dd7427..5d56161 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -230,4 +230,15 @@ config PHY_XGENE help This option enables support for APM X-Gene SoC multi-purpose PHY. +config PHY_QCOM_DWC3 + tristate "QCOM DWC3 USB PHY support" + depends on ARCH_QCOM + depends on HAS_IOMEM + depends on OF + select GENERIC_PHY + help + This option enables support for the Synopsis PHYs present inside the + Qualcomm USB3.0 DWC3 controller. This driver supports both HS and SS + PHY controllers. + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 95c69ed..aa16f30 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -28,3 +28,4 @@ obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o obj-$(CONFIG_PHY_XGENE)+= phy-xgene.o +obj-$(CONFIG_PHY_QCOM_DWC3)+= phy-qcom-dwc3.o diff --git a/drivers/phy/phy-qcom-dwc3.c b/drivers/phy/phy-qcom-dwc3.c new file mode 100644 index 000..2c7b316 --- /dev/null +++ b/drivers/phy/phy-qcom-dwc3.c @@ -0,0 +1,483 @@ +/* Copyright (c) 2013-2014, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + * USB QSCRATCH Hardware registers + */ +#define QSCRATCH_GENERAL_CFG (0x08) +#define HSUSB_PHY_CTRL_REG (0x10) + +/* PHY_CTRL_REG */ +#define HSUSB_CTRL_DMSEHV_CLAMPBIT(24) +#define HSUSB_CTRL_USB2_SUSPENDBIT(23) +#define HSUSB_CTRL_UTMI_CLK_EN BIT(21) +#defineHSUSB_CTRL_UTMI_OTG_VBUS_VALID BIT(20) +#define HSUSB_CTRL_USE_CLKCORE BIT(18) +#define HSUSB_CTRL_DPSEHV_CLAMPBIT(17) +#define HSUSB_CTRL_COMMONONN BIT(11) +#define HSUSB_CTRL_ID_HV_CLAMP BIT(9) +#define HSUSB_CTRL_OTGSESSVLD_CLAMPBIT(8) +#define HSUSB_CTRL_CLAMP_ENBIT(7) +#define HSUSB_CTRL_RETENABLEN BIT(1) +#define HSUSB_CTRL_POR BIT(0) + +/* QSCRATCH_GENERAL_CFG */ +#define HSUSB_GCFG_XHCI_REVBIT(2) + +/** + * USB QSCRATCH Hardware registers + */ +#define SSUSB_PHY_CTRL_REG (0x00) +#define SSUSB_PHY_PARAM_CTRL_1 (0x04) +#define SSUSB_PHY_PARAM_CTRL_2 (0x08) +#define CR_PROTOCOL_DATA_IN_REG(0x0c) +#define CR_PROTOCOL_DATA_OUT_REG (0x10) +#define CR_PROTOCOL_CAP_ADDR_REG (0x14) +#define CR_PROTOCOL_CAP_DATA_REG (0x18) +#define CR_PROTOCOL_READ_REG (0x1c) +#define CR_PROTOCOL_WRITE_REG (0x20) + +/* PHY_CTRL_REG */ +#define SSUSB_CTRL_REF_USE_PAD BIT(28) +#define SSUSB_CTRL_TEST_POWERDOWN BIT(27) +#define SSUSB_CTRL_LANE0_PWR_PRESENT BIT(24) +#define SSUSB_CTRL_SS_PHY_EN BIT(8) +#define SSUSB_CTRL_SS_PHY_RESETBIT(7) + +/* SSPHY control registers */ +#define SSPHY_CTRL_RX_OVRD_IN_HI(lane) (0x1006 + 0x100 * lane) +#define SSPHY_CTRL_TX_OVRD_DRV_LO(lane)(0x1002 + 0x100 * lane) + +/* RX OVRD IN HI bits */ +#define RX_OVRD_IN_HI_RX_RESET_OVRDBIT(13) +#define RX_OVRD_IN_HI_RX_RX_RESET BIT(12) +#define RX_OVRD_IN_HI_RX_EQ_OVRD BIT(11) +#define RX_OVRD_IN_HI_RX_EQ_MASK 0x0700 +#define RX_OVRD_IN_HI_RX_EQ_SHIFT 8 +#define RX_OVRD_IN_HI_RX_EQ_EN_OVRDBIT(7) +#define RX_OVRD_IN_HI_RX_EQ_EN BIT(6) +#define RX_OVRD_IN_HI_RX_LOS_FILTER_OVRD BIT(5) +#define RX_OVRD_IN_HI_RX_LOS_FILTER_MASK 0x0018 +#define RX_OVRD_IN_HI_RX_RATE_OVRD BIT(2) +#define RX_OVRD_IN_HI_RX_RATE_MASK 0x0003 + +/* TX OVRD DRV LO register bits */ +#define TX_OVRD_DRV_LO_AMPLITUDE_MASK 0x007F +#define TX_OVRD_DRV_LO_PRE
Re: [PATCH v8 3/3] phy: Add Qualcomm DWC3 HS/SS PHY driver
Yay nitpicks!
On 09/12/14 10:29, Andy Gross wrote:
> +
> +struct qcom_dwc3_usb_phy {
> + void __iomem*base;
> + struct device *dev;
> + struct phy *phy;
Align with other members?
>
> +
> +static int wait_for_latch(void __iomem *addr)
> +{
> + u32 retry = 10;
Why not just int?
> +
> + while (true) {
> + if (!readl(addr))
> + break;
> +
> + if (--retry == 0)
> + return -ETIMEDOUT;
> +
> + usleep_range(10, 20);
> + }
> +
> + return 0;
> +}
[...]
> +
> +static int qcom_dwc3_ss_phy_init(struct qcom_dwc3_usb_phy *phy_dwc3)
> +{
> + u32 data = 0;
> +
Unnecessary initialization.
>
>
> +
> +static struct phy_ops qcom_dwc3_phy_ops = {
Can this be const?
> + .init = qcom_dwc3_phy_init,
> + .exit = qcom_dwc3_phy_exit,
> + .power_on = qcom_dwc3_phy_power_on,
> + .power_off = qcom_dwc3_phy_power_off,
> + .owner = THIS_MODULE,
> +};
> +
[...]
> +
> +static int qcom_dwc3_phy_probe(struct platform_device *pdev)
> +{
> + struct qcom_dwc3_usb_phy*phy_dwc3;
> + struct phy_provider *phy_provider;
> + struct resource *res;
> + const struct of_device_id *match;
> +
> +
Weird two newlines here.
> + phy_dwc3 = devm_kzalloc(&pdev->dev, sizeof(*phy_dwc3), GFP_KERNEL);
> + if (!phy_dwc3)
> + return -ENOMEM;
> +
>
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Re: [PATCH v8 3/3] phy: Add Qualcomm DWC3 HS/SS PHY driver
On Fri, Sep 12, 2014 at 12:50:23PM -0500, Josh Cartwright wrote:
> Hey Andy-
>
> Mostly cosmetic things below:
>
> On Fri, Sep 12, 2014 at 12:29:46PM -0500, Andy Gross wrote:
> > This patch adds a new driver for the Qualcomm USB 3.0 PHY that exists on
> > some
> > Qualcomm platforms. This driver uses the generic PHY framework and will
> > interact with the DWC3 controller.
> >
> > Signed-off-by: Andy Gross
> > ---
> > drivers/phy/Kconfig | 11 +
> > drivers/phy/Makefile|1 +
> > drivers/phy/phy-qcom-dwc3.c | 500
> > +++
> > 3 files changed, 512 insertions(+)
> > create mode 100644 drivers/phy/phy-qcom-dwc3.c
> >
> > diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> > index 0dd7427..5d56161 100644
> > --- a/drivers/phy/Kconfig
> > +++ b/drivers/phy/Kconfig
> > @@ -230,4 +230,15 @@ config PHY_XGENE
> > help
> > This option enables support for APM X-Gene SoC multi-purpose PHY.
> >
> > +config PHY_QCOM_DWC3
> > + tristate "QCOM DWC3 USB PHY support"
> > + depends on ARCH_QCOM
> > + depends on HAS_IOMEM
> > + depends on OF
> > + select GENERIC_PHY
> > + help
> > + This option enables support for the Synopsis PHYs present inside the
> > + Qualcomm USB3.0 DWC3 controller. This driver supports both HS and SS
> > + PHY controllers.
> > +
> > endmenu
> > diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> > index 95c69ed..aa16f30 100644
> > --- a/drivers/phy/Makefile
> > +++ b/drivers/phy/Makefile
> > @@ -28,3 +28,4 @@ obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) +=
> > phy-qcom-ipq806x-sata.o
> > obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
> > obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
> > obj-$(CONFIG_PHY_XGENE)+= phy-xgene.o
> > +obj-$(CONFIG_PHY_QCOM_DWC3)+= phy-qcom-dwc3.o
> > diff --git a/drivers/phy/phy-qcom-dwc3.c b/drivers/phy/phy-qcom-dwc3.c
> > new file mode 100644
> > index 000..05b8e1d
> > --- /dev/null
> > +++ b/drivers/phy/phy-qcom-dwc3.c
> [..]
> > +/* TX OVRD DRV LO register bits */
> > +#define TX_OVRD_DRV_LO_AMPLITUDE_MASK 0x007F
> > +#define TX_OVRD_DRV_LO_PREEMPH_MASK0x3F80
> > +#define TX_OVRD_DRV_LO_PREEMPH_SHIFT 7
> > +#define TX_OVRD_DRV_LO_EN BIT(14)
> > +
> > +struct qcom_dwc3_usb_phy;
>
> Do you need this?
No, this was a set of interim changes that should have been squashed.
Incidently, this was used when I had a separate ops table for the phys.
> > +
> > +enum qcom_dwc3_phy_id {
> > + QCOM_DWC3_PHY_UTMI = 0,
> > + QCOM_DWC3_PHY_PIPE,
> > + QCOM_DWC3_PHYS_NUM,
> > +};
> > +
> > +struct qcom_dwc3_usb_phy {
> > + void __iomem*base;
> > + struct device *dev;
> > + struct phy *phy;
> > + enum qcom_dwc3_phy_id index;
> > +
> > + struct clk *xo_clk;
> > + struct clk *ref_clk;
> > +};
> > +
> > +/**
> > + * Write register and read back masked value to confirm it is written
> > + *
> > + * @base - QCOM DWC3 PHY base virtual address.
> > + * @offset - register offset.
> > + * @mask - register bitmask specifying what should be updated
> > + * @val - value to write.
> > + */
> > +static inline void qcom_dwc3_phy_write_readback(
> > + struct qcom_dwc3_usb_phy *phy_dwc3, u32 offset,
> > + const u32 mask, u32 val)
> > +{
> > + u32 write_val, tmp = readl(phy_dwc3->base + offset);
> > +
> > + tmp &= ~mask; /* retain other bits */
> > + write_val = tmp | val;
> > +
> > + writel(write_val, phy_dwc3->base + offset);
> > +
> > + /* Read back to see if val was written */
> > + tmp = readl(phy_dwc3->base + offset);
> > + tmp &= mask;/* clear other bits */
> > +
> > + if (tmp != val)
> > + dev_err(phy_dwc3->dev, "write: %x to QSCRATCH: %x FAILED\n",
> > + val, offset);
> > +}
> > +
> > +static int wait_for_latch(void __iomem *addr)
> > +{
> > + u32 retry = 10;
> > +
> > + while (true) {
> > + if (!readl(addr))
> > + break;
> > +
> > + if (--retry == 0)
> > + return -ETIMEDOUT;
> > +
> > + usleep_range(10, 20);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +/**
> > + * Write SSPHY register
> > + *
> > + * @base - QCOM DWC3 PHY base virtual address.
> > + * @addr - SSPHY address to write.
> > + * @val - value to write.
> > + */
> > +static int qcom_dwc3_ss_write_phycreg(void __iomem *base, u32 addr, u32
> > val)
> > +{
> > + writel(addr, base + CR_PROTOCOL_DATA_IN_REG);
> > + writel(0x1, base + CR_PROTOCOL_CAP_ADDR_REG);
> > +
> > + if (wait_for_latch(base + CR_PROTOCOL_CAP_ADDR_REG))
> > + return 1;
>
> I'm not too familiar with the GENERIC_PHY infrastructure, does it
> understand that '1' is an error case? I'm wondering if you should
> instead propogate the -ETIMEDOUT up.
Actually, yeah I need to return something < 0. Let me respin to fix
Re: [PATCH v8 2/3] usb: dwc3: Add Qualcomm DWC3 glue layer driver
On Fri, Sep 12, 2014 at 12:47:04PM -0500, Felipe Balbi wrote:
> Hi,
>
> On Fri, Sep 12, 2014 at 12:29:45PM -0500, Andy Gross wrote:
> > From: "Ivan T. Ivanov"
> >
> > DWC3 glue layer is hardware layer around Synopsys DesignWare
> > USB3 core. Its purpose is to supply Synopsys IP with required
> > clocks, voltages and interface it with the rest of the SoC.
> >
> > Signed-off-by: Ivan T. Ivanov
> > Signed-off-by: Andy Gross
> > ---
> > drivers/usb/dwc3/Kconfig |9 +++
> > drivers/usb/dwc3/Makefile|1 +
> > drivers/usb/dwc3/dwc3-qcom.c | 133
> > ++
> > 3 files changed, 143 insertions(+)
> > create mode 100644 drivers/usb/dwc3/dwc3-qcom.c
> >
> > diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
> > index 785510a..e9f258e 100644
> > --- a/drivers/usb/dwc3/Kconfig
> > +++ b/drivers/usb/dwc3/Kconfig
> > @@ -80,6 +80,15 @@ config USB_DWC3_KEYSTONE
> > Support of USB2/3 functionality in TI Keystone2 platforms.
> > Say 'Y' or 'M' here if you have one such device
> >
> > +config USB_DWC3_QCOM
> > + tristate "Qualcomm Platforms"
> > + depends on ARCH_QCOM || COMPILE_TEST
> > + default USB_DWC3
> > + select PHY_QCOM_DWC3
>
> I would rather steer away from selecting the PHY as it prevents having
> PHYs as modules. Also, this will add a Kconfig warning for selecting a
> symbol that doesn't exist (yet).
True. The one downside is people having to fish around to find the phy config
option.
>
> If it's all the same with you, I can clean this up when applying.
>
Thats fine.
> > diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
> > new file mode 100644
> > index 000..2067c04
> > --- /dev/null
> > +++ b/drivers/usb/dwc3/dwc3-qcom.c
> > @@ -0,0 +1,133 @@
> > +/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 and
> > + * only version 2 as published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
> > +#include
>
> doesn't look like you need regulator/consumer.h and usb/phy.h. I can
> clean it up when applying.
Ack, interim changes that should have been removed. you can do that or I can
respin no big deal.
>
> > +struct dwc3_qcom {
> > + struct device *dev;
> > +
> > + struct clk *core_clk;
> > + struct clk *iface_clk;
> > + struct clk *sleep_clk;
> > +};
> > +
> > +static int dwc3_qcom_probe(struct platform_device *pdev)
> > +{
> > + struct device_node *node = pdev->dev.of_node;
> > + struct dwc3_qcom *qdwc;
> > + int ret = 0;
> > +
> > + qdwc = devm_kzalloc(&pdev->dev, sizeof(*qdwc), GFP_KERNEL);
> > + if (!qdwc)
> > + return -ENOMEM;
> > +
> > + platform_set_drvdata(pdev, qdwc);
> > +
> > + qdwc->dev = &pdev->dev;
> > +
> > + qdwc->core_clk = devm_clk_get(qdwc->dev, "core");
> > + if (IS_ERR(qdwc->core_clk)) {
> > + dev_dbg(qdwc->dev, "failed to get core clock\n");
>
> this one would be a dev_err() since core can't work without its clock. I
> can fix when applying.
Right. That's fine.
>
> --
> balbi
--
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Re: [PATCH v8 3/3] phy: Add Qualcomm DWC3 HS/SS PHY driver
Hey Andy-
Mostly cosmetic things below:
On Fri, Sep 12, 2014 at 12:29:46PM -0500, Andy Gross wrote:
> This patch adds a new driver for the Qualcomm USB 3.0 PHY that exists on some
> Qualcomm platforms. This driver uses the generic PHY framework and will
> interact with the DWC3 controller.
>
> Signed-off-by: Andy Gross
> ---
> drivers/phy/Kconfig | 11 +
> drivers/phy/Makefile|1 +
> drivers/phy/phy-qcom-dwc3.c | 500
> +++
> 3 files changed, 512 insertions(+)
> create mode 100644 drivers/phy/phy-qcom-dwc3.c
>
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 0dd7427..5d56161 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -230,4 +230,15 @@ config PHY_XGENE
> help
> This option enables support for APM X-Gene SoC multi-purpose PHY.
>
> +config PHY_QCOM_DWC3
> + tristate "QCOM DWC3 USB PHY support"
> + depends on ARCH_QCOM
> + depends on HAS_IOMEM
> + depends on OF
> + select GENERIC_PHY
> + help
> + This option enables support for the Synopsis PHYs present inside the
> + Qualcomm USB3.0 DWC3 controller. This driver supports both HS and SS
> + PHY controllers.
> +
> endmenu
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index 95c69ed..aa16f30 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -28,3 +28,4 @@ obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) +=
> phy-qcom-ipq806x-sata.o
> obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
> obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
> obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
> +obj-$(CONFIG_PHY_QCOM_DWC3) += phy-qcom-dwc3.o
> diff --git a/drivers/phy/phy-qcom-dwc3.c b/drivers/phy/phy-qcom-dwc3.c
> new file mode 100644
> index 000..05b8e1d
> --- /dev/null
> +++ b/drivers/phy/phy-qcom-dwc3.c
[..]
> +/* TX OVRD DRV LO register bits */
> +#define TX_OVRD_DRV_LO_AMPLITUDE_MASK0x007F
> +#define TX_OVRD_DRV_LO_PREEMPH_MASK 0x3F80
> +#define TX_OVRD_DRV_LO_PREEMPH_SHIFT 7
> +#define TX_OVRD_DRV_LO_ENBIT(14)
> +
> +struct qcom_dwc3_usb_phy;
Do you need this?
> +
> +enum qcom_dwc3_phy_id {
> + QCOM_DWC3_PHY_UTMI = 0,
> + QCOM_DWC3_PHY_PIPE,
> + QCOM_DWC3_PHYS_NUM,
> +};
> +
> +struct qcom_dwc3_usb_phy {
> + void __iomem*base;
> + struct device *dev;
> + struct phy *phy;
> + enum qcom_dwc3_phy_id index;
> +
> + struct clk *xo_clk;
> + struct clk *ref_clk;
> +};
> +
> +/**
> + * Write register and read back masked value to confirm it is written
> + *
> + * @base - QCOM DWC3 PHY base virtual address.
> + * @offset - register offset.
> + * @mask - register bitmask specifying what should be updated
> + * @val - value to write.
> + */
> +static inline void qcom_dwc3_phy_write_readback(
> + struct qcom_dwc3_usb_phy *phy_dwc3, u32 offset,
> + const u32 mask, u32 val)
> +{
> + u32 write_val, tmp = readl(phy_dwc3->base + offset);
> +
> + tmp &= ~mask; /* retain other bits */
> + write_val = tmp | val;
> +
> + writel(write_val, phy_dwc3->base + offset);
> +
> + /* Read back to see if val was written */
> + tmp = readl(phy_dwc3->base + offset);
> + tmp &= mask;/* clear other bits */
> +
> + if (tmp != val)
> + dev_err(phy_dwc3->dev, "write: %x to QSCRATCH: %x FAILED\n",
> + val, offset);
> +}
> +
> +static int wait_for_latch(void __iomem *addr)
> +{
> + u32 retry = 10;
> +
> + while (true) {
> + if (!readl(addr))
> + break;
> +
> + if (--retry == 0)
> + return -ETIMEDOUT;
> +
> + usleep_range(10, 20);
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * Write SSPHY register
> + *
> + * @base - QCOM DWC3 PHY base virtual address.
> + * @addr - SSPHY address to write.
> + * @val - value to write.
> + */
> +static int qcom_dwc3_ss_write_phycreg(void __iomem *base, u32 addr, u32 val)
> +{
> + writel(addr, base + CR_PROTOCOL_DATA_IN_REG);
> + writel(0x1, base + CR_PROTOCOL_CAP_ADDR_REG);
> +
> + if (wait_for_latch(base + CR_PROTOCOL_CAP_ADDR_REG))
> + return 1;
I'm not too familiar with the GENERIC_PHY infrastructure, does it
understand that '1' is an error case? I'm wondering if you should
instead propogate the -ETIMEDOUT up.
> +
> + writel(val, base + CR_PROTOCOL_DATA_IN_REG);
> + writel(0x1, base + CR_PROTOCOL_CAP_DATA_REG);
> +
> + if (wait_for_latch(base + CR_PROTOCOL_CAP_DATA_REG))
> + return 1;
> +
> + writel(0x1, base + CR_PROTOCOL_WRITE_REG);
> +
> + if (wait_for_latch(base + CR_PROTOCOL_WRITE_REG))
> + return 1;
> +
> + return 0;
> +}
> +
[..]
> +
> +static struct phy_ops qcom_dwc3_phy_ops = {
> + .init = qcom_dwc3_phy_init,
> + .exit = qcom_dwc3
Re: [PATCH v8 3/3] phy: Add Qualcomm DWC3 HS/SS PHY driver
Hi, On Fri, Sep 12, 2014 at 12:29:46PM -0500, Andy Gross wrote: > This patch adds a new driver for the Qualcomm USB 3.0 PHY that exists on some > Qualcomm platforms. This driver uses the generic PHY framework and will > interact with the DWC3 controller. > > Signed-off-by: Andy Gross Kishon, this looks good to my eyes. It has no direct dependency with dwc3 glue layer. Can you still grab this for v3.18 merge window ? Reviewed-by: Felipe Balbi Acked-by: Felipe Balbi cheers -- balbi signature.asc Description: Digital signature
Re: [PATCH v8 2/3] usb: dwc3: Add Qualcomm DWC3 glue layer driver
Hi,
On Fri, Sep 12, 2014 at 12:29:45PM -0500, Andy Gross wrote:
> From: "Ivan T. Ivanov"
>
> DWC3 glue layer is hardware layer around Synopsys DesignWare
> USB3 core. Its purpose is to supply Synopsys IP with required
> clocks, voltages and interface it with the rest of the SoC.
>
> Signed-off-by: Ivan T. Ivanov
> Signed-off-by: Andy Gross
> ---
> drivers/usb/dwc3/Kconfig |9 +++
> drivers/usb/dwc3/Makefile|1 +
> drivers/usb/dwc3/dwc3-qcom.c | 133
> ++
> 3 files changed, 143 insertions(+)
> create mode 100644 drivers/usb/dwc3/dwc3-qcom.c
>
> diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
> index 785510a..e9f258e 100644
> --- a/drivers/usb/dwc3/Kconfig
> +++ b/drivers/usb/dwc3/Kconfig
> @@ -80,6 +80,15 @@ config USB_DWC3_KEYSTONE
> Support of USB2/3 functionality in TI Keystone2 platforms.
> Say 'Y' or 'M' here if you have one such device
>
> +config USB_DWC3_QCOM
> + tristate "Qualcomm Platforms"
> + depends on ARCH_QCOM || COMPILE_TEST
> + default USB_DWC3
> + select PHY_QCOM_DWC3
I would rather steer away from selecting the PHY as it prevents having
PHYs as modules. Also, this will add a Kconfig warning for selecting a
symbol that doesn't exist (yet).
If it's all the same with you, I can clean this up when applying.
> diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
> new file mode 100644
> index 000..2067c04
> --- /dev/null
> +++ b/drivers/usb/dwc3/dwc3-qcom.c
> @@ -0,0 +1,133 @@
> +/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
doesn't look like you need regulator/consumer.h and usb/phy.h. I can
clean it up when applying.
> +struct dwc3_qcom {
> + struct device *dev;
> +
> + struct clk *core_clk;
> + struct clk *iface_clk;
> + struct clk *sleep_clk;
> +};
> +
> +static int dwc3_qcom_probe(struct platform_device *pdev)
> +{
> + struct device_node *node = pdev->dev.of_node;
> + struct dwc3_qcom *qdwc;
> + int ret = 0;
> +
> + qdwc = devm_kzalloc(&pdev->dev, sizeof(*qdwc), GFP_KERNEL);
> + if (!qdwc)
> + return -ENOMEM;
> +
> + platform_set_drvdata(pdev, qdwc);
> +
> + qdwc->dev = &pdev->dev;
> +
> + qdwc->core_clk = devm_clk_get(qdwc->dev, "core");
> + if (IS_ERR(qdwc->core_clk)) {
> + dev_dbg(qdwc->dev, "failed to get core clock\n");
this one would be a dev_err() since core can't work without its clock. I
can fix when applying.
--
balbi
signature.asc
Description: Digital signature
[PATCH v8 1/3] usb: dwc3: qcom: Add device tree binding
From: "Ivan T. Ivanov"
QCOM USB3.0 core wrapper consist of USB3.0 IP from Synopsys
(SNPS) and HS, SS PHY's control and configuration registers.
It could operate in device mode (SS, HS, FS) and host
mode (SS, HS, FS, LS).
Signed-off-by: Ivan T. Ivanov
Signed-off-by: Andy Gross
---
.../devicetree/bindings/phy/qcom-dwc3-usb-phy.txt | 39
.../devicetree/bindings/usb/qcom,dwc3.txt | 66
2 files changed, 105 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt
create mode 100644 Documentation/devicetree/bindings/usb/qcom,dwc3.txt
diff --git a/Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt
b/Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt
new file mode 100644
index 000..86f2dbe
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt
@@ -0,0 +1,39 @@
+Qualcomm DWC3 HS AND SS PHY CONTROLLER
+--
+
+DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer
+controllers. Each DWC3 PHY controller should have its own node.
+
+Required properties:
+- compatible: should contain one of the following:
+ - "qcom,dwc3-hs-usb-phy" for High Speed Synopsis PHY controller
+ - "qcom,dwc3-ss-usb-phy" for Super Speed Synopsis PHY controller
+- reg: offset and length of the DWC3 PHY controller register set
+- #phy-cells: must be zero
+- clocks: a list of phandles and clock-specifier pairs, one for each entry in
+ clock-names.
+- clock-names: Should contain "ref" for the PHY reference clock
+
+Optional clocks:
+ "xo" External reference clock
+
+Example:
+ phy@100f8800 {
+ compatible = "qcom,dwc3-hs-usb-phy";
+ reg = <0x100f8800 0x30>;
+ clocks = <&gcc USB30_0_UTMI_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+
+ status = "ok";
+ };
+
+ phy@100f8830 {
+ compatible = "qcom,dwc3-ss-usb-phy";
+ reg = <0x100f8830 0x30>;
+ clocks = <&gcc USB30_0_MASTER_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+
+ status = "ok";
+ };
diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
new file mode 100644
index 000..ca164e7
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.txt
@@ -0,0 +1,66 @@
+Qualcomm SuperSpeed DWC3 USB SoC controller
+
+Required properties:
+- compatible: should contain "qcom,dwc3"
+- clocks: A list of phandle + clock-specifier pairs for the
+ clocks listed in clock-names
+- clock-names: Should contain the following:
+ "core" Master/Core clock, have to be >= 125 MHz for SS
+ operation and >= 60MHz for HS operation
+
+Optional clocks:
+ "iface" System bus AXI clock. Not present on all platforms
+ "sleep" Sleep clock, used when USB3 core goes into low
+ power mode (U3).
+
+Required child node:
+A child node must exist to represent the core DWC3 IP block. The name of
+the node is not important. The content of the node is defined in dwc3.txt.
+
+Phy documentation is provided in the following places:
+Documentation/devicetree/bindings/phy/qcom,dwc3-usb-phy.txt
+
+Example device nodes:
+
+ hs_phy: phy@100f8800 {
+ compatible = "qcom,dwc3-hs-usb-phy";
+ reg = <0x100f8800 0x30>;
+ clocks = <&gcc USB30_0_UTMI_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+
+ status = "ok";
+ };
+
+ ss_phy: phy@100f8830 {
+ compatible = "qcom,dwc3-ss-usb-phy";
+ reg = <0x100f8830 0x30>;
+ clocks = <&gcc USB30_0_MASTER_CLK>;
+ clock-names = "ref";
+ #phy-cells = <0>;
+
+ status = "ok";
+ };
+
+ usb3_0: usb30@0 {
+ compatible = "qcom,dwc3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ clocks = <&gcc USB30_0_MASTER_CLK>;
+ clock-names = "core";
+
+ ranges;
+
+ status = "ok";
+
+ dwc3@1000 {
+ compatible = "snps,dwc3";
+ reg = <0x1000 0xcd00>;
+ interrupts = <0 205 0x4>;
+ phys = <&hs_phy>, <&ss_phy>;
+ phy-names = "usb2-phy", "u
[PATCH v8 2/3] usb: dwc3: Add Qualcomm DWC3 glue layer driver
From: "Ivan T. Ivanov"
DWC3 glue layer is hardware layer around Synopsys DesignWare
USB3 core. Its purpose is to supply Synopsys IP with required
clocks, voltages and interface it with the rest of the SoC.
Signed-off-by: Ivan T. Ivanov
Signed-off-by: Andy Gross
---
drivers/usb/dwc3/Kconfig |9 +++
drivers/usb/dwc3/Makefile|1 +
drivers/usb/dwc3/dwc3-qcom.c | 133 ++
3 files changed, 143 insertions(+)
create mode 100644 drivers/usb/dwc3/dwc3-qcom.c
diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
index 785510a..e9f258e 100644
--- a/drivers/usb/dwc3/Kconfig
+++ b/drivers/usb/dwc3/Kconfig
@@ -80,6 +80,15 @@ config USB_DWC3_KEYSTONE
Support of USB2/3 functionality in TI Keystone2 platforms.
Say 'Y' or 'M' here if you have one such device
+config USB_DWC3_QCOM
+ tristate "Qualcomm Platforms"
+ depends on ARCH_QCOM || COMPILE_TEST
+ default USB_DWC3
+ select PHY_QCOM_DWC3
+ help
+ Recent Qualcomm SoCs ship with one DesignWare Core USB3 IP inside,
+ say 'Y' or 'M' if you have one such device.
+
comment "Debugging features"
config USB_DWC3_DEBUG
diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile
index 10ac3e7..0da8e75 100644
--- a/drivers/usb/dwc3/Makefile
+++ b/drivers/usb/dwc3/Makefile
@@ -33,3 +33,4 @@ obj-$(CONFIG_USB_DWC3_OMAP) += dwc3-omap.o
obj-$(CONFIG_USB_DWC3_EXYNOS) += dwc3-exynos.o
obj-$(CONFIG_USB_DWC3_PCI) += dwc3-pci.o
obj-$(CONFIG_USB_DWC3_KEYSTONE)+= dwc3-keystone.o
+obj-$(CONFIG_USB_DWC3_QCOM)+= dwc3-qcom.o
diff --git a/drivers/usb/dwc3/dwc3-qcom.c b/drivers/usb/dwc3/dwc3-qcom.c
new file mode 100644
index 000..2067c04
--- /dev/null
+++ b/drivers/usb/dwc3/dwc3-qcom.c
@@ -0,0 +1,133 @@
+/* Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+struct dwc3_qcom {
+ struct device *dev;
+
+ struct clk *core_clk;
+ struct clk *iface_clk;
+ struct clk *sleep_clk;
+};
+
+static int dwc3_qcom_probe(struct platform_device *pdev)
+{
+ struct device_node *node = pdev->dev.of_node;
+ struct dwc3_qcom *qdwc;
+ int ret = 0;
+
+ qdwc = devm_kzalloc(&pdev->dev, sizeof(*qdwc), GFP_KERNEL);
+ if (!qdwc)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, qdwc);
+
+ qdwc->dev = &pdev->dev;
+
+ qdwc->core_clk = devm_clk_get(qdwc->dev, "core");
+ if (IS_ERR(qdwc->core_clk)) {
+ dev_dbg(qdwc->dev, "failed to get core clock\n");
+ return PTR_ERR(qdwc->core_clk);
+ }
+
+ qdwc->iface_clk = devm_clk_get(qdwc->dev, "iface");
+ if (IS_ERR(qdwc->iface_clk)) {
+ dev_dbg(qdwc->dev, "failed to get optional iface clock\n");
+ qdwc->iface_clk = NULL;
+ }
+
+ qdwc->sleep_clk = devm_clk_get(qdwc->dev, "sleep");
+ if (IS_ERR(qdwc->sleep_clk)) {
+ dev_dbg(qdwc->dev, "failed to get optional sleep clock\n");
+ qdwc->sleep_clk = NULL;
+ }
+
+ ret = clk_prepare_enable(qdwc->core_clk);
+ if (ret) {
+ dev_err(qdwc->dev, "failed to enable core clock\n");
+ goto err_core;
+ }
+
+ ret = clk_prepare_enable(qdwc->iface_clk);
+ if (ret) {
+ dev_err(qdwc->dev, "failed to enable optional iface clock\n");
+ goto err_iface;
+ }
+
+ ret = clk_prepare_enable(qdwc->sleep_clk);
+ if (ret) {
+ dev_err(qdwc->dev, "failed to enable optional sleep clock\n");
+ goto err_sleep;
+ }
+
+ ret = of_platform_populate(node, NULL, NULL, qdwc->dev);
+ if (ret) {
+ dev_err(qdwc->dev, "failed to register core - %d\n", ret);
+ goto err_clks;
+ }
+
+ return 0;
+
+err_clks:
+ clk_disable_unprepare(qdwc->sleep_clk);
+err_sleep:
+ clk_disable_unprepare(qdwc->iface_clk);
+err_iface:
+ clk_disable_unprepare(qdwc->core_clk);
+err_core:
+ return ret;
+}
+
+static int dwc3_qcom_remove(struct platform_device *pdev)
+{
+ struct dwc3_qcom *qdwc = platform_get_drvdata(pdev);
+
+ of_platform_depopulate(&pdev->dev);
+
+ clk_disable_unprepare(qdwc->sleep_clk);
+ clk_disable_unprepare(qd
[PATCH v8 0/3] DWC3 USB support for Qualcomm platform
These patches add basic support for USB3.0 controllers found on MSM platforms. USB3.0 core is based on Synopsys DesignWare SuperSpeed IP. This work was started by Ivan Ivanov and went through a number of iterations. I picked these patches up and did a little rework to get them working. Changes since v7: * Reworked phy driver to conform to the generic phy framework. * Collapsed HS and SS phy drivers into same source file. * Dropped regulators from the drivers. The only platform where we can utilize this driver has regulators on all the time. Will add regulators back in when they are required. * Added timeouts to the phy register accesses * Put in definitions for the phy specific registers and bitfields * Removed unnecessary workarounds. Changes since v6: * Renamed all MSM references to qcom, including file names * Removed direct TCSR manipulation. This done from new TCSR driver. * Added defines for register bits * XO clk is optional on some platforms. Corrected logic to handle this. * Ignore set_voltage failures. This allows us to support dummy regulators on platforms where there is no voltage control. * Reworked devicetree binding to remove TCSR reg resources Changes since v5: * devicetree bindings descriptions fixes * Fixed NULL pointer dereferences in dev_prink's * Removed extra space in "sleep " clock name Changes since v4: * Substitute references to "wc3" with just "dw" in USB PHY drivers and file names. This is to indicate that the PHY's are DesignWare, but not necessarily related to DWC3 IP core. Changes since v3: * Remove "_clk" suffix from clock names * Clarify required child node for qcom,dwc3 * Fix comments in functions headers * Use dbg instead err in drivers probe functions. Changes since v2: * Several improvements in devicetree bindings description * Disable regulators in glue layer if there is error during ioremap. Changes since first version: * Split devicetree bindings description file to separate patch * Address comments for device bindings description * Fix typo in 'gdsc' requlator name. Andy Gross (1): phy: Add Qualcomm DWC3 HS/SS PHY driver Ivan T. Ivanov (2): usb: dwc3: qcom: Add device tree binding usb: dwc3: Add Qualcomm DWC3 glue layer driver .../devicetree/bindings/phy/qcom-dwc3-usb-phy.txt | 39 ++ .../devicetree/bindings/usb/qcom,dwc3.txt | 66 +++ drivers/phy/Kconfig| 11 + drivers/phy/Makefile |1 + drivers/phy/phy-qcom-dwc3.c| 500 drivers/usb/dwc3/Kconfig |9 + drivers/usb/dwc3/Makefile |1 + drivers/usb/dwc3/dwc3-qcom.c | 133 ++ 8 files changed, 760 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt create mode 100644 Documentation/devicetree/bindings/usb/qcom,dwc3.txt create mode 100644 drivers/phy/phy-qcom-dwc3.c create mode 100644 drivers/usb/dwc3/dwc3-qcom.c -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v8 3/3] phy: Add Qualcomm DWC3 HS/SS PHY driver
This patch adds a new driver for the Qualcomm USB 3.0 PHY that exists on some Qualcomm platforms. This driver uses the generic PHY framework and will interact with the DWC3 controller. Signed-off-by: Andy Gross --- drivers/phy/Kconfig | 11 + drivers/phy/Makefile|1 + drivers/phy/phy-qcom-dwc3.c | 500 +++ 3 files changed, 512 insertions(+) create mode 100644 drivers/phy/phy-qcom-dwc3.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 0dd7427..5d56161 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -230,4 +230,15 @@ config PHY_XGENE help This option enables support for APM X-Gene SoC multi-purpose PHY. +config PHY_QCOM_DWC3 + tristate "QCOM DWC3 USB PHY support" + depends on ARCH_QCOM + depends on HAS_IOMEM + depends on OF + select GENERIC_PHY + help + This option enables support for the Synopsis PHYs present inside the + Qualcomm USB3.0 DWC3 controller. This driver supports both HS and SS + PHY controllers. + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 95c69ed..aa16f30 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -28,3 +28,4 @@ obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o obj-$(CONFIG_PHY_XGENE)+= phy-xgene.o +obj-$(CONFIG_PHY_QCOM_DWC3)+= phy-qcom-dwc3.o diff --git a/drivers/phy/phy-qcom-dwc3.c b/drivers/phy/phy-qcom-dwc3.c new file mode 100644 index 000..05b8e1d --- /dev/null +++ b/drivers/phy/phy-qcom-dwc3.c @@ -0,0 +1,500 @@ +/* Copyright (c) 2013-2014, Code Aurora Forum. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + * USB QSCRATCH Hardware registers + */ +#define QSCRATCH_GENERAL_CFG (0x08) +#define HSUSB_PHY_CTRL_REG (0x10) + +/* PHY_CTRL_REG */ +#define HSUSB_CTRL_DMSEHV_CLAMPBIT(24) +#define HSUSB_CTRL_USB2_SUSPENDBIT(23) +#define HSUSB_CTRL_UTMI_CLK_EN BIT(21) +#defineHSUSB_CTRL_UTMI_OTG_VBUS_VALID BIT(20) +#define HSUSB_CTRL_USE_CLKCORE BIT(18) +#define HSUSB_CTRL_DPSEHV_CLAMPBIT(17) +#define HSUSB_CTRL_COMMONONN BIT(11) +#define HSUSB_CTRL_ID_HV_CLAMP BIT(9) +#define HSUSB_CTRL_OTGSESSVLD_CLAMPBIT(8) +#define HSUSB_CTRL_CLAMP_ENBIT(7) +#define HSUSB_CTRL_RETENABLEN BIT(1) +#define HSUSB_CTRL_POR BIT(0) + +/* QSCRATCH_GENERAL_CFG */ +#define HSUSB_GCFG_XHCI_REVBIT(2) + +/** + * USB QSCRATCH Hardware registers + */ +#define SSUSB_PHY_CTRL_REG (0x00) +#define SSUSB_PHY_PARAM_CTRL_1 (0x04) +#define SSUSB_PHY_PARAM_CTRL_2 (0x08) +#define CR_PROTOCOL_DATA_IN_REG(0x0c) +#define CR_PROTOCOL_DATA_OUT_REG (0x10) +#define CR_PROTOCOL_CAP_ADDR_REG (0x14) +#define CR_PROTOCOL_CAP_DATA_REG (0x18) +#define CR_PROTOCOL_READ_REG (0x1c) +#define CR_PROTOCOL_WRITE_REG (0x20) + +/* PHY_CTRL_REG */ +#define SSUSB_CTRL_REF_USE_PAD BIT(28) +#define SSUSB_CTRL_TEST_POWERDOWN BIT(27) +#define SSUSB_CTRL_LANE0_PWR_PRESENT BIT(24) +#define SSUSB_CTRL_SS_PHY_EN BIT(8) +#define SSUSB_CTRL_SS_PHY_RESETBIT(7) + +/* SSPHY control registers */ +#define SSPHY_CTRL_RX_OVRD_IN_HI(lane) (0x1006 + 0x100 * lane) +#define SSPHY_CTRL_TX_OVRD_DRV_LO(lane)(0x1002 + 0x100 * lane) + +/* RX OVRD IN HI bits */ +#define RX_OVRD_IN_HI_RX_RESET_OVRDBIT(13) +#define RX_OVRD_IN_HI_RX_RX_RESET BIT(12) +#define RX_OVRD_IN_HI_RX_EQ_OVRD BIT(11) +#define RX_OVRD_IN_HI_RX_EQ_MASK 0x0700 +#define RX_OVRD_IN_HI_RX_EQ_SHIFT 8 +#define RX_OVRD_IN_HI_RX_EQ_EN_OVRDBIT(7) +#define RX_OVRD_IN_HI_RX_EQ_EN BIT(6) +#define RX_OVRD_IN_HI_RX_LOS_FILTER_OVRD BIT(5) +#define RX_OVRD_IN_HI_RX_LOS_FILTER_MASK 0x0018 +#define RX_OVRD_IN_HI_RX_RATE_OVRD BIT(2) +#define RX_OVRD_IN_HI_RX_RATE_MASK 0x0003 + +/* TX OVRD DRV LO register bits */ +#define TX_OVRD_DRV_LO_AMPLITUDE_MASK 0x007F +#define TX_OVRD
Re: [PATCH/RESEND] tty: serial: msm: Add DT based earlycon support
On 09/11/14 18:56, Rob Herring wrote:
> On Thu, Sep 11, 2014 at 5:14 PM, Stephen Boyd wrote:
>> Add support for DT based early console on platforms with the msm
>> serial hardware.
>>
>> Cc: Rob Herring
>> Signed-off-by: Stephen Boyd
> One comment, but looks good to me.
>
> Acked-by: Rob Herring
Thanks.
>> +static int __init
>> +msm_serial_early_console_setup(struct earlycon_device *device, const char
>> *opt)
>> +{
>> + if (!device->port.membase)
>> + return -ENODEV;
>> +
>> + device->con->write = msm_serial_early_write;
>> + return 0;
>> +}
>> +OF_EARLYCON_DECLARE(msm_serial, "qcom,msm-uart",
>> + msm_serial_early_console_setup);
> Don't you want to support kernel command line as well? Then if you
> can't change the DT or bootloader's command line, you can add it into
> the kernel build with the appended command line. Don't forget to
> document it in kernel-parameters.txt if you do.
>
>
Ok. Here's the interdiff. I'll send a v2.
---8<
diff --git a/Documentation/kernel-parameters.txt
b/Documentation/kernel-parameters.txt
index 5ae8608ca9f5..22302931e9d4 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -936,6 +936,18 @@ bytes respectively. Such letter suffixes can also be
entirely omitted.
must already be setup and configured. Options are not
yet supported.
+ msm_serial,
+ Start an early, polled-mode console on an msm serial
+ port at the specified address. The serial port
+ must already be setup and configured. Options are not
+ yet supported.
+
+ msm_serial_dm,
+ Start an early, polled-mode console on an msm serial
+ dm port at the specified address. The serial port
+ must already be setup and configured. Options are not
+ yet supported.
+
smh Use ARM semihosting calls for early console.
earlyprintk=[X86,SH,BLACKFIN,ARM,M68k]
diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
index d3881991e8d3..4b6c78331a64 100644
--- a/drivers/tty/serial/msm_serial.c
+++ b/drivers/tty/serial/msm_serial.c
@@ -976,6 +976,7 @@ msm_serial_early_console_setup(struct earlycon_device
*device, const char *opt)
device->con->write = msm_serial_early_write;
return 0;
}
+EARLYCON_DECLARE(msm_serial, msm_serial_early_console_setup);
OF_EARLYCON_DECLARE(msm_serial, "qcom,msm-uart",
msm_serial_early_console_setup);
@@ -997,6 +998,7 @@ msm_serial_early_console_setup_dm(struct earlycon_device
*device,
device->con->write = msm_serial_early_write_dm;
return 0;
}
+EARLYCON_DECLARE(msm_serial_dm, msm_serial_early_console_setup_dm);
OF_EARLYCON_DECLARE(msm_serial_dm, "qcom,msm-uartdm",
msm_serial_early_console_setup_dm);
--
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Re: kexec on APQ8074
2014-09-12 4:02 GMT+02:00 Wang, Yalin :
> What's your @memory parameters in your dtb file?
> And what's your PHYSICAL_OFFSET of your kexec kernel ?
TEXT_OFFSET is 0x8000;
Here's the content of the memory node:
memory {
#address-cells = <0x1>;
#size-cells = <0x1>;
device_type = "memory";
reg = <0x0 0x4000 0x4000 0x4000>;
secure_region {
linux,contiguous-region;
reg = <0x0 0xfc0>;
label = "secure_mem";
linux,phandle = <0x1b>;
phandle = <0x1b>;
};
adsp_region {
linux,contiguous-region;
reg = <0x0 0x2f0>;
label = "adsp_mem";
linux,phandle = <0x1c>;
phandle = <0x1c>;
};
qsecom_region {
linux,contiguous-region;
reg = <0x0 0x110>;
label = "qseecom_mem";
linux,phandle = <0x1d>;
phandle = <0x1d>;
};
};
Thanks a lot,
Noé
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[PATCH] rtc: pm8xxx: rework to support pm8941 rtc
Adds support for RTC device inside PM8941 PMIC. The RTC
in this PMIC have two register spaces. Thus the rtc-pm8xxx
is slightly reworked to reflect these differences.
The register set for different PMIC chips are selected
on DT compatible string base.
Signed-off-by: Stanimir Varbanov
---
drivers/rtc/Kconfig |2 +-
drivers/rtc/rtc-pm8xxx.c | 217 --
2 files changed, 134 insertions(+), 85 deletions(-)
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index a168e96..7dd323c 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -1283,7 +1283,7 @@ config RTC_DRV_LPC32XX
config RTC_DRV_PM8XXX
tristate "Qualcomm PMIC8XXX RTC"
- depends on MFD_PM8XXX
+ depends on MFD_PM8XXX || MFD_SPMI_PMIC
help
If you say yes here you get support for the
Qualcomm PMIC8XXX RTC.
diff --git a/drivers/rtc/rtc-pm8xxx.c b/drivers/rtc/rtc-pm8xxx.c
index 197699f..c30e9d9 100644
--- a/drivers/rtc/rtc-pm8xxx.c
+++ b/drivers/rtc/rtc-pm8xxx.c
@@ -27,21 +27,36 @@
/* RTC_CTRL register bit fields */
#define PM8xxx_RTC_ENABLE BIT(7)
-#define PM8xxx_RTC_ALARM_ENABLEBIT(1)
#define PM8xxx_RTC_ALARM_CLEAR BIT(0)
#define NUM_8_BIT_RTC_REGS 0x4
/**
+ * struct pm8xxx_rtc_regs - describe RTC registers per PMIC versions
+ * @ctrl: base address of control register
+ * @write: base address of write register
+ * @read: base address of read register
+ * @alarm_ctrl: base address of alarm control register
+ * @alarm_ctrl2: base address of alarm control2 register
+ * @alarm_rw: base address of alarm read-write register
+ * @alarm_en: alarm enable mask
+ */
+struct pm8xxx_rtc_regs {
+ unsigned int ctrl;
+ unsigned int write;
+ unsigned int read;
+ unsigned int alarm_ctrl;
+ unsigned int alarm_ctrl2;
+ unsigned int alarm_rw;
+ unsigned int alarm_en;
+};
+
+/**
* struct pm8xxx_rtc - rtc driver internal structure
* @rtc: rtc device for this driver.
* @regmap:regmap used to access RTC registers
* @allow_set_time:indicates whether writing to the RTC is allowed
* @rtc_alarm_irq: rtc alarm irq number.
- * @rtc_base: address of rtc control register.
- * @rtc_read_base: base address of read registers.
- * @rtc_write_base:base address of write registers.
- * @alarm_rw_base: base address of alarm registers.
* @ctrl_reg: rtc control register.
* @rtc_dev: device structure.
* @ctrl_reg_lock: spinlock protecting access to ctrl_reg.
@@ -51,11 +66,7 @@ struct pm8xxx_rtc {
struct regmap *regmap;
bool allow_set_time;
int rtc_alarm_irq;
- int rtc_base;
- int rtc_read_base;
- int rtc_write_base;
- int alarm_rw_base;
- u8 ctrl_reg;
+ const struct pm8xxx_rtc_regs *regs;
struct device *rtc_dev;
spinlock_t ctrl_reg_lock;
};
@@ -71,8 +82,10 @@ static int pm8xxx_rtc_set_time(struct device *dev, struct
rtc_time *tm)
{
int rc, i;
unsigned long secs, irq_flags;
- u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0, ctrl_reg;
+ u8 value[NUM_8_BIT_RTC_REGS], alarm_enabled = 0;
+ unsigned int ctrl_reg;
struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
+ const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
if (!rtc_dd->allow_set_time)
return -EACCES;
@@ -87,30 +100,32 @@ static int pm8xxx_rtc_set_time(struct device *dev, struct
rtc_time *tm)
dev_dbg(dev, "Seconds value to be written to RTC = %lu\n", secs);
spin_lock_irqsave(&rtc_dd->ctrl_reg_lock, irq_flags);
- ctrl_reg = rtc_dd->ctrl_reg;
- if (ctrl_reg & PM8xxx_RTC_ALARM_ENABLE) {
+ rc = regmap_read(rtc_dd->regmap, regs->ctrl, &ctrl_reg);
+ if (rc)
+ goto rtc_rw_fail;
+
+ if (ctrl_reg & regs->alarm_en) {
alarm_enabled = 1;
- ctrl_reg &= ~PM8xxx_RTC_ALARM_ENABLE;
- rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_base, ctrl_reg);
+ ctrl_reg &= ~regs->alarm_en;
+ rc = regmap_write(rtc_dd->regmap, regs->ctrl, ctrl_reg);
if (rc) {
dev_err(dev, "Write to RTC control register failed\n");
goto rtc_rw_fail;
}
- rtc_dd->ctrl_reg = ctrl_reg;
} else {
spin_unlock_irqrestore(&rtc_dd->ctrl_reg_lock, irq_flags);
}
/* Write 0 to Byte[0] */
- rc = regmap_write(rtc_dd->regmap, rtc_dd->rtc_write_base, 0);
+ rc = regmap_write(rtc_dd->regmap, regs->write, 0);
if (rc) {
dev_err(dev, "Write to RTC write data register failed\n");
goto rtc_rw_fail;
}
/* Write Byte[1], Byte[2], Byte[3] */
- rc = regmap_bulk_write(rtc_dd->regmap, rtc_dd->rtc_write_base + 1,
+ rc = r
