Re: [PATCH 5/9] clk: qcom: gcc-msm8960: add child devices support.

[Rajendra Nayak]

[]..

Also, I don't like having a subnode in DT. Why can't we use the
same node as the GCC node and create a virtual child device here
for tsens? We can assign the same of_node that this platform
device has so that DT keeps working correctly.


So the current driver looks up data based on compatible strings.


The tsens device is always the same piece of hardware. The only


Well, not always. The one in 8960 does need additional initializations,
requires you to save/restore context as it can be powered off
not being in an always powered on domain etc.


thing that's changing is the qfprom data and the number of
sensors. So we should be looking at the qfprom compatible string


How? Tsens uses nvmem framework apis to read the qfprom atleast
in this series.


to figure out how to interpret the qfprom data which would
include the number of sensors and how the data is encoded.


So you suggesting to create a virtual child device for gcc and
associate the gcc DT node to it? (And have the tsens compatible
mentioned as part of the gcc DT node?)


No. The driver should work just fine without having to
interrogate the device's compatible string. If we still need the
compatible check for some reason, then we can always match based
on qcom,gcc-msm8960, qcom,gcc-apq8064, etc. But I don't see why


Thats not quite possible I guess. 2 drivers (gcc and tsens) matching
the same compatibles? Will it not just depend on which ends up being
the first match?


we need to do that when we should be looking at what type of
qfprom is connected so we can correctly parse the data.

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Re: [PATCH v8 10/13] arm: dts: qcom: Add #power-domain-cells property

[Stephen Boyd]

On 08/12/2015 09:24 PM, Rajendra Nayak wrote:

On 08/11/2015 12:23 PM, Stephen Boyd wrote:

On 08/06, Rajendra Nayak wrote:

msm8974 has gcc and mmcc nodes, and apq8084 has a gcc node which
implement gdsc powerdomains. Add the #power-domain-cells property
to them.

Signed-off-by: Rajendra Nayak 
---


This needs to go through  Andy's tree and arm-soc. Also, I don't
see an update for the binding anywhere. Please update the binding
too.


Will do, I hope you mean update the bindings in qcom,mmcc.txt and
qcom,gcc.txt?


Yes.

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Re: [PATCH 5/9] clk: qcom: gcc-msm8960: add child devices support.

[Stephen Boyd]

On 08/12, Bjorn Andersson wrote:
> On Wed 12 Aug 14:57 PDT 2015, Stephen Boyd wrote:
> 
> > Here's the patch I'm suggesting. The device name is probably wrong, but 
> > you get the idea.
> 
> Looks very much like my take on it as well, I do however have concerns
> that suddenly the node called "clock-controller" will have to come with
> tsens related properties.
> 
> Are all the tsens-in-gcc blocks the same?

Yes they're all the same, except some of them have more sensors
than others. It depends on what SoC the hardware is instantiated
in. They also messed up the software interface and had to add
discontinuous registers for the sensors because it was never
designed to have more than 4 sensors or something like that. But
even that sort of change can be handled by figuring out the
format of the sensor data in the qfprom.

> Or do you intend to of_match
> on the gcc compatible in the tsens driver?
> 

I hope we don't have to of_match in the tsens driver on gcc
compatible strings.

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Re: [PATCH 5/9] clk: qcom: gcc-msm8960: add child devices support.

[Stephen Boyd]

On 08/13, Rajendra Nayak wrote:
> >On 11/08/15 23:49, Stephen Boyd wrote:
> >>On 07/08, Rajendra Nayak wrote:
> >>>diff --git a/drivers/clk/qcom/gcc-msm8960.c
> >>>b/drivers/clk/qcom/gcc-msm8960.c
> >>>index eb6a4f9..2c80d03 100644
> >>>--- a/drivers/clk/qcom/gcc-msm8960.c
> >>>+++ b/drivers/clk/qcom/gcc-msm8960.c
> >>>@@ -15,6 +15,7 @@
> >>>  #include 
> >>>  #include 
> >>>  #include 
> >>>+#include 
> >>>  #include 
> >>>  #include 
> >>>  #include 
> >>>@@ -3520,7 +3521,8 @@ static int gcc_msm8960_probe(struct
> >>>platform_device *pdev)
> >>>  if (IS_ERR(clk))
> >>>  return PTR_ERR(clk);
> >>>
> >>>-return qcom_cc_probe(pdev, match->data);
> >>>+qcom_cc_probe(pdev, match->data);
> >>>+return of_platform_populate(pdev->dev.of_node, NULL, NULL,
> >>>&pdev->dev);
> >>
> >>We just lost the error code from qcom_cc_probe()...
> >>
> >I think Rajendra picked up the wrong patch for this series, I did submit
> >a v2 (https://patches.linaro.org/44033/) with the above fixed.
> 
> ah, sorry about that.
> 
> >>Also, I don't like having a subnode in DT. Why can't we use the
> >>same node as the GCC node and create a virtual child device here
> >>for tsens? We can assign the same of_node that this platform
> >>device has so that DT keeps working correctly.
> 
> So the current driver looks up data based on compatible strings.

The tsens device is always the same piece of hardware. The only
thing that's changing is the qfprom data and the number of
sensors. So we should be looking at the qfprom compatible string
to figure out how to interpret the qfprom data which would
include the number of sensors and how the data is encoded.

> So you suggesting to create a virtual child device for gcc and
> associate the gcc DT node to it? (And have the tsens compatible
> mentioned as part of the gcc DT node?)

No. The driver should work just fine without having to
interrogate the device's compatible string. If we still need the
compatible check for some reason, then we can always match based
on qcom,gcc-msm8960, qcom,gcc-apq8064, etc. But I don't see why
we need to do that when we should be looking at what type of
qfprom is connected so we can correctly parse the data.

> How is this any different from creating a subnode in DT anyway?

The difference is we don't make up nodes to satisfy linux device
driver design. I suspect the hardware engineers put tsens inside
gcc because both blocks were written by the same person/team and
they just needed some place to jam some registers and call it a
day. That doesn't constitute an MFD or bus, which is what we
would be expressing in DT if we made a child node, it constitutes
a horrible software interface design that we have to live with.

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[PATCH] drm/msm/dsi: Introduce DSI configuration module

[Hai Li]

With more platforms supported, the DSI host
configuration array keeps expanding. This change
moves those to a separate dsi_cfg module.

Signed-off-by: Hai Li 
---
 drivers/gpu/drm/msm/Makefile   |   1 +
 drivers/gpu/drm/msm/dsi/dsi_cfg.c  |  92 ++
 drivers/gpu/drm/msm/dsi/dsi_cfg.h  |  44 +
 drivers/gpu/drm/msm/dsi/dsi_host.c | 186 -
 4 files changed, 177 insertions(+), 146 deletions(-)
 create mode 100644 drivers/gpu/drm/msm/dsi/dsi_cfg.c
 create mode 100644 drivers/gpu/drm/msm/dsi/dsi_cfg.h

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 89debc7..0a543eb 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -54,6 +54,7 @@ msm-$(CONFIG_DRM_MSM_FBDEV) += msm_fbdev.o
 msm-$(CONFIG_COMMON_CLK) += mdp/mdp4/mdp4_lvds_pll.o
 
 msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \
+   dsi/dsi_cfg.o \
dsi/dsi_host.o \
dsi/dsi_manager.o \
dsi/phy/dsi_phy.o \
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c 
b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
new file mode 100644
index 000..5872d5e
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2015, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include "dsi_cfg.h"
+
+/* DSI v2 has not been supported by now */
+static const struct msm_dsi_config dsi_v2_cfg = {
+   .io_offset = 0,
+};
+
+static const struct msm_dsi_config msm8974_apq8084_dsi_cfg = {
+   .io_offset = DSI_6G_REG_SHIFT,
+   .reg_cfg = {
+   .num = 4,
+   .regs = {
+   {"gdsc", -1, -1, -1, -1},
+   {"vdd", 300, 300, 15, 100},
+   {"vdda", 120, 120, 10, 100},
+   {"vddio", 180, 180, 10, 100},
+   },
+   },
+};
+
+static const struct msm_dsi_config msm8916_dsi_cfg = {
+   .io_offset = DSI_6G_REG_SHIFT,
+   .reg_cfg = {
+   .num = 4,
+   .regs = {
+   {"gdsc", -1, -1, -1, -1},
+   {"vdd", 285, 285, 10, 100},
+   {"vdda", 120, 120, 10, 100},
+   {"vddio", 180, 180, 10, 100},
+   },
+   },
+};
+
+static const struct msm_dsi_config msm8994_dsi_cfg = {
+   .io_offset = DSI_6G_REG_SHIFT,
+   .reg_cfg = {
+   .num = 7,
+   .regs = {
+   {"gdsc", -1, -1, -1, -1},
+   {"vdda", 125, 125, 10, 100},
+   {"vddio", 180, 180, 10, 100},
+   {"vcca", 100, 100, 1, 100},
+   {"vdd", 180, 180, 10, 100},
+   {"lab_reg", -1, -1, -1, -1},
+   {"ibb_reg", -1, -1, -1, -1},
+   },
+   }
+};
+
+static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = {
+   {MSM_DSI_VER_MAJOR_V2, U32_MAX, &dsi_v2_cfg},
+   {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_0,
+   &msm8974_apq8084_dsi_cfg},
+   {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_1,
+   &msm8974_apq8084_dsi_cfg},
+   {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_1_1,
+   &msm8974_apq8084_dsi_cfg},
+   {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_2,
+   &msm8974_apq8084_dsi_cfg},
+   {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3, &msm8994_dsi_cfg},
+   {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_3_1, &msm8916_dsi_cfg},
+};
+
+const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor)
+{
+   const struct msm_dsi_cfg_handler *cfg_hnd = NULL;
+   int i;
+
+   for (i = ARRAY_SIZE(dsi_cfg_handlers) - 1; i >= 0; i--) {
+   if ((dsi_cfg_handlers[i].major == major) &&
+   (dsi_cfg_handlers[i].minor == minor)) {
+   cfg_hnd = &dsi_cfg_handlers[i];
+   break;
+   }
+   }
+
+   return cfg_hnd;
+}
+
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h 
b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
new file mode 100644
index 000..4cf8872
--- /dev/null
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright 

[PATCH 2/5] drm/msm/dsi: Specify bitmask to set source PLL

[Hai Li]

The bit position to configure source PLL will change
on new types of PHYs. The caller should pass down
this information.

Signed-off-by: Hai Li 
---
 drivers/gpu/drm/msm/dsi/dsi_phy.c | 16 +++-
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_phy.c 
b/drivers/gpu/drm/msm/dsi/dsi_phy.c
index bd37e61..799201e 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_phy.c
@@ -157,17 +157,21 @@ fail:
return ret;
 }
 
-static void dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg)
+static void dsi_phy_set_src_pll(struct msm_dsi_phy *phy, int pll_id, u32 reg,
+   u32 bit_mask)
 {
int phy_id = phy->id;
+   u32 val;
 
if ((phy_id >= DSI_MAX) || (pll_id >= DSI_MAX))
return;
 
+   val = dsi_phy_read(phy->base + reg);
+
if (phy->cfg->src_pll_truthtable[phy_id][pll_id])
-   dsi_phy_write(phy->base + reg, 0x01);
+   dsi_phy_write(phy->base + reg, val | bit_mask);
else
-   dsi_phy_write(phy->base + reg, 0x00);
+   dsi_phy_write(phy->base + reg, val & (~bit_mask));
 }
 
 #define S_DIV_ROUND_UP(n, d)   \
@@ -389,7 +393,8 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int 
src_pll_id,
 
dsi_phy_write(base + REG_DSI_28nm_PHY_CTRL_0, 0x5f);
 
-   dsi_phy_set_src_pll(phy, src_pll_id, REG_DSI_28nm_PHY_GLBL_TEST_CTRL);
+   dsi_phy_set_src_pll(phy, src_pll_id, REG_DSI_28nm_PHY_GLBL_TEST_CTRL,
+   DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL);
 
return 0;
 }
@@ -451,7 +456,8 @@ static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy, int 
src_pll_id,
 
dsi_phy_write(base + REG_DSI_20nm_PHY_STRENGTH_0, 0xff);
 
-   dsi_phy_set_src_pll(phy, src_pll_id, REG_DSI_20nm_PHY_GLBL_TEST_CTRL);
+   dsi_phy_set_src_pll(phy, src_pll_id, REG_DSI_20nm_PHY_GLBL_TEST_CTRL,
+   DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL);
 
for (i = 0; i < 4; i++) {
dsi_phy_write(base + REG_DSI_20nm_PHY_LN_CFG_3(i),
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[PATCH 4/5] drm/msm/dsi: Split PHY drivers to separate files

[Hai Li]

This change moves each PHY type specific code into
separate files.

Signed-off-by: Hai Li 
---
 drivers/gpu/drm/msm/Makefile   |   6 +-
 drivers/gpu/drm/msm/dsi/dsi_phy.c  | 756 -
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c  | 448 +
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h  |  89 
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c | 150 ++
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 166 +++
 6 files changed, 857 insertions(+), 758 deletions(-)
 delete mode 100644 drivers/gpu/drm/msm/dsi/dsi_phy.c
 create mode 100644 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
 create mode 100644 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
 create mode 100644 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
 create mode 100644 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c

diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 14d167e..30f998a 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -1,5 +1,5 @@
 ccflags-y := -Iinclude/drm -Idrivers/gpu/drm/msm
-ccflags-$(CONFIG_DRM_MSM_DSI_PLL) += -Idrivers/gpu/drm/msm/dsi
+ccflags-$(CONFIG_DRM_MSM_DSI) += -Idrivers/gpu/drm/msm/dsi
 
 msm-y := \
adreno/adreno_device.o \
@@ -56,7 +56,9 @@ msm-$(CONFIG_COMMON_CLK) += mdp/mdp4/mdp4_lvds_pll.o
 msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \
dsi/dsi_host.o \
dsi/dsi_manager.o \
-   dsi/dsi_phy.o \
+   dsi/phy/dsi_phy.o \
+   dsi/phy/dsi_phy_20nm.o \
+   dsi/phy/dsi_phy_28nm.o \
mdp/mdp5/mdp5_cmd_encoder.o
 
 msm-$(CONFIG_DRM_MSM_DSI_PLL) += dsi/pll/dsi_pll.o \
diff --git a/drivers/gpu/drm/msm/dsi/dsi_phy.c 
b/drivers/gpu/drm/msm/dsi/dsi_phy.c
deleted file mode 100644
index 77f1efe..000
--- a/drivers/gpu/drm/msm/dsi/dsi_phy.c
+++ /dev/null
@@ -1,756 +0,0 @@
-/*
- * Copyright (c) 2015, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include 
-#include 
-
-#include "dsi.h"
-#include "dsi.xml.h"
-
-#define dsi_phy_read(offset) msm_readl((offset))
-#define dsi_phy_write(offset, data) msm_writel((data), (offset))
-
-struct dsi_phy_ops {
-   int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,
-   const unsigned long bit_rate, const unsigned long esc_rate);
-   void (*disable)(struct msm_dsi_phy *phy);
-};
-
-struct dsi_phy_cfg {
-   enum msm_dsi_phy_type type;
-   struct dsi_reg_config reg_cfg;
-   struct dsi_phy_ops ops;
-
-   /* Each cell {phy_id, pll_id} of the truth table indicates
-* if the source PLL is on the right side of the PHY.
-* Fill default H/W values in illegal cells, eg. cell {0, 1}.
-*/
-   bool src_pll_truthtable[DSI_MAX][DSI_MAX];
-};
-
-struct dsi_dphy_timing {
-   u32 clk_pre;
-   u32 clk_post;
-   u32 clk_zero;
-   u32 clk_trail;
-   u32 clk_prepare;
-   u32 hs_exit;
-   u32 hs_zero;
-   u32 hs_prepare;
-   u32 hs_trail;
-   u32 hs_rqst;
-   u32 ta_go;
-   u32 ta_sure;
-   u32 ta_get;
-};
-
-struct msm_dsi_phy {
-   struct platform_device *pdev;
-   void __iomem *base;
-   void __iomem *reg_base;
-   int id;
-
-   struct clk *ahb_clk;
-   struct regulator_bulk_data supplies[DSI_DEV_REGULATOR_MAX];
-
-   struct dsi_dphy_timing timing;
-   const struct dsi_phy_cfg *cfg;
-
-   bool regulator_ldo_mode;
-
-   struct msm_dsi_pll *pll;
-};
-
-static int dsi_phy_regulator_init(struct msm_dsi_phy *phy)
-{
-   struct regulator_bulk_data *s = phy->supplies;
-   const struct dsi_reg_entry *regs = phy->cfg->reg_cfg.regs;
-   struct device *dev = &phy->pdev->dev;
-   int num = phy->cfg->reg_cfg.num;
-   int i, ret;
-
-   for (i = 0; i < num; i++)
-   s[i].supply = regs[i].name;
-
-   ret = devm_regulator_bulk_get(&phy->pdev->dev, num, s);
-   if (ret < 0) {
-   dev_err(dev, "%s: failed to init regulator, ret=%d\n",
-   __func__, ret);
-   return ret;
-   }
-
-   for (i = 0; i < num; i++) {
-   if ((regs[i].min_voltage >= 0) && (regs[i].max_voltage >= 0)) {
-   ret = regulator_set_voltage(s[i].consumer,
-   regs[i].min_voltage, regs[i].max_voltage);
-   if (ret < 0) {
-   dev_err(dev,
-   "regulator 

[PATCH 3/5] drm/msm/dsi: Return void from msm_dsi_phy_disable()

[Hai Li]

We are not checking the return value from msm_dsi_phy_disable().
Change the return type to void.

Signed-off-by: Hai Li 
---
 drivers/gpu/drm/msm/dsi/dsi.h |  2 +-
 drivers/gpu/drm/msm/dsi/dsi_phy.c | 16 +---
 2 files changed, 6 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 09492bf..5f5a373 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -168,7 +168,7 @@ void msm_dsi_phy_driver_register(void);
 void msm_dsi_phy_driver_unregister(void);
 int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int src_pll_id,
const unsigned long bit_rate, const unsigned long esc_rate);
-int msm_dsi_phy_disable(struct msm_dsi_phy *phy);
+void msm_dsi_phy_disable(struct msm_dsi_phy *phy);
 void msm_dsi_phy_get_clk_pre_post(struct msm_dsi_phy *phy,
u32 *clk_pre, u32 *clk_post);
 struct msm_dsi_pll *msm_dsi_phy_get_pll(struct msm_dsi_phy *phy);
diff --git a/drivers/gpu/drm/msm/dsi/dsi_phy.c 
b/drivers/gpu/drm/msm/dsi/dsi_phy.c
index 799201e..77f1efe 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_phy.c
@@ -23,7 +23,7 @@
 struct dsi_phy_ops {
int (*enable)(struct msm_dsi_phy *phy, int src_pll_id,
const unsigned long bit_rate, const unsigned long esc_rate);
-   int (*disable)(struct msm_dsi_phy *phy);
+   void (*disable)(struct msm_dsi_phy *phy);
 };
 
 struct dsi_phy_cfg {
@@ -399,7 +399,7 @@ static int dsi_28nm_phy_enable(struct msm_dsi_phy *phy, int 
src_pll_id,
return 0;
 }
 
-static int dsi_28nm_phy_disable(struct msm_dsi_phy *phy)
+static void dsi_28nm_phy_disable(struct msm_dsi_phy *phy)
 {
dsi_phy_write(phy->base + REG_DSI_28nm_PHY_CTRL_0, 0);
dsi_28nm_phy_regulator_ctrl(phy, false);
@@ -409,8 +409,6 @@ static int dsi_28nm_phy_disable(struct msm_dsi_phy *phy)
 * ensure that the phy is completely disabled
 */
wmb();
-
-   return 0;
 }
 
 static void dsi_20nm_phy_regulator_ctrl(struct msm_dsi_phy *phy, bool enable)
@@ -515,12 +513,10 @@ static int dsi_20nm_phy_enable(struct msm_dsi_phy *phy, 
int src_pll_id,
return 0;
 }
 
-static int dsi_20nm_phy_disable(struct msm_dsi_phy *phy)
+static void dsi_20nm_phy_disable(struct msm_dsi_phy *phy)
 {
dsi_phy_write(phy->base + REG_DSI_20nm_PHY_CTRL_0, 0);
dsi_20nm_phy_regulator_ctrl(phy, false);
-
-   return 0;
 }
 
 static int dsi_phy_enable_resource(struct msm_dsi_phy *phy)
@@ -730,15 +726,13 @@ int msm_dsi_phy_enable(struct msm_dsi_phy *phy, int 
src_pll_id,
return phy->cfg->ops.enable(phy, src_pll_id, bit_rate, esc_rate);
 }
 
-int msm_dsi_phy_disable(struct msm_dsi_phy *phy)
+void msm_dsi_phy_disable(struct msm_dsi_phy *phy)
 {
if (!phy || !phy->cfg->ops.disable)
-   return -EINVAL;
+   return;
 
phy->cfg->ops.disable(phy);
dsi_phy_regulator_disable(phy);
-
-   return 0;
 }
 
 void msm_dsi_phy_get_clk_pre_post(struct msm_dsi_phy *phy,
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[PATCH 5/5] drm/msm/dsi: Make each PHY type compilation independent

[Hai Li]

On a certain platform, only one type of DSI PHY is used.
This change allows the user to only compile the PHY type
which is being used.

Signed-off-by: Hai Li 
---
 drivers/gpu/drm/msm/Kconfig   | 14 ++
 drivers/gpu/drm/msm/Makefile  | 11 +++
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c |  4 
 drivers/gpu/drm/msm/dsi/pll/dsi_pll.h |  8 
 4 files changed, 33 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index 331b291..8e6c7c6 100644
--- a/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@ -54,3 +54,17 @@ config DRM_MSM_DSI_PLL
help
  Choose this option to enable DSI PLL driver which provides DSI
  source clocks under common clock framework.
+
+config DRM_MSM_DSI_28NM_PHY
+   bool "Enable DSI 28nm PHY driver in MSM DRM"
+   depends on DRM_MSM_DSI
+   default y
+   help
+ Choose this option if the 28nm DSI PHY is used on the platform.
+
+config DRM_MSM_DSI_20NM_PHY
+   bool "Enable DSI 20nm PHY driver in MSM DRM"
+   depends on DRM_MSM_DSI
+   default y
+   help
+ Choose this option if the 20nm DSI PHY is used on the platform.
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 30f998a..89debc7 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -57,11 +57,14 @@ msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \
dsi/dsi_host.o \
dsi/dsi_manager.o \
dsi/phy/dsi_phy.o \
-   dsi/phy/dsi_phy_20nm.o \
-   dsi/phy/dsi_phy_28nm.o \
mdp/mdp5/mdp5_cmd_encoder.o
 
-msm-$(CONFIG_DRM_MSM_DSI_PLL) += dsi/pll/dsi_pll.o \
-   dsi/pll/dsi_pll_28nm.o
+msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/phy/dsi_phy_28nm.o
+msm-$(CONFIG_DRM_MSM_DSI_20NM_PHY) += dsi/phy/dsi_phy_20nm.o
+
+ifeq ($(CONFIG_DRM_MSM_DSI_PLL),y)
+msm-y += dsi/pll/dsi_pll.o
+msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/pll/dsi_pll_28nm.o
+endif
 
 obj-$(CONFIG_DRM_MSM)  += msm.o
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c 
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
index 828a94c..401ff58 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
@@ -267,12 +267,16 @@ static void dsi_phy_disable_resource(struct msm_dsi_phy 
*phy)
 }
 
 static const struct of_device_id dsi_phy_dt_match[] = {
+#ifdef CONFIG_DRM_MSM_DSI_28NM_PHY
{ .compatible = "qcom,dsi-phy-28nm-hpm",
  .data = &dsi_phy_28nm_hpm_cfgs },
{ .compatible = "qcom,dsi-phy-28nm-lp",
  .data = &dsi_phy_28nm_lp_cfgs },
+#endif
+#ifdef CONFIG_DRM_MSM_DSI_20NM_PHY
{ .compatible = "qcom,dsi-phy-20nm",
  .data = &dsi_phy_20nm_cfgs },
+#endif
{}
 };
 
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll.h 
b/drivers/gpu/drm/msm/dsi/pll/dsi_pll.h
index b69df19..063caa2 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll.h
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll.h
@@ -83,8 +83,16 @@ void msm_dsi_pll_helper_unregister_clks(struct 
platform_device *pdev,
 /*
  * Initialization for Each PLL Type
  */
+#ifdef CONFIG_DRM_MSM_DSI_28NM_PHY
 struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev,
enum msm_dsi_phy_type type, int id);
+#else
+static inline struct msm_dsi_pll *msm_dsi_pll_28nm_init(
+   struct platform_device *pdev, enum msm_dsi_phy_type type, int id)
+{
+   return ERR_PTR(-ENODEV);
+}
+#endif
 
 #endif /* __DSI_PLL_H__ */
 
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[PATCH 1/5] drm/msm/dsi: Update generated header file for DSI PHY

[Hai Li]

This change is to update DSI register definition changes
introduced by the following change:

rnndb/dsi: Add more bits for DSI PHY

More registers and bit fields are added for PHY timings
and bitclk source selection.

Signed-off-by: Hai Li 
---
 drivers/gpu/drm/msm/dsi/dsi.xml.h | 5 +
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h 
b/drivers/gpu/drm/msm/dsi/dsi.xml.h
index 0af0981..41c6376 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.xml.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h
@@ -440,6 +440,9 @@ static inline uint32_t DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(enum 
dsi_lane_swap val)
 #define REG_DSI_PHY_RESET  0x0128
 #define DSI_PHY_RESET_RESET0x0001
 
+#define REG_DSI_T_CLK_PRE_EXTEND   0x017c
+#define DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK  0x0001
+
 #define REG_DSI_RDBK_DATA_CTRL 0x01d0
 #define DSI_RDBK_DATA_CTRL_COUNT__MASK 0x00ff
 #define DSI_RDBK_DATA_CTRL_COUNT__SHIFT16
@@ -835,6 +838,7 @@ static inline uint32_t 
DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
 #define REG_DSI_28nm_PHY_BIST_CTRL_5   0x01c8
 
 #define REG_DSI_28nm_PHY_GLBL_TEST_CTRL
0x01d4
+#define DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL  0x0001
 
 #define REG_DSI_28nm_PHY_LDO_CNTRL 0x01dc
 
@@ -1161,6 +1165,7 @@ static inline uint32_t 
DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
 #define REG_DSI_20nm_PHY_BIST_CTRL_5   0x01c8
 
 #define REG_DSI_20nm_PHY_GLBL_TEST_CTRL
0x01d4
+#define DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL  0x0001
 
 #define REG_DSI_20nm_PHY_LDO_CNTRL 0x01dc
 
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[PATCH 0/5] drm/msm/dsi: Split different types of PHY drivers

[Hai Li]

The DSI PHY driver currently includes the implementation of all PHY types.
To support more types in the future, this patch series is moving each PHY
code into a separate file and making them compile independent. Some clean
up patches for DSI PHY are also included.

Hai Li (5):
  drm/msm/dsi: Update generated header file for DSI PHY
  drm/msm/dsi: Specify bitmask to set source PLL
  drm/msm/dsi: Return void from msm_dsi_phy_disable()
  drm/msm/dsi: Split PHY drivers to separate files
  drm/msm/dsi: Make each PHY type compilation independent

 drivers/gpu/drm/msm/Kconfig|  14 +
 drivers/gpu/drm/msm/Makefile   |  13 +-
 drivers/gpu/drm/msm/dsi/dsi.h  |   2 +-
 drivers/gpu/drm/msm/dsi/dsi.xml.h  |   5 +
 drivers/gpu/drm/msm/dsi/dsi_phy.c  | 756 -
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c  | 452 +
 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h  |  89 
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c | 150 ++
 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 166 +++
 drivers/gpu/drm/msm/dsi/pll/dsi_pll.h  |   8 +
 10 files changed, 894 insertions(+), 761 deletions(-)
 delete mode 100644 drivers/gpu/drm/msm/dsi/dsi_phy.c
 create mode 100644 drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
 create mode 100644 drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
 create mode 100644 drivers/gpu/drm/msm/dsi/phy/dsi_phy_20nm.c
 create mode 100644 drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c

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[PATCH] rnndb/dsi: Add more bits for DSI PHY

[Hai Li]

More registers and bit fields are added for PHY timings
and bitclk source selection.

Signed-off-by: Hai Li 
---
 rnndb/dsi/dsi.xml | 11 +--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/rnndb/dsi/dsi.xml b/rnndb/dsi/dsi.xml
index 02cfa3b..956f3ff 100644
--- a/rnndb/dsi/dsi.xml
+++ b/rnndb/dsi/dsi.xml
@@ -217,6 +217,9 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ 
rules-ng.xsd">



+   
+   
+   



@@ -437,7 +440,9 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ 
rules-ng.xsd">


 
-   
+   
+   
+   

 
 
@@ -608,7 +613,9 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ 
rules-ng.xsd">


 
-   
+   
+   
+   

 
 
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Re: [GIT PULL] qcom SoC changes for 4.3 *CORRECTED*

[Andy Gross]

On Thu, Aug 13, 2015 at 03:08:18PM +0200, Olof Johansson wrote:
> On Fri, Jul 31, 2015 at 04:47:55PM -0500, Andy Gross wrote:
> > The following changes since commit d770e558e21961ad6cfdf0ff7df0eb5d7d4f0754:
> > 
> >   Linux 4.2-rc1 (2015-07-05 11:01:52 -0700)
> > 
> > are available in the git repository at:
> > 
> >   git://codeaurora.org/quic/kernel/agross-msm.git tags/qcom-soc-for-4.3
> > 
> > for you to fetch changes up to ba68227e610cec8e0bef7da7e04af3f479d9797d:
> > 
> >   devicetree: soc: Add Qualcomm SMD based RPM DT binding (2015-07-29 
> > 14:13:48 -0500)
> > 
> > 
> > Qualcomm ARM Based SoC Updates for 4.3
> > 
> > * Add SMEM driver
> > * Add SMD driver
> > * Add RPM over SMD driver
> > * Select QCOM_SCM by default
> > 
> > 
> > Bjorn Andersson (5):
> >   soc: qcom: Add Shared Memory Manager driver
> >   soc: qcom: Add device tree binding for Shared Memory Device
> >   soc: qcom: Add Shared Memory Driver
> >   soc: qcom: Driver for the Qualcomm RPM over SMD
> >   devicetree: soc: Add Qualcomm SMD based RPM DT binding
> > 
> > Lina Iyer (1):
> >   drivers: qcom: Select QCOM_SCM unconditionally for QCOM_PM
> 
> Ok, after looking through it, I've decided to merge this branch.
> 
> I'm still concerned that we are picking up similar functionality without
> any shared implementation for a lot of platforms right now. At some
> point we'll have to say that enough is enough and someone will have to
> clean it up.
> 
> In the past, Linaro has done some of that work since several members have been
> affected. I don't know if this is the right time to kick something off though,
> or if we should let a few more implementations surface such that there is
> a better set of needed use cases to base a common framework on.

We can certainly discuss this at the coming Connect.  I'll bring this up then.

Thanks for pulling this in.

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Re: [PATCH RFC v2 0/2] hwspinlock: Introduce raw capability for hwspinlock_device

[Andy Gross]

On Thu, Aug 13, 2015 at 09:34:13AM +0300, Ohad Ben-Cohen wrote:
> On Wed, Jul 29, 2015 at 12:51 AM, Lina Iyer  wrote:
> >> Let's not make this more complicated than needed, so please add the
> >> hwcaps member to hwspinlock_device instead of to hwspinlock struct. We
> >> could always change this later if it proves to be insufficient.
> >>
> > But this could yield wrong locking scenarios. If banks are allowed RAW
> > capability and is not enforced on a per-lock basis, a driver may lock
> > using non-raw lock using the _raw API, while another driver may
> > 'acquire' the lock (since the value written to the lock would be the
> > same as raw api would). That is why you should have the capability on
> > hwspinlock and not on hwspinlock_device. Locks that are defined are RAW
> > capable should be used as RAW only.
> >
> > QCOM platform hwlock #7 is unique that different CPUs trying to acquire
> > the lock would write different values and hence would be fine. But, the
> > same is not true for other locks in the bank.
> 
> As far as I understand, there is nothing special about QCOM's hwlock
> #7 in terms of hardware. It's exactly the same lock as all the others.
> 
> The only difference in hwlock #7 is the way you use it, and that
> sounds like a decision the driver should be able to make. It's a
> policy, and I'm not sure we should put it in the DT. I'm also not sure
> we need this hwlock-specific complexity in the hwspinlock framework.

The issue in hardwiring this into the driver itself means forfeiting
extensibility.  So on one side (w/ raw support), we get the ability to deal with
the lock number changing.  On the other side (w/o raw), we'd have to probably
tie this to chip compat to figure out which lock is the 'special' if it ever
changes.

> 
> The driver already makes a decision whether to disable the interrupts
> or not and whether to save their state or not. So it can also make a
> decision whether to take a sw spinlock at all or not --- if the
> hardware allows it. and that if should be encoded in an accessible
> vendor specific (not hwlock specific) struct, which is setup by the
> underlying vendor specific hwspinlock driver (no DT involved).

It's arbitrary right now.  The remote processor selected a number, not the
processor running Linux.

> 
> Let's go over your aforementioned concerns:
> > But this could yield wrong locking scenarios. If banks are allowed RAW
> > capability and is not enforced on a per-lock basis, a driver may lock
> > using non-raw lock using the _raw API
> 
> If this is allowed by the hardware, then this is a valid scenario.
> There's no such thing a non-raw lock: a lock is raw if a raw
> functionality is required.
> 
> > while another driver may
> > 'acquire' the lock (since the value written to the lock would be the
> > same as raw api would).
> 
> Not sure I understand this one. If a lock has already been assigned to
> a driver, it cannot be re-assigned to another driver.
> 

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[PATCH v3 1/4] clk: qcom: Add MSM8916 iommu clocks

[Georgi Djakov]

Add support for the msm8916 TCU (Translation Control Unit) clocks that
are needed for IOMMU.

Signed-off-by: Georgi Djakov 
---
 drivers/clk/qcom/gcc-msm8916.c   |   48 ++
 include/dt-bindings/clock/qcom,gcc-msm8916.h |3 ++
 2 files changed, 51 insertions(+)

diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
index 3bf4fb3deef6..83b7df476453 100644
--- a/drivers/clk/qcom/gcc-msm8916.c
+++ b/drivers/clk/qcom/gcc-msm8916.c
@@ -2358,6 +2358,51 @@ static struct clk_branch gcc_sdcc2_apps_clk = {
},
 };
 
+static struct clk_rcg2 bimc_ddr_clk_src = {
+   .cmd_rcgr = 0x32004,
+   .hid_width = 5,
+   .parent_map = gcc_xo_gpll0_bimc_map,
+   .clkr.hw.init = &(struct clk_init_data){
+   .name = "bimc_ddr_clk_src",
+   .parent_names = gcc_xo_gpll0_bimc,
+   .num_parents = 3,
+   .ops = &clk_rcg2_ops,
+   .flags = CLK_GET_RATE_NOCACHE,
+   },
+};
+
+static struct clk_branch gcc_apss_tcu_clk = {
+   .halt_reg = 0x12018,
+   .clkr = {
+   .enable_reg = 0x4500c,
+   .enable_mask = BIT(1),
+   .hw.init = &(struct clk_init_data){
+   .name = "gcc_apss_tcu_clk",
+   .parent_names = (const char *[]){
+   "bimc_ddr_clk_src",
+   },
+   .num_parents = 1,
+   .ops = &clk_branch2_ops,
+   },
+   },
+};
+
+static struct clk_branch gcc_gfx_tcu_clk = {
+   .halt_reg = 0x12020,
+   .clkr = {
+   .enable_reg = 0x4500c,
+   .enable_mask = BIT(2),
+   .hw.init = &(struct clk_init_data){
+   .name = "gcc_gfx_tcu_clk",
+   .parent_names = (const char *[]){
+   "bimc_ddr_clk_src",
+   },
+   .num_parents = 1,
+   .ops = &clk_branch2_ops,
+   },
+   },
+};
+
 static struct clk_branch gcc_gtcu_ahb_clk = {
.halt_reg = 0x12044,
.clkr = {
@@ -2701,6 +2746,9 @@ static struct clk_regmap *gcc_msm8916_clocks[] = {
[GCC_VENUS0_AHB_CLK] = &gcc_venus0_ahb_clk.clkr,
[GCC_VENUS0_AXI_CLK] = &gcc_venus0_axi_clk.clkr,
[GCC_VENUS0_VCODEC0_CLK] = &gcc_venus0_vcodec0_clk.clkr,
+   [BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr,
+   [GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
+   [GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
 };
 
 static const struct qcom_reset_map gcc_msm8916_resets[] = {
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8916.h 
b/include/dt-bindings/clock/qcom,gcc-msm8916.h
index e430f644dd6c..53b39293d759 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8916.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8916.h
@@ -152,5 +152,8 @@
 #define GCC_VENUS0_AHB_CLK 135
 #define GCC_VENUS0_AXI_CLK 136
 #define GCC_VENUS0_VCODEC0_CLK 137
+#define BIMC_DDR_CLK_SRC   138
+#define GCC_APSS_TCU_CLK   139
+#define GCC_GFX_TCU_CLK140
 
 #endif
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[PATCH v3 4/4] clk: qcom: Add MSM8916 audio clocks

[Georgi Djakov]

Add support for the msm8916 audio clocks. This includes core bus,
low-power audio and codec clocks. They are required for audio playback.

Signed-off-by: Georgi Djakov 
---
 drivers/clk/qcom/gcc-msm8916.c   |  388 ++
 include/dt-bindings/clock/qcom,gcc-msm8916.h |   16 ++
 2 files changed, 404 insertions(+)

diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
index 9a3e3504502a..1290ee2dc66a 100644
--- a/drivers/clk/qcom/gcc-msm8916.c
+++ b/drivers/clk/qcom/gcc-msm8916.c
@@ -44,6 +44,9 @@ enum {
P_SLEEP_CLK,
P_DSI0_PHYPLL_BYTE,
P_DSI0_PHYPLL_DSI,
+   P_EXT_PRI_I2S,
+   P_EXT_SEC_I2S,
+   P_EXT_MCLK,
 };
 
 static const struct parent_map gcc_xo_gpll0_map[] = {
@@ -190,6 +193,76 @@ static const char * const gcc_xo_gpll0a_gpll1_gpll2[] = {
"gpll2_vote",
 };
 
+static const struct parent_map gcc_xo_gpll0_gpll1_sleep_map[] = {
+   { P_XO, 0 },
+   { P_GPLL0, 1 },
+   { P_GPLL1, 2 },
+   { P_SLEEP_CLK, 6 }
+};
+
+static const char * const gcc_xo_gpll0_gpll1_sleep[] = {
+   "xo",
+   "gpll0_vote",
+   "gpll1_vote",
+   "sleep_clk",
+};
+
+static const struct parent_map gcc_xo_gpll1_epi2s_emclk_sleep_map[] = {
+   { P_XO, 0 },
+   { P_GPLL1, 1 },
+   { P_EXT_PRI_I2S, 2 },
+   { P_EXT_MCLK, 3 },
+   { P_SLEEP_CLK, 6 }
+};
+
+static const char * const gcc_xo_gpll1_epi2s_emclk_sleep[] = {
+   "xo",
+   "gpll1_vote",
+   "ext_pri_i2s",
+   "ext_mclk",
+   "sleep_clk",
+};
+
+static const struct parent_map gcc_xo_gpll1_esi2s_emclk_sleep_map[] = {
+   { P_XO, 0 },
+   { P_GPLL1, 1 },
+   { P_EXT_SEC_I2S, 2 },
+   { P_EXT_MCLK, 3 },
+   { P_SLEEP_CLK, 6 }
+};
+
+static const char * const gcc_xo_gpll1_esi2s_emclk_sleep[] = {
+   "xo",
+   "gpll1_vote",
+   "ext_sec_i2s",
+   "ext_mclk",
+   "sleep_clk",
+};
+
+static const struct parent_map gcc_xo_sleep_map[] = {
+   { P_XO, 0 },
+   { P_SLEEP_CLK, 6 }
+};
+
+static const char * const gcc_xo_sleep[] = {
+   "xo",
+   "sleep_clk",
+};
+
+static const struct parent_map gcc_xo_gpll1_emclk_sleep_map[] = {
+   { P_XO, 0 },
+   { P_GPLL1, 1 },
+   { P_EXT_MCLK, 2 },
+   { P_SLEEP_CLK, 6 }
+};
+
+static const char * const gcc_xo_gpll1_emclk_sleep[] = {
+   "xo",
+   "gpll1_vote",
+   "ext_mclk",
+   "sleep_clk",
+};
+
 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
 
 static struct clk_pll gpll0 = {
@@ -1136,6 +1209,305 @@ static struct clk_rcg2 usb_hs_system_clk_src = {
},
 };
 
+static const struct freq_tbl ftbl_gcc_ultaudio_ahb_clk[] = {
+   F(320, P_XO, 6, 0, 0),
+   F(640, P_XO, 3, 0, 0),
+   F(960, P_XO, 2, 0, 0),
+   F(1920, P_XO, 1, 0, 0),
+   F(4000, P_GPLL0, 10, 1, 2),
+   F(6667, P_GPLL0, 12, 0, 0),
+   F(8000, P_GPLL0, 10, 0, 0),
+   F(1, P_GPLL0, 8, 0, 0),
+   { }
+};
+
+static struct clk_rcg2 ultaudio_ahbfabric_clk_src = {
+   .cmd_rcgr = 0x1c010,
+   .hid_width = 5,
+   .mnd_width = 8,
+   .parent_map = gcc_xo_gpll0_gpll1_sleep_map,
+   .freq_tbl = ftbl_gcc_ultaudio_ahb_clk,
+   .clkr.hw.init = &(struct clk_init_data){
+   .name = "ultaudio_ahbfabric_clk_src",
+   .parent_names = gcc_xo_gpll0_gpll1_sleep,
+   .num_parents = 4,
+   .ops = &clk_rcg2_ops,
+   },
+};
+
+static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_clk = {
+   .halt_reg = 0x1c028,
+   .clkr = {
+   .enable_reg = 0x1c028,
+   .enable_mask = BIT(0),
+   .hw.init = &(struct clk_init_data){
+   .name = "gcc_ultaudio_ahbfabric_ixfabric_clk",
+   .parent_names = (const char *[]){
+   "ultaudio_ahbfabric_clk_src",
+   },
+   .num_parents = 1,
+   .flags = CLK_SET_RATE_PARENT,
+   .ops = &clk_branch2_ops,
+   },
+   },
+};
+
+static struct clk_branch gcc_ultaudio_ahbfabric_ixfabric_lpm_clk = {
+   .halt_reg = 0x1c024,
+   .clkr = {
+   .enable_reg = 0x1c024,
+   .enable_mask = BIT(0),
+   .hw.init = &(struct clk_init_data){
+   .name = "gcc_ultaudio_ahbfabric_ixfabric_lpm_clk",
+   .parent_names = (const char *[]){
+   "ultaudio_ahbfabric_clk_src",
+   },
+   .num_parents = 1,
+   .flags = CLK_SET_RATE_PARENT,
+   .ops = &clk_branch2_ops,
+   },
+   },
+};
+
+static const struct freq_tbl ftbl_gcc_ultaudio_lpaif_i2s_clk[] = {
+   F(256000, P_XO, 5, 1, 15),
+   F(512000, P_XO, 5, 2, 15),
+   F(705600, P_GPLL1, 16, 1, 80),
+   F(768000, P_XO, 5, 1, 

[PATCH v3 3/4] clk: qcom: Add MSM8916 gpu clocks

[Georgi Djakov]

Add support for the msm8916 BIMC (Bus Integrated Memory Controller)
clocks that are needed for GPU.

Signed-off-by: Georgi Djakov 
---
 drivers/clk/qcom/gcc-msm8916.c   |   61 ++
 include/dt-bindings/clock/qcom,gcc-msm8916.h |3 ++
 2 files changed, 64 insertions(+)

diff --git a/drivers/clk/qcom/gcc-msm8916.c b/drivers/clk/qcom/gcc-msm8916.c
index 83b7df476453..9a3e3504502a 100644
--- a/drivers/clk/qcom/gcc-msm8916.c
+++ b/drivers/clk/qcom/gcc-msm8916.c
@@ -1094,6 +1094,30 @@ static struct clk_rcg2 apss_tcu_clk_src = {
},
 };
 
+static const struct freq_tbl ftbl_gcc_bimc_gpu_clk[] = {
+   F(1920, P_XO, 1, 0, 0),
+   F(1, P_GPLL0, 8, 0, 0),
+   F(2, P_GPLL0, 4, 0, 0),
+   F(26650, P_BIMC, 4, 0, 0),
+   F(4, P_GPLL0, 2, 0, 0),
+   F(53300, P_BIMC, 2, 0, 0),
+   { }
+};
+
+static struct clk_rcg2 bimc_gpu_clk_src = {
+   .cmd_rcgr = 0x31028,
+   .hid_width = 5,
+   .parent_map = gcc_xo_gpll0_bimc_map,
+   .freq_tbl = ftbl_gcc_bimc_gpu_clk,
+   .clkr.hw.init = &(struct clk_init_data){
+   .name = "bimc_gpu_clk_src",
+   .parent_names = gcc_xo_gpll0_bimc,
+   .num_parents = 3,
+   .flags = CLK_GET_RATE_NOCACHE,
+   .ops = &clk_rcg2_shared_ops,
+   },
+};
+
 static const struct freq_tbl ftbl_gcc_usb_hs_system_clk[] = {
F(8000, P_GPLL0, 10, 0, 0),
{ }
@@ -2420,6 +2444,40 @@ static struct clk_branch gcc_gtcu_ahb_clk = {
},
 };
 
+static struct clk_branch gcc_bimc_gfx_clk = {
+   .halt_reg = 0x31024,
+   .clkr = {
+   .enable_reg = 0x31024,
+   .enable_mask = BIT(0),
+   .hw.init = &(struct clk_init_data){
+   .name = "gcc_bimc_gfx_clk",
+   .parent_names = (const char *[]){
+   "bimc_gpu_clk_src",
+   },
+   .num_parents = 1,
+   .flags = CLK_SET_RATE_PARENT,
+   .ops = &clk_branch2_ops,
+   },
+   },
+};
+
+static struct clk_branch gcc_bimc_gpu_clk = {
+   .halt_reg = 0x31040,
+   .clkr = {
+   .enable_reg = 0x31040,
+   .enable_mask = BIT(0),
+   .hw.init = &(struct clk_init_data){
+   .name = "gcc_bimc_gpu_clk",
+   .parent_names = (const char *[]){
+   "bimc_gpu_clk_src",
+   },
+   .num_parents = 1,
+   .flags = CLK_SET_RATE_PARENT,
+   .ops = &clk_branch2_ops,
+   },
+   },
+};
+
 static struct clk_branch gcc_jpeg_tbu_clk = {
.halt_reg = 0x12034,
.clkr = {
@@ -2749,6 +2807,9 @@ static struct clk_regmap *gcc_msm8916_clocks[] = {
[BIMC_DDR_CLK_SRC] = &bimc_ddr_clk_src.clkr,
[GCC_APSS_TCU_CLK] = &gcc_apss_tcu_clk.clkr,
[GCC_GFX_TCU_CLK] = &gcc_gfx_tcu_clk.clkr,
+   [BIMC_GPU_CLK_SRC] = &bimc_gpu_clk_src.clkr,
+   [GCC_BIMC_GFX_CLK] = &gcc_bimc_gfx_clk.clkr,
+   [GCC_BIMC_GPU_CLK] = &gcc_bimc_gpu_clk.clkr,
 };
 
 static const struct qcom_reset_map gcc_msm8916_resets[] = {
diff --git a/include/dt-bindings/clock/qcom,gcc-msm8916.h 
b/include/dt-bindings/clock/qcom,gcc-msm8916.h
index 53b39293d759..d54a9715c37e 100644
--- a/include/dt-bindings/clock/qcom,gcc-msm8916.h
+++ b/include/dt-bindings/clock/qcom,gcc-msm8916.h
@@ -155,5 +155,8 @@
 #define BIMC_DDR_CLK_SRC   138
 #define GCC_APSS_TCU_CLK   139
 #define GCC_GFX_TCU_CLK140
+#define BIMC_GPU_CLK_SRC   141
+#define GCC_BIMC_GFX_CLK   142
+#define GCC_BIMC_GPU_CLK   143
 
 #endif
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[PATCH v3 0/5] Add support for more MSM8916 clocks

[Georgi Djakov]

This patchset adds support for the iommu, gpu and audio clocks on
the MSM8916 platforms.

Changes since v2 (https://lkml.org/lkml/2015/6/5/324)
* Dropped patch for read-only RCGs as it is not needed.
* Updated RCGs with shared branches patch and addressed various issues
  pointed by Stephen.
* Rebased on clk-next.

Changes since v1
* Added a set of ops for read-only RCGs and RCGs with shared branches.

Georgi Djakov (4):
  clk: qcom: Add MSM8916 iommu clocks
  clk: qcom: Add support for RCGs with shared branches
  clk: qcom: Add MSM8916 gpu clocks
  clk: qcom: Add MSM8916 audio clocks

 drivers/clk/qcom/clk-rcg.h   |4 +-
 drivers/clk/qcom/clk-rcg2.c  |   77 
 drivers/clk/qcom/gcc-msm8916.c   |  497 ++
 include/dt-bindings/clock/qcom,gcc-msm8916.h |   22 ++
 4 files changed, 599 insertions(+), 1 deletion(-)

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[PATCH v3 2/4] clk: qcom: Add support for RCGs with shared branches

[Georgi Djakov]

Some root clock generators may have child branches that are controlled
by different CPUs. These RCGs require some special operations:
 - some enable bits have to be toggled when we set the rate;
 - if RCG is disabled we only cache the rate and set it later when enabled;
 - when the RCG is disabled, the mux is set to the safe source;

Signed-off-by: Georgi Djakov 
---
 drivers/clk/qcom/clk-rcg.h  |4 ++-
 drivers/clk/qcom/clk-rcg2.c |   77 +++
 2 files changed, 80 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index 56028bb31d87..0693b9e0b15e 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -153,8 +153,8 @@ extern const struct clk_ops clk_dyn_rcg_ops;
  * @hid_width: number of bits in half integer divider
  * @parent_map: map from software's parent index to hardware's src_sel field
  * @freq_tbl: frequency table
+ * @current_freq: last cached frequency when using branches with shared RCGs
  * @clkr: regmap clock handle
- * @lock: register lock
  *
  */
 struct clk_rcg2 {
@@ -163,12 +163,14 @@ struct clk_rcg2 {
u8  hid_width;
const struct parent_map *parent_map;
const struct freq_tbl   *freq_tbl;
+   unsigned long   current_freq;
struct clk_regmap   clkr;
 };
 
 #define to_clk_rcg2(_hw) container_of(to_clk_regmap(_hw), struct clk_rcg2, 
clkr)
 
 extern const struct clk_ops clk_rcg2_ops;
+extern const struct clk_ops clk_rcg2_shared_ops;
 extern const struct clk_ops clk_edp_pixel_ops;
 extern const struct clk_ops clk_byte_ops;
 extern const struct clk_ops clk_pixel_ops;
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 9aec1761fd29..681faf2dcdc5 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -300,6 +300,83 @@ const struct clk_ops clk_rcg2_ops = {
 };
 EXPORT_SYMBOL_GPL(clk_rcg2_ops);
 
+static int clk_rcg2_shared_force_enable(struct clk_hw *hw, unsigned long rate)
+{
+   struct clk_rcg2 *rcg = to_clk_rcg2(hw);
+   const char *name = clk_hw_get_name(hw);
+   int ret, count;
+
+   /* force enable RCG */
+   ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
+CMD_ROOT_EN, CMD_ROOT_EN);
+   if (ret)
+   return ret;
+
+   /* wait for RCG to turn ON */
+   for (count = 500; count > 0; count--) {
+   ret = clk_rcg2_is_enabled(hw);
+   if (ret)
+   break;
+   udelay(1);
+   }
+   if (!count)
+   pr_err("%s: RCG did not turn on\n", name);
+
+   /* set clock rate */
+   ret = __clk_rcg2_set_rate(hw, rate);
+   if (ret)
+   return ret;
+
+   /* clear force enable RCG */
+   return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
+CMD_ROOT_EN, 0);
+}
+
+static int clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate,
+   unsigned long parent_rate)
+{
+   struct clk_rcg2 *rcg = to_clk_rcg2(hw);
+
+   /* cache the rate */
+   rcg->current_freq = rate;
+
+   if (!__clk_is_enabled(hw->clk))
+   return 0;
+
+   return clk_rcg2_shared_force_enable(hw, rcg->current_freq);
+}
+
+static int clk_rcg2_shared_enable(struct clk_hw *hw)
+{
+   struct clk_rcg2 *rcg = to_clk_rcg2(hw);
+   const char *name = clk_hw_get_name(hw);
+
+   if (!rcg->current_freq) {
+   pr_err("%s: Please set rate before enabling\n", name);
+   rcg->current_freq = rcg->freq_tbl[0].freq;
+   }
+
+   return clk_rcg2_shared_force_enable(hw, rcg->current_freq);
+}
+
+static void clk_rcg2_shared_disable(struct clk_hw *hw)
+{
+   struct clk_rcg2 *rcg = to_clk_rcg2(hw);
+
+   /* switch to XO, which is the lowest entry in the freq table */
+   clk_rcg2_shared_set_rate(hw, rcg->freq_tbl[0].freq, 0);
+}
+
+const struct clk_ops clk_rcg2_shared_ops = {
+   .enable = clk_rcg2_shared_enable,
+   .disable = clk_rcg2_shared_disable,
+   .get_parent = clk_rcg2_get_parent,
+   .recalc_rate = clk_rcg2_recalc_rate,
+   .determine_rate = clk_rcg2_determine_rate,
+   .set_rate = clk_rcg2_shared_set_rate,
+};
+EXPORT_SYMBOL_GPL(clk_rcg2_shared_ops);
+
 struct frac_entry {
int num;
int den;
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Re: [GIT PULL] qcom SoC changes for 4.3 *CORRECTED*

[Olof Johansson]

On Fri, Jul 31, 2015 at 04:47:55PM -0500, Andy Gross wrote:
> The following changes since commit d770e558e21961ad6cfdf0ff7df0eb5d7d4f0754:
> 
>   Linux 4.2-rc1 (2015-07-05 11:01:52 -0700)
> 
> are available in the git repository at:
> 
>   git://codeaurora.org/quic/kernel/agross-msm.git tags/qcom-soc-for-4.3
> 
> for you to fetch changes up to ba68227e610cec8e0bef7da7e04af3f479d9797d:
> 
>   devicetree: soc: Add Qualcomm SMD based RPM DT binding (2015-07-29 14:13:48 
> -0500)
> 
> 
> Qualcomm ARM Based SoC Updates for 4.3
> 
> * Add SMEM driver
> * Add SMD driver
> * Add RPM over SMD driver
> * Select QCOM_SCM by default
> 
> 
> Bjorn Andersson (5):
>   soc: qcom: Add Shared Memory Manager driver
>   soc: qcom: Add device tree binding for Shared Memory Device
>   soc: qcom: Add Shared Memory Driver
>   soc: qcom: Driver for the Qualcomm RPM over SMD
>   devicetree: soc: Add Qualcomm SMD based RPM DT binding
> 
> Lina Iyer (1):
>   drivers: qcom: Select QCOM_SCM unconditionally for QCOM_PM

Ok, after looking through it, I've decided to merge this branch.

I'm still concerned that we are picking up similar functionality without
any shared implementation for a lot of platforms right now. At some
point we'll have to say that enough is enough and someone will have to
clean it up.

In the past, Linaro has done some of that work since several members have been
affected. I don't know if this is the right time to kick something off though,
or if we should let a few more implementations surface such that there is
a better set of needed use cases to base a common framework on.


-Olof

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RE: [PATCH 3/5] iommu/msm: Add support for generic master bindings

[Sricharan]

Hi Stephen,

> -Original Message-
> From: Stephen Boyd [mailto:sb...@codeaurora.org]
> Sent: Thursday, August 13, 2015 12:42 AM
> To: Sricharan R
> Cc: linux-arm-ker...@lists.infradead.org;
io...@lists.linux-foundation.org;
> devicet...@vger.kernel.org; linux-arm-msm@vger.kernel.org;
> robin.mur...@arm.com; robdcl...@gmail.com; j...@8bytes.org;
> srinivas.kandaga...@linaro.org; laurent.pinch...@ideasonboard.com;
> will.dea...@arm.com; step...@codeaurora.org; tred...@nvidia.com
> Subject: Re: [PATCH 3/5] iommu/msm: Add support for generic master
> bindings
> 
> On 08/12/2015 07:47 AM, Sricharan R wrote:
> > @@ -702,6 +703,44 @@ static void print_ctx_regs(void __iomem *base,
> int ctx)
> >GET_PRRR(base, ctx), GET_NMRR(base, ctx));
> >   }
> >
> > +static void insert_iommu_master(struct device *dev,
> > +   struct msm_iommu_dev *iommu,
> > +   struct of_phandle_args *spec)
> > +{
> > +   struct msm_iommu_ctx_dev *master;
> > +   int sid;
> > +
> > +   master = kzalloc(sizeof(*master), GFP_KERNEL);
> 
> This is called with irqs disabled, but it's not GFP_ATOMIC. Please test
with
> DEBUG_ATOMIC_SLEEP=y.

Ok. I will have to adjust the locking here. It should be granular only
for the list manipulation.
> 
> > +   master->of_node = dev->of_node;
> > +   list_add(&master->list, &iommu->ctx_list);
> > +
> > +   for (sid = 0; sid < spec->args_count; sid++)
> > +   master->mids[sid] = spec->args[sid];
> > +
> > +   master->num_mids = spec->args_count; }
> > +
> > +static int qcom_iommu_of_xlate(struct device *dev,
> > +  struct of_phandle_args *spec) {
> > +   struct msm_iommu_dev *iommu;
> > +   unsigned long flags;
> > +
> > +   spin_lock_irqsave(&msm_iommu_lock, flags);
> > +   list_for_each_entry(iommu, &qcom_iommu_devices, dev_node) {
> > +   if (iommu->dev->of_node == spec->np)
> > +   break;
> > +   }
> 
> The braces are unnecessary here.
 Ok, will remove this.
> 
> > +
> > +   if (!iommu || (iommu->dev->of_node != spec->np))
> 
> Please remove extraneous parentheses.
> 
 Ok.

> > +   return -ENODEV;
> > +
> > +   insert_iommu_master(dev, iommu, spec);
> > +   spin_unlock_irqrestore(&msm_iommu_lock, flags);
> > +
> > +   return 0;
> > +}
> > +
> >   irqreturn_t msm_iommu_fault_handler(int irq, void *dev_id)
> >   {
> > struct msm_iommu_dev *iommu = dev_id; @@ -737,7 +776,7 @@
> fail:
> > return 0;
> >   }
> >
> > -static const struct iommu_ops msm_iommu_ops = {
> > +static struct iommu_ops msm_iommu_ops = {
> 
> Is there a reason why we can't make of_iommu_set_ops() take a const ops
> pointer?
> 
  Hmm right. of_iommu_set_ops is the one that needs change. I will add a
separate
  patch to correct that.

Regards,
 Sricharan

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