Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
On Tuesday 24 November 2015 17:51:37 Stephen Boyd wrote:
> On 11/24, Arnd Bergmann wrote:
> > On Monday 23 November 2015 15:13:52 Stephen Boyd wrote:
> > IOW, anything with CPU implementer 0x56 part 0x581 should use those,
> > while part 0x584 can use the sdiv/udiv that it reports correctly.
> >
>
> It looks like we have some sort of function that mostly does
> this, except it doesn't differentiate on that lower bit for 1 vs
> 4. I guess I'll write another one for that.
>
> static inline int cpu_is_pj4(void)
> {
> unsigned int id;
>
> id = read_cpuid_id();
> if ((id & 0xff0fff00) == 0x560f5800)
> return 1;
>
> return 0;
> }
Correct, thanks.
Arnd
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Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
On 11/24, Arnd Bergmann wrote:
> On Monday 23 November 2015 15:13:52 Stephen Boyd wrote:
> > On 11/23, Arnd Bergmann wrote:
> > >
> > > - PJ4/PJ4B (not PJ4B-MP) has a different custom opcode for udiv and sdiv
> > > in ARM mode. We don't support that with true multiplatform kernels
> > > because those opcodes work nowhere else, though with your proposed
> > > series we could easily do that for dynamic patching.
> >
> > Do you have the information on these custom opcodes? I can work
> > that into the patches assuming the MIDR is different.
>
> Thomas Petazzoni said this in a private mail:
>
> | According to the datasheet, the PJ4B has integer signed and unsigned
> | divide, similar to the sdiv and udiv ARM instructions. But the way to
> | access it is by doing a MRC instruction.
> |
> |MRC p6, 1, Rd , CRn , CRm, 4
> |
> |for PJ4B is the same as:
> |
> |SDIV Rd , Rn, Rm
> |
> | on ARM cores.
> |
> |And:
> |
> |MRC p6, 1, Rd , CRn , CRm, 0
> |
> |for PJ4B is the same as:
> |
> |UDIV Rd , Rn, Rm
> |
> |on ARM cores.
> |
> |This is documented in the "Extended instructions" section of the
> |PJ4B datasheet.
>
> I assume what he meant was that this is true for both PJ4 and PJ4B
> but not for PJ4B-MP, which has the normal udiv/sdiv instructions.
>
> IOW, anything with CPU implementer 0x56 part 0x581 should use those,
> while part 0x584 can use the sdiv/udiv that it reports correctly.
>
It looks like we have some sort of function that mostly does
this, except it doesn't differentiate on that lower bit for 1 vs
4. I guess I'll write another one for that.
static inline int cpu_is_pj4(void)
{
unsigned int id;
id = read_cpuid_id();
if ((id & 0xff0fff00) == 0x560f5800)
return 1;
return 0;
}
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Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
On Tuesday 24 November 2015 20:35:16 Russell King - ARM Linux wrote:
> We'd need to do something similar for v7VE as well. As we're getting
> more of this, I'd suggest we move to:
>
> arch-v7a-y =$(call
> cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a)
> arch-v7a-$(CONFIG_CPU_32v7VE) =... whatever it was...
> arch-$(CONFIG_CPU_32v7) =-D__LINUX_ARM_ARCH__=7 $(arch-v7a-y)
> arch-v6-y =$(call cc-option,-march=armv6,-march=armv5t
> -Wa$(comma)-march=armv6)
> arch-v6-$(CONFIG_CPU_32v6K) =$(call cc-option,-march=armv6k,-march=armv5t
> -Wa$(comma)-march=armv6k)
> arch-$(CONFIG_CPU_32v6) =-D__LINUX_ARM_ARCH__=6 $(arch-v6-y)
I would argue that V7VE is different from V6K here: The instructions
that are added in V6K compared to V6 are not generated by gcc but
are typically used in assembly like
static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int
size)
{
...
#ifndef CONFIG_CPU_V6
asm volatile(...); /* v6k specific instruction */
#endif
}
while the logic in your example above would break normal v7 support when
both V7 and V7VE are enabled.
> > My understanding is that we want to support CPU_V7VE without
> > CPU_V7 enabled so that it uses the idiv instructions in that
> > configuration. When V7VE and V7 are both enabled, we should
> > degrade to the aeabi functions, and the same is true for when
> > V7VE is disabled.
>
> Let me have another look at this, it's been a while since I touched these
> options...
There is one idea that I've had in the back of my mind for a long
while, and probably mentioned on the list before:
We could decide to simplify the CPU architecture selection for
multiplatform a lot if we turn the somewhat overengineered ARCH_MULTI_*
options into a choice statement, where each of them implies the
higher architecture levels. That way we can linearize
ARMv6/v6k/v7/v7VE/v8/v8.1 so that you just pick which platforms you
want to see by selecting the minimum level, and all higher ones will
automatically be available (for v8 and v8.1 that means just MACH_VIRT,
as we don't really want to run 32-bit kernels on bare metal v8-A
machines).
That way, we can have LPAE and -march=armv7ve support depend on
CONFIG_ARCH_MULTI_V7VE, which would imply that we don't support
CPU_V7 based platforms.
Arnd
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Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
On Tue, Nov 24, 2015 at 12:07:30PM -0800, Stephen Boyd wrote: > Ok. Presumably the order of arch-$(CONFIG) lines in the Makefile > are done in an order to allow the build to degrade to the lowest > common denominator among architecture support. Correct. Make processes the directives in the order listed in the makefile, which means that a variable final value results from its last assignment. > CPU_V7 selects > CPU_32v7 and we're using that config to select -march=armv7-a in > the Makefile. The patch currently uses CPU_32v7VE to select > -march=armv7ve. If CPU_V7VE selects CPU_V7 we'll never be able to > use -march=armv7ve because CPU_V7 will be selecting CPU_32v7 and > that will come after CPU_32v7VE in the Makefile. Right, but look at how the V6K stuff is handled: arch-$(CONFIG_CPU_32v6) =-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6) # Only override the compiler option if ARMv6. The ARMv6K extensions are # always available in ARMv7 ifeq ($(CONFIG_CPU_32v6),y) arch-$(CONFIG_CPU_32v6K)=-D__LINUX_ARM_ARCH__=6 $(call cc-option,-march=armv6k,-march=armv5t -Wa$(comma)-march=armv6k) endif We'd need to do something similar for v7VE as well. As we're getting more of this, I'd suggest we move to: arch-v7a-y =$(call cc-option,-march=armv7-a,-march=armv5t -Wa$(comma)-march=armv7-a) arch-v7a-$(CONFIG_CPU_32v7VE) =... whatever it was... arch-$(CONFIG_CPU_32v7) =-D__LINUX_ARM_ARCH__=7 $(arch-v7a-y) arch-v6-y =$(call cc-option,-march=armv6,-march=armv5t -Wa$(comma)-march=armv6) arch-v6-$(CONFIG_CPU_32v6K) =$(call cc-option,-march=armv6k,-march=armv5t -Wa$(comma)-march=armv6k) arch-$(CONFIG_CPU_32v6) =-D__LINUX_ARM_ARCH__=6 $(arch-v6-y) > My understanding is that we want to support CPU_V7VE without > CPU_V7 enabled so that it uses the idiv instructions in that > configuration. When V7VE and V7 are both enabled, we should > degrade to the aeabi functions, and the same is true for when > V7VE is disabled. Let me have another look at this, it's been a while since I touched these options... -- FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up according to speedtest.net. -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
On 11/24, Russell King - ARM Linux wrote: > On Tue, Nov 24, 2015 at 12:53:49AM -0800, Stephen Boyd wrote: > > > > And adding CPU_V7VE causes a cascade of changes to wherever > > CPU_V7 is being used today. Here's the patch I currently have, > > without the platform changes: > > @@ -1069,7 +1075,7 @@ config ARM_ERRATA_411920 > > > > config ARM_ERRATA_430973 > > bool "ARM errata: Stale prediction on replaced interworking branch" > > - depends on CPU_V7 > > + depends on CPU_V7 || CPU_V7VE > > NAK on all this. The fact that you're having to add CPU_V7VE at all > sites which have CPU_V7 shows that this is a totally broken way of > approaching this. > > Make CPU_V7VE be an _add-on_ to CPU_V7. In other words, when CPU_V7VE > is enabled, CPU_V7 should also be enabled, just like we do for CPU_V6K. > > Note that v7M is different because that's not an add-on feature, it's > a different CPU class from (what should be) v7A. > Ok. Presumably the order of arch-$(CONFIG) lines in the Makefile are done in an order to allow the build to degrade to the lowest common denominator among architecture support. CPU_V7 selects CPU_32v7 and we're using that config to select -march=armv7-a in the Makefile. The patch currently uses CPU_32v7VE to select -march=armv7ve. If CPU_V7VE selects CPU_V7 we'll never be able to use -march=armv7ve because CPU_V7 will be selecting CPU_32v7 and that will come after CPU_32v7VE in the Makefile. My understanding is that we want to support CPU_V7VE without CPU_V7 enabled so that it uses the idiv instructions in that configuration. When V7VE and V7 are both enabled, we should degrade to the aeabi functions, and the same is true for when V7VE is disabled. I suppose we can fix this by making CPU_V7 a hidden option? Or I need some coffee because I'm missing something. ---8< diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ccd0d5553d38..158ffb983387 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -626,7 +626,7 @@ config ARCH_SHMOBILE_LEGACY select ARCH_SHMOBILE select ARM_PATCH_PHYS_VIRT if MMU select CLKDEV_LOOKUP - select CPU_V7 + select CPU_V7_NOEXT select GENERIC_CLOCKEVENTS select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP @@ -802,7 +802,7 @@ config ARCH_MULTI_V7 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)" default y select ARCH_MULTI_V6_V7 - select CPU_V7 + select CPU_V7_NOEXT select HAVE_SMP config ARCH_MULTI_V7VE diff --git a/arch/arm/mach-prima2/Kconfig b/arch/arm/mach-prima2/Kconfig index 9ab8932403e5..7e1b36400e14 100644 --- a/arch/arm/mach-prima2/Kconfig +++ b/arch/arm/mach-prima2/Kconfig @@ -25,7 +25,7 @@ config ARCH_ATLAS7 bool "CSR SiRFSoC ATLAS7 ARM Cortex A7 Platform" default y select ARM_GIC - select CPU_V7 + select CPU_V7_NOEXT select HAVE_ARM_SCU if SMP select HAVE_SMP help diff --git a/arch/arm/mach-realview/Kconfig b/arch/arm/mach-realview/Kconfig index 565925f37dc5..7e084c34071c 100644 --- a/arch/arm/mach-realview/Kconfig +++ b/arch/arm/mach-realview/Kconfig @@ -24,7 +24,7 @@ config MACH_REALVIEW_EB config REALVIEW_EB_A9MP bool "Support Multicore Cortex-A9 Tile" depends on MACH_REALVIEW_EB - select CPU_V7 + select CPU_V7_NOEXT select HAVE_ARM_SCU if SMP select HAVE_ARM_TWD if SMP select HAVE_SMP @@ -93,7 +93,7 @@ config REALVIEW_PB1176_SECURE_FLASH config MACH_REALVIEW_PBA8 bool "Support RealView(R) Platform Baseboard for Cortex(tm)-A8 platform" select ARM_GIC - select CPU_V7 + select CPU_V7_NOEXT select HAVE_PATA_PLATFORM help Include support for the ARM(R) RealView Platform Baseboard for diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index e4ff161da98f..02a887235155 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -350,11 +350,11 @@ config CPU_FEROCEON_OLD_ID config CPU_PJ4 bool select ARM_THUMBEE - select CPU_V7 + select CPU_V7_NOEXT config CPU_PJ4B bool - select CPU_V7 + select CPU_V7_NOEXT # ARMv6 config CPU_V6 @@ -383,11 +383,9 @@ config CPU_V6K select CPU_PABRT_V6 select CPU_TLB_V6 if MMU -# ARMv7 config CPU_V7 - bool "Support ARM V7 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V7) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX) + bool select CPU_32v6K - select CPU_32v7 select CPU_ABRT_EV7 select CPU_CACHE_V7 select CPU_CACHE_VIPT @@ -398,6 +396,12 @@ config CPU_V7 select CPU_PABRT_V7 select CPU_TLB_V7 if MMU +# ARMv7 +config CPU_V7_NOEXT + bool "Support ARM V7 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V7) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX) + select CPU_32v7 + select CPU_V7 + # ARMv7M config CPU_V7M bool @
Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
Russell King - ARM Linux writes: > On Tue, Nov 24, 2015 at 12:29:06PM +, Måns Rullgård wrote: >> Russell King - ARM Linux writes: >> >> > On Tue, Nov 24, 2015 at 12:10:02PM +, Måns Rullgård wrote: >> >> Russell King - ARM Linux writes: >> >> >> >> > On Tue, Nov 24, 2015 at 11:38:53AM +0100, Arnd Bergmann wrote: >> >> >> I suggested using -mcpu=cortex-a15 because there are old gcc versions >> >> >> that don't know about -march=armv7ve or -march=armv7-a+idiv yet, but >> >> >> that do understand -mcpu=cortex-a15. >> >> > >> >> > That's not all. The bigger problem is that there are toolchains out >> >> > there which accept these options, but do _not_ support IDIV in either >> >> > ARM or Thumb mode. I'm afraid that makes it impossible to add this >> >> > feature to the mainline kernel in this form: we need to run a test >> >> > build to check that -march=armv7ve or what-not really does work >> >> > through both GCC and GAS. >> >> >> >> If the compiler accepts the option but doesn't actually emit any div >> >> instructions, is there any real harm? >> > >> > That's not what I've found. I've found that asking the assembler >> > to accept idiv instructions appears to be ignored, which is something >> > completely different. >> > >> > Further to this, what it comes down to is the stupid idea that the >> > compiler should embed .arch / .cpu in the assembly output, which has >> > the effect of overriding the command line arguments given to it via >> > -Wa. So, giving -Wa,-mcpu=cortex-a15 is a total no-op, because the >> > first thing in the assembly output is: >> > >> >.arch armv7-a >> > >> > which kills off any attempt to set the assembly level ISA from the >> > command line. >> >> Oh, you mean the compiler knows about the instructions but the assembler >> doesn't or isn't passed the right options. It's infuriating when that >> happens. > > No, that isn't what I meant. Then what do you mean? The compiler either emits the instructions or it doesn't. If it doesn't, what the assembler accepts is irrelevant. -- Måns Rullgård m...@mansr.com -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
On Tue, Nov 24, 2015 at 12:29:06PM +, Måns Rullgård wrote: > Russell King - ARM Linux writes: > > > On Tue, Nov 24, 2015 at 12:10:02PM +, Måns Rullgård wrote: > >> Russell King - ARM Linux writes: > >> > >> > On Tue, Nov 24, 2015 at 11:38:53AM +0100, Arnd Bergmann wrote: > >> >> I suggested using -mcpu=cortex-a15 because there are old gcc versions > >> >> that don't know about -march=armv7ve or -march=armv7-a+idiv yet, but > >> >> that do understand -mcpu=cortex-a15. > >> > > >> > That's not all. The bigger problem is that there are toolchains out > >> > there which accept these options, but do _not_ support IDIV in either > >> > ARM or Thumb mode. I'm afraid that makes it impossible to add this > >> > feature to the mainline kernel in this form: we need to run a test > >> > build to check that -march=armv7ve or what-not really does work > >> > through both GCC and GAS. > >> > >> If the compiler accepts the option but doesn't actually emit any div > >> instructions, is there any real harm? > > > > That's not what I've found. I've found that asking the assembler > > to accept idiv instructions appears to be ignored, which is something > > completely different. > > > > Further to this, what it comes down to is the stupid idea that the > > compiler should embed .arch / .cpu in the assembly output, which has > > the effect of overriding the command line arguments given to it via > > -Wa. So, giving -Wa,-mcpu=cortex-a15 is a total no-op, because the > > first thing in the assembly output is: > > > > .arch armv7-a > > > > which kills off any attempt to set the assembly level ISA from the > > command line. > > Oh, you mean the compiler knows about the instructions but the assembler > doesn't or isn't passed the right options. It's infuriating when that > happens. No, that isn't what I meant. -- FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up according to speedtest.net. -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
On Tuesday 24 November 2015 12:15:13 Måns Rullgård wrote: > Arnd Bergmann writes: > > On Monday 23 November 2015 15:13:52 Stephen Boyd wrote: > >> On 11/23, Arnd Bergmann wrote: > >> > On Monday 23 November 2015 13:32:06 Stephen Boyd wrote: > >> > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig > >> > index b251013eef0a..bad6343c34d5 100644 > >> Do you have the information on these custom opcodes? I can work > >> that into the patches assuming the MIDR is different. > > > > Thomas Petazzoni said this in a private mail: > > > > | According to the datasheet, the PJ4B has integer signed and unsigned > > | divide, similar to the sdiv and udiv ARM instructions. But the way to > > | access it is by doing a MRC instruction. > > | > > |MRC p6, 1, Rd , CRn , CRm, 4 > > | > > |for PJ4B is the same as: > > | > > |SDIV Rd , Rn, Rm > > | > > | on ARM cores. > > | > > |And: > > | > > |MRC p6, 1, Rd , CRn , CRm, 0 > > | > > |for PJ4B is the same as: > > | > > |UDIV Rd , Rn, Rm > > | > > |on ARM cores. > > | > > |This is documented in the "Extended instructions" section of the > > |PJ4B datasheet. > > > > I assume what he meant was that this is true for both PJ4 and PJ4B > > but not for PJ4B-MP, which has the normal udiv/sdiv instructions. > > > > IOW, anything with CPU implementer 0x56 part 0x581 should use those, > > while part 0x584 can use the sdiv/udiv that it reports correctly. > > Or we could simply ignore those and they'd be no worse off than they are > now. Well, if we add all the infrastructure to do dynamic patching, we might as well use it here, that is a very little extra effort. I'm not convinced that the dynamic patching for idiv is actually needed but I'm not objecting either, and Stephen has done the work already. Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
Russell King - ARM Linux writes: > On Tue, Nov 24, 2015 at 12:10:02PM +, Måns Rullgård wrote: >> Russell King - ARM Linux writes: >> >> > On Tue, Nov 24, 2015 at 11:38:53AM +0100, Arnd Bergmann wrote: >> >> I suggested using -mcpu=cortex-a15 because there are old gcc versions >> >> that don't know about -march=armv7ve or -march=armv7-a+idiv yet, but >> >> that do understand -mcpu=cortex-a15. >> > >> > That's not all. The bigger problem is that there are toolchains out >> > there which accept these options, but do _not_ support IDIV in either >> > ARM or Thumb mode. I'm afraid that makes it impossible to add this >> > feature to the mainline kernel in this form: we need to run a test >> > build to check that -march=armv7ve or what-not really does work >> > through both GCC and GAS. >> >> If the compiler accepts the option but doesn't actually emit any div >> instructions, is there any real harm? > > That's not what I've found. I've found that asking the assembler > to accept idiv instructions appears to be ignored, which is something > completely different. > > Further to this, what it comes down to is the stupid idea that the > compiler should embed .arch / .cpu in the assembly output, which has > the effect of overriding the command line arguments given to it via > -Wa. So, giving -Wa,-mcpu=cortex-a15 is a total no-op, because the > first thing in the assembly output is: > > .arch armv7-a > > which kills off any attempt to set the assembly level ISA from the > command line. Oh, you mean the compiler knows about the instructions but the assembler doesn't or isn't passed the right options. It's infuriating when that happens. -- Måns Rullgård m...@mansr.com -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
On Tue, Nov 24, 2015 at 12:10:02PM +, Måns Rullgård wrote: > Russell King - ARM Linux writes: > > > On Tue, Nov 24, 2015 at 11:38:53AM +0100, Arnd Bergmann wrote: > >> I suggested using -mcpu=cortex-a15 because there are old gcc versions > >> that don't know about -march=armv7ve or -march=armv7-a+idiv yet, but > >> that do understand -mcpu=cortex-a15. > > > > That's not all. The bigger problem is that there are toolchains out > > there which accept these options, but do _not_ support IDIV in either > > ARM or Thumb mode. I'm afraid that makes it impossible to add this > > feature to the mainline kernel in this form: we need to run a test > > build to check that -march=armv7ve or what-not really does work > > through both GCC and GAS. > > If the compiler accepts the option but doesn't actually emit any div > instructions, is there any real harm? That's not what I've found. I've found that asking the assembler to accept idiv instructions appears to be ignored, which is something completely different. Further to this, what it comes down to is the stupid idea that the compiler should embed .arch / .cpu in the assembly output, which has the effect of overriding the command line arguments given to it via -Wa. So, giving -Wa,-mcpu=cortex-a15 is a total no-op, because the first thing in the assembly output is: .arch armv7-a which kills off any attempt to set the assembly level ISA from the command line. It does appear after all that Ubuntu 14.04 does support sdiv/idiv with -mcpu=cortex-a15, but there is no -march=armv7ve. -- FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up according to speedtest.net. -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
Arnd Bergmann writes: > On Monday 23 November 2015 15:13:52 Stephen Boyd wrote: >> On 11/23, Arnd Bergmann wrote: >> > On Monday 23 November 2015 13:32:06 Stephen Boyd wrote: >> > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig >> > index b251013eef0a..bad6343c34d5 100644 >> > --- a/drivers/clocksource/Kconfig >> > +++ b/drivers/clocksource/Kconfig >> > @@ -324,8 +324,9 @@ config EM_TIMER_STI >> > such as EMEV2 from former NEC Electronics. >> > >> > config CLKSRC_QCOM >> > - bool "Qualcomm MSM timer" if COMPILE_TEST >> > + bool "Qualcomm MSM timer" if ARCH_QCOM || COMPILE_TEST >> >depends on ARM >> > + default ARCH_QCOM >> >select CLKSRC_OF >> >help >> > This enables the clocksource and the per CPU clockevent driver for the >> > >> > would make both of them equally configurable and not clutter up >> > the Kconfig file when ARCH_QCOM is not selected. I've added >> > Daniel Lezcano to Cc, he probably has an opinion on this too. >> >> Yeah I think that architected timers are an outlier. I recall >> some words from John Stultz that platforms should select the >> clocksources they use, but maybe things have changed. For this >> kind of thing I wouldn't mind putting it in the defconfig though. >> I'll put the patches on the list to get the discussion started. > > Ok, thanks! > >> > This works perfectly for Cortex-A5, -A8, -A9, -A12, -A15, -A17, Brahma-B15, >> > PJ4B-MP, Scorpion and Krait-450, which all clearly fall into one of >> > the two other categories. >> > >> > The two exceptions that don't quite fit are still "good enough": >> > >> > - PJ4/PJ4B (not PJ4B-MP) has a different custom opcode for udiv and sdiv >> > in ARM mode. We don't support that with true multiplatform kernels >> > because those opcodes work nowhere else, though with your proposed >> > series we could easily do that for dynamic patching. >> >> Do you have the information on these custom opcodes? I can work >> that into the patches assuming the MIDR is different. > > Thomas Petazzoni said this in a private mail: > > | According to the datasheet, the PJ4B has integer signed and unsigned > | divide, similar to the sdiv and udiv ARM instructions. But the way to > | access it is by doing a MRC instruction. > | > |MRC p6, 1, Rd , CRn , CRm, 4 > | > |for PJ4B is the same as: > | > |SDIV Rd , Rn, Rm > | > | on ARM cores. > | > |And: > | > |MRC p6, 1, Rd , CRn , CRm, 0 > | > |for PJ4B is the same as: > | > |UDIV Rd , Rn, Rm > | > |on ARM cores. > | > |This is documented in the "Extended instructions" section of the > |PJ4B datasheet. > > I assume what he meant was that this is true for both PJ4 and PJ4B > but not for PJ4B-MP, which has the normal udiv/sdiv instructions. > > IOW, anything with CPU implementer 0x56 part 0x581 should use those, > while part 0x584 can use the sdiv/udiv that it reports correctly. Or we could simply ignore those and they'd be no worse off than they are now. -- Måns Rullgård m...@mansr.com -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
Russell King - ARM Linux writes: > On Tue, Nov 24, 2015 at 11:38:53AM +0100, Arnd Bergmann wrote: >> I suggested using -mcpu=cortex-a15 because there are old gcc versions >> that don't know about -march=armv7ve or -march=armv7-a+idiv yet, but >> that do understand -mcpu=cortex-a15. > > That's not all. The bigger problem is that there are toolchains out > there which accept these options, but do _not_ support IDIV in either > ARM or Thumb mode. I'm afraid that makes it impossible to add this > feature to the mainline kernel in this form: we need to run a test > build to check that -march=armv7ve or what-not really does work > through both GCC and GAS. If the compiler accepts the option but doesn't actually emit any div instructions, is there any real harm? -- Måns Rullgård m...@mansr.com -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
On Tue, Nov 24, 2015 at 11:38:53AM +0100, Arnd Bergmann wrote: > I suggested using -mcpu=cortex-a15 because there are old gcc versions > that don't know about -march=armv7ve or -march=armv7-a+idiv yet, but > that do understand -mcpu=cortex-a15. That's not all. The bigger problem is that there are toolchains out there which accept these options, but do _not_ support IDIV in either ARM or Thumb mode. I'm afraid that makes it impossible to add this feature to the mainline kernel in this form: we need to run a test build to check that -march=armv7ve or what-not really does work through both GCC and GAS. Given that Ubuntu 14.04 LTS suffers with this, it's something that must be resolved. -- FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up according to speedtest.net. -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
On Tue, Nov 24, 2015 at 12:53:49AM -0800, Stephen Boyd wrote: > On 11/23, Stephen Boyd wrote: > > On 11/23, Arnd Bergmann wrote: > > > > > > Ok, thanks for the confirmation. > > > > > > Summarizing what we've found, I think we can get away with just > > > introducing two Kconfig symbols ARCH_MULTI_V7VE and CPU_V7VE. > > > Most CPUs fall clearly into one category or the other, and then > > > we can allow LPAE to be selected for V7VE-only build but not > > > for plain V7, and we can unconditionally build the kernel with > > > > > > arch-$(CONFIG_CPU_32v7VE) = -D__LINUX_ARM_ARCH__=7 $(call > > > cc-option,-march=armv7ve,-march=armv7-a -mcpu=cortex-a15) > > > > > > > This causes compiler spew for me: > > > > warning: switch -mcpu=cortex-a15 conflicts with -march=armv7-a switch > > > > Removing -march=armv7-a from there makes it quiet. > > > > Also, it's sort of feels wrong to have -mcpu in a place where > > we're exclusively doing -march. Perhaps the fallback should be > > bog standard -march=armv7-a? (or the fallback for that one > > "-march=armv5t -Wa$(comma)-march=armv7-a")? > > > > And adding CPU_V7VE causes a cascade of changes to wherever > CPU_V7 is being used today. Here's the patch I currently have, > without the platform changes: > > ---8< > arch/arm/Kconfig | 68 > +- > arch/arm/Kconfig-nommu | 2 +- > arch/arm/Makefile | 1 + > arch/arm/boot/compressed/head.S| 2 +- > arch/arm/boot/compressed/misc.c| 2 +- > arch/arm/include/asm/cacheflush.h | 2 +- > arch/arm/include/asm/glue-cache.h | 2 +- > arch/arm/include/asm/glue-proc.h | 2 +- > arch/arm/include/asm/switch_to.h | 2 +- > arch/arm/include/debug/icedcc.S| 2 +- > arch/arm/kernel/entry-armv.S | 6 ++-- > arch/arm/kernel/perf_event_v7.c| 4 +-- > arch/arm/kvm/Kconfig | 2 +- > arch/arm/mm/Kconfig| 41 --- > arch/arm/mm/Makefile | 1 + > arch/arm/probes/kprobes/test-arm.c | 2 +- > drivers/bus/Kconfig| 6 ++-- > 17 files changed, 86 insertions(+), 61 deletions(-) > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > index 9e2d2adcc85b..ccd0d5553d38 100644 > --- a/arch/arm/Kconfig > +++ b/arch/arm/Kconfig > @@ -32,7 +32,7 @@ config ARM > select HANDLE_DOMAIN_IRQ > select HARDIRQS_SW_RESEND > select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT) > - select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6 > + select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7 || CPU_32_v7VE) > && !CPU_32v6 > select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 > select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 > select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT) > @@ -46,12 +46,12 @@ config ARM > select HAVE_DMA_ATTRS > select HAVE_DMA_CONTIGUOUS if MMU > select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 > - select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) > && MMU > + select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7 > || CPU_V7VE) && MMU > select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL) > select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL) > select HAVE_FUNCTION_TRACER if (!XIP_KERNEL) > select HAVE_GENERIC_DMA_COHERENT > - select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || > CPU_V7)) > + select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || > CPU_V7 || CPU_V7VE)) > select HAVE_IDE if PCI || ISA || PCMCIA > select HAVE_IRQ_TIME_ACCOUNTING > select HAVE_KERNEL_GZIP > @@ -805,6 +805,12 @@ config ARCH_MULTI_V7 > select CPU_V7 > select HAVE_SMP > > +config ARCH_MULTI_V7VE > + bool "ARMv7 w/ virtualization extensions based platforms (Cortex-A, > PJ4-MP, Krait)" > + select ARCH_MULTI_V6_V7 > + select CPU_V7VE > + select HAVE_SMP > + > config ARCH_MULTI_V6_V7 > bool > select MIGHT_HAVE_CACHE_L2X0 > @@ -1069,7 +1075,7 @@ config ARM_ERRATA_411920 > > config ARM_ERRATA_430973 > bool "ARM errata: Stale prediction on replaced interworking branch" > - depends on CPU_V7 > + depends on CPU_V7 || CPU_V7VE NAK on all this. The fact that you're having to add CPU_V7VE at all sites which have CPU_V7 shows that this is a totally broken way of approaching this. Make CPU_V7VE be an _add-on_ to CPU_V7. In other words, when CPU_V7VE is enabled, CPU_V7 should also be enabled, just like we do for CPU_V6K. Note that v7M is different because that's not an add-on feature, it's a different CPU class from (what should be) v7A. -- FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up according to speedtest.net. -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majord...@vger.kernel.org More majo
Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
On Tuesday 24 November 2015 00:53:49 Stephen Boyd wrote:
> On 11/23, Stephen Boyd wrote:
> > On 11/23, Arnd Bergmann wrote:
> > >
> > > Ok, thanks for the confirmation.
> > >
> > > Summarizing what we've found, I think we can get away with just
> > > introducing two Kconfig symbols ARCH_MULTI_V7VE and CPU_V7VE.
> > > Most CPUs fall clearly into one category or the other, and then
> > > we can allow LPAE to be selected for V7VE-only build but not
> > > for plain V7, and we can unconditionally build the kernel with
> > >
> > > arch-$(CONFIG_CPU_32v7VE) = -D__LINUX_ARM_ARCH__=7 $(call
> > > cc-option,-march=armv7ve,-march=armv7-a -mcpu=cortex-a15)
> > >
> >
> > This causes compiler spew for me:
> >
> > warning: switch -mcpu=cortex-a15 conflicts with -march=armv7-a switch
> >
> > Removing -march=armv7-a from there makes it quiet.
> >
> > Also, it's sort of feels wrong to have -mcpu in a place where
> > we're exclusively doing -march. Perhaps the fallback should be
> > bog standard -march=armv7-a? (or the fallback for that one
> > "-march=armv5t -Wa$(comma)-march=armv7-a")?
I suggested using -mcpu=cortex-a15 because there are old gcc versions
that don't know about -march=armv7ve or -march=armv7-a+idiv yet, but
that do understand -mcpu=cortex-a15. I might be misremembering the
exact options we want though, and we could now just decided that if
your gcc is too old, you get no idiv even if it supports that on
Cortex-A15.
> And adding CPU_V7VE causes a cascade of changes to wherever
> CPU_V7 is being used today. Here's the patch I currently have,
> without the platform changes:
Thanks a lot for looking into this. I think we can simplify a couple
of them, as long as we also fix all the platforms to have the correct
dependencies:
> @@ -1069,7 +1075,7 @@ config ARM_ERRATA_411920
>
> config ARM_ERRATA_430973
> bool "ARM errata: Stale prediction on replaced interworking branch"
> - depends on CPU_V7
> + depends on CPU_V7 || CPU_V7VE
> help
> This option enables the workaround for the 430973 Cortex-A8
> r1p* erratum. If a code sequence containing an ARM/Thumb
If it's a Cortex-A8 erratum, we don't need the "|| CPU_V7VE". Same for
a lot of the following errata.
> @@ -1246,7 +1252,7 @@ config ARM_ERRATA_775420
>
> config ARM_ERRATA_798181
> bool "ARM errata: TLBI/DSB failure on Cortex-A15"
> - depends on CPU_V7 && SMP
> + depends on (CPU_V7 || CPU_V7VE) && SMP
> help
> On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
> adequately shooting down all use of the old entries. This
> @@ -1256,7 +1262,7 @@ config ARM_ERRATA_798181
>
> config ARM_ERRATA_773022
> bool "ARM errata: incorrect instructions may be executed from loop
> buffer"
> - depends on CPU_V7
> + depends on CPU_V7 || CPU_V7VE
> help
> This option enables the workaround for the 773022 Cortex-A15
> (up to r0p4) erratum. In certain rare sequences of code, the
And conversely, these will only need to depend on CPU_V7VE.
> @@ -1373,7 +1379,7 @@ config SMP_ON_UP
>
> config ARM_CPU_TOPOLOGY
> bool "Support cpu topology definition"
> - depends on SMP && CPU_V7
> + depends on SMP && (CPU_V7 || CPU_V7VE)
> default y
> help
> Support ARM cpu topology definition. The MPIDR register defines
Does topology make sense with Cortex-A5/A9 or Scorpion?
Otherwise it can also be V7VE-only.
> @@ -1417,7 +1423,7 @@ config HAVE_ARM_TWD
>
> config MCPM
> bool "Multi-Cluster Power Management"
> - depends on CPU_V7 && SMP
> + depends on (CPU_V7 || CPU_V7VE) && SMP
> help
> This option provides the common power management infrastructure
> for (multi-)cluster based systems, such as big.LITTLE based
> @@ -1434,7 +1440,7 @@ config MCPM_QUAD_CLUSTER
>
> config BIG_LITTLE
> bool "big.LITTLE support (Experimental)"
> - depends on CPU_V7 && SMP
> + depends on (CPU_V7 || CPU_V7VE) && SMP
> select MCPM
> help
> This option enables support selections for the big.LITTLE
multi-cluster and big.little are also V7VE-only by definition,
as pre-VE ARMv7 cores are all limited to one cluster.
> @@ -1642,7 +1648,7 @@ config AEABI
>
> config ARM_PATCH_UIDIV
> bool "Runtime patch calls to __aeabi_{u}idiv() with udiv/sdiv"
> - depends on CPU_V7 && !XIP_KERNEL && AEABI
> + depends on CPU_32v7 && !XIP_KERNEL && AEABI
> help
> Some v7 CPUs have support for the udiv and sdiv instructions
> that can be used in place of calls to __aeabi_uidiv and __aeabi_idiv
How about making this
depends on (CPU_V6 || CPU_V6K || CPU_V7) && CPU_V7VE
> @@ -1843,7 +1849,7 @@ config XEN_DOM0
> config XEN
> bool "Xen guest support on ARM"
> depends on ARM && AEABI && OF
> - depends on CPU_V7 && !CPU_V6
> + depends on (CPU_V7 || CPU_V7VE) && !CPU_V6
> depends on !GENERIC_ATOMIC64
> depends on MMU
>
Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
On Mon, Nov 23, 2015 at 04:13:06PM -0800, Stephen Boyd wrote: > On 11/23, Arnd Bergmann wrote: > > > > Ok, thanks for the confirmation. > > > > Summarizing what we've found, I think we can get away with just > > introducing two Kconfig symbols ARCH_MULTI_V7VE and CPU_V7VE. > > Most CPUs fall clearly into one category or the other, and then > > we can allow LPAE to be selected for V7VE-only build but not > > for plain V7, and we can unconditionally build the kernel with > > > > arch-$(CONFIG_CPU_32v7VE) = -D__LINUX_ARM_ARCH__=7 $(call > > cc-option,-march=armv7ve,-march=armv7-a -mcpu=cortex-a15) > > > > This causes compiler spew for me: > > warning: switch -mcpu=cortex-a15 conflicts with -march=armv7-a switch > > Removing -march=armv7-a from there makes it quiet. > > Also, it's sort of feels wrong to have -mcpu in a place where > we're exclusively doing -march. Perhaps the fallback should be > bog standard -march=armv7-a? (or the fallback for that one > "-march=armv5t -Wa$(comma)-march=armv7-a")? How it was explained to me years ago is that -march selects the instruction set, -mtune selects the instruction scheduling, and -mcpu selects both. -- FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up according to speedtest.net. -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
On Monday 23 November 2015 15:13:52 Stephen Boyd wrote: > On 11/23, Arnd Bergmann wrote: > > On Monday 23 November 2015 13:32:06 Stephen Boyd wrote: > > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig > > index b251013eef0a..bad6343c34d5 100644 > > --- a/drivers/clocksource/Kconfig > > +++ b/drivers/clocksource/Kconfig > > @@ -324,8 +324,9 @@ config EM_TIMER_STI > > such as EMEV2 from former NEC Electronics. > > > > config CLKSRC_QCOM > > - bool "Qualcomm MSM timer" if COMPILE_TEST > > + bool "Qualcomm MSM timer" if ARCH_QCOM || COMPILE_TEST > > depends on ARM > > + default ARCH_QCOM > > select CLKSRC_OF > > help > > This enables the clocksource and the per CPU clockevent driver for the > > > > would make both of them equally configurable and not clutter up > > the Kconfig file when ARCH_QCOM is not selected. I've added > > Daniel Lezcano to Cc, he probably has an opinion on this too. > > Yeah I think that architected timers are an outlier. I recall > some words from John Stultz that platforms should select the > clocksources they use, but maybe things have changed. For this > kind of thing I wouldn't mind putting it in the defconfig though. > I'll put the patches on the list to get the discussion started. Ok, thanks! > > This works perfectly for Cortex-A5, -A8, -A9, -A12, -A15, -A17, Brahma-B15, > > PJ4B-MP, Scorpion and Krait-450, which all clearly fall into one of > > the two other categories. > > > > The two exceptions that don't quite fit are still "good enough": > > > > - PJ4/PJ4B (not PJ4B-MP) has a different custom opcode for udiv and sdiv > > in ARM mode. We don't support that with true multiplatform kernels > > because those opcodes work nowhere else, though with your proposed > > series we could easily do that for dynamic patching. > > Do you have the information on these custom opcodes? I can work > that into the patches assuming the MIDR is different. Thomas Petazzoni said this in a private mail: | According to the datasheet, the PJ4B has integer signed and unsigned | divide, similar to the sdiv and udiv ARM instructions. But the way to | access it is by doing a MRC instruction. | |MRC p6, 1, Rd , CRn , CRm, 4 | |for PJ4B is the same as: | |SDIV Rd , Rn, Rm | | on ARM cores. | |And: | |MRC p6, 1, Rd , CRn , CRm, 0 | |for PJ4B is the same as: | |UDIV Rd , Rn, Rm | |on ARM cores. | |This is documented in the "Extended instructions" section of the |PJ4B datasheet. I assume what he meant was that this is true for both PJ4 and PJ4B but not for PJ4B-MP, which has the normal udiv/sdiv instructions. IOW, anything with CPU implementer 0x56 part 0x581 should use those, while part 0x584 can use the sdiv/udiv that it reports correctly. > > - Krait (pre-450) won't run kernels with LPAE disabled, but if we only > > have one global ARCH_QCOM option that can be enabled for both > > ARCH_MULTI_V7VE and ARCH_MULTI_V7, we still win: a mach-qcom > > kernel with only ARCH_MULTI_V7VE will use IDIV by default, and > > give you the option to enable LPAE. If you pick LPAE, it will > > still work fine on Krait-450 but not the older ones, and that is > > a user error. If you enable ARCH_MULTI_V7 / CPU_V7, you get neither > > LPAE nor IDIV, and the kernel will be able to run on both Scorpion > > and Krait, as long as you have the right drivers too. > > > > So if I have built mach-qcom with ARCH_MULTI_V7VE won't I get a > kernel that uses idiv instructions that could be run on Scorpion, > where the instruction doesn't exist? Or is that a user error > again like picking LPAE? Right. If you want to run on Scorpion, you have to select ARCH_MULTI_V7. If both are set, we should build with -march=armv7-a and not use the idiv instructions. > It seems fine to me to go ahead with this approach. Should I take > care of cooking up the patches? I can package this all up into a > series that adds the new CPU type, updates the affected > platforms, and layers the runtime patching on top when plain V7 > is a selected CPU type. That would be nice, yes. Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
On 11/23, Arnd Bergmann wrote: > > Ok, thanks for the confirmation. > > Summarizing what we've found, I think we can get away with just > introducing two Kconfig symbols ARCH_MULTI_V7VE and CPU_V7VE. > Most CPUs fall clearly into one category or the other, and then > we can allow LPAE to be selected for V7VE-only build but not > for plain V7, and we can unconditionally build the kernel with > > arch-$(CONFIG_CPU_32v7VE) = -D__LINUX_ARM_ARCH__=7 $(call > cc-option,-march=armv7ve,-march=armv7-a -mcpu=cortex-a15) > This causes compiler spew for me: warning: switch -mcpu=cortex-a15 conflicts with -march=armv7-a switch Removing -march=armv7-a from there makes it quiet. Also, it's sort of feels wrong to have -mcpu in a place where we're exclusively doing -march. Perhaps the fallback should be bog standard -march=armv7-a? (or the fallback for that one "-march=armv5t -Wa$(comma)-march=armv7-a")? -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
On 11/23, Arnd Bergmann wrote: > On Monday 23 November 2015 13:32:06 Stephen Boyd wrote: > > On 11/23, Arnd Bergmann wrote: > > > On Monday 23 November 2015 12:38:47 Stephen Boyd wrote: > > > > It would be nice to drop the ARCH_MSM* configs entirely. If we > > could select the right timers from kconfig without using selects > > then we could drop them. Or we could just select both types of > > timers when building qcom platforms. > > Ok, dropping the specific Kconfig entries is actually an awesome > idea, as it completely solves the other problem as well, more on > that below. > > In that case, don't worry about listing all the models, once > we stop listing a subset of them, the confusion is already > reduced by the fact that one has to look at the .dts files > so see which models we support, and I assume there will be > additional ones coming in for at least a few more years (before > you stop caring about 32-bit MSM and compatibles). > > Regarding the timers: > HAVE_ARM_ARCH_TIMER is already user-selectable, so maybe something > like > > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig > index b251013eef0a..bad6343c34d5 100644 > --- a/drivers/clocksource/Kconfig > +++ b/drivers/clocksource/Kconfig > @@ -324,8 +324,9 @@ config EM_TIMER_STI > such as EMEV2 from former NEC Electronics. > > config CLKSRC_QCOM > - bool "Qualcomm MSM timer" if COMPILE_TEST > + bool "Qualcomm MSM timer" if ARCH_QCOM || COMPILE_TEST > depends on ARM > + default ARCH_QCOM > select CLKSRC_OF > help > This enables the clocksource and the per CPU clockevent driver for the > > would make both of them equally configurable and not clutter up > the Kconfig file when ARCH_QCOM is not selected. I've added > Daniel Lezcano to Cc, he probably has an opinion on this too. Yeah I think that architected timers are an outlier. I recall some words from John Stultz that platforms should select the clocksources they use, but maybe things have changed. For this kind of thing I wouldn't mind putting it in the defconfig though. I'll put the patches on the list to get the discussion started. > > > > > > The ones we do support are MSM8x60 (Scorpion), MSM8960 > > > > > (Krait-without-number),and MSM7874 (Krait 400). Do those all > > > > > support IDIV but not LPAE? > > > > > > > > > > > > > Krait supports IDIV for all versions. Scorpion doesn't support > > > > IDIV or lpae. Here's the output of /proc/cpuinfo on that device. > > > > > > > > # cat /proc/cpuinfo > > > > processor : 0 > > > > model name : ARMv7 Processor rev 2 (v7l) > > > > BogoMIPS: 13.50 > > > > Features: half thumb fastmult vfp edsp neon vfpv3 tls vfpd32 > > > > CPU implementer : 0x51 > > > > CPU architecture: 7 > > > > CPU variant : 0x0 > > > > CPU part: 0x02d > > > > CPU revision: 2 > > > > > > Ok, that leaves just one missing puzzle piece: can you confirm that > > > no supported Krait variant other than Krait 450 / apq8084 has LPAE? > > > > > > > Right, apq8084 is the only SoC with a Krait CPU that supports > > LPAE. > > Ok, thanks for the confirmation. > > Summarizing what we've found, I think we can get away with just > introducing two Kconfig symbols ARCH_MULTI_V7VE and CPU_V7VE. > Most CPUs fall clearly into one category or the other, and then > we can allow LPAE to be selected for V7VE-only build but not > for plain V7, and we can unconditionally build the kernel with > > arch-$(CONFIG_CPU_32v7VE) = -D__LINUX_ARM_ARCH__=7 $(call > cc-option,-march=armv7ve,-march=armv7-a -mcpu=cortex-a15) > > This works perfectly for Cortex-A5, -A8, -A9, -A12, -A15, -A17, Brahma-B15, > PJ4B-MP, Scorpion and Krait-450, which all clearly fall into one of > the two other categories. > > The two exceptions that don't quite fit are still "good enough": > > - PJ4/PJ4B (not PJ4B-MP) has a different custom opcode for udiv and sdiv > in ARM mode. We don't support that with true multiplatform kernels > because those opcodes work nowhere else, though with your proposed > series we could easily do that for dynamic patching. Do you have the information on these custom opcodes? I can work that into the patches assuming the MIDR is different. > > - Krait (pre-450) won't run kernels with LPAE disabled, but if we only > have one global ARCH_QCOM option that can be enabled for both > ARCH_MULTI_V7VE and ARCH_MULTI_V7, we still win: a mach-qcom > kernel with only ARCH_MULTI_V7VE will use IDIV by default, and > give you the option to enable LPAE. If you pick LPAE, it will > still work fine on Krait-450 but not the older ones, and that is > a user error. If you enable ARCH_MULTI_V7 / CPU_V7, you get neither > LPAE nor IDIV, and the kernel will be able to run on both Scorpion > and Krait, as long as you have the right drivers too. > So if I have built mach-qcom with ARCH_MULTI_V7VE won't I get a kernel that uses idiv instructions that could be run on Scorp
Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
On Monday 23 November 2015 13:32:06 Stephen Boyd wrote: > On 11/23, Arnd Bergmann wrote: > > On Monday 23 November 2015 12:38:47 Stephen Boyd wrote: > > > On 11/23, Arnd Bergmann wrote: > > > > On Monday 23 November 2015 09:14:39 Christopher Covington wrote: > > > > > On 11/23/2015 03:15 AM, Arnd Bergmann wrote: > > > > > LPAE is only supported in the Krait 450. > > > > > > > > > > http://www.anandtech.com/show/7537/qualcomms-snapdragon-805-25ghz-128bit-memory-interface-d3d11class-graphics-more > > > > > > > > > > I'm pretty sure idiv support came earlier, but I don't have the > > > > > specifics on hand. > > > > > > > > I have seen that article, but didn't trust it as a canonical > > > > source of information here. > > > > > > > > If you can confirm that it's right, that would mean that we > > > > don't support LPAE on mach-qcom, as the only SoC with Krait 450 > > > > seems to be APQ8084, and mainline Linux doesn't run on that. > > > > > > arch/arm/boot/dts/qcom-apq8084.dtsi exists in the mainline > > > kernel. We support more than what's in the Kconfig language > > > under mach-qcom. > > > > Ok, cool. I'm sometimes confused by the model numbers, could you > > do a separate patch to update the Kconfig help text? > > What did you have in mind? I'm also confused by the model numbers > so I don't know how helpful I will be. > > It would be nice to drop the ARCH_MSM* configs entirely. If we > could select the right timers from kconfig without using selects > then we could drop them. Or we could just select both types of > timers when building qcom platforms. Ok, dropping the specific Kconfig entries is actually an awesome idea, as it completely solves the other problem as well, more on that below. In that case, don't worry about listing all the models, once we stop listing a subset of them, the confusion is already reduced by the fact that one has to look at the .dts files so see which models we support, and I assume there will be additional ones coming in for at least a few more years (before you stop caring about 32-bit MSM and compatibles). Regarding the timers: HAVE_ARM_ARCH_TIMER is already user-selectable, so maybe something like diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index b251013eef0a..bad6343c34d5 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -324,8 +324,9 @@ config EM_TIMER_STI such as EMEV2 from former NEC Electronics. config CLKSRC_QCOM - bool "Qualcomm MSM timer" if COMPILE_TEST + bool "Qualcomm MSM timer" if ARCH_QCOM || COMPILE_TEST depends on ARM + default ARCH_QCOM select CLKSRC_OF help This enables the clocksource and the per CPU clockevent driver for the would make both of them equally configurable and not clutter up the Kconfig file when ARCH_QCOM is not selected. I've added Daniel Lezcano to Cc, he probably has an opinion on this too. > > > > The ones we do support are MSM8x60 (Scorpion), MSM8960 > > > > (Krait-without-number),and MSM7874 (Krait 400). Do those all > > > > support IDIV but not LPAE? > > > > > > > > > > Krait supports IDIV for all versions. Scorpion doesn't support > > > IDIV or lpae. Here's the output of /proc/cpuinfo on that device. > > > > > > # cat /proc/cpuinfo > > > processor : 0 > > > model name : ARMv7 Processor rev 2 (v7l) > > > BogoMIPS: 13.50 > > > Features: half thumb fastmult vfp edsp neon vfpv3 tls vfpd32 > > > CPU implementer : 0x51 > > > CPU architecture: 7 > > > CPU variant : 0x0 > > > CPU part: 0x02d > > > CPU revision: 2 > > > > Ok, that leaves just one missing puzzle piece: can you confirm that > > no supported Krait variant other than Krait 450 / apq8084 has LPAE? > > > > Right, apq8084 is the only SoC with a Krait CPU that supports > LPAE. Ok, thanks for the confirmation. Summarizing what we've found, I think we can get away with just introducing two Kconfig symbols ARCH_MULTI_V7VE and CPU_V7VE. Most CPUs fall clearly into one category or the other, and then we can allow LPAE to be selected for V7VE-only build but not for plain V7, and we can unconditionally build the kernel with arch-$(CONFIG_CPU_32v7VE) = -D__LINUX_ARM_ARCH__=7 $(call cc-option,-march=armv7ve,-march=armv7-a -mcpu=cortex-a15) This works perfectly for Cortex-A5, -A8, -A9, -A12, -A15, -A17, Brahma-B15, PJ4B-MP, Scorpion and Krait-450, which all clearly fall into one of the two other categories. The two exceptions that don't quite fit are still "good enough": - PJ4/PJ4B (not PJ4B-MP) has a different custom opcode for udiv and sdiv in ARM mode. We don't support that with true multiplatform kernels because those opcodes work nowhere else, though with your proposed series we could easily do that for dynamic patching. - Krait (pre-450) won't run kernels with LPAE disabled, but if we only have one global ARCH_QCOM option that can be enabled for both ARCH_MULTI_V7VE and ARCH_MULTI_V7,
Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
On 11/23, Arnd Bergmann wrote: > On Monday 23 November 2015 12:38:47 Stephen Boyd wrote: > > On 11/23, Arnd Bergmann wrote: > > > On Monday 23 November 2015 09:14:39 Christopher Covington wrote: > > > > On 11/23/2015 03:15 AM, Arnd Bergmann wrote: > > > > LPAE is only supported in the Krait 450. > > > > > > > > http://www.anandtech.com/show/7537/qualcomms-snapdragon-805-25ghz-128bit-memory-interface-d3d11class-graphics-more > > > > > > > > I'm pretty sure idiv support came earlier, but I don't have the > > > > specifics on hand. > > > > > > I have seen that article, but didn't trust it as a canonical > > > source of information here. > > > > > > If you can confirm that it's right, that would mean that we > > > don't support LPAE on mach-qcom, as the only SoC with Krait 450 > > > seems to be APQ8084, and mainline Linux doesn't run on that. > > > > arch/arm/boot/dts/qcom-apq8084.dtsi exists in the mainline > > kernel. We support more than what's in the Kconfig language > > under mach-qcom. > > Ok, cool. I'm sometimes confused by the model numbers, could you > do a separate patch to update the Kconfig help text? What did you have in mind? I'm also confused by the model numbers so I don't know how helpful I will be. It would be nice to drop the ARCH_MSM* configs entirely. If we could select the right timers from kconfig without using selects then we could drop them. Or we could just select both types of timers when building qcom platforms. > > > > The ones we do support are MSM8x60 (Scorpion), MSM8960 > > > (Krait-without-number),and MSM7874 (Krait 400). Do those all > > > support IDIV but not LPAE? > > > > > > > Krait supports IDIV for all versions. Scorpion doesn't support > > IDIV or lpae. Here's the output of /proc/cpuinfo on that device. > > > > # cat /proc/cpuinfo > > processor : 0 > > model name : ARMv7 Processor rev 2 (v7l) > > BogoMIPS: 13.50 > > Features: half thumb fastmult vfp edsp neon vfpv3 tls vfpd32 > > CPU implementer : 0x51 > > CPU architecture: 7 > > CPU variant : 0x0 > > CPU part: 0x02d > > CPU revision: 2 > > Ok, that leaves just one missing puzzle piece: can you confirm that > no supported Krait variant other than Krait 450 / apq8084 has LPAE? > Right, apq8084 is the only SoC with a Krait CPU that supports LPAE. -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
On Monday 23 November 2015 12:38:47 Stephen Boyd wrote: > On 11/23, Arnd Bergmann wrote: > > On Monday 23 November 2015 09:14:39 Christopher Covington wrote: > > > On 11/23/2015 03:15 AM, Arnd Bergmann wrote: > > > LPAE is only supported in the Krait 450. > > > > > > http://www.anandtech.com/show/7537/qualcomms-snapdragon-805-25ghz-128bit-memory-interface-d3d11class-graphics-more > > > > > > I'm pretty sure idiv support came earlier, but I don't have the > > > specifics on hand. > > > > I have seen that article, but didn't trust it as a canonical > > source of information here. > > > > If you can confirm that it's right, that would mean that we > > don't support LPAE on mach-qcom, as the only SoC with Krait 450 > > seems to be APQ8084, and mainline Linux doesn't run on that. > > arch/arm/boot/dts/qcom-apq8084.dtsi exists in the mainline > kernel. We support more than what's in the Kconfig language > under mach-qcom. Ok, cool. I'm sometimes confused by the model numbers, could you do a separate patch to update the Kconfig help text? > And yes LPAE is supported by apq8084 (as is > IDIV). Here's the /proc/cpuinfo on that device. > # cat /proc/cpuinfo > processor : 0 > model name : ARMv7 Processor rev 1 (v7l) > BogoMIPS: 38.40 > Features: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva > idivt vfpd32 lpae evtstrm Ok. > > The ones we do support are MSM8x60 (Scorpion), MSM8960 > > (Krait-without-number),and MSM7874 (Krait 400). Do those all > > support IDIV but not LPAE? > > > > Krait supports IDIV for all versions. Scorpion doesn't support > IDIV or lpae. Here's the output of /proc/cpuinfo on that device. > > # cat /proc/cpuinfo > processor : 0 > model name : ARMv7 Processor rev 2 (v7l) > BogoMIPS: 13.50 > Features: half thumb fastmult vfp edsp neon vfpv3 tls vfpd32 > CPU implementer : 0x51 > CPU architecture: 7 > CPU variant : 0x0 > CPU part: 0x02d > CPU revision: 2 Ok, that leaves just one missing puzzle piece: can you confirm that no supported Krait variant other than Krait 450 / apq8084 has LPAE? Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
On 11/23, Arnd Bergmann wrote: > On Monday 23 November 2015 09:14:39 Christopher Covington wrote: > > On 11/23/2015 03:15 AM, Arnd Bergmann wrote: > > > On Sunday 22 November 2015 21:36:45 Nicolas Pitre wrote: > > >> On Sun, 22 Nov 2015, Arnd Bergmann wrote: > > > > > > Ok, thanks a lot! So the reporting in /proc/cpuinfo clearly matches > > > the actual features, and we can just treat this as no LPAE / no IDIV > > > for kernel compilation, as nobody ever seems to use THUMB2_KERNEL > > > in practice. > > > > > > PJ4-MP is like Cortex-A15/A7/A12/A17 and supports both IDIV and LPAE, > > > which leaves the question whether Scorpion or Krait do the same as > > > well, or whether they are outliers and need a special configuration. > > > > LPAE is only supported in the Krait 450. > > > > http://www.anandtech.com/show/7537/qualcomms-snapdragon-805-25ghz-128bit-memory-interface-d3d11class-graphics-more > > > > I'm pretty sure idiv support came earlier, but I don't have the > > specifics on hand. > > I have seen that article, but didn't trust it as a canonical > source of information here. > > If you can confirm that it's right, that would mean that we > don't support LPAE on mach-qcom, as the only SoC with Krait 450 > seems to be APQ8084, and mainline Linux doesn't run on that. arch/arm/boot/dts/qcom-apq8084.dtsi exists in the mainline kernel. We support more than what's in the Kconfig language under mach-qcom. And yes LPAE is supported by apq8084 (as is IDIV). Here's the /proc/cpuinfo on that device. # cat /proc/cpuinfo processor : 0 model name : ARMv7 Processor rev 1 (v7l) BogoMIPS: 38.40 Features: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm CPU implementer : 0x51 CPU architecture: 7 CPU variant : 0x3 CPU part: 0x06f CPU revision: 1 processor : 1 model name : ARMv7 Processor rev 1 (v7l) BogoMIPS: 38.40 Features: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm CPU implementer : 0x51 CPU architecture: 7 CPU variant : 0x3 CPU part: 0x06f CPU revision: 1 processor : 2 model name : ARMv7 Processor rev 1 (v7l) BogoMIPS: 38.40 Features: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm CPU implementer : 0x51 CPU architecture: 7 CPU variant : 0x3 CPU part: 0x06f CPU revision: 1 processor : 3 model name : ARMv7 Processor rev 1 (v7l) BogoMIPS: 38.40 Features: half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm CPU implementer : 0x51 CPU architecture: 7 CPU variant : 0x3 CPU part: 0x06f CPU revision: 1 Hardware: Qualcomm (Flattened Device Tree) Revision: Serial : > > The ones we do support are MSM8x60 (Scorpion), MSM8960 > (Krait-without-number),and MSM7874 (Krait 400). Do those all > support IDIV but not LPAE? > Krait supports IDIV for all versions. Scorpion doesn't support IDIV or lpae. Here's the output of /proc/cpuinfo on that device. # cat /proc/cpuinfo processor : 0 model name : ARMv7 Processor rev 2 (v7l) BogoMIPS: 13.50 Features: half thumb fastmult vfp edsp neon vfpv3 tls vfpd32 CPU implementer : 0x51 CPU architecture: 7 CPU variant : 0x0 CPU part: 0x02d CPU revision: 2 processor : 1 model name : ARMv7 Processor rev 2 (v7l) BogoMIPS: 13.50 Features: half thumb fastmult vfp edsp neon vfpv3 tls vfpd32 CPU implementer : 0x51 CPU architecture: 7 CPU variant : 0x0 CPU part: 0x02d CPU revision: 2 Hardware: Qualcomm (Flattened Device Tree) Revision: Serial : -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
On Monday 23 November 2015 09:14:39 Christopher Covington wrote: > On 11/23/2015 03:15 AM, Arnd Bergmann wrote: > > On Sunday 22 November 2015 21:36:45 Nicolas Pitre wrote: > >> On Sun, 22 Nov 2015, Arnd Bergmann wrote: > > > > Ok, thanks a lot! So the reporting in /proc/cpuinfo clearly matches > > the actual features, and we can just treat this as no LPAE / no IDIV > > for kernel compilation, as nobody ever seems to use THUMB2_KERNEL > > in practice. > > > > PJ4-MP is like Cortex-A15/A7/A12/A17 and supports both IDIV and LPAE, > > which leaves the question whether Scorpion or Krait do the same as > > well, or whether they are outliers and need a special configuration. > > LPAE is only supported in the Krait 450. > > http://www.anandtech.com/show/7537/qualcomms-snapdragon-805-25ghz-128bit-memory-interface-d3d11class-graphics-more > > I'm pretty sure idiv support came earlier, but I don't have the > specifics on hand. I have seen that article, but didn't trust it as a canonical source of information here. If you can confirm that it's right, that would mean that we don't support LPAE on mach-qcom, as the only SoC with Krait 450 seems to be APQ8084, and mainline Linux doesn't run on that. The ones we do support are MSM8x60 (Scorpion), MSM8960 (Krait-without-number),and MSM7874 (Krait 400). Do those all support IDIV but not LPAE? Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
On 11/23/2015 03:15 AM, Arnd Bergmann wrote:
> On Sunday 22 November 2015 21:36:45 Nicolas Pitre wrote:
>> On Sun, 22 Nov 2015, Arnd Bergmann wrote:
>>
>>> I've also found some /proc/cpuinfo output to cross-reference SoCs
>>> to their core names.
>>>
>>> variant partrevisionnamefeatures
>>> dove: 0 0x581 5 PJ4 idivt
>>
>> I just managed to boot my dusty Dove DB and ran a quick test programon
>> it. Its cpuinfo corresponds to the above.
>>
>> $ cat m.c
>> #include
>> int mydiv(int, int);
>> int main()
>> {
>> printf("div test\n");
>> printf("%d\n", mydiv(12345678, 37));
>> return 0;
>> }
>> $ cat d.c
>> int mydiv(int x, int y)
>> {
>> return x/y;
>> }
>> $ gcc -o test m.c d.c
>> $ ./test
>> div test
>> 333666
>> $ gcc -o test m.c d.c -march=armv7ve -mthumb
>> $ ./test
>> div test
>> 333666
>> $ gcc -o test m.c d.c -march=armv7ve -marm
>> $ ./test
>> div test
>> Illegal instruction (core dumped)
>> $
>
> Ok, thanks a lot! So the reporting in /proc/cpuinfo clearly matches
> the actual features, and we can just treat this as no LPAE / no IDIV
> for kernel compilation, as nobody ever seems to use THUMB2_KERNEL
> in practice.
>
> PJ4-MP is like Cortex-A15/A7/A12/A17 and supports both IDIV and LPAE,
> which leaves the question whether Scorpion or Krait do the same as
> well, or whether they are outliers and need a special configuration.
LPAE is only supported in the Krait 450.
http://www.anandtech.com/show/7537/qualcomms-snapdragon-805-25ghz-128bit-memory-interface-d3d11class-graphics-more
I'm pretty sure idiv support came earlier, but I don't have the
specifics on hand.
Regards,
Christopher Covington
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Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
On Sunday 22 November 2015 21:36:45 Nicolas Pitre wrote:
> On Sun, 22 Nov 2015, Arnd Bergmann wrote:
>
> > I've also found some /proc/cpuinfo output to cross-reference SoCs
> > to their core names.
> >
> > variant partrevisionnamefeatures
> > dove: 0 0x581 5 PJ4 idivt
>
> I just managed to boot my dusty Dove DB and ran a quick test programon
> it. Its cpuinfo corresponds to the above.
>
> $ cat m.c
> #include
> int mydiv(int, int);
> int main()
> {
> printf("div test\n");
> printf("%d\n", mydiv(12345678, 37));
> return 0;
> }
> $ cat d.c
> int mydiv(int x, int y)
> {
> return x/y;
> }
> $ gcc -o test m.c d.c
> $ ./test
> div test
> 333666
> $ gcc -o test m.c d.c -march=armv7ve -mthumb
> $ ./test
> div test
> 333666
> $ gcc -o test m.c d.c -march=armv7ve -marm
> $ ./test
> div test
> Illegal instruction (core dumped)
> $
Ok, thanks a lot! So the reporting in /proc/cpuinfo clearly matches
the actual features, and we can just treat this as no LPAE / no IDIV
for kernel compilation, as nobody ever seems to use THUMB2_KERNEL
in practice.
PJ4-MP is like Cortex-A15/A7/A12/A17 and supports both IDIV and LPAE,
which leaves the question whether Scorpion or Krait do the same as
well, or whether they are outliers and need a special configuration.
Arnd
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Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
On Sun, 22 Nov 2015, Arnd Bergmann wrote:
> I've also found some /proc/cpuinfo output to cross-reference SoCs
> to their core names.
>
> variant partrevisionnamefeatures
> dove: 0 0x581 5 PJ4 idivt
I just managed to boot my dusty Dove DB and ran a quick test programon
it. Its cpuinfo corresponds to the above.
$ cat m.c
#include
int mydiv(int, int);
int main()
{
printf("div test\n");
printf("%d\n", mydiv(12345678, 37));
return 0;
}
$ cat d.c
int mydiv(int x, int y)
{
return x/y;
}
$ gcc -o test m.c d.c
$ ./test
div test
333666
$ gcc -o test m.c d.c -march=armv7ve -mthumb
$ ./test
div test
333666
$ gcc -o test m.c d.c -march=armv7ve -marm
$ ./test
div test
Illegal instruction (core dumped)
$
Nicolas
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Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
On Sunday 22 November 2015 20:39:54 Måns Rullgård wrote: > Arnd Bergmann writes: > > > arnd@wuerfel:/tmp$ arm-linux-gnueabihf-gcc -Wall -O2 -mcpu=cortex-a15 > > idiv.c -c -o idiv-arm.o > > arnd@wuerfel:/tmp$ objdump -dr idiv-arm.o > > > > idiv-arm.o: file format elf32-littlearm > > > > Disassembly of section .text: > > > > : > >0: fbb0 f0f1 udivr0, r0, r1 > >4: 4770bx lr > >6: bf00nop > > > > 0008 : > >8: fb90 f0f1 sdivr0, r0, r1 > >c: 4770bx lr > >e: bf00nop > > Your compiler seems to default to thumb so you should add -marm. > Sorry about that. Arnd arnd@wuerfel:/tmp$ arm-linux-gnueabihf-gcc -Wall -O2 -mcpu=cortex-a15 idiv.c -c -o idiv-arm.o -marm arnd@wuerfel:/tmp$ objdump -dr idiv-arm.o idiv-arm.o: file format elf32-littlearm Disassembly of section .text: : 0: e730f110udivr0, r0, r1 4: e12fff1ebx lr 0008 : 8: e710f110sdivr0, r0, r1 c: e12fff1ebx lr idiv-arm.o Description: application/object
Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
On Sunday 22 November 2015 20:03:26 Russell King - ARM Linux wrote:
> On Sun, Nov 22, 2015 at 08:58:08PM +0100, Arnd Bergmann wrote:
> > does it work with -mcpu=cortex-a15? I've tried crosstool as versions
> > 2.23.52.20130913, 2.24.0.20141017 and 2.25.51.20150518, and they
> > all seem to behave as expected, failing with -mcpu=cortex-a9 and
> > marvell-pj4 but succeeding with -mcpu=cortex-a15 or marvell-pj4+idiv.
>
> Appears not:
>
> root@cubox:~# gcc -O2 -o idiv idiv.c -Wa,-mcpu='cortex-a15+idiv' -marm
> /tmp/ccSovg32.s: Assembler messages:
> /tmp/ccSovg32.s:32: Error: selected processor does not support ARM mode `udiv
> ip,r5,r4'
> root@cubox:~# gcc -O2 -o idiv idiv.c -Wa,-mcpu='cortex-a15+idiv' -mthumb
> /tmp/cchbT3EE.s: Assembler messages:
> /tmp/cchbT3EE.s:36: Error: selected processor does not support Thumb mode
> `udiv r6,r5,r4'
>
> Same without the +idiv.
I've attached files with those instructions, maybe that helps.
> > I've also found some /proc/cpuinfo output to cross-reference SoCs
> > to their core names.
> >
> > variant partrevisionnamefeatures
> > mmp2: 0 0x581 5 PJ4 idivt
> > dove: 0 0x581 5 PJ4 idivt
>
> Yes, that agrees with my dove.
ok.
arnd@wuerfel:/tmp$ cat idiv.c
unsigned int udiv(unsigned int a, unsigned int b)
{
return a / b;
}
int sdiv(int a, int b)
{
return a / b;
}
arnd@wuerfel:/tmp$ arm-linux-gnueabihf-gcc -Wall -O2 -mcpu=cortex-a15 idiv.c -c
-o idiv-arm.o
arnd@wuerfel:/tmp$ objdump -dr idiv-arm.o
idiv-arm.o: file format elf32-littlearm
Disassembly of section .text:
:
0: fbb0 f0f1 udivr0, r0, r1
4: 4770bx lr
6: bf00nop
0008 :
8: fb90 f0f1 sdivr0, r0, r1
c: 4770bx lr
e: bf00nop
arnd@wuerfel:/tmp$ arm-linux-gnueabihf-gcc -Wall -O2 -mcpu=cortex-a15 idiv.c -c
-o idiv-thumb.o -mthumb
arnd@wuerfel:/tmp$ objdump -dr idiv-thumb.o
idiv-thumb.o: file format elf32-littlearm
Disassembly of section .text:
:
0: fbb0 f0f1 udivr0, r0, r1
4: 4770bx lr
6: bf00nop
0008 :
8: fb90 f0f1 sdivr0, r0, r1
c: 4770bx lr
e: bf00nop
Arnd
idiv-arm.o
Description: application/object
idiv-thumb.o
Description: application/object
unsigned int udiv(unsigned int a, unsigned int b)
{
return a / b;
}
int sdiv(int a, int b)
{
return a / b;
}
Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
Arnd Bergmann writes: > arnd@wuerfel:/tmp$ arm-linux-gnueabihf-gcc -Wall -O2 -mcpu=cortex-a15 idiv.c > -c -o idiv-arm.o > arnd@wuerfel:/tmp$ objdump -dr idiv-arm.o > > idiv-arm.o: file format elf32-littlearm > > Disassembly of section .text: > > : >0: fbb0 f0f1 udivr0, r0, r1 >4: 4770bx lr >6: bf00nop > > 0008 : >8: fb90 f0f1 sdivr0, r0, r1 >c: 4770bx lr >e: bf00nop Your compiler seems to default to thumb so you should add -marm. -- Måns Rullgård m...@mansr.com -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
On Sun, Nov 22, 2015 at 08:58:08PM +0100, Arnd Bergmann wrote: > does it work with -mcpu=cortex-a15? I've tried crosstool as versions > 2.23.52.20130913, 2.24.0.20141017 and 2.25.51.20150518, and they > all seem to behave as expected, failing with -mcpu=cortex-a9 and > marvell-pj4 but succeeding with -mcpu=cortex-a15 or marvell-pj4+idiv. Appears not: root@cubox:~# gcc -O2 -o idiv idiv.c -Wa,-mcpu='cortex-a15+idiv' -marm /tmp/ccSovg32.s: Assembler messages: /tmp/ccSovg32.s:32: Error: selected processor does not support ARM mode `udiv ip,r5,r4' root@cubox:~# gcc -O2 -o idiv idiv.c -Wa,-mcpu='cortex-a15+idiv' -mthumb /tmp/cchbT3EE.s: Assembler messages: /tmp/cchbT3EE.s:36: Error: selected processor does not support Thumb mode `udiv r6,r5,r4' Same without the +idiv. > I've also found some /proc/cpuinfo output to cross-reference SoCs > to their core names. > > variant partrevisionnamefeatures > mmp2: 0 0x581 5 PJ4 idivt > dove: 0 0x581 5 PJ4 idivt Yes, that agrees with my dove. -- FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up according to speedtest.net. -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
On Sunday 22 November 2015 19:47:05 Russell King - ARM Linux wrote: > On Sun, Nov 22, 2015 at 08:25:27PM +0100, Arnd Bergmann wrote: > > The question is really about Marvell Dove, MMP and Armada 370, > > which are all based on PJ4 or PJ4B (CPU part : 0x581), so ARMv7-A > > and report idivt support but idiva. > > Well, it's pretty hard to test when binutils blocks your ability to > write assembly using the instructions. > > root@cubox:~# gcc -O2 -o idiv idiv.c -Wa,-mcpu='cortex-a9+idiv' -marm > /tmp/cc8WPQiB.s: Assembler messages: > /tmp/cc8WPQiB.s:32: Error: selected processor does not support ARM mode `udiv > ip,r5,r4' > root@cubox:~# gcc -O2 -o idiv idiv.c -Wa,-mcpu='cortex-a9+idiv' -mthumb > /tmp/ccRzgAlM.s: Assembler messages: > /tmp/ccRzgAlM.s:36: Error: selected processor does not support Thumb mode > `udiv r6,r5,r4' > root@cubox:~# gcc -O2 -o idiv idiv.c -Wa,-mcpu='marvell-pj4+idiv' -mthumb > /tmp/cc1JYyFD.s: Assembler messages: > /tmp/cc1JYyFD.s:36: Error: selected processor does not support Thumb mode > `udiv r6,r5,r4' > root@cubox:~# gcc -O2 -o idiv idiv.c -Wa,-mcpu='marvell-pj4+idiv' -marm > /tmp/ccEQbQpp.s: Assembler messages: > /tmp/ccEQbQpp.s:32: Error: selected processor does not support ARM mode `udiv > ip,r5,r4' > > That's binutils 2.24 and gcc 4.8.4 as found on Ubuntu 14.04. I'm > sorry, but I don't have spare time to work out what the opcodes > would be. > does it work with -mcpu=cortex-a15? I've tried crosstool as versions 2.23.52.20130913, 2.24.0.20141017 and 2.25.51.20150518, and they all seem to behave as expected, failing with -mcpu=cortex-a9 and marvell-pj4 but succeeding with -mcpu=cortex-a15 or marvell-pj4+idiv. I've also found some /proc/cpuinfo output to cross-reference SoCs to their core names. variant partrevisionnamefeatures mmp2: 0 0x581 5 PJ4 idivt dove: 0 0x581 5 PJ4 idivt Armada 370 1 0x581 1 PJ4Bidivt mmp3: 2 0x584 2 PJ4-MP idiva idivt lpae Armada XP 2 0x584 2 PJ4-MP idiva idivt lpae Berlin 2 0x584 2 PJ4-MP idiva idivt lpae Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
On Sun, Nov 22, 2015 at 08:25:27PM +0100, Arnd Bergmann wrote: > The question is really about Marvell Dove, MMP and Armada 370, > which are all based on PJ4 or PJ4B (CPU part : 0x581), so ARMv7-A > and report idivt support but idiva. Well, it's pretty hard to test when binutils blocks your ability to write assembly using the instructions. root@cubox:~# gcc -O2 -o idiv idiv.c -Wa,-mcpu='cortex-a9+idiv' -marm /tmp/cc8WPQiB.s: Assembler messages: /tmp/cc8WPQiB.s:32: Error: selected processor does not support ARM mode `udiv ip,r5,r4' root@cubox:~# gcc -O2 -o idiv idiv.c -Wa,-mcpu='cortex-a9+idiv' -mthumb /tmp/ccRzgAlM.s: Assembler messages: /tmp/ccRzgAlM.s:36: Error: selected processor does not support Thumb mode `udiv r6,r5,r4' root@cubox:~# gcc -O2 -o idiv idiv.c -Wa,-mcpu='marvell-pj4+idiv' -mthumb /tmp/cc1JYyFD.s: Assembler messages: /tmp/cc1JYyFD.s:36: Error: selected processor does not support Thumb mode `udiv r6,r5,r4' root@cubox:~# gcc -O2 -o idiv idiv.c -Wa,-mcpu='marvell-pj4+idiv' -marm /tmp/ccEQbQpp.s: Assembler messages: /tmp/ccEQbQpp.s:32: Error: selected processor does not support ARM mode `udiv ip,r5,r4' That's binutils 2.24 and gcc 4.8.4 as found on Ubuntu 14.04. I'm sorry, but I don't have spare time to work out what the opcodes would be. -- FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up according to speedtest.net. -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
Arnd Bergmann writes: > On Sunday 22 November 2015 13:29:29 Peter Maydell wrote: >> On 21 November 2015 at 23:21, Arnd Bergmann wrote: >> > Regarding PJ4, it's still unclear whether that has the same >> > problem and it only reports idivt when it actually supports idiva, >> > or whether the lack of idiva support on PJ4 is instead the reason >> > why the ARM ARM was updated to have separate flags. >> >> SDIV/IDIV were originally introduced for R and M profile only >> and there the Thumb encodings of SDIV/IDIV are mandatory >> whereas the ARM ones are optional (and weren't initially >> defined at all). So if you're looking for CPUs with only the >> Thumb encodings I would try checking older R profile cores >> like the Cortex-R4. > > The question is really about Marvell Dove, MMP and Armada 370, > which are all based on PJ4 or PJ4B (CPU part : 0x581), so ARMv7-A > and report idivt support but idiva. > > There are a couple of explanations here: > > a) Marvell really implemented only idivt but not idiva >and reports it correctly, and the people from >https://groups.google.com/a/dartlang.org/forum/#!topic/reviews/9wvsJvq0YYY >just misinterpreted the flags > > b) the dartlag.org folks are correct, and it supports neither >idivt nor idiva, and the /proc/cpuinfo flag is just wrong >and requires a fixup > > c) like Krait, it actually implements both idiva and idivt but >gets the reporting wrong. It's trivial to test for someone who has one. -- Måns Rullgård m...@mansr.com -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
On Sunday 22 November 2015 13:29:29 Peter Maydell wrote: > On 21 November 2015 at 23:21, Arnd Bergmann wrote: > > Regarding PJ4, it's still unclear whether that has the same > > problem and it only reports idivt when it actually supports idiva, > > or whether the lack of idiva support on PJ4 is instead the reason > > why the ARM ARM was updated to have separate flags. > > SDIV/IDIV were originally introduced for R and M profile only > and there the Thumb encodings of SDIV/IDIV are mandatory > whereas the ARM ones are optional (and weren't initially > defined at all). So if you're looking for CPUs with only the > Thumb encodings I would try checking older R profile cores > like the Cortex-R4. The question is really about Marvell Dove, MMP and Armada 370, which are all based on PJ4 or PJ4B (CPU part : 0x581), so ARMv7-A and report idivt support but idiva. There are a couple of explanations here: a) Marvell really implemented only idivt but not idiva and reports it correctly, and the people from https://groups.google.com/a/dartlang.org/forum/#!topic/reviews/9wvsJvq0YYY just misinterpreted the flags b) the dartlag.org folks are correct, and it supports neither idivt nor idiva, and the /proc/cpuinfo flag is just wrong and requires a fixup c) like Krait, it actually implements both idiva and idivt but gets the reporting wrong. Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
On 21 November 2015 at 23:21, Arnd Bergmann wrote: > Regarding PJ4, it's still unclear whether that has the same > problem and it only reports idivt when it actually supports idiva, > or whether the lack of idiva support on PJ4 is instead the reason > why the ARM ARM was updated to have separate flags. SDIV/IDIV were originally introduced for R and M profile only and there the Thumb encodings of SDIV/IDIV are mandatory whereas the ARM ones are optional (and weren't initially defined at all). So if you're looking for CPUs with only the Thumb encodings I would try checking older R profile cores like the Cortex-R4. thanks -- PMM -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
On Sunday 22 November 2015 00:14:14 Arnd Bergmann wrote: > On Saturday 21 November 2015 22:11:36 Måns Rullgård wrote: > > Arnd Bergmann writes: > > > On Saturday 21 November 2015 20:45:38 Måns Rullgård wrote: > > >> On 21 November 2015 20:39:58 GMT+00:00, Arnd Bergmann > > >> wrote: > > >> > > >> The ARM ARM says anything with virt has idiv, lpae doesn't matter. > > > > > > Ok, and anything with virt also has lpae by definition. The question is > > > whether we care about using idiv on cores that do not have lpae, or that > > > have neither lpae nor virt. > > > > The question is, are there any such cores? GCC doesn't know of any, but > > then it's missing most non-ARM designs. > > Exactly. Stephen should be able to find out about the Qualcomm cores, > and http://comments.gmane.org/gmane.linux.ports.arm.kernel/426289 has > some information about the others: > * Brahma-B15 supports all three. > * Dove (PJ4) reports idiv only in thumb mode, which I'm tempted to ignore >for the kernel, as it supports neither lpae nor idiva. > * Armada 370/XP (PJ4B) reports support for idiva and idivt, but according to >https://groups.google.com/a/dartlang.org/forum/#!topic/reviews/9wvsJvq0YYY >that may be a lie. > * According to the same source, Krait fails to report idiva and idivt, >but supports both anyway. However, I found reports on the web where >/proc/cpuinfo correctly contains the flags on the same SoC (APQ8064) >that was mentioned there, so maybe they were just running an old >kernel. This has some more information: commit 120ecfafabec382c4feb79ff159ef42a39b6d33b Author: Stepan Moskovchenko Date: Mon Mar 18 19:44:16 2013 +0100 ARM: 7678/1: Work around faulty ISAR0 register in some Krait CPUs Some early versions of the Krait CPU design incorrectly indicate that they only support the UDIV and SDIV instructions in Thumb mode when they actually support them in ARM and Thumb mode. It seems that these CPUs follow the DDI0406B ARM ARM which has two possible values for the divide instructions field, instead of the DDI0406C document which has three possible values. Work around this problem by checking the MIDR against Krait CPUs with this faulty ISAR0 register and force the hwcaps to indicate support in both modes. [sboyd: Rewrote commit text to reflect real reasoning now that we autodetect udiv/sdiv] Signed-off-by: Stepan Moskovchenko Acked-by: Will Deacon Signed-off-by: Stephen Boyd Signed-off-by: Russell King so Krait clearly supports them, and this also explains why some machines misreport it depending on the CPU version and kernel release running on it. Regarding PJ4, it's still unclear whether that has the same problem and it only reports idivt when it actually supports idiva, or whether the lack of idiva support on PJ4 is instead the reason why the ARM ARM was updated to have separate flags. Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
On Saturday 21 November 2015 22:11:36 Måns Rullgård wrote: > Arnd Bergmann writes: > > On Saturday 21 November 2015 20:45:38 Måns Rullgård wrote: > >> On 21 November 2015 20:39:58 GMT+00:00, Arnd Bergmann > >> wrote: > >> > >> The ARM ARM says anything with virt has idiv, lpae doesn't matter. > > > > Ok, and anything with virt also has lpae by definition. The question is > > whether we care about using idiv on cores that do not have lpae, or that > > have neither lpae nor virt. > > The question is, are there any such cores? GCC doesn't know of any, but > then it's missing most non-ARM designs. Exactly. Stephen should be able to find out about the Qualcomm cores, and http://comments.gmane.org/gmane.linux.ports.arm.kernel/426289 has some information about the others: * Brahma-B15 supports all three. * Dove (PJ4) reports idiv only in thumb mode, which I'm tempted to ignore for the kernel, as it supports neither lpae nor idiva. * Armada 370/XP (PJ4B) reports support for idiva and idivt, but according to https://groups.google.com/a/dartlang.org/forum/#!topic/reviews/9wvsJvq0YYY that may be a lie. * According to the same source, Krait fails to report idiva and idivt, but supports both anyway. However, I found reports on the web where /proc/cpuinfo correctly contains the flags on the same SoC (APQ8064) that was mentioned there, so maybe they were just running an old kernel. Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
Arnd Bergmann writes: > On Saturday 21 November 2015 20:45:38 Måns Rullgård wrote: >> On 21 November 2015 20:39:58 GMT+00:00, Arnd Bergmann wrote: >> >On Friday 20 November 2015 17:23:14 Stephen Boyd wrote: >> >> This is a respin of a patch series from about a year ago[1]. I >> >realized >> >> that we already had most of the code in recordmcount to figure out >> >> where we make calls to particular functions, so recording where >> >> we make calls to the integer division functions should be easy enough >> >> to add support for in the same codepaths. Looking back on the thread >> >> it seems like Mans was thinking along the same lines, although it >> >wasn't >> >> obvious to me back then or even over the last few days when I wrote >> >this. >> > >> >Shouldn't we start by allowing to build the kernel for -march=armv7ve >> >on platforms that allow it? That would seem like a simpler change >> >and likely generate better code for most people, except when you >> >actually >> >care about running the same binary kernel on older platforms. >> > >> >I tried to get a complete list of CPU cores with idiv, lpae and >> >virtualization support at some point, but I don't remember the >> >details for all Qualcomm and Marvell cores any more, to create the >> >complete configuration matrix. IIRC, all CPUs that support >> >virtualization also do lpae (they have to) and all CPUs that >> >do lpae also do idiv, but the opposite is not true. >> > >> >> The ARM ARM says anything with virt has idiv, lpae doesn't matter. > > Ok, and anything with virt also has lpae by definition. The question is > whether we care about using idiv on cores that do not have lpae, or that > have neither lpae nor virt. The question is, are there any such cores? GCC doesn't know of any, but then it's missing most non-ARM designs. -- Måns Rullgård m...@mansr.com -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
On Saturday 21 November 2015 20:45:38 Måns Rullgård wrote: > On 21 November 2015 20:39:58 GMT+00:00, Arnd Bergmann wrote: > >On Friday 20 November 2015 17:23:14 Stephen Boyd wrote: > >> This is a respin of a patch series from about a year ago[1]. I > >realized > >> that we already had most of the code in recordmcount to figure out > >> where we make calls to particular functions, so recording where > >> we make calls to the integer division functions should be easy enough > >> to add support for in the same codepaths. Looking back on the thread > >> it seems like Mans was thinking along the same lines, although it > >wasn't > >> obvious to me back then or even over the last few days when I wrote > >this. > > > >Shouldn't we start by allowing to build the kernel for -march=armv7ve > >on platforms that allow it? That would seem like a simpler change > >and likely generate better code for most people, except when you > >actually > >care about running the same binary kernel on older platforms. > > > >I tried to get a complete list of CPU cores with idiv, lpae and > >virtualization support at some point, but I don't remember the > >details for all Qualcomm and Marvell cores any more, to create the > >complete configuration matrix. IIRC, all CPUs that support > >virtualization also do lpae (they have to) and all CPUs that > >do lpae also do idiv, but the opposite is not true. > > > > The ARM ARM says anything with virt has idiv, lpae doesn't matter. Ok, and anything with virt also has lpae by definition. The question is whether we care about using idiv on cores that do not have lpae, or that have neither lpae nor virt. We have a related problem at the moment where we don't handle configuration of lpae correctly in Kconfig: you can simply turn that on for any ARMv7-only kernel, but it breaks running on Cortex-A8, Cortex-A9 and at least some subset of PJ4/Scorpion/Krait (not sure which). If we add a way to configure idiv support, we should do it right and handle lpae correctly too. If we are lucky, each CPU we support either has both or neither, and then we just need one additional Kconfig option. We don't need another option for virt, because KVM support can be handled in a way that it doesn't break on cores with lpae but without virt (it requires lpae). > ARMv7-R also has idiv. I've no idea if anyone runs Linux on those though. Not mainline at least. There were patches at some point, but they never got merged. Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
On 21 November 2015 20:39:58 GMT+00:00, Arnd Bergmann wrote: >On Friday 20 November 2015 17:23:14 Stephen Boyd wrote: >> This is a respin of a patch series from about a year ago[1]. I >realized >> that we already had most of the code in recordmcount to figure out >> where we make calls to particular functions, so recording where >> we make calls to the integer division functions should be easy enough >> to add support for in the same codepaths. Looking back on the thread >> it seems like Mans was thinking along the same lines, although it >wasn't >> obvious to me back then or even over the last few days when I wrote >this. > >Shouldn't we start by allowing to build the kernel for -march=armv7ve >on platforms that allow it? That would seem like a simpler change >and likely generate better code for most people, except when you >actually >care about running the same binary kernel on older platforms. > >I tried to get a complete list of CPU cores with idiv, lpae and >virtualization support at some point, but I don't remember the >details for all Qualcomm and Marvell cores any more, to create the >complete configuration matrix. IIRC, all CPUs that support >virtualization also do lpae (they have to) and all CPUs that >do lpae also do idiv, but the opposite is not true. > > Arnd The ARM ARM says anything with virt has idiv, lpae doesn't matter. ARMv7-R also has idiv. I've no idea if anyone runs Linux on those though. -- Måns Rullgård -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
On Friday 20 November 2015 17:23:14 Stephen Boyd wrote: > This is a respin of a patch series from about a year ago[1]. I realized > that we already had most of the code in recordmcount to figure out > where we make calls to particular functions, so recording where > we make calls to the integer division functions should be easy enough > to add support for in the same codepaths. Looking back on the thread > it seems like Mans was thinking along the same lines, although it wasn't > obvious to me back then or even over the last few days when I wrote this. Shouldn't we start by allowing to build the kernel for -march=armv7ve on platforms that allow it? That would seem like a simpler change and likely generate better code for most people, except when you actually care about running the same binary kernel on older platforms. I tried to get a complete list of CPU cores with idiv, lpae and virtualization support at some point, but I don't remember the details for all Qualcomm and Marvell cores any more, to create the complete configuration matrix. IIRC, all CPUs that support virtualization also do lpae (they have to) and all CPUs that do lpae also do idiv, but the opposite is not true. Arnd -- To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC/PATCH 0/3] ARM: Use udiv/sdiv for __aeabi_{u}idiv library functions
This is a respin of a patch series from about a year ago[1]. I realized
that we already had most of the code in recordmcount to figure out
where we make calls to particular functions, so recording where
we make calls to the integer division functions should be easy enough
to add support for in the same codepaths. Looking back on the thread
it seems like Mans was thinking along the same lines, although it wasn't
obvious to me back then or even over the last few days when I wrote this.
This series extends recordmcount to record the locations of the calls
to the library functions on ARM builds, and puts those locations into a
table that we use to patch instructions at boot. The first two patches
are the recordmcount changes, while the last patch implements the runtime
patching for modules and kernel code. The module part also hooks into the
relocation patching code we already have.
The RFC tag is because I'm thinking of splitting the recordmcount changes
into a new program based on recordmcount so that we don't drag in a lot
of corner cases and stuff when we don't need to. I suspect it will be
cleaner that way too. Does anyone prefer one way or the other?
Comments/feedback appreciated.
[1]
http://lkml.kernel.org/r/1383951632-6090-1-git-send-email-sb...@codeaurora.org
Cc: Nicolas Pitre
Cc: Arnd Bergmann
Cc: Steven Rostedt
Cc: Måns Rullgård
Stephen Boyd (3):
scripts: Allow recordmcount to be used without tracing enabled
recordmcount: Record locations of __aeabi_{u}idiv() calls on ARM
ARM: Replace calls to __aeabi_{u}idiv with udiv/sdiv instructions
Makefile | 7 +
arch/arm/Kconfig | 14 ++
arch/arm/kernel/module.c | 44 ++
arch/arm/kernel/setup.c | 34 +
arch/arm/kernel/vmlinux.lds.S | 13 ++
kernel/trace/Kconfig | 4 +
scripts/Makefile.build| 15 +-
scripts/recordmcount.c| 10 +-
scripts/recordmcount.h| 337 +-
scripts/recordmcount.pl | 11 +-
10 files changed, 406 insertions(+), 83 deletions(-)
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