Re: [PATCH v2 1/3] clk: bcm2835: Add bindings for the auxiliary peripheral clock gates.
On Tue, Dec 15, 2015 at 03:35:57PM -0800, Eric Anholt wrote: > These will be used for enabling UART1, SPI1, and SPI2. > > Signed-off-by: Eric Anholt > --- > > v2: Make the binding cover both the IRQ and clock enable registers. > > .../bindings/clock/brcm,bcm2835-aux-clock.txt | 31 > ++ > include/dt-bindings/clock/bcm2835-aux.h| 17 > 2 files changed, 48 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/clock/brcm,bcm2835-aux-clock.txt > create mode 100644 include/dt-bindings/clock/bcm2835-aux.h Acked-by: Rob Herring -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] clk: rockchip: only enter pll slow-mode directly before reboots on rk3288
Heiko,
On Fri, Dec 18, 2015 at 10:33 AM, Heiko Stübner
wrote:
> As commit 1d33929e2a2b ("clk: rockchip: switch PLLs to slow mode before
> reboot for rk3288") states, switching the PLLs to slow-mode is only
> necessary when rebooting using the soft-reset done through the CRU.
>
> The dwc2 controllers used create really big number of interrupts in
> special constellations involving usb-hubs and their number is so high,
> it can even overwhelm the interrupt handler if the cpu-speed os to low.
>
> Right now the PLLs are put into slow-mode in a shutdown syscore_ops
> callback which means it happens on all reboots (not only the soft-reset
> ones) and even on poweroff actions.
>
> This can result in the system not powering off and getting stuck instead,
> so we should move the slow-mode change nearer to the actual reboot action.
>
> For this we introduce the possiblity to also set a callback that gets
> called from the restart-handler directly prior to restarting the system
> and move the shutdown-callback to this new option.
>
> With this the slow-mode switch is done only on the necessary reboots
> and also has a smaller possibility of causing artifacts.
>
> Fixes: 1d33929e2a2b ("clk: rockchip: switch PLLs to slow mode before reboot
> for rk3288")
> Signed-off-by: Heiko Stuebner
> ---
> drivers/clk/rockchip/clk-rk3036.c | 2 +-
> drivers/clk/rockchip/clk-rk3188.c | 2 +-
> drivers/clk/rockchip/clk-rk3228.c | 2 +-
> drivers/clk/rockchip/clk-rk3288.c | 4 ++--
> drivers/clk/rockchip/clk-rk3368.c | 2 +-
> drivers/clk/rockchip/clk.c| 7 ++-
> drivers/clk/rockchip/clk.h| 2 +-
> 7 files changed, 13 insertions(+), 8 deletions(-)
Reviewed-by: Douglas Anderson
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[PATCH] clk: rockchip: only enter pll slow-mode directly before reboots on rk3288
As commit 1d33929e2a2b ("clk: rockchip: switch PLLs to slow mode before
reboot for rk3288") states, switching the PLLs to slow-mode is only
necessary when rebooting using the soft-reset done through the CRU.
The dwc2 controllers used create really big number of interrupts in
special constellations involving usb-hubs and their number is so high,
it can even overwhelm the interrupt handler if the cpu-speed os to low.
Right now the PLLs are put into slow-mode in a shutdown syscore_ops
callback which means it happens on all reboots (not only the soft-reset
ones) and even on poweroff actions.
This can result in the system not powering off and getting stuck instead,
so we should move the slow-mode change nearer to the actual reboot action.
For this we introduce the possiblity to also set a callback that gets
called from the restart-handler directly prior to restarting the system
and move the shutdown-callback to this new option.
With this the slow-mode switch is done only on the necessary reboots
and also has a smaller possibility of causing artifacts.
Fixes: 1d33929e2a2b ("clk: rockchip: switch PLLs to slow mode before reboot for
rk3288")
Signed-off-by: Heiko Stuebner
---
drivers/clk/rockchip/clk-rk3036.c | 2 +-
drivers/clk/rockchip/clk-rk3188.c | 2 +-
drivers/clk/rockchip/clk-rk3228.c | 2 +-
drivers/clk/rockchip/clk-rk3288.c | 4 ++--
drivers/clk/rockchip/clk-rk3368.c | 2 +-
drivers/clk/rockchip/clk.c| 7 ++-
drivers/clk/rockchip/clk.h| 2 +-
7 files changed, 13 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3036.c
b/drivers/clk/rockchip/clk-rk3036.c
index 75553af..1651f7d 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -473,6 +473,6 @@ static void __init rk3036_clk_init(struct device_node *np)
rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
ROCKCHIP_SOFTRST_HIWORD_MASK);
- rockchip_register_restart_notifier(RK2928_GLB_SRST_FST);
+ rockchip_register_restart_notifier(RK2928_GLB_SRST_FST, NULL);
}
CLK_OF_DECLARE(rk3036_cru, "rockchip,rk3036-cru", rk3036_clk_init);
diff --git a/drivers/clk/rockchip/clk-rk3188.c
b/drivers/clk/rockchip/clk-rk3188.c
index 7836a97..3521f6f 100644
--- a/drivers/clk/rockchip/clk-rk3188.c
+++ b/drivers/clk/rockchip/clk-rk3188.c
@@ -745,7 +745,7 @@ static void __init rk3188_common_clk_init(struct
device_node *np)
rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
ROCKCHIP_SOFTRST_HIWORD_MASK);
- rockchip_register_restart_notifier(RK2928_GLB_SRST_FST);
+ rockchip_register_restart_notifier(RK2928_GLB_SRST_FST, NULL);
}
static void __init rk3066a_clk_init(struct device_node *np)
diff --git a/drivers/clk/rockchip/clk-rk3228.c
b/drivers/clk/rockchip/clk-rk3228.c
index 87a7e59..981a502 100644
--- a/drivers/clk/rockchip/clk-rk3228.c
+++ b/drivers/clk/rockchip/clk-rk3228.c
@@ -673,6 +673,6 @@ static void __init rk3228_clk_init(struct device_node *np)
rockchip_register_softrst(np, 9, reg_base + RK2928_SOFTRST_CON(0),
ROCKCHIP_SOFTRST_HIWORD_MASK);
- rockchip_register_restart_notifier(RK3228_GLB_SRST_FST);
+ rockchip_register_restart_notifier(RK3228_GLB_SRST_FST, NULL);
}
CLK_OF_DECLARE(rk3228_cru, "rockchip,rk3228-cru", rk3228_clk_init);
diff --git a/drivers/clk/rockchip/clk-rk3288.c
b/drivers/clk/rockchip/clk-rk3288.c
index 3ecaa9d..2a6eca0 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -848,7 +848,6 @@ static void rk3288_clk_shutdown(void)
static struct syscore_ops rk3288_clk_syscore_ops = {
.suspend = rk3288_clk_suspend,
.resume = rk3288_clk_resume,
- .shutdown = rk3288_clk_shutdown,
};
static void __init rk3288_clk_init(struct device_node *np)
@@ -900,7 +899,8 @@ static void __init rk3288_clk_init(struct device_node *np)
rk3288_cru_base + RK3288_SOFTRST_CON(0),
ROCKCHIP_SOFTRST_HIWORD_MASK);
- rockchip_register_restart_notifier(RK3288_GLB_SRST_FST);
+ rockchip_register_restart_notifier(RK3288_GLB_SRST_FST,
+ rk3288_clk_shutdown);
register_syscore_ops(&rk3288_clk_syscore_ops);
}
CLK_OF_DECLARE(rk3288_cru, "rockchip,rk3288-cru", rk3288_clk_init);
diff --git a/drivers/clk/rockchip/clk-rk3368.c
b/drivers/clk/rockchip/clk-rk3368.c
index 1faf160..be0ede5 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -889,6 +889,6 @@ static void __init rk3368_clk_init(struct device_node *np)
rockchip_register_softrst(np, 15, reg_base + RK3368_SOFTRST_CON(0),
ROCKCHIP_SOFTRST_HIWORD_MASK);
- rockchip_register_restart_notifier(RK3368_GLB_SRST_FST);
+ rockchip_register_restart_notifier(RK3368_GLB_SRST_FST, NULL)
Re: [PATCH v2 0/4] Add Cygnus audio clock support
Hi Stephen/Michael, If these clock changes look fine to you, can they be merged for v4.5? Thanks, Ray On 12/3/2015 9:37 AM, Ray Jui wrote: Hi Stephen/Mike, Do these clock changes look okay to you? Thanks, Ray On 11/24/2015 4:13 PM, Florian Fainelli wrote: On 23/11/15 09:50, Ray Jui wrote: This patch series adds support for the Cygnus audio clock based on existing iProc clock support This patch series is developed based on v4.4-rc1 with full tree available on GITHUB: repo: https://github.com/Broadcom/cygnus-linux.git branch: cygnus-audio-clk-v2 Changes from v1: - Remove function prototype of a non-exist function 'iproc_audiopll_clk_setup' - Remove __init macros from all functions prototypes in iproc-clk.h Ray Jui (1): clk: iproc: Remove __init from header Simran Rai (3): Documentation: dt-bindings: Add DT bindings for Cygnus audio clock clk: iproc: Add support for Cygnus audio clocks ARM: dts: enable audio clock support for Cygnus Stephen, Mike, do these clock changes look sensible to you? If so, could you also put the drivers/clk/ changes in a branch that I could merge as part of including the DTS changes? Thanks! -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH] clk: tegra: Fix clock sources for tegra210 EMC
On 12/18/2015 8:45 AM, Jon Hunter wrote:
> The EMC clock sources for tegra210 currently incorrectly include pll_c2
> and pll_c3. However, both of these should have been pll_mb as shown in
> the TRM. If tegra210 happens to be configured such that the pll_mb is the
> default clock for the EMC, as configured by the bootloader, then this will
> cause a system hang on boot. This is because the kernel will disable the
> pll_mb when disabling unused clock as it appears to be unused when it is
> not.
>
> Also add the additional pll_p clock source for the EMC.
>
> Signed-off-by: Jon Hunter
> ---
> drivers/clk/tegra/clk-tegra210.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/tegra/clk-tegra210.c
> b/drivers/clk/tegra/clk-tegra210.c
> index 58514c44ea83..849be30b52bf 100644
> --- a/drivers/clk/tegra/clk-tegra210.c
> +++ b/drivers/clk/tegra/clk-tegra210.c
> @@ -243,7 +243,8 @@ static unsigned long tegra210_input_freq[] = {
> };
>
> static const char *mux_pllmcp_clkm[] = {
> - "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_c2", "pll_c3",
> + "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_mb", "pll_mb",
> + "pll_p",
> };
> #define mux_pllmcp_clkm_idx NULL
>
>
Acked-by: Rhyland Klein
-rhyland
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Re: [RFC 6/9] clk: ti: add support for omap4 module clocks
* Tero Kristo [151218 05:57]:
> Previously, hwmod core has been used for controlling the hwmod level
> clocks. This has certain drawbacks, like being unable to share the
> clocks for multiple users, missing usecounting and generally being
> totally incompatible with common clock framework.
>
> Add support for new clock type under the TI clock driver, which will
> be used to convert all the existing hwmod clocks to. This helps to
> get rid of the clock related hwmod data from kernel and instead
> parsing this from DT.
Good to see this happening, few comments on what I've noticed so
far that should be considered.
We should be able to do a generic "ti,mux-div-gate" clock and use
it for the clkctrl too I think. See the suggested binding elsewhere
in this thread. That would also work for the clkout register at least.
Maybe the "ti,mux-div-gate" clock needs a separate clkctrl type
compatible to know it needs to sleep to wait for the status bit.
Also, we already know these clkctrl register do have multiple clocks,
like the GPIO debounce and dividers for debugss clock. And we want
to get rid of the overlapping reg entries.
> +static int _omap4_hwmod_clk_enable(struct clk_hw *hw)
> +{
> + struct clk_hw_omap *clk = to_clk_hw_omap(hw);
> + u32 val;
> + int timeout = 0;
> + int ret;
> +
> + if (!clk->enable_bit)
> + return 0;
> +
> + if (clk->clkdm) {
> + ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk);
> + if (ret) {
> + WARN(1,
> + "%s: could not enable %s's clockdomain %s: %d\n",
> + __func__, clk_hw_get_name(hw),
> + clk->clkdm_name, ret);
> + return ret;
> + }
> + }
> +
> + val = ti_clk_ll_ops->clk_readl(clk->enable_reg);
> +
> + val &= ~OMAP4_MODULEMODE_MASK;
> + val |= clk->enable_bit;
> +
> + ti_clk_ll_ops->clk_writel(val, clk->enable_reg);
> +
> + /* Wait until module is enabled */
> + while (!_omap4_is_ready(val)) {
> + udelay(1);
> + timeout++;
> + if (timeout > OMAP4_MAX_MODULE_READY_TIME) {
> + pr_err("%s: failed to enable\n", clk_hw_get_name(hw));
> + return -EBUSY;
> + }
> + val = ti_clk_ll_ops->clk_readl(clk->enable_reg);
> + }
> +
> + return 0;
> +}
Clocks that need to wait to lock need to be set up with clk_prepare
instead of clk_enable as pointed out by TGLX recently. Also see the
"[PATCH] clk: ti: Fix FAPLL udelay in clk_enable with clk_prepare".
Not sure what all needs to be fixed in the hwmod code for that to
happen and PM to work, but that probably needs to be done first.
Regards,
Tony
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Re: [RFC 8/9] ARM: OMAP4: hwmod_data: use module clocks from DT
* Tero Kristo [151218 05:57]:
> Replace the usage of prcm->clkstctrl with main_clk:s provided via DT.
> This is done in preparation to get rid of hwmod data from kernel.
...
> --- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> +++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
> @@ -334,10 +329,9 @@ static struct omap_hwmod omap44xx_counter_32k_hwmod = {
> .class = &omap44xx_counter_hwmod_class,
> .clkdm_name = "l4_wkup_clkdm",
> .flags = HWMOD_SWSUP_SIDLE,
> - .main_clk = "sys_32k_ck",
> + .main_clk = "counter_32k_mod_ck",
> .prcm = {
> .omap4 = {
> - .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET,
> .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET,
> },
> },
Care to describe why the main_clk now needs to be modified or
added? Can that too come from dts now?
Regards,
Tony
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Re: [RFC 1/9] ARM: OMAP2+: omap_device: create clock alias purely from DT data
* Tero Kristo [151218 05:57]: > This avoids the need to add most of the clock aliases under > drivers/clk/ti/clk-xyz.c files. Yup is badly needed. Right now we have strange hidden dependencies in multiple subsystems to enable a single device driver: 1. Add a clock alias for a device 2. Add hwmod entries for a device 3. Add dts entries for a device 4. Add a device driver We really should only need steps 3 and 4 to do that, hopefully this takes out #1 on the list above. Regards, Tony -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [RFC 7/9] ARM: dts: omap4: add hwmod module clocks
* Tero Kristo [151218 05:57]:
> + mmu_dsp_mod_ck: mmu_dsp_mod_ck {
> + #clock-cells = <0>;
> + compatible = "ti,omap4-hw-mod-clock";
> + reg = <0x0420>;
> + clocks = <&dpll_iva_m4x2_ck>;
> + };
> +
> + dsp_mod_ck: dsp_mod_ck {
> + #clock-cells = <0>;
> + compatible = "ti,omap4-hw-mod-clock";
> + reg = <0x0420>;
> + clocks = <&dpll_iva_m4x2_ck>;
> + };
In general we should get rid of the overlapping reg entries
for clocks. That's a separate patch series for sure.. But I
think it can be done simply with something like this probably
for all of them (totally untested):
mux_div_gate_ck: clk@420 {
#clock-cells = <1>;
compatible = "ti,mux-divider-gate";
clock-indices = <0>, <1>;
clock-output-names = "mux", "div", "gate";
reg = <0x420 0x4>;
foo_mux_ck: clock@0 {
reg = <0>;
compatible = "ti,mux-clock";
};
foo_div_ck: clock@8 {
reg = <8>;
compatible = "ti,divider-clock";
ti,max-div = <31>;
};
foo_gate_ck: clock@16 {
reg = <16>;
compatible = "ti,gate-clock";
clocks = <&mux_source_ck>;
};
};
Then the output can be referenced with the standard clock binding
index. For example to use the mux clock:
clocks = <&mux_div_gate_ck 0>;
Regards,
Tony
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[RFC 3/9] clk: ti: remove un-used definitions from public clk_hw_omap struct
Clksel support has been deprecated a while back, so remove these from
the struct also.
Signed-off-by: Tero Kristo
---
include/linux/clk/ti.h |4
1 file changed, 4 deletions(-)
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 223be69..ec5613a 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -127,8 +127,6 @@ struct clk_hw_omap_ops {
* @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
* @flags: see "struct clk.flags possibilities" above
* @clksel_reg: for clksel clks, register va containing src/divisor select
- * @clksel_mask: bitmask in @clksel_reg for the src/divisor selector
- * @clksel: for clksel clks, pointer to struct clksel for this clock
* @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
* @clkdm_name: clockdomain name that this clock is contained in
* @clkdm: pointer to struct clockdomain, resolved from @clkdm_name at runtime
@@ -143,8 +141,6 @@ struct clk_hw_omap {
u8 enable_bit;
u8 flags;
void __iomem*clksel_reg;
- u32 clksel_mask;
- const struct clksel *clksel;
struct dpll_data*dpll_data;
const char *clkdm_name;
struct clockdomain *clkdm;
--
1.7.9.5
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[RFC 2/9] ARM: OMAP2+: hwmod: initialize main clocks directly from DT
This avoids the need to add clock aliases under drivers/clk/ti/clk-xyz.c
files.
Signed-off-by: Tero Kristo
---
arch/arm/mach-omap2/omap_hwmod.c | 19 ++-
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 48495ad..5fa8965 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -786,11 +786,20 @@ static int _init_main_clk(struct omap_hwmod *oh)
if (!oh->main_clk)
return 0;
- oh->_clk = clk_get(NULL, oh->main_clk);
- if (IS_ERR(oh->_clk)) {
- pr_warn("omap_hwmod: %s: cannot clk_get main_clk %s\n",
- oh->name, oh->main_clk);
- return -EINVAL;
+ if (of_have_populated_dt()) {
+ struct of_phandle_args clkspec;
+
+ clkspec.np = of_find_node_by_name(NULL, oh->main_clk);
+ oh->_clk = of_clk_get_from_provider(&clkspec);
+ }
+
+ if (!oh->_clk) {
+ oh->_clk = clk_get(NULL, oh->main_clk);
+ if (IS_ERR(oh->_clk)) {
+ pr_warn("omap_hwmod: %s: cannot clk_get main_clk %s\n",
+ oh->name, oh->main_clk);
+ return -EINVAL;
+ }
}
/*
* HACK: This needs a re-visit once clk_prepare() is implemented
--
1.7.9.5
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[RFC 0/9] ARM: OMAP4: hwmod clkctrl conversion to DT + clock driver
Hi, This series adds support for hwmod gate clock type, and changes OMAP4 as an example to use the new clock type, converting the existing hwmod_data clkctrl definitions to clock nodes under device tree. Some additional magic is required for handling timer clocks, as the clock driver assumes it can do mux operations on the hwmod main clock, the mux-mod clock type variants are for this purpose. The data files have been automatically converted by scripting, so doing the same conversion for any AMxyz / OMAP4+ SoC should be relatively easy to do. Boot tested on OMAP4 panda ES board, also tried that suspend-resume / cpuidle works fine. Testing done on top of 4.4-rc3. This series is one part of the work to get rid of hwmod data from kernel. -Tero -- To unsubscribe from this list: send the line "unsubscribe linux-clk" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[RFC 8/9] ARM: OMAP4: hwmod_data: use module clocks from DT
Replace the usage of prcm->clkstctrl with main_clk:s provided via DT.
This is done in preparation to get rid of hwmod data from kernel.
Signed-off-by: Tero Kristo
---
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 339
1 file changed, 95 insertions(+), 244 deletions(-)
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index a5e444b..8da75eb 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -67,10 +67,10 @@ static struct omap_hwmod omap44xx_dmm_hwmod = {
.clkdm_name = "l3_emif_clkdm",
.prcm = {
.omap4 = {
- .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
},
},
+ .main_clk = "dmm_mod_ck",
};
/*
@@ -88,11 +88,10 @@ static struct omap_hwmod omap44xx_l3_instr_hwmod = {
.clkdm_name = "l3_instr_clkdm",
.prcm = {
.omap4 = {
- .clkctrl_offs =
OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
.context_offs =
OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
},
},
+ .main_clk = "l3_instr_mod_ck",
};
/* l3_main_1 */
@@ -102,10 +101,10 @@ static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
.clkdm_name = "l3_1_clkdm",
.prcm = {
.omap4 = {
- .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
},
},
+ .main_clk = "l3_main_1_mod_ck",
};
/* l3_main_2 */
@@ -115,10 +114,10 @@ static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
.clkdm_name = "l3_2_clkdm",
.prcm = {
.omap4 = {
- .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
},
},
+ .main_clk = "l3_main_2_mod_ck",
};
/* l3_main_3 */
@@ -128,11 +127,10 @@ static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
.clkdm_name = "l3_instr_clkdm",
.prcm = {
.omap4 = {
- .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
},
},
+ .main_clk = "l3_main_3_mod_ck",
};
/*
@@ -150,12 +148,12 @@ static struct omap_hwmod omap44xx_l4_abe_hwmod = {
.clkdm_name = "abe_clkdm",
.prcm = {
.omap4 = {
- .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
.lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
.flags= HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
},
},
+ .main_clk = "l4_abe_mod_ck",
};
/* l4_cfg */
@@ -165,10 +163,10 @@ static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
.clkdm_name = "l4_cfg_clkdm",
.prcm = {
.omap4 = {
- .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
},
},
+ .main_clk = "l4_cfg_mod_ck",
};
/* l4_per */
@@ -178,10 +176,10 @@ static struct omap_hwmod omap44xx_l4_per_hwmod = {
.clkdm_name = "l4_per_clkdm",
.prcm = {
.omap4 = {
- .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
},
},
+ .main_clk = "l4_per_mod_ck",
};
/* l4_wkup */
@@ -191,10 +189,10 @@ static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
.clkdm_name = "l4_wkup_clkdm",
.prcm = {
.omap4 = {
- .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
},
},
+ .main_clk = "l4_wkup_mod_ck",
};
/*
@@ -232,11 +230,10 @@ static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
.clkdm_name = "l3_instr_clkdm",
.prcm = {
.omap4 = {
- .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
.context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
},
},
+ .main_clk = "ocp_wp_noc_mod_ck",
};
/*
@@ -276,13 +273,11 @@ static struct omap_hwmod omap44xx_aess_hwmod = {
[RFC 9/9] clk: ti: omap4: update clock aliases to reflect new module clocks
The clock data in DT has been updated, and the clock aliases must be
updated to match.
Signed-off-by: Tero Kristo
---
drivers/clk/ti/clk-44xx.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/ti/clk-44xx.c b/drivers/clk/ti/clk-44xx.c
index 7a8b51b..81cd26e 100644
--- a/drivers/clk/ti/clk-44xx.c
+++ b/drivers/clk/ti/clk-44xx.c
@@ -164,17 +164,17 @@ static struct ti_dt_clk omap44xx_clks[] = {
DT_CLK(NULL, "smartreflex_core_fck", "smartreflex_core_fck"),
DT_CLK(NULL, "smartreflex_iva_fck", "smartreflex_iva_fck"),
DT_CLK(NULL, "smartreflex_mpu_fck", "smartreflex_mpu_fck"),
- DT_CLK(NULL, "dmt1_clk_mux", "dmt1_clk_mux"),
- DT_CLK(NULL, "cm2_dm10_mux", "cm2_dm10_mux"),
- DT_CLK(NULL, "cm2_dm11_mux", "cm2_dm11_mux"),
- DT_CLK(NULL, "cm2_dm2_mux", "cm2_dm2_mux"),
- DT_CLK(NULL, "cm2_dm3_mux", "cm2_dm3_mux"),
- DT_CLK(NULL, "cm2_dm4_mux", "cm2_dm4_mux"),
- DT_CLK(NULL, "timer5_sync_mux", "timer5_sync_mux"),
- DT_CLK(NULL, "timer6_sync_mux", "timer6_sync_mux"),
- DT_CLK(NULL, "timer7_sync_mux", "timer7_sync_mux"),
- DT_CLK(NULL, "timer8_sync_mux", "timer8_sync_mux"),
- DT_CLK(NULL, "cm2_dm9_mux", "cm2_dm9_mux"),
+ DT_CLK(NULL, "timer1_mod_ck", "timer1_mod_ck"),
+ DT_CLK(NULL, "timer10_mod_ck", "timer10_mod_ck"),
+ DT_CLK(NULL, "timer11_mod_ck", "timer11_mod_ck"),
+ DT_CLK(NULL, "timer2_mod_ck", "timer2_mod_ck"),
+ DT_CLK(NULL, "timer3_mod_ck", "timer3_mod_ck"),
+ DT_CLK(NULL, "timer4_mod_ck", "timer4_mod_ck"),
+ DT_CLK(NULL, "timer5_mod_ck", "timer5_mod_ck"),
+ DT_CLK(NULL, "timer6_mod_ck", "timer6_mod_ck"),
+ DT_CLK(NULL, "timer7_mod_ck", "timer7_mod_ck"),
+ DT_CLK(NULL, "timer8_mod_ck", "timer8_mod_ck"),
+ DT_CLK(NULL, "timer9_mod_ck", "timer9_mod_ck"),
DT_CLK(NULL, "usb_host_fs_fck", "usb_host_fs_fck"),
DT_CLK("usbhs_omap", "fs_fck", "usb_host_fs_fck"),
DT_CLK(NULL, "utmi_p1_gfclk", "utmi_p1_gfclk"),
--
1.7.9.5
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[RFC 4/9] clk: ti: mux: export mux clock APIs locally
get_parent and set_parent are going to be required by the support of
module clocks, so export these locally.
Signed-off-by: Tero Kristo
---
drivers/clk/ti/clock.h |3 +++
drivers/clk/ti/mux.c |4 ++--
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h
index 90f3f47..7eca8a1 100644
--- a/drivers/clk/ti/clock.h
+++ b/drivers/clk/ti/clock.h
@@ -224,6 +224,9 @@ extern const struct clk_hw_omap_ops
clkhwops_am35xx_ipss_wait;
extern const struct clk_ops ti_clk_divider_ops;
extern const struct clk_ops ti_clk_mux_ops;
+u8 ti_clk_mux_get_parent(struct clk_hw *hw);
+int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index);
+
int omap2_clkops_enable_clkdm(struct clk_hw *hw);
void omap2_clkops_disable_clkdm(struct clk_hw *hw);
diff --git a/drivers/clk/ti/mux.c b/drivers/clk/ti/mux.c
index 69f08a1..d723dad 100644
--- a/drivers/clk/ti/mux.c
+++ b/drivers/clk/ti/mux.c
@@ -28,7 +28,7 @@
#define to_clk_mux(_hw) container_of(_hw, struct clk_mux, hw)
-static u8 ti_clk_mux_get_parent(struct clk_hw *hw)
+u8 ti_clk_mux_get_parent(struct clk_hw *hw)
{
struct clk_mux *mux = to_clk_mux(hw);
int num_parents = clk_hw_get_num_parents(hw);
@@ -65,7 +65,7 @@ static u8 ti_clk_mux_get_parent(struct clk_hw *hw)
return val;
}
-static int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
+int ti_clk_mux_set_parent(struct clk_hw *hw, u8 index)
{
struct clk_mux *mux = to_clk_mux(hw);
u32 val;
--
1.7.9.5
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[RFC 7/9] ARM: dts: omap4: add hwmod module clocks
Add clock nodes for the SoC hwmods. This is done in preparation to remove
hwmod data from kernel, hwmod will use the clock nodes instead for
module level enable / disable logic.
Signed-off-by: Tero Kristo
---
arch/arm/boot/dts/omap44xx-clocks.dtsi | 854 +---
1 file changed, 781 insertions(+), 73 deletions(-)
diff --git a/arch/arm/boot/dts/omap44xx-clocks.dtsi
b/arch/arm/boot/dts/omap44xx-clocks.dtsi
index f2c48f0..1d3e0b8 100644
--- a/arch/arm/boot/dts/omap44xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap44xx-clocks.dtsi
@@ -183,6 +183,20 @@
reg = <0x0528>;
};
+ aess_mod_ck: aess_mod_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0528>;
+ clocks = <&aess_fclk>;
+ };
+
+ mcpdm_mod_ck: mcpdm_mod_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0530>;
+ clocks = <&pad_clks_ck>;
+ };
+
dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
#clock-cells = <0>;
compatible = "ti,divider-clock";
@@ -194,6 +208,34 @@
ti,invert-autoidle-bit;
};
+ mpu_mod_ck: mpu_mod_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0320>;
+ clocks = <&dpll_mpu_m2_ck>;
+ };
+
+ mmu_dsp_mod_ck: mmu_dsp_mod_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0420>;
+ clocks = <&dpll_iva_m4x2_ck>;
+ };
+
+ dsp_mod_ck: dsp_mod_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x0420>;
+ clocks = <&dpll_iva_m4x2_ck>;
+ };
+
+ l4_abe_mod_ck: l4_abe_mod_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-mod-clock";
+ reg = <0x0520>;
+ clocks = <&ocp_abe_iclk>;
+ };
+
core_hsd_byp_clk_mux_ck: core_hsd_byp_clk_mux_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -480,6 +522,13 @@
reg = <0x0538>;
};
+ dmic_mod_ck: dmic_mod_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0538>;
+ clocks = <&func_dmic_abe_gfclk>;
+ };
+
func_dmic_abe_gfclk: func_dmic_abe_gfclk {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -496,6 +545,13 @@
reg = <0x0540>;
};
+ mcasp_mod_ck: mcasp_mod_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0540>;
+ clocks = <&func_mcasp_abe_gfclk>;
+ };
+
func_mcasp_abe_gfclk: func_mcasp_abe_gfclk {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -520,6 +576,13 @@
reg = <0x0548>;
};
+ mcbsp1_mod_ck: mcbsp1_mod_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0548>;
+ clocks = <&func_mcbsp1_gfclk>;
+ };
+
mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -536,6 +599,13 @@
reg = <0x0550>;
};
+ mcbsp2_mod_ck: mcbsp2_mod_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0550>;
+ clocks = <&func_mcbsp2_gfclk>;
+ };
+
mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
@@ -552,6 +622,13 @@
reg = <0x0558>;
};
+ mcbsp3_mod_ck: mcbsp3_mod_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x0558>;
+ clocks = <&func_mcbsp3_gfclk>;
+ };
+
slimbus1_fclk_1: slimbus1_fclk_1 {
#clock-cells = <0>;
compatible = "ti,gate-clock";
@@ -568,52 +645,66 @@
reg = <0x0560>;
};
- slimbus1_fclk_2: slimbus1_fclk_2 {
+ slimbus1_mod_ck: slimbus1_mod_ck {
#clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&pad_clks_ck>;
- ti,bit-shift = <10>;
+ compatible = "ti,omap4-sw-mod-clock";
reg = <0x0560>;
+ clocks = <&slimbus1_fclk_0>;
};
- slimbus1_slimbus_clk: slimbus1_slimbus_clk {
+ timer5_mod_ck: timer5_mod_ck {
#clock-cells = <0>;
- compatible = "ti,gate-clock";
- clocks = <&slimbus_
[RFC 6/9] clk: ti: add support for omap4 module clocks
Previously, hwmod core has been used for controlling the hwmod level
clocks. This has certain drawbacks, like being unable to share the
clocks for multiple users, missing usecounting and generally being
totally incompatible with common clock framework.
Add support for new clock type under the TI clock driver, which will
be used to convert all the existing hwmdo clocks to. This helps to
get rid of the clock related hwmod data from kernel and instead
parsing this from DT.
Signed-off-by: Tero Kristo
---
drivers/clk/ti/Makefile |3 +-
drivers/clk/ti/clkt_mod.c | 351 +
include/linux/clk/ti.h|2 +
3 files changed, 355 insertions(+), 1 deletion(-)
create mode 100644 drivers/clk/ti/clkt_mod.c
diff --git a/drivers/clk/ti/Makefile b/drivers/clk/ti/Makefile
index d4ac960..d1b9d41 100644
--- a/drivers/clk/ti/Makefile
+++ b/drivers/clk/ti/Makefile
@@ -1,7 +1,8 @@
obj-y += clk.o autoidle.o clockdomain.o
clk-common = dpll.o composite.o divider.o gate.o \
fixed-factor.o mux.o apll.o \
- clkt_dpll.o clkt_iclk.o clkt_dflt.o
+ clkt_dpll.o clkt_iclk.o clkt_dflt.o \
+ clkt_mod.o
obj-$(CONFIG_SOC_AM33XX) += $(clk-common) clk-33xx.o dpll3xxx.o
obj-$(CONFIG_SOC_TI81XX) += $(clk-common) fapll.o clk-814x.o
clk-816x.o
obj-$(CONFIG_ARCH_OMAP2) += $(clk-common) interface.o clk-2xxx.o
diff --git a/drivers/clk/ti/clkt_mod.c b/drivers/clk/ti/clkt_mod.c
new file mode 100644
index 000..186d5f7
--- /dev/null
+++ b/drivers/clk/ti/clkt_mod.c
@@ -0,0 +1,351 @@
+/*
+ * OMAP hardware module clock support
+ *
+ * Copyright (C) 2015 Texas Instruments, Inc.
+ *
+ * Tero Kristo
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include "clock.h"
+
+#undef pr_fmt
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#define OMAP4_MODULEMODE_MASK 0x3
+
+#define MODULEMODE_HWCTRL 0x1
+#define MODULEMODE_SWCTRL 0x2
+
+#define OMAP4_IDLEST_MASK (0x3 << 16)
+#define OMAP4_IDLEST_SHIFT 16
+
+#define CLKCTRL_IDLEST_FUNCTIONAL 0x0
+#define CLKCTRL_IDLEST_INTERFACE_IDLE 0x2
+#define CLKCTRL_IDLEST_DISABLED0x3
+
+#define OMAP4_MAX_MODULE_READY_TIME2000
+#define OMAP4_MAX_MODULE_DISABLE_TIME 5000
+
+static u32 _omap4_idlest(u32 val)
+{
+ val &= OMAP4_IDLEST_MASK;
+ val >>= OMAP4_IDLEST_SHIFT;
+
+ return val;
+}
+
+static bool _omap4_is_idle(u32 val)
+{
+ val = _omap4_idlest(val);
+
+ return val == CLKCTRL_IDLEST_DISABLED;
+}
+
+static bool _omap4_is_ready(u32 val)
+{
+ val = _omap4_idlest(val);
+
+ return val == CLKCTRL_IDLEST_FUNCTIONAL ||
+ val == CLKCTRL_IDLEST_INTERFACE_IDLE;
+}
+
+static int _omap4_hwmod_clk_enable(struct clk_hw *hw)
+{
+ struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+ u32 val;
+ int timeout = 0;
+ int ret;
+
+ if (!clk->enable_bit)
+ return 0;
+
+ if (clk->clkdm) {
+ ret = ti_clk_ll_ops->clkdm_clk_enable(clk->clkdm, hw->clk);
+ if (ret) {
+ WARN(1,
+"%s: could not enable %s's clockdomain %s: %d\n",
+__func__, clk_hw_get_name(hw),
+clk->clkdm_name, ret);
+ return ret;
+ }
+ }
+
+ val = ti_clk_ll_ops->clk_readl(clk->enable_reg);
+
+ val &= ~OMAP4_MODULEMODE_MASK;
+ val |= clk->enable_bit;
+
+ ti_clk_ll_ops->clk_writel(val, clk->enable_reg);
+
+ /* Wait until module is enabled */
+ while (!_omap4_is_ready(val)) {
+ udelay(1);
+ timeout++;
+ if (timeout > OMAP4_MAX_MODULE_READY_TIME) {
+ pr_err("%s: failed to enable\n", clk_hw_get_name(hw));
+ return -EBUSY;
+ }
+ val = ti_clk_ll_ops->clk_readl(clk->enable_reg);
+ }
+
+ return 0;
+}
+
+static void _omap4_hwmod_clk_disable(struct clk_hw *hw)
+{
+ struct clk_hw_omap *clk = to_clk_hw_omap(hw);
+ u32 val;
+ int timeout = 0;
+
+ if (!clk->enable_bit)
+ return;
+
+ val = ti_clk_ll_ops->clk_readl(clk->enable_reg);
+
+ val &= ~OMAP4_M
[RFC 5/9] dt-bindings: clk: ti: Document module clock type
Document the new TI module clock type, which is intended to replace the
internal clock control handling within omap_hwmod. Module clock is
effectively a gate clock controlling both interface and functional
clocks for a single hardware IP block.
Signed-off-by: Tero Kristo
---
.../devicetree/bindings/clock/ti/module.txt| 57
1 file changed, 57 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/ti/module.txt
diff --git a/Documentation/devicetree/bindings/clock/ti/module.txt
b/Documentation/devicetree/bindings/clock/ti/module.txt
new file mode 100644
index 000..a5f70f2
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/module.txt
@@ -0,0 +1,57 @@
+Binding for Texas Instruments module clock.
+
+Binding status: Unstable - ABI compatibility may be broken in the future
+
+This binding uses the common clock binding[1]. This clock is
+quite much similar to the basic gate-clock [2], however, internally
+it controls an OMAP module clock, which effectively handles
+both interface and functional clocks for a single module. In some
+cases, support for mux clock [3] is composited to the same clock node,
+currently only needed for proper support of timer module clocks.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/clock/ti/gate.txt
+[3] Documentation/devicetree/bindings/clock/ti/mux.txt
+
+Required properties:
+- compatible : shall be one of:
+ "ti,omap4-mod-clock" - basic module clock, no gating supported
+ "ti,omap4-hw-mod-clock" - module clock with hardware gating support
+ "ti,omap4-sw-mod-clock" - module clock with software forced gating support
+ "ti,omap4-mux-mod-clock" - composite clock with mux and module clocks, no
+gating supported
+ "ti,omap4-hw-mux-mod-clock" - composite clock with mux and module clocks,
+ with hardware gating
+ "ti,omap4-sw-mux-mod-clock" - composite clock with mux and module clocks,
+ with software forced gating
+
+- #clock-cells : from common clock binding; shall be set to 0
+- clocks : link to phandle of parent clock(s)
+- reg : offset for register controlling adjustable gate and optional mux
+
+Optional properties:
+- ti,bit-shift : bit shift for programming the clock mux, only needed for
+the nodes of the mux variant
+
+Examples:
+ timer6_mod_ck: timer6_mod_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mux-mod-clock";
+ reg = <0x0570>;
+ clocks = <&syc_clk_div_ck>, <&sys_32k_ck>;
+ ti,bit-shift = <24>;
+ };
+
+ i2c1_mod_ck: i2c1_mod_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-sw-mod-clock";
+ reg = <0x14a0>;
+ clocks = <&func_96m_fclk>;
+ };
+
+ hsi_mod_ck: hsi_mod_ck {
+ #clock-cells = <0>;
+ compatible = "ti,omap4-hw-mod-clock";
+ reg = <0x1338>;
+ clocks = <&hsi_fck>;
+ };
--
1.7.9.5
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[RFC 1/9] ARM: OMAP2+: omap_device: create clock alias purely from DT data
This avoids the need to add most of the clock aliases under
drivers/clk/ti/clk-xyz.c files.
Signed-off-by: Tero Kristo
---
arch/arm/mach-omap2/omap_device.c | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/mach-omap2/omap_device.c
b/arch/arm/mach-omap2/omap_device.c
index 72ebc4c..3389ce7 100644
--- a/arch/arm/mach-omap2/omap_device.c
+++ b/arch/arm/mach-omap2/omap_device.c
@@ -62,6 +62,18 @@ static void _add_clkdev(struct omap_device *od, const char
*clk_alias,
return;
}
+ r = clk_get_sys(NULL, clk_name);
+
+ if (IS_ERR(r) && of_have_populated_dt()) {
+ struct of_phandle_args clkspec;
+
+ clkspec.np = of_find_node_by_name(NULL, clk_name);
+
+ r = of_clk_get_from_provider(&clkspec);
+
+ clk_register_clkdev(r, clk_name, NULL);
+ }
+
rc = clk_add_alias(clk_alias, dev_name(&od->pdev->dev), clk_name, NULL);
if (rc) {
if (rc == -ENODEV || rc == -ENOMEM)
--
1.7.9.5
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[PATCH] clk: tegra: Fix clock sources for tegra210 EMC
The EMC clock sources for tegra210 currently incorrectly include pll_c2
and pll_c3. However, both of these should have been pll_mb as shown in
the TRM. If tegra210 happens to be configured such that the pll_mb is the
default clock for the EMC, as configured by the bootloader, then this will
cause a system hang on boot. This is because the kernel will disable the
pll_mb when disabling unused clock as it appears to be unused when it is
not.
Also add the additional pll_p clock source for the EMC.
Signed-off-by: Jon Hunter
---
drivers/clk/tegra/clk-tegra210.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 58514c44ea83..849be30b52bf 100644
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -243,7 +243,8 @@ static unsigned long tegra210_input_freq[] = {
};
static const char *mux_pllmcp_clkm[] = {
- "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_c2", "pll_c3",
+ "pll_m", "pll_c", "pll_p", "clk_m", "pll_m_ud", "pll_mb", "pll_mb",
+ "pll_p",
};
#define mux_pllmcp_clkm_idx NULL
--
2.1.4
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