Re: [PATCH] crypto: exynoes-rng: Set cra_ctxsize to 0

[Krzysztof Kozlowski]

On Sun, May 21, 2017 at 8:09 AM, PrasannaKumar Muralidharan
 wrote:
> As cra_ctxsize is set but the allocated space is not used, set it 0.

Why do you think it is not used? Did you test our change on hardware?

Best regards,
Krzysztof

>
> Signed-off-by: PrasannaKumar Muralidharan 
> ---
>  drivers/crypto/exynos-rng.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/crypto/exynos-rng.c b/drivers/crypto/exynos-rng.c
> index 451620b..d009df6 100644
> --- a/drivers/crypto/exynos-rng.c
> +++ b/drivers/crypto/exynos-rng.c
> @@ -260,7 +260,7 @@ static int exynos_rng_kcapi_init(struct crypto_tfm *tfm)
> .cra_name   = "stdrng",
> .cra_driver_name= "exynos_rng",
> .cra_priority   = 100,
> -   .cra_ctxsize= sizeof(struct exynos_rng_ctx),
> +   .cra_ctxsize= 0,
> .cra_module = THIS_MODULE,
> .cra_init   = exynos_rng_kcapi_init,
> }
> --
> 1.8.5.6
>

[PATCH] crypto: exynoes-rng: Set cra_ctxsize to 0

[PrasannaKumar Muralidharan]

As cra_ctxsize is set but the allocated space is not used, set it 0.

Signed-off-by: PrasannaKumar Muralidharan 
---
 drivers/crypto/exynos-rng.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/crypto/exynos-rng.c b/drivers/crypto/exynos-rng.c
index 451620b..d009df6 100644
--- a/drivers/crypto/exynos-rng.c
+++ b/drivers/crypto/exynos-rng.c
@@ -260,7 +260,7 @@ static int exynos_rng_kcapi_init(struct crypto_tfm *tfm)
.cra_name   = "stdrng",
.cra_driver_name= "exynos_rng",
.cra_priority   = 100,
-   .cra_ctxsize= sizeof(struct exynos_rng_ctx),
+   .cra_ctxsize= 0,
.cra_module = THIS_MODULE,
.cra_init   = exynos_rng_kcapi_init,
}
-- 
1.8.5.6

[PATCH v2 2/5] dt-bindings : Document the STM32F4 CRC32 binding

[Cosar Dindar]

Add device tree binding for STM32F4.

Signed-off-by: Cosar Dindar 
---
 Documentation/devicetree/bindings/crypto/st,stm32-crc.txt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt 
b/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt
index 3ba92a5..7b30f1e 100644
--- a/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt
+++ b/Documentation/devicetree/bindings/crypto/st,stm32-crc.txt
@@ -1,7 +1,7 @@
 * STMicroelectronics STM32 CRC
 
 Required properties:
-- compatible: Should be "st,stm32f7-crc".
+- compatible: Can be either "st,stm32f7-crc" or "st,srm32f4-crc".
 - reg: The address and length of the peripheral registers space
 - clocks: The input clock of the CRC instance
 
@@ -10,7 +10,7 @@ Optional properties: none
 Example:
 
 crc: crc@40023000 {
-   compatible = "st,stm32f7-crc";
+   compatible = "st,stm32f7-crc", "st,stm32f4-crc";
reg = <0x40023000 0x400>;
clocks = <&rcc 0 12>;
 };
-- 
2.7.4

[PATCH v2 1/5] crypto : stm32 - Add STM32F4 CRC32 support

[Cosar Dindar]

This patch adds CRC (CRC32 Crypto) support for STM32F4 series.

As an hardware limitation polynomial and key setting are not supported.
They are fixed as 0x4C11DB7 (poly) and 0x (key).
CRC32C Castagnoli algorithm is not used.

Signed-off-by: Cosar Dindar 
---
 drivers/crypto/stm32/stm32_crc32.c | 68 --
 1 file changed, 58 insertions(+), 10 deletions(-)

diff --git a/drivers/crypto/stm32/stm32_crc32.c 
b/drivers/crypto/stm32/stm32_crc32.c
index ec83b1e..12fbd98 100644
--- a/drivers/crypto/stm32/stm32_crc32.c
+++ b/drivers/crypto/stm32/stm32_crc32.c
@@ -7,6 +7,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 
 #include 
@@ -39,6 +40,9 @@ struct stm32_crc {
struct clk   *clk;
u8   pending_data[sizeof(u32)];
size_t   nb_pending_bytes;
+   bool key_support;
+   bool poly_support;
+   bool reverse_support;
 };
 
 struct stm32_crc_list {
@@ -106,13 +110,31 @@ static int stm32_crc_init(struct shash_desc *desc)
}
spin_unlock_bh(&crc_list.lock);
 
-   /* Reset, set key, poly and configure in bit reverse mode */
-   writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
-   writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
-   writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
+   /* set key */
+   if (ctx->crc->key_support) {
+   writel(bitrev32(mctx->key), ctx->crc->regs + CRC_INIT);
+   } else if (mctx->key != CRC_INIT_DEFAULT) {
+   dev_err(ctx->crc->dev, "Unsupported key value! Should be: 
0x%x\n",
+   CRC_INIT_DEFAULT);
+   return -EINVAL;
+   }
+
+   /* set poly */
+   if (ctx->crc->poly_support)
+   writel(bitrev32(mctx->poly), ctx->crc->regs + CRC_POL);
+
+   /* reset and configure in bit reverse mode if supported */
+   if (ctx->crc->reverse_support)
+   writel(CRC_CR_RESET | CRC_CR_REVERSE, ctx->crc->regs + CRC_CR);
+   else
+   writel(CRC_CR_RESET, ctx->crc->regs + CRC_CR);
+
+   /* store partial result */
+   if (!ctx->crc->reverse_support)
+   ctx->partial = bitrev32(readl(crc->regs + CRC_DR));
+   else
+   ctx->partial = readl(ctx->crc->regs + CRC_DR);
 
-   /* Store partial result */
-   ctx->partial = readl(ctx->crc->regs + CRC_DR);
ctx->crc->nb_pending_bytes = 0;
 
return 0;
@@ -135,7 +157,12 @@ static int stm32_crc_update(struct shash_desc *desc, const 
u8 *d8,
 
if (crc->nb_pending_bytes == sizeof(u32)) {
/* Process completed pending data */
-   writel(*(u32 *)crc->pending_data, crc->regs + CRC_DR);
+   if (!ctx->crc->reverse_support)
+   writel(bitrev32(*(u32 *)crc->pending_data),
+  crc->regs + CRC_DR);
+   else
+   writel(*(u32 *)crc->pending_data,
+  crc->regs + CRC_DR);
crc->nb_pending_bytes = 0;
}
}
@@ -143,10 +170,16 @@ static int stm32_crc_update(struct shash_desc *desc, 
const u8 *d8,
d32 = (u32 *)d8;
for (i = 0; i < length >> 2; i++)
/* Process 32 bits data */
-   writel(*(d32++), crc->regs + CRC_DR);
+   if (!ctx->crc->reverse_support)
+   writel(bitrev32(*(d32++)), crc->regs + CRC_DR);
+   else
+   writel(*(d32++), crc->regs + CRC_DR);
 
/* Store partial result */
-   ctx->partial = readl(crc->regs + CRC_DR);
+   if (!ctx->crc->reverse_support)
+   ctx->partial = bitrev32(readl(crc->regs + CRC_DR));
+   else
+   ctx->partial = readl(crc->regs + CRC_DR);
 
/* Check for pending data (non 32 bits) */
length &= 3;
@@ -243,6 +276,7 @@ static int stm32_crc_probe(struct platform_device *pdev)
struct stm32_crc *crc;
struct resource *res;
int ret;
+   int algs_size;
 
crc = devm_kzalloc(dev, sizeof(*crc), GFP_KERNEL);
if (!crc)
@@ -269,13 +303,26 @@ static int stm32_crc_probe(struct platform_device *pdev)
return ret;
}
 
+   /* set key, poly and reverse support if device is of F7 series */
+   if (of_device_is_compatible(crc->dev->of_node, "st,stm32f7-crc")) {
+   crc->key_support = true;
+   crc->poly_support = true;
+   crc->reverse_support = true;
+   }
+
platform_set_drvdata(pdev, crc);
 
spin_lock(&crc_list.lock);
list_add(&crc->list, &crc_list.dev_list);
spin_unlock(&crc_list.lock);
 
-   ret = crypto_register_shashes(algs, ARRAY_SIZE(algs));
+   /* For F4 series only CRC32 algorithm will be used */
+   if (of_d

[PATCH v2 0/5] Add support for the STM32F4 CRC32

[Cosar Dindar]

This patch series add hardware CRC32 ("Ethernet") calculation support
for STMicroelectronics STM32F429.

Polynomial and key setting are not supported, key is fixed as 0x4C11DB7
and poly is 0x.

Module is tested on STM32F429-disco board with crypto testmgr using
cases within the key 0x.

Cosar Dindar (5):
  crypto : stm32 - Add STM32F4 CRC32 support
  dt-bindings : Document the STM32F4 CRC32 binding
  ARM: dts: stm32: enable CRC32 on stm32429-disco board
  ARM: dts: stm32: enable CRC32 on stm32429i-eval board
  ARM: dts: stm32: Add CRC support to stm32f429

 .../devicetree/bindings/crypto/st,stm32-crc.txt|  4 +-
 arch/arm/boot/dts/stm32429i-eval.dts   |  4 ++
 arch/arm/boot/dts/stm32f429-disco.dts  |  4 ++
 arch/arm/boot/dts/stm32f429.dtsi   |  7 +++
 drivers/crypto/stm32/stm32_crc32.c | 68 ++
 5 files changed, 75 insertions(+), 12 deletions(-)

-- 
2.7.4