Re: [PATCH 2/6] crypto: engine - Permit to enqueue all async requests
On Wed, Jan 03, 2018 at 09:11:05PM +0100, Corentin Labbe wrote:
> The crypto engine could actually only enqueue hash and ablkcipher request.
> This patch permit it to enqueue any type of crypto_async_request.
>
> Signed-off-by: Corentin Labbe
> ---
> crypto/crypto_engine.c | 230
>
> include/crypto/engine.h | 59 +++--
> 2 files changed, 148 insertions(+), 141 deletions(-)
>
> diff --git a/crypto/crypto_engine.c b/crypto/crypto_engine.c
> index 61e7c4e02fd2..036270b61648 100644
> --- a/crypto/crypto_engine.c
> +++ b/crypto/crypto_engine.c
> @@ -15,7 +15,6 @@
> #include
> #include
> #include
> -#include
> #include
> #include "internal.h"
>
> @@ -34,11 +33,10 @@ static void crypto_pump_requests(struct crypto_engine
> *engine,
>bool in_kthread)
> {
> struct crypto_async_request *async_req, *backlog;
> - struct ahash_request *hreq;
> - struct ablkcipher_request *breq;
> unsigned long flags;
> bool was_busy = false;
> - int ret, rtype;
> + int ret;
> + struct crypto_engine_reqctx *enginectx;
This all looks very good. Just one minor nit, since you're storing
this in the tfm ctx as opposed to the request ctx (which is indeed
an improvement), you should remove the "req" from its name.
Thanks!
--
Email: Herbert Xu
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
Re: [PATCH 1/2] crypto: Implement a generic crypto statistics
Am Donnerstag, 11. Januar 2018, 20:56:56 CET schrieb Corentin Labbe:
Hi Corentin,
> This patch implement a generic way to get statistics about all crypto
> usages.
>
> Signed-off-by: Corentin Labbe
> ---
> crypto/Kconfig | 11
> crypto/ablkcipher.c | 9 +++
> crypto/acompress.c | 9 +++
> crypto/aead.c | 10
> crypto/ahash.c | 8 ++
> crypto/akcipher.c | 13 ++
> crypto/algapi.c | 6 +
> crypto/blkcipher.c | 9 +++
> crypto/crypto_user.c| 28 +
> crypto/kpp.c| 7 ++
> crypto/rng.c| 8 ++
> crypto/scompress.c | 9 +++
> crypto/shash.c | 5
> crypto/skcipher.c | 9 +++
> include/crypto/acompress.h | 22
> include/crypto/aead.h | 22
> include/crypto/akcipher.h | 42 +++
> include/crypto/hash.h | 21
> include/crypto/kpp.h| 28 +
> include/crypto/rng.h| 17 +
> include/crypto/skcipher.h | 22
> include/linux/crypto.h | 56
> + include/uapi/linux/cryptouser.h |
> 34 +
> 23 files changed, 405 insertions(+)
>
> diff --git a/crypto/Kconfig b/crypto/Kconfig
> index 971d558494c3..3b88fba14b59 100644
> --- a/crypto/Kconfig
> +++ b/crypto/Kconfig
> @@ -1780,6 +1780,17 @@ config CRYPTO_USER_API_AEAD
> This option enables the user-spaces interface for AEAD
> cipher algorithms.
>
> +config CRYPTO_STATS
> + bool "Crypto usage statistics for User-space"
> + help
> + This option enables the gathering of crypto stats.
> + This will collect:
> + - encrypt/decrypt size and numbers of symmeric operations
> + - compress/decompress size and numbers of compress operations
> + - size and numbers of hash operations
> + - encrypt/decrypt/sign/verify numbers for asymmetric operations
> + - generate/seed numbers for rng operations
> +
> config CRYPTO_HASH_INFO
> bool
>
> diff --git a/crypto/ablkcipher.c b/crypto/ablkcipher.c
> index d880a4897159..f6d20e4ca977 100644
> --- a/crypto/ablkcipher.c
> +++ b/crypto/ablkcipher.c
> @@ -369,6 +369,7 @@ static int crypto_init_ablkcipher_ops(struct crypto_tfm
> *tfm, u32 type, static int crypto_ablkcipher_report(struct sk_buff *skb,
> struct crypto_alg *alg) {
> struct crypto_report_blkcipher rblkcipher;
> + u64 v;
>
> strncpy(rblkcipher.type, "ablkcipher", sizeof(rblkcipher.type));
> strncpy(rblkcipher.geniv, alg->cra_ablkcipher.geniv ?: "",
> @@ -378,6 +379,14 @@ static int crypto_ablkcipher_report(struct sk_buff
> *skb, struct crypto_alg *alg) rblkcipher.min_keysize =
> alg->cra_ablkcipher.min_keysize;
> rblkcipher.max_keysize = alg->cra_ablkcipher.max_keysize;
> rblkcipher.ivsize = alg->cra_ablkcipher.ivsize;
> + v = atomic_read(&alg->encrypt_cnt);
> + rblkcipher.stat_encrypt_cnt = v;
> + v = atomic_read(&alg->encrypt_tlen);
> + rblkcipher.stat_encrypt_tlen = v;
> + v = atomic_read(&alg->decrypt_cnt);
> + rblkcipher.stat_decrypt_cnt = v;
> + v = atomic_read(&alg->decrypt_tlen);
> + rblkcipher.stat_decrypt_tlen = v;
>
> if (nla_put(skb, CRYPTOCFGA_REPORT_BLKCIPHER,
> sizeof(struct crypto_report_blkcipher), &rblkcipher))
> diff --git a/crypto/acompress.c b/crypto/acompress.c
> index 1544b7c057fb..524c8a3e3f80 100644
> --- a/crypto/acompress.c
> +++ b/crypto/acompress.c
> @@ -32,8 +32,17 @@ static const struct crypto_type crypto_acomp_type;
> static int crypto_acomp_report(struct sk_buff *skb, struct crypto_alg *alg)
> {
> struct crypto_report_acomp racomp;
> + u64 v;
>
> strncpy(racomp.type, "acomp", sizeof(racomp.type));
> + v = atomic_read(&alg->compress_cnt);
> + racomp.stat_compress_cnt = v;
> + v = atomic_read(&alg->compress_tlen);
> + racomp.stat_compress_tlen = v;
> + v = atomic_read(&alg->decompress_cnt);
> + racomp.stat_decompress_cnt = v;
> + v = atomic_read(&alg->decompress_tlen);
> + racomp.stat_decompress_tlen = v;
>
> if (nla_put(skb, CRYPTOCFGA_REPORT_ACOMP,
> sizeof(struct crypto_report_acomp), &racomp))
> diff --git a/crypto/aead.c b/crypto/aead.c
> index fe00cbd7243d..de13bd345d8b 100644
> --- a/crypto/aead.c
> +++ b/crypto/aead.c
> @@ -109,6 +109,7 @@ static int crypto_aead_report(struct sk_buff *skb,
> struct crypto_alg *alg) {
> struct crypto_report_aead raead;
> struct aead_alg *aead = container_of(alg, struct aead_alg, base);
> + u64 v;
>
> strncpy(raead.type, "aead", sizeof(raead.type));
> strncpy(raead.geniv, "", sizeof(raead.geniv));
Crypto Fixes for 4.15
Hi Linus: This push fixes a NULL pointer dereference in crypto_remove_spawns that can be triggered through af_alg. Please pull from git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6.git linus Eric Biggers (1): crypto: algapi - fix NULL dereference in crypto_remove_spawns() crypto/algapi.c | 12 1 file changed, 12 insertions(+) Thanks, -- Email: Herbert Xu Home Page: http://gondor.apana.org.au/~herbert/ PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
Re: kernel failure while loading X.509 certificate
> Il giorno 11 gen 2018, alle ore 23:37, Arnd Bergmann ha > scritto: > > On Thu, Jan 11, 2018 at 7:29 PM, Paolo Valente > wrote: >> Hi guys, >> this is a help request, for a problem that has been driving me crazy >> all day long, without any success :( >> >> I've compiled a 4.15-rc7 custom kernel on a freshly-installed Fedora >> 27, using the usual "make ; make modules_install ; make install" >> procedure. No error reported while building. But at boot the >> kernel immediately fails as follows, apparently while loading/parsing >> an X.509 certificate: > > The BUG_ON() you hit is this one in public_key_verify_signature(): > >BUG_ON(!sig->digest); > > There was a patch series by Eric Biggers that touched these files to > add some fixes > after v4.15-rc1. I'm not runnig that code myself, but it sounds like > a real regression, > so I'm adding Eric (to look at the code), the corresponding mailing > list and Thorsten > (for regression tracking) to Cc. > > x509_cert_parse() allocates the 'cert->sig' structure, and calls > x509_get_sig_params(), > which may or may not allocate a digest. It returns with > cert->unsupported_sig=true > in case it fails to allocate a digest for some reason (crypto_alloc_shash > failed > or no sig->hash_algo). > > The full set of Eric's patches is > > 54c1fb39fe04 X.509: fix comparisons of ->pkey_algo > 18026d866801 KEYS: reject NULL restriction string when type is specified > 3d1f0255426a security: keys: remove redundant assignment to key_ref > aa3300362060 X.509: use crypto_shash_digest() > 72f9a07b6bfa KEYS: be careful with error codes in > public_key_verify_signature() > a80745a6de51 pkcs7: use crypto_shash_digest() > 7204eb8590c7 pkcs7: fix check for self-signed certificate > 8ecb506d3476 pkcs7: return correct error code if pkcs7_check_authattrs() fails > 8dfd2f22d3bf 509: fix printing uninitialized stack memory when OID is empty > 47e0a208fb9d X.509: fix buffer overflow detection in sprint_oid() > 0f30cbea005b X.509: reject invalid BIT STRING for subjectPublicKey > 81a7be2cd69b ASN.1: check for error from ASN1_OP_END__ACT actions > e0058f3a874e ASN.1: fix out-of-bounds read when parsing indefinite length item > 4dca6ea1d943 KEYS: add missing permission check for request_key() destination > a2d8737d5c78 KEYS: remove unnecessary get/put of explicit dest_keyring > > and it's based on -rc2. If you want to do a quicker bisection, I'd > suggest you try > 4.15-rc2 and 54c1fb39fe04 to start with. > Thank you very much Arnd. Fortunately, for the task I'm performing, a 4.14 will do too. And I'm under pressure to finally finish this task. Yet, even before I finish with this task, I'm willing to do any test that the guys you added may want me to do. And, if more useful for the community, ok for me to switch to the most appropriate public mailing lists. Thanks, Paolo >> ... >> [2.078978] Loading compiled-in X.509 certificates >> [2.080890] [ cut here ] >> [2.081240] kernel BUG at >> /mnt/linux-dev/linux/crypto/asymmetric_keys/public_key.c:82! >> [2.081808] invalid opcode: [#1] SMP PTI >> [2.082105] Modules linked in: >> [2.082333] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 4.15.0-bfq-mq-rc7+ >> #6 >> [2.082851] Hardware name: Parallels Software International Inc. >> Parallels Virtual Platform/Parallels Virtual Platform, BIOS 1.3.0 (19714) >> 12/15/2017 >> [2.083778] RIP: 0010:public_key_verify_signature+0x2cc/0x300 >> [2.084178] RSP: 0018:ba42c0327b50 EFLAGS: 00010246 >> [2.084549] RAX: RBX: 9887f4ed00c0 RCX: >> >> [2.085045] RDX: 9887f4e9d1b6 RSI: 9887f4e9c780 RDI: >> 9887f4e9dc60 >> [2.085544] RBP: 9887f4e9c780 R08: 0001 R09: >> 697542230c030455 >> [2.086036] R10: 656e65676f747561 R11: 20656d697420646c R12: >> 9887f4e9dc60 >> [2.086534] R13: 908a5f78 R14: 0542 R15: >> 0542 >> [2.087036] FS: () GS:98883ce4() >> knlGS: >> [2.087591] CS: 0010 DS: ES: CR0: 80050033 >> [2.087989] CR2: 7fc579bc1000 CR3: 5020a003 CR4: >> 001606e0 >> [2.088488] Call Trace: >> [2.088668] ? cryptomgr_notify+0xe7/0x4f0 >> [2.088956] ? asymmetric_key_generate_id+0x2f/0x70 >> [2.089365] ? crypto_larval_lookup+0x20/0x20 >> [2.089672] ? __slab_alloc+0x1c/0x30 >> [2.089931] ? __kmalloc+0x1ae/0x210 >> [2.090187] ? asymmetric_key_generate_id+0x2f/0x70 >> [2.090532] x509_check_for_self_signed+0x8f/0xe0 >> [2.090862] x509_cert_parse+0x16f/0x1c0 >> [2.091149] x509_key_preparse+0x23/0x1d0 >> [2.091450] asymmetric_key_preparse+0x57/0xc0 >> [2.091764] key_create_or_update+0x143/0x430 >> [2.092071] load_system_certificate_list+0x8f/0xea >> [2.092424] ? context_tracking_cpu_set+0x57/0x57 >> [2.092764] ? set_debug_rodata+0x11/0x11
Re: kernel failure while loading X.509 certificate
On Thu, Jan 11, 2018 at 7:29 PM, Paolo Valente wrote: > Hi guys, > this is a help request, for a problem that has been driving me crazy > all day long, without any success :( > > I've compiled a 4.15-rc7 custom kernel on a freshly-installed Fedora > 27, using the usual "make ; make modules_install ; make install" > procedure. No error reported while building. But at boot the > kernel immediately fails as follows, apparently while loading/parsing > an X.509 certificate: The BUG_ON() you hit is this one in public_key_verify_signature(): BUG_ON(!sig->digest); There was a patch series by Eric Biggers that touched these files to add some fixes after v4.15-rc1. I'm not runnig that code myself, but it sounds like a real regression, so I'm adding Eric (to look at the code), the corresponding mailing list and Thorsten (for regression tracking) to Cc. x509_cert_parse() allocates the 'cert->sig' structure, and calls x509_get_sig_params(), which may or may not allocate a digest. It returns with cert->unsupported_sig=true in case it fails to allocate a digest for some reason (crypto_alloc_shash failed or no sig->hash_algo). The full set of Eric's patches is 54c1fb39fe04 X.509: fix comparisons of ->pkey_algo 18026d866801 KEYS: reject NULL restriction string when type is specified 3d1f0255426a security: keys: remove redundant assignment to key_ref aa3300362060 X.509: use crypto_shash_digest() 72f9a07b6bfa KEYS: be careful with error codes in public_key_verify_signature() a80745a6de51 pkcs7: use crypto_shash_digest() 7204eb8590c7 pkcs7: fix check for self-signed certificate 8ecb506d3476 pkcs7: return correct error code if pkcs7_check_authattrs() fails 8dfd2f22d3bf 509: fix printing uninitialized stack memory when OID is empty 47e0a208fb9d X.509: fix buffer overflow detection in sprint_oid() 0f30cbea005b X.509: reject invalid BIT STRING for subjectPublicKey 81a7be2cd69b ASN.1: check for error from ASN1_OP_END__ACT actions e0058f3a874e ASN.1: fix out-of-bounds read when parsing indefinite length item 4dca6ea1d943 KEYS: add missing permission check for request_key() destination a2d8737d5c78 KEYS: remove unnecessary get/put of explicit dest_keyring and it's based on -rc2. If you want to do a quicker bisection, I'd suggest you try 4.15-rc2 and 54c1fb39fe04 to start with. > ... > [2.078978] Loading compiled-in X.509 certificates > [2.080890] [ cut here ] > [2.081240] kernel BUG at > /mnt/linux-dev/linux/crypto/asymmetric_keys/public_key.c:82! > [2.081808] invalid opcode: [#1] SMP PTI > [2.082105] Modules linked in: > [2.082333] CPU: 1 PID: 1 Comm: swapper/0 Not tainted 4.15.0-bfq-mq-rc7+ #6 > [2.082851] Hardware name: Parallels Software International Inc. Parallels > Virtual Platform/Parallels Virtual Platform, BIOS 1.3.0 (19714) 12/15/2017 > [2.083778] RIP: 0010:public_key_verify_signature+0x2cc/0x300 > [2.084178] RSP: 0018:ba42c0327b50 EFLAGS: 00010246 > [2.084549] RAX: RBX: 9887f4ed00c0 RCX: > > [2.085045] RDX: 9887f4e9d1b6 RSI: 9887f4e9c780 RDI: > 9887f4e9dc60 > [2.085544] RBP: 9887f4e9c780 R08: 0001 R09: > 697542230c030455 > [2.086036] R10: 656e65676f747561 R11: 20656d697420646c R12: > 9887f4e9dc60 > [2.086534] R13: 908a5f78 R14: 0542 R15: > 0542 > [2.087036] FS: () GS:98883ce4() > knlGS: > [2.087591] CS: 0010 DS: ES: CR0: 80050033 > [2.087989] CR2: 7fc579bc1000 CR3: 5020a003 CR4: > 001606e0 > [2.088488] Call Trace: > [2.088668] ? cryptomgr_notify+0xe7/0x4f0 > [2.088956] ? asymmetric_key_generate_id+0x2f/0x70 > [2.089365] ? crypto_larval_lookup+0x20/0x20 > [2.089672] ? __slab_alloc+0x1c/0x30 > [2.089931] ? __kmalloc+0x1ae/0x210 > [2.090187] ? asymmetric_key_generate_id+0x2f/0x70 > [2.090532] x509_check_for_self_signed+0x8f/0xe0 > [2.090862] x509_cert_parse+0x16f/0x1c0 > [2.091149] x509_key_preparse+0x23/0x1d0 > [2.091450] asymmetric_key_preparse+0x57/0xc0 > [2.091764] key_create_or_update+0x143/0x430 > [2.092071] load_system_certificate_list+0x8f/0xea > [2.092424] ? context_tracking_cpu_set+0x57/0x57 > [2.092764] ? set_debug_rodata+0x11/0x11 > [2.093047] do_one_initcall+0x4b/0x190 > [2.093326] kernel_init_freeable+0x19b/0x23c > [2.093688] ? rest_init+0xb0/0xb0 > [2.094038] kernel_init+0xa/0xfc > [2.094431] ret_from_fork+0x1f/0x30 > [2.094797] Code: ff ff 0f ff b8 ea ff ff ff e9 13 ff ff ff 4c 89 f7 e8 89 > 3c 4a 00 c7 44 24 48 00 00 00 00 8b 44 24 68 e9 c0 fe ff ff 0f 0b 0f 0b <0f> > 0b 0f 0b 48 89 ee 48 89 ef e8 b5 80 fd ff b8 f4 ff ff ff e9 > [2.096692] RIP: public_key_verify_signature+0x2cc/0x300 RSP: > ba42c0327b50 > [2.097475] ---[ end trace 6ad74f81d3fa3473 ]--- > [2.097916] Kernel pa
Re: [PATCH V4 2/2] ARM: dts: imx7s: add snvs rtc clock
On Tue, Jan 09, 2018 at 05:52:06PM +0800, Anson Huang wrote: > Add i.MX7 SNVS RTC clock. > > Signed-off-by: Anson Huang > --- > change since v3: > add optional for clocks in binding doc statement. > Documentation/devicetree/bindings/crypto/fsl-sec4.txt | 17 + > arch/arm/boot/dts/imx7s.dtsi | 2 ++ > 2 files changed, 19 insertions(+) Reviewed-by: Rob Herring
Re: [PATCH V4 1/2] clk: imx: imx7d: add the snvs clock
On Tue, Jan 09, 2018 at 05:52:05PM +0800, Anson Huang wrote: > According to the i.MX7D Reference Manual, > SNVS block has a clock gate, accessing SNVS block > would need this clock gate to be enabled, add it > into clock tree so that SNVS module driver can > operate this clock gate. > > Signed-off-by: Anson Huang > Acked-by: Dong Aisheng > Reviewed-by: Fabio Estevam > --- > drivers/clk/imx/clk-imx7d.c | 1 + > include/dt-bindings/clock/imx7d-clock.h | 3 ++- > 2 files changed, 3 insertions(+), 1 deletion(-) Reviewed-by: Rob Herring
[PATCH] hwrng: imx-rngc: simplify the power management definitions
Use the SIMPLE_DEV_PM_OPS() macro instead of populating a struct
dev_pm_ops directly. The suspend and resume functions will now be used
for both hibernation and suspend to ram.
If power management is disabled, SIMPLE_DEV_PM_OPS() evaluates to
nothing, The two functions won't be used and won't be included in the
kernel. Mark them as __maybe_unused to clarify that this is intended
behaviour.
With these modifications in place, we don't need the #ifdefs for power
management any more.
Signed-off-by: Martin Kaiser
---
drivers/char/hw_random/imx-rngc.c | 13 +++--
1 file changed, 3 insertions(+), 10 deletions(-)
diff --git a/drivers/char/hw_random/imx-rngc.c
b/drivers/char/hw_random/imx-rngc.c
index 88db42d..eca8724 100644
--- a/drivers/char/hw_random/imx-rngc.c
+++ b/drivers/char/hw_random/imx-rngc.c
@@ -282,8 +282,7 @@ static int __exit imx_rngc_remove(struct platform_device
*pdev)
return 0;
}
-#ifdef CONFIG_PM
-static int imx_rngc_suspend(struct device *dev)
+static int __maybe_unused imx_rngc_suspend(struct device *dev)
{
struct imx_rngc *rngc = dev_get_drvdata(dev);
@@ -292,7 +291,7 @@ static int imx_rngc_suspend(struct device *dev)
return 0;
}
-static int imx_rngc_resume(struct device *dev)
+static int __maybe_unused imx_rngc_resume(struct device *dev)
{
struct imx_rngc *rngc = dev_get_drvdata(dev);
@@ -301,11 +300,7 @@ static int imx_rngc_resume(struct device *dev)
return 0;
}
-static const struct dev_pm_ops imx_rngc_pm_ops = {
- .suspend= imx_rngc_suspend,
- .resume = imx_rngc_resume,
-};
-#endif
+SIMPLE_DEV_PM_OPS(imx_rngc_pm_ops, imx_rngc_suspend, imx_rngc_resume);
static const struct of_device_id imx_rngc_dt_ids[] = {
{ .compatible = "fsl,imx25-rngb", .data = NULL, },
@@ -316,9 +311,7 @@ MODULE_DEVICE_TABLE(of, imx_rngc_dt_ids);
static struct platform_driver imx_rngc_driver = {
.driver = {
.name = "imx_rngc",
-#ifdef CONFIG_PM
.pm = &imx_rngc_pm_ops,
-#endif
.of_match_table = imx_rngc_dt_ids,
},
.remove = __exit_p(imx_rngc_remove),
--
2.1.4
[PATCH 1/2] crypto: Implement a generic crypto statistics
This patch implement a generic way to get statistics about all crypto
usages.
Signed-off-by: Corentin Labbe
---
crypto/Kconfig | 11
crypto/ablkcipher.c | 9 +++
crypto/acompress.c | 9 +++
crypto/aead.c | 10
crypto/ahash.c | 8 ++
crypto/akcipher.c | 13 ++
crypto/algapi.c | 6 +
crypto/blkcipher.c | 9 +++
crypto/crypto_user.c| 28 +
crypto/kpp.c| 7 ++
crypto/rng.c| 8 ++
crypto/scompress.c | 9 +++
crypto/shash.c | 5
crypto/skcipher.c | 9 +++
include/crypto/acompress.h | 22
include/crypto/aead.h | 22
include/crypto/akcipher.h | 42 +++
include/crypto/hash.h | 21
include/crypto/kpp.h| 28 +
include/crypto/rng.h| 17 +
include/crypto/skcipher.h | 22
include/linux/crypto.h | 56 +
include/uapi/linux/cryptouser.h | 34 +
23 files changed, 405 insertions(+)
diff --git a/crypto/Kconfig b/crypto/Kconfig
index 971d558494c3..3b88fba14b59 100644
--- a/crypto/Kconfig
+++ b/crypto/Kconfig
@@ -1780,6 +1780,17 @@ config CRYPTO_USER_API_AEAD
This option enables the user-spaces interface for AEAD
cipher algorithms.
+config CRYPTO_STATS
+ bool "Crypto usage statistics for User-space"
+ help
+ This option enables the gathering of crypto stats.
+ This will collect:
+ - encrypt/decrypt size and numbers of symmeric operations
+ - compress/decompress size and numbers of compress operations
+ - size and numbers of hash operations
+ - encrypt/decrypt/sign/verify numbers for asymmetric operations
+ - generate/seed numbers for rng operations
+
config CRYPTO_HASH_INFO
bool
diff --git a/crypto/ablkcipher.c b/crypto/ablkcipher.c
index d880a4897159..f6d20e4ca977 100644
--- a/crypto/ablkcipher.c
+++ b/crypto/ablkcipher.c
@@ -369,6 +369,7 @@ static int crypto_init_ablkcipher_ops(struct crypto_tfm
*tfm, u32 type,
static int crypto_ablkcipher_report(struct sk_buff *skb, struct crypto_alg
*alg)
{
struct crypto_report_blkcipher rblkcipher;
+ u64 v;
strncpy(rblkcipher.type, "ablkcipher", sizeof(rblkcipher.type));
strncpy(rblkcipher.geniv, alg->cra_ablkcipher.geniv ?: "",
@@ -378,6 +379,14 @@ static int crypto_ablkcipher_report(struct sk_buff *skb,
struct crypto_alg *alg)
rblkcipher.min_keysize = alg->cra_ablkcipher.min_keysize;
rblkcipher.max_keysize = alg->cra_ablkcipher.max_keysize;
rblkcipher.ivsize = alg->cra_ablkcipher.ivsize;
+ v = atomic_read(&alg->encrypt_cnt);
+ rblkcipher.stat_encrypt_cnt = v;
+ v = atomic_read(&alg->encrypt_tlen);
+ rblkcipher.stat_encrypt_tlen = v;
+ v = atomic_read(&alg->decrypt_cnt);
+ rblkcipher.stat_decrypt_cnt = v;
+ v = atomic_read(&alg->decrypt_tlen);
+ rblkcipher.stat_decrypt_tlen = v;
if (nla_put(skb, CRYPTOCFGA_REPORT_BLKCIPHER,
sizeof(struct crypto_report_blkcipher), &rblkcipher))
diff --git a/crypto/acompress.c b/crypto/acompress.c
index 1544b7c057fb..524c8a3e3f80 100644
--- a/crypto/acompress.c
+++ b/crypto/acompress.c
@@ -32,8 +32,17 @@ static const struct crypto_type crypto_acomp_type;
static int crypto_acomp_report(struct sk_buff *skb, struct crypto_alg *alg)
{
struct crypto_report_acomp racomp;
+ u64 v;
strncpy(racomp.type, "acomp", sizeof(racomp.type));
+ v = atomic_read(&alg->compress_cnt);
+ racomp.stat_compress_cnt = v;
+ v = atomic_read(&alg->compress_tlen);
+ racomp.stat_compress_tlen = v;
+ v = atomic_read(&alg->decompress_cnt);
+ racomp.stat_decompress_cnt = v;
+ v = atomic_read(&alg->decompress_tlen);
+ racomp.stat_decompress_tlen = v;
if (nla_put(skb, CRYPTOCFGA_REPORT_ACOMP,
sizeof(struct crypto_report_acomp), &racomp))
diff --git a/crypto/aead.c b/crypto/aead.c
index fe00cbd7243d..de13bd345d8b 100644
--- a/crypto/aead.c
+++ b/crypto/aead.c
@@ -109,6 +109,7 @@ static int crypto_aead_report(struct sk_buff *skb, struct
crypto_alg *alg)
{
struct crypto_report_aead raead;
struct aead_alg *aead = container_of(alg, struct aead_alg, base);
+ u64 v;
strncpy(raead.type, "aead", sizeof(raead.type));
strncpy(raead.geniv, "", sizeof(raead.geniv));
@@ -116,6 +117,15 @@ static int crypto_aead_report(struct sk_buff *skb, struct
crypto_alg *alg)
raead.blocksize = alg->cra_blocksize;
raead.maxauthsize = aead->maxauthsize;
[PATCH 2/2] crypto: tools: Add cryptostat userspace
Signed-off-by: Corentin Labbe
---
tools/crypto/getstat.c | 283 +
1 file changed, 283 insertions(+)
create mode 100644 tools/crypto/getstat.c
diff --git a/tools/crypto/getstat.c b/tools/crypto/getstat.c
new file mode 100644
index ..e73f2a73e0f6
--- /dev/null
+++ b/tools/crypto/getstat.c
@@ -0,0 +1,283 @@
+/* Heavily copied from libkcapi 2015 - 2017, Stephan Mueller
*/
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define CR_RTA(x) ((struct rtattr *)(((char *)(x)) +
NLMSG_ALIGN(sizeof(struct crypto_user_alg
+
+static int get_stat(const char *drivername)
+{
+ struct {
+ struct nlmsghdr n;
+ struct crypto_user_alg cru;
+ } req;
+ struct sockaddr_nl nl;
+ int sd = 0, ret;
+ socklen_t addr_len;
+ struct iovec iov;
+ struct msghdr msg;
+ char buf[4096];
+ struct nlmsghdr *res_n = (struct nlmsghdr *)buf;
+ struct crypto_user_alg *cru_res = NULL;
+ int res_len = 0;
+ struct rtattr *tb[CRYPTOCFGA_MAX + 1];
+ struct rtattr *rta;
+
+ memset(&req, 0, sizeof(req));
+ memset(&buf, 0, sizeof(buf));
+ memset(&msg, 0, sizeof(msg));
+
+ req.n.nlmsg_len = NLMSG_LENGTH(sizeof(req.cru));
+ req.n.nlmsg_flags = NLM_F_REQUEST;
+ req.n.nlmsg_type = CRYPTO_MSG_GETALG;
+ req.n.nlmsg_seq = time(NULL);
+
+ strncpy(req.cru.cru_driver_name, drivername, strlen(drivername));
+
+ sd = socket(AF_NETLINK, SOCK_RAW, NETLINK_CRYPTO);
+ if (sd < 0) {
+ fprintf(stderr, "Netlink error: cannot open netlink socket");
+ return -errno;
+ }
+ memset(&nl, 0, sizeof(nl));
+ nl.nl_family = AF_NETLINK;
+ if (bind(sd, (struct sockaddr *)&nl, sizeof(nl)) < 0) {
+ ret = -errno;
+ fprintf(stderr, "Netlink error: cannot bind netlink socket");
+ goto out;
+ }
+
+ /* sanity check that netlink socket was successfully opened */
+ addr_len = sizeof(nl);
+ if (getsockname(sd, (struct sockaddr *)&nl, &addr_len) < 0) {
+ ret = -errno;
+ printf("Netlink error: cannot getsockname");
+ goto out;
+ }
+ if (addr_len != sizeof(nl)) {
+ ret = -errno;
+ printf("Netlink error: wrong address length %d", addr_len);
+ goto out;
+ }
+ if (nl.nl_family != AF_NETLINK) {
+ ret = -errno;
+ printf("Netlink error: wrong address family %d",
+ nl.nl_family);
+ goto out;
+ }
+
+ memset(&nl, 0, sizeof(nl));
+ nl.nl_family = AF_NETLINK;
+ iov.iov_base = (void *)&req.n;
+ iov.iov_len = req.n.nlmsg_len;
+ msg.msg_name = &nl;
+ msg.msg_namelen = sizeof(nl);
+ msg.msg_iov = &iov;
+ msg.msg_iovlen = 1;
+ if (sendmsg(sd, &msg, 0) < 0) {
+ ret = -errno;
+ printf("Netlink error: sendmsg failed");
+ goto out;
+ }
+ memset(buf, 0, sizeof(buf));
+ iov.iov_base = buf;
+ while (1) {
+ iov.iov_len = sizeof(buf);
+ ret = recvmsg(sd, &msg, 0);
+ if (ret < 0) {
+ if (errno == EINTR || errno == EAGAIN)
+ continue;
+ ret = -errno;
+ printf("Netlink error: netlink receive error");
+ goto out;
+ }
+ if (ret == 0) {
+ ret = -errno;
+ printf("Netlink error: no data");
+ goto out;
+ }
+ if (ret > sizeof(buf)) {
+ ret = -errno;
+ printf("Netlink error: received too much data");
+ goto out;
+ }
+ break;
+ }
+
+ ret = -EFAULT;
+ res_len = res_n->nlmsg_len;
+ if (res_n->nlmsg_type == NLMSG_ERROR) {
+ /*
+* return -EAGAIN -- this error will occur if we received a
+* driver name, but used it for a generic name. Allow caller
+* to invoke function again where driver name is looked up
+*/
+ ret = -EAGAIN;
+ goto out;
+ }
+
+ if (res_n->nlmsg_type == CRYPTO_MSG_GETALG) {
+ cru_res = NLMSG_DATA(res_n);
+ res_len -= NLMSG_SPACE(sizeof(*cru_res));
+ }
+ if (res_len < 0) {
+ printf("Netlink error: nlmsg len %d\n", res_len);
+ goto out;
+ }
+
+ if (!cru_res) {
+ ret = -EFAULT;
+ printf("Netlink error: no cru_res\n");
+ goto out;
+ }
+
+ rta = CR_RTA(cru_res);
+
[PATCH 0/2] crypto: Implement generic crypto statistics
Hello This patch is a try to implement a generic crypto driver statistics. The goal is to have an "ifconfig" for crypto device. Some driver tried to implement this via a debugfs interface. This serie do it directly in the crypto API and give access to stats via the crypto_user(netlink) API. Then an userspace tool will collect information via netlink. Note that this userspace tool is heavily copied from libkcapi and if Stephan Mueller agree, I will made a PR for adding getstat to it. Example of output: gcc getstat.c -o getstat && ./getstat authenc(hmac(sha512-generic),cbc-des3_ede-asm) AEAD Encrypt: 6 bytes: 768 Decrypt: 0 bytes: 0 authenc(hmac(sha512-generic),cbc(des-generic)) AEAD Encrypt: 8 bytes: 1024 Decrypt: 0 bytes: 0 authenc(hmac(sha384-generic),cbc-des3_ede-asm) AEAD Encrypt: 6 bytes: 768 Decrypt: 0 bytes: 0 authenc(hmac(sha384-generic),cbc(des-generic)) AEAD Encrypt: 8 bytes: 1024 Decrypt: 0 bytes: 0 authenc(hmac(sha256-generic),cbc-des3_ede-asm) AEAD Encrypt: 6 bytes: 768 Decrypt: 0 bytes: 0 authenc(hmac(sha256-generic),cbc(des-generic)) AEAD Encrypt: 8 bytes: 1024 Decrypt: 0 bytes: 0 authenc(hmac(sha224-generic),cbc-des3_ede-asm) AEAD Encrypt: 6 bytes: 768 Decrypt: 0 bytes: 0 authenc(hmac(sha224-generic),cbc(des-generic)) AEAD Encrypt: 8 bytes: 1024 Decrypt: 0 bytes: 0 authenc(hmac(sha1-generic),cbc-des3_ede-asm)AEAD Encrypt: 6 bytes: 768 Decrypt: 0 bytes: 0 authenc(hmac(sha1-generic),cbc(des-generic))AEAD Encrypt: 8 bytes: 1024 Decrypt: 0 bytes: 0 authenc(hmac(sha1-generic),ecb-cipher_null) AEAD Encrypt: 12 bytes: 366 Decrypt: 12 bytes: 606 authenc(hmac(md5-generic),ecb-cipher_null) AEAD Encrypt: 12 bytes: 366 Decrypt: 12 bytes: 558 authenc(hmac(sha1-generic),virtio_crypto_aes_cbc) AEAD Encrypt: 42 bytes: 2208 Decrypt: 0 bytes: 0 cmac(des3_ede-asm) Hash: 32 bytes: 480 cmac(aes-asm) Hash: 48 bytes: 1472 rfc4543(gcm_base(ctr(aes-asm),ghash-generic)) AEAD Encrypt: 6 bytes: 312 Decrypt: 12 bytes: 816 rfc4106(gcm_base(ctr(aes-asm),ghash-generic)) AEAD Encrypt: 138 bytes: 6864 Decrypt: 138 bytes: 9072 crc32-generic Hash: 56 bytes: 10850 vmac(aes-asm) Hash: 88 bytes: 8328 xcbc(aes-asm) Hash: 64 bytes: 936 hmac(sha224-generic) Hash: 46 bytes: 3868 hmac(sha512-generic) Hash: 46 bytes: 3868 hmac(sha384-generic) Hash: 46 bytes: 3868 hmac(sha1-generic) Hash: 136 bytes: 7884 hmac(md5-generic) Hash: 80 bytes: 2940 crct10dif-generic Hash: 40 bytes: 4492 rfc4309(ccm_base(ctr(aes-asm),cbcmac(aes-asm))) AEAD Encrypt: 138 bytes: 6864 Decrypt: 138 bytes: 9072 ccm_base(ctr(aes-asm),cbcmac(aes-asm)) AEAD Encrypt: 222 bytes: 8946 Decrypt: 240 bytes: 12246 cbcmac(aes-asm) Hash: 478 bytes: 21034 gcm_base(ctr(aes-asm),ghash-generic)AEAD Encrypt: 196 bytes: 8424 Decrypt: 196 bytes: 12304 rfc3686(ctr(aes-asm)) Cipher Encrypt: 40 bytes: 17264 Decrypt: 36 bytes: 864 ctr(aes-asm)Cipher Encrypt: 924 bytes: 59560 Decrypt: 474 bytes: 36192 xts(ecb(aes-asm)) Cipher Encrypt: 44 bytes: 11008 Decrypt: 44 bytes: 11008 lrw(ecb(aes-asm)) Cipher Encrypt: 68 bytes: 7040 Decrypt: 68 bytes: 7040 ecb(aes-asm)Cipher Encrypt: 140 bytes: 23296 Decrypt: 140 bytes: 23296 ctr(des-generic)Cipher Encrypt: 24 bytes: 5940 Decrypt: 24 bytes: 5940 cbc(des-generic)Cipher Encrypt: 88 bytes: 8576 Decrypt: 40 bytes: 3200 ecb(des-generic)Cipher Encrypt: 64 bytes: 3744 Decrypt: 36 bytes: 3232 pkcs1pad(rsa-generic,sha1) Akcipher Encrypt: 0 bytes: 0 Decrypt: 0 bytes: 0 Sign: 0 Verify: 13 virtio_crypto_aes_cbc Cipher Encrypt: 82 bytes: 8320 Decrypt: 38 bytes: 6080 ecdh-genericKPP Setsecret: 4 Generate public key: 3 Compute_shared_secret: 4 ghash-generic Hash: 440 bytes: 10728 jitterentropy_rng RNG Seed: 0 Generate: 0 bytes: 0 drbg_nopr_hmac_sha256 RNG Seed: 5 Generate: 9 bytes: 1056 drbg_nopr_hmac_sha512 RNG Seed: 0 Generate: 0 bytes: 0 drbg_nopr_hmac_sha384 RNG Seed: 0 Generate: 0 bytes: 0 drbg_nopr_hmac_sha1 RNG Seed: 0 Generate: 0 bytes: 0 hmac(sha256-generic) Hash: 94 bytes: 5592 drbg_pr_hmac_sha256 RNG Seed: 4 Generate: 8 bytes: 1024 drbg_pr_hmac_sha512 RNG Seed: 0 Generate: 0 bytes: 0 drbg_pr_hmac_sha384 RNG Seed: 0 Generate: 0 bytes: 0 drbg_pr_hmac_sha1 RNG Seed: 0 Generate: 0 bytes: 0 lzo-s
Patch "hwrng: core - sleep interruptible in read" has been added to the 4.4-stable tree
This is a note to let you know that I've just added the patch titled
hwrng: core - sleep interruptible in read
to the 4.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
hwrng-core-sleep-interruptible-in-read.patch
and it can be found in the queue-4.4 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let know about it.
>From 1ab87298cb59b649d8d648d25dc15b36ab865f5a Mon Sep 17 00:00:00 2001
From: Jiri Slaby
Date: Fri, 27 Nov 2015 16:50:43 +0100
Subject: hwrng: core - sleep interruptible in read
From: Jiri Slaby
commit 1ab87298cb59b649d8d648d25dc15b36ab865f5a upstream.
hwrng kthread can be waiting via hwrng_fillfn for some data from a rng
like virtio-rng:
hwrng D 880093e17798 0 382 2 0x
...
Call Trace:
[] wait_for_completion_killable+0x96/0x210
[] virtio_read+0x57/0xf0 [virtio_rng]
[] hwrng_fillfn+0x75/0x130
[] kthread+0xf3/0x110
And when some user program tries to read the /dev node in this state,
we get:
rngdD 880093e17798 0 762 1 0x0004
...
Call Trace:
[] mutex_lock_nested+0x15c/0x3e0
[] rng_dev_read+0x6e/0x240
[] __vfs_read+0x28/0xe0
[] vfs_read+0x83/0x130
And this is indeed unkillable. So use mutex_lock_interruptible
instead of mutex_lock in rng_dev_read and exit immediatelly when
interrupted. And possibly return already read data, if any (as POSIX
allows).
v2: use ERESTARTSYS instead of EINTR
Signed-off-by: Jiri Slaby
Cc: Matt Mackall
Cc: Herbert Xu
Cc:
Signed-off-by: Herbert Xu
Signed-off-by: Greg Kroah-Hartman
---
drivers/char/hw_random/core.c |6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
--- a/drivers/char/hw_random/core.c
+++ b/drivers/char/hw_random/core.c
@@ -238,7 +238,10 @@ static ssize_t rng_dev_read(struct file
goto out;
}
- mutex_lock(&reading_mutex);
+ if (mutex_lock_interruptible(&reading_mutex)) {
+ err = -ERESTARTSYS;
+ goto out_put;
+ }
if (!data_avail) {
bytes_read = rng_get_data(rng, rng_buffer,
rng_buffer_size(),
@@ -288,6 +291,7 @@ out:
out_unlock_reading:
mutex_unlock(&reading_mutex);
+out_put:
put_rng(rng);
goto out;
}
Patches currently in stable-queue which might be from jsl...@suse.cz are
queue-4.4/hwrng-core-sleep-interruptible-in-read.patch
Re: [Part2 PATCH v9 00/38] x86: Secure Encrypted Virtualization (AMD)
On 05/12/2017 02:04, Brijesh Singh wrote: > This part of Secure Encrypted Virtualization (SEV) patch series focuses on KVM > changes required to create and manage SEV guests. > > SEV is an extension to the AMD-V architecture which supports running encrypted > virtual machine (VMs) under the control of a hypervisor. Encrypted VMs have > their > pages (code and data) secured such that only the guest itself has access to > unencrypted version. Each encrypted VM is associated with a unique encryption > key; > if its data is accessed to a different entity using a different key the > encrypted > guest's data will be incorrectly decrypted, leading to unintelligible data. > This security model ensures that hypervisor will no longer able to inspect or > alter any guest code or data. > > The key management of this feature is handled by a separate processor known as > the AMD Secure Processor (AMD-SP) which is present on AMD SOCs. The SEV Key > Management Specification (see below) provides a set of commands which can be > used by hypervisor to load virtual machine keys through the AMD-SP driver. > > The patch series adds a new ioctl in KVM driver (KVM_MEMORY_ENCRYPT_OP). The > ioctl will be used by qemu to issue SEV guest-specific commands defined in Key > Management Specification. > > The following links provide additional details: > > AMD Memory Encryption white paper: > http://amd-dev.wpengine.netdna-cdn.com/wordpress/media/2013/12/AMD_Memory_Encryption_Whitepaper_v7-Public.pdf > > AMD64 Architecture Programmer's Manual: > http://support.amd.com/TechDocs/24593.pdf > SME is section 7.10 > SEV is section 15.34 > > SEV Key Management: > http://support.amd.com/TechDocs/55766_SEV-KM API_Specification.pdf > > KVM Forum Presentation: > http://www.linux-kvm.org/images/7/74/02x08A-Thomas_Lendacky-AMDs_Virtualizatoin_Memory_Encryption_Technology.pdf > > SEV Guest BIOS support: > SEV support has been add to EDKII/OVMF BIOS > https://github.com/tianocore/edk2 Merged! Thanks, Paolo
Re: [PATCH] hwrng: exynos - Signedness bug in exynos_trng_do_read()
It was <2018-01-10 śro 10:36>, when Dan Carpenter wrote:
> "val" needs to be signed for the error handling to work.
>
> Fixes: 6cd225cc5d8a ("hwrng: exynos - add Samsung Exynos True RNG driver")
> Signed-off-by: Dan Carpenter
>
Acked-by: Łukasz Stelmach
--
Łukasz Stelmach
Samsung R&D Institute Poland
Samsung Electronics
signature.asc
Description: PGP signature
[PATCH 0/5] crypto: chelsio - Cleanup and bug fixes
This series include cleanup, bug fixes and authenc algo supporting ctr(aes)-sha operation. Harsh Jain (5): crypto: chelsio - Fix Indentation crypto: chelsio - check for sg null crypto: chelsio - Fix IV updated in XTS operation crypto: chelsio - Add authenc versions of ctr and sha crypto: chelsio - Remove dst sg size zero check drivers/crypto/chelsio/chcr_algo.c | 299 ++- drivers/crypto/chelsio/chcr_crypto.h | 7 +- 2 files changed, 233 insertions(+), 73 deletions(-) -- 2.1.4
[PATCH 1/5] crypto: chelsio - Fix Indentation
Fix inconsistent Indenting.
Reported-by: Dan Carpenter
Signed-off-by: Harsh Jain
---
drivers/crypto/chelsio/chcr_algo.c | 28 +---
1 file changed, 13 insertions(+), 15 deletions(-)
diff --git a/drivers/crypto/chelsio/chcr_algo.c
b/drivers/crypto/chelsio/chcr_algo.c
index b663b93..f6b1161 100644
--- a/drivers/crypto/chelsio/chcr_algo.c
+++ b/drivers/crypto/chelsio/chcr_algo.c
@@ -683,7 +683,7 @@ static int chcr_sg_ent_in_wr(struct scatterlist *src,
if (srclen <= dstlen)
break;
less = min_t(unsigned int, sg_dma_len(dst) - offset -
- dstskip, CHCR_DST_SG_SIZE);
+dstskip, CHCR_DST_SG_SIZE);
dstlen += less;
offset += less;
if (offset == sg_dma_len(dst)) {
@@ -694,7 +694,7 @@ static int chcr_sg_ent_in_wr(struct scatterlist *src,
dstskip = 0;
}
src = sg_next(src);
-srcskip = 0;
+ srcskip = 0;
}
return min(srclen, dstlen);
}
@@ -1142,10 +1142,10 @@ static int chcr_handle_cipher_resp(struct
ablkcipher_request *req,
bytes = chcr_sg_ent_in_wr(reqctx->srcsg, reqctx->dstsg, 1,
SPACE_LEFT(ablkctx->enckey_len),
reqctx->src_ofst, reqctx->dst_ofst);
- if ((bytes + reqctx->processed) >= req->nbytes)
- bytes = req->nbytes - reqctx->processed;
- else
- bytes = ROUND_16(bytes);
+ if ((bytes + reqctx->processed) >= req->nbytes)
+ bytes = req->nbytes - reqctx->processed;
+ else
+ bytes = ROUND_16(bytes);
} else {
/*CTR mode counter overfloa*/
bytes = req->nbytes - reqctx->processed;
@@ -1246,15 +1246,15 @@ static int process_cipher(struct ablkcipher_request
*req,
MIN_CIPHER_SG,
SPACE_LEFT(ablkctx->enckey_len),
0, 0);
- if ((bytes + reqctx->processed) >= req->nbytes)
- bytes = req->nbytes - reqctx->processed;
- else
- bytes = ROUND_16(bytes);
+ if ((bytes + reqctx->processed) >= req->nbytes)
+ bytes = req->nbytes - reqctx->processed;
+ else
+ bytes = ROUND_16(bytes);
} else {
bytes = req->nbytes;
}
if (get_cryptoalg_subtype(crypto_ablkcipher_tfm(tfm)) ==
- CRYPTO_ALG_SUB_TYPE_CTR) {
+ CRYPTO_ALG_SUB_TYPE_CTR) {
bytes = adjust_ctr_overflow(req->info, bytes);
}
if (get_cryptoalg_subtype(crypto_ablkcipher_tfm(tfm)) ==
@@ -2399,10 +2399,8 @@ void chcr_add_hash_src_ent(struct ahash_request *req,
ulptx_walk_add_page(&ulp_walk, param->bfr_len,
&reqctx->dma_addr);
ulptx_walk_add_sg(&ulp_walk, req->src, param->sg_len,
- 0);
-//reqctx->srcsg = ulp_walk.last_sg;
-//reqctx->src_ofst = ulp_walk.last_sg_len;
- ulptx_walk_end(&ulp_walk);
+ 0);
+ ulptx_walk_end(&ulp_walk);
}
}
--
2.1.4
[PATCH 3/5] crypto: chelsio - Fix IV updated in XTS operation
Skip decrypt operation on IV received from HW for last request.
Signed-off-by: Harsh Jain
---
drivers/crypto/chelsio/chcr_algo.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
mode change 100644 => 100755 drivers/crypto/chelsio/chcr_algo.c
diff --git a/drivers/crypto/chelsio/chcr_algo.c
b/drivers/crypto/chelsio/chcr_algo.c
old mode 100644
new mode 100755
index 280377f..27ee920
--- a/drivers/crypto/chelsio/chcr_algo.c
+++ b/drivers/crypto/chelsio/chcr_algo.c
@@ -1017,7 +1017,8 @@ static unsigned int adjust_ctr_overflow(u8 *iv, u32 bytes)
return bytes;
}
-static int chcr_update_tweak(struct ablkcipher_request *req, u8 *iv)
+static int chcr_update_tweak(struct ablkcipher_request *req, u8 *iv,
+u32 isfinal)
{
struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(req);
struct ablk_ctx *ablkctx = ABLK_CTX(c_ctx(tfm));
@@ -1044,7 +1045,8 @@ static int chcr_update_tweak(struct ablkcipher_request
*req, u8 *iv)
for (i = 0; i < (round % 8); i++)
gf128mul_x_ble((le128 *)iv, (le128 *)iv);
- crypto_cipher_decrypt_one(cipher, iv, iv);
+ if (!isfinal)
+ crypto_cipher_decrypt_one(cipher, iv, iv);
out:
return ret;
}
@@ -1065,7 +1067,7 @@ static int chcr_update_cipher_iv(struct
ablkcipher_request *req,
CTR_RFC3686_IV_SIZE) = cpu_to_be32((reqctx->processed /
AES_BLOCK_SIZE) + 1);
else if (subtype == CRYPTO_ALG_SUB_TYPE_XTS)
- ret = chcr_update_tweak(req, iv);
+ ret = chcr_update_tweak(req, iv, 0);
else if (subtype == CRYPTO_ALG_SUB_TYPE_CBC) {
if (reqctx->op)
sg_pcopy_to_buffer(req->src, sg_nents(req->src), iv,
@@ -1096,7 +1098,7 @@ static int chcr_final_cipher_iv(struct ablkcipher_request
*req,
ctr_add_iv(iv, req->info, (reqctx->processed /
AES_BLOCK_SIZE));
else if (subtype == CRYPTO_ALG_SUB_TYPE_XTS)
- ret = chcr_update_tweak(req, iv);
+ ret = chcr_update_tweak(req, iv, 1);
else if (subtype == CRYPTO_ALG_SUB_TYPE_CBC) {
if (reqctx->op)
sg_pcopy_to_buffer(req->src, sg_nents(req->src), iv,
--
2.1.4
[PATCH 2/5] crypto: chelsio - check for sg null
Add warning message if sg is NULL after skipping bytes.
Reported-by: Dan Carpenter
Signed-off-by: Harsh Jain
---
drivers/crypto/chelsio/chcr_algo.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/chelsio/chcr_algo.c
b/drivers/crypto/chelsio/chcr_algo.c
index f6b1161..280377f 100644
--- a/drivers/crypto/chelsio/chcr_algo.c
+++ b/drivers/crypto/chelsio/chcr_algo.c
@@ -574,7 +574,8 @@ static void ulptx_walk_add_sg(struct ulptx_walk *walk,
skip = 0;
}
}
- if (walk->nents == 0) {
+ WARN(!sg, "SG should not be null here\n");
+ if (sg && (walk->nents == 0)) {
small = min_t(unsigned int, sg_dma_len(sg) - skip_len, len);
sgmin = min_t(unsigned int, small, CHCR_SRC_SG_SIZE);
walk->sgl->len0 = cpu_to_be32(sgmin);
--
2.1.4
[PATCH 5/5] crypto: chelsio - Remove dst sg size zero check
sg_nents_xlen will take care of zero length sg list.
Remove Destination sg list size zero check.
Signed-off-by: Harsh Jain
---
drivers/crypto/chelsio/chcr_algo.c | 43 --
1 file changed, 13 insertions(+), 30 deletions(-)
diff --git a/drivers/crypto/chelsio/chcr_algo.c
b/drivers/crypto/chelsio/chcr_algo.c
index 5cc84c4..a9c894b 100644
--- a/drivers/crypto/chelsio/chcr_algo.c
+++ b/drivers/crypto/chelsio/chcr_algo.c
@@ -2109,20 +2109,14 @@ static struct sk_buff *create_authenc_wr(struct
aead_request *req,
null = 1;
assoclen = 0;
}
- dst_size = assoclen + req->cryptlen + (op_type ? -authsize :
- authsize);
error = chcr_aead_common_init(req, op_type);
if (error)
return ERR_PTR(error);
- if (dst_size) {
dnents = sg_nents_xlen(req->dst, assoclen, CHCR_DST_SG_SIZE, 0);
dnents += sg_nents_xlen(req->dst, req->cryptlen +
(op_type ? -authsize : authsize), CHCR_DST_SG_SIZE,
req->assoclen);
dnents += MIN_AUTH_SG; // For IV
- } else {
- dnents = 0;
- }
dst_size = get_space_for_phys_dsgl(dnents);
kctx_len = (ntohl(KEY_CONTEXT_CTX_LEN_V(aeadctx->key_ctx_hdr)) << 4)
@@ -2687,8 +2681,6 @@ static struct sk_buff *create_aead_ccm_wr(struct
aead_request *req,
sub_type = get_aead_subtype(tfm);
if (sub_type == CRYPTO_ALG_SUB_TYPE_AEAD_RFC4309)
assoclen -= 8;
- dst_size = assoclen + req->cryptlen + (op_type ? -authsize :
- authsize);
error = chcr_aead_common_init(req, op_type);
if (error)
return ERR_PTR(error);
@@ -2698,15 +2690,11 @@ static struct sk_buff *create_aead_ccm_wr(struct
aead_request *req,
error = aead_ccm_validate_input(op_type, req, aeadctx, sub_type);
if (error)
goto err;
- if (dst_size) {
- dnents = sg_nents_xlen(req->dst, assoclen, CHCR_DST_SG_SIZE, 0);
- dnents += sg_nents_xlen(req->dst, req->cryptlen
- + (op_type ? -authsize : authsize),
- CHCR_DST_SG_SIZE, req->assoclen);
- dnents += MIN_CCM_SG; // For IV and B0
- } else {
- dnents = 0;
- }
+ dnents = sg_nents_xlen(req->dst, assoclen, CHCR_DST_SG_SIZE, 0);
+ dnents += sg_nents_xlen(req->dst, req->cryptlen
+ + (op_type ? -authsize : authsize),
+ CHCR_DST_SG_SIZE, req->assoclen);
+ dnents += MIN_CCM_SG; // For IV and B0
dst_size = get_space_for_phys_dsgl(dnents);
kctx_len = ((DIV_ROUND_UP(aeadctx->enckey_len, 16)) << 4) * 2;
transhdr_len = CIPHER_TRANSHDR_SIZE(kctx_len, dst_size);
@@ -2801,19 +2789,14 @@ static struct sk_buff *create_gcm_wr(struct
aead_request *req,
assoclen = req->assoclen - 8;
reqctx->b0_dma = 0;
- dst_size = assoclen + req->cryptlen + (op_type ? -authsize : authsize);
error = chcr_aead_common_init(req, op_type);
- if (error)
- return ERR_PTR(error);
- if (dst_size) {
- dnents = sg_nents_xlen(req->dst, assoclen, CHCR_DST_SG_SIZE, 0);
- dnents += sg_nents_xlen(req->dst,
- req->cryptlen + (op_type ? -authsize : authsize),
+ if (error)
+ return ERR_PTR(error);
+ dnents = sg_nents_xlen(req->dst, assoclen, CHCR_DST_SG_SIZE, 0);
+ dnents += sg_nents_xlen(req->dst, req->cryptlen +
+ (op_type ? -authsize : authsize),
CHCR_DST_SG_SIZE, req->assoclen);
- dnents += MIN_GCM_SG; // For IV
- } else {
- dnents = 0;
- }
+ dnents += MIN_GCM_SG; // For IV
dst_size = get_space_for_phys_dsgl(dnents);
kctx_len = ((DIV_ROUND_UP(aeadctx->enckey_len, 16)) << 4) +
AEAD_H_SIZE;
@@ -2850,10 +2833,10 @@ static struct sk_buff *create_gcm_wr(struct
aead_request *req,
chcr_req->sec_cpl.aadstart_cipherstop_hi = FILL_SEC_CPL_CIPHERSTOP_HI(
assoclen ? 1 : 0, assoclen,
assoclen + IV + 1, 0);
- chcr_req->sec_cpl.cipherstop_lo_authinsert =
+ chcr_req->sec_cpl.cipherstop_lo_authinsert =
FILL_SEC_CPL_AUTHINSERT(0, assoclen + IV + 1,
temp, temp);
- chcr_req->sec_cpl.seqno_numivs =
+ chcr_req->sec_cpl.seqno_numivs =
FILL_SEC_CPL_SCMD0_SEQNO(op_type, (op_type ==
CHCR_ENCRYPT_OP) ? 1 : 0,
CHCR_SCMD_CIPHER_MODE_
[PATCH 4/5] crypto: chelsio - Add authenc versions of ctr and sha
Add ctr and sha combination of algo in authenc mode.
Signed-off-by: Harsh Jain
---
drivers/crypto/chelsio/chcr_algo.c | 215 +++
drivers/crypto/chelsio/chcr_crypto.h | 7 +-
2 files changed, 199 insertions(+), 23 deletions(-)
mode change 100755 => 100644 drivers/crypto/chelsio/chcr_algo.c
diff --git a/drivers/crypto/chelsio/chcr_algo.c
b/drivers/crypto/chelsio/chcr_algo.c
old mode 100755
new mode 100644
index 27ee920..5cc84c4
--- a/drivers/crypto/chelsio/chcr_algo.c
+++ b/drivers/crypto/chelsio/chcr_algo.c
@@ -2090,7 +2090,7 @@ static struct sk_buff *create_authenc_wr(struct
aead_request *req,
struct cpl_rx_phys_dsgl *phys_cpl;
struct ulptx_sgl *ulptx;
unsigned int transhdr_len;
- unsigned int dst_size = 0, temp;
+ unsigned int dst_size = 0, temp, subtype = get_aead_subtype(tfm);
unsigned int kctx_len = 0, dnents;
unsigned int assoclen = req->assoclen;
unsigned int authsize = crypto_aead_authsize(tfm);
@@ -2104,7 +2104,8 @@ static struct sk_buff *create_authenc_wr(struct
aead_request *req,
return NULL;
reqctx->b0_dma = 0;
- if (get_aead_subtype(tfm) == CRYPTO_ALG_SUB_TYPE_AEAD_NULL) {
+ if (subtype == CRYPTO_ALG_SUB_TYPE_CBC_NULL ||
+ subtype == CRYPTO_ALG_SUB_TYPE_CTR_NULL) {
null = 1;
assoclen = 0;
}
@@ -2169,16 +2170,23 @@ static struct sk_buff *create_authenc_wr(struct
aead_request *req,
temp & 0xF,
null ? 0 : assoclen + IV + 1,
temp, temp);
+ if (subtype == CRYPTO_ALG_SUB_TYPE_CTR_NULL ||
+ subtype == CRYPTO_ALG_SUB_TYPE_CTR_SHA)
+ temp = CHCR_SCMD_CIPHER_MODE_AES_CTR;
+ else
+ temp = CHCR_SCMD_CIPHER_MODE_AES_CBC;
chcr_req->sec_cpl.seqno_numivs = FILL_SEC_CPL_SCMD0_SEQNO(op_type,
(op_type == CHCR_ENCRYPT_OP) ? 1 : 0,
- CHCR_SCMD_CIPHER_MODE_AES_CBC,
+ temp,
actx->auth_mode, aeadctx->hmac_ctrl,
IV >> 1);
chcr_req->sec_cpl.ivgen_hdrlen = FILL_SEC_CPL_IVGEN_HDRLEN(0, 0, 1,
0, 0, dst_size);
chcr_req->key_ctx.ctx_hdr = aeadctx->key_ctx_hdr;
- if (op_type == CHCR_ENCRYPT_OP)
+ if (op_type == CHCR_ENCRYPT_OP ||
+ subtype == CRYPTO_ALG_SUB_TYPE_CTR_SHA ||
+ subtype == CRYPTO_ALG_SUB_TYPE_CTR_NULL)
memcpy(chcr_req->key_ctx.key, aeadctx->key,
aeadctx->enckey_len);
else
@@ -2188,7 +2196,16 @@ static struct sk_buff *create_authenc_wr(struct
aead_request *req,
memcpy(chcr_req->key_ctx.key + (DIV_ROUND_UP(aeadctx->enckey_len, 16) <<
4), actx->h_iopad, kctx_len -
(DIV_ROUND_UP(aeadctx->enckey_len, 16) << 4));
- memcpy(reqctx->iv, req->iv, IV);
+ if (subtype == CRYPTO_ALG_SUB_TYPE_CTR_SHA ||
+ subtype == CRYPTO_ALG_SUB_TYPE_CTR_NULL) {
+ memcpy(reqctx->iv, aeadctx->nonce, CTR_RFC3686_NONCE_SIZE);
+ memcpy(reqctx->iv + CTR_RFC3686_NONCE_SIZE, req->iv,
+ CTR_RFC3686_IV_SIZE);
+ *(__be32 *)(reqctx->iv + CTR_RFC3686_NONCE_SIZE +
+ CTR_RFC3686_IV_SIZE) = cpu_to_be32(1);
+ } else {
+ memcpy(reqctx->iv, req->iv, IV);
+ }
phys_cpl = (struct cpl_rx_phys_dsgl *)((u8 *)(chcr_req + 1) + kctx_len);
ulptx = (struct ulptx_sgl *)((u8 *)(phys_cpl + 1) + dst_size);
chcr_add_aead_dst_ent(req, phys_cpl, assoclen, op_type, qid);
@@ -3216,7 +3233,7 @@ static int chcr_authenc_setkey(struct crypto_aead
*authenc, const u8 *key,
struct chcr_authenc_ctx *actx = AUTHENC_CTX(aeadctx);
/* it contains auth and cipher key both*/
struct crypto_authenc_keys keys;
- unsigned int bs;
+ unsigned int bs, subtype;
unsigned int max_authsize = crypto_aead_alg(authenc)->maxauthsize;
int err = 0, i, key_ctx_len = 0;
unsigned char ck_size = 0;
@@ -3245,6 +3262,15 @@ static int chcr_authenc_setkey(struct crypto_aead
*authenc, const u8 *key,
pr_err("chcr : Unsupported digest size\n");
goto out;
}
+ subtype = get_aead_subtype(authenc);
+ if (subtype == CRYPTO_ALG_SUB_TYPE_CTR_SHA ||
+ subtype == CRYPTO_ALG_SUB_TYPE_CTR_NULL) {
+ if (keys.enckeylen < CTR_RFC3686_NONCE_SIZE)
+ goto out;
+ memcpy(aeadctx->nonce, keys.enckey + (keys.enckeylen
+ - CTR_RFC3686_NONCE_SIZE), CTR_RFC3686_NONCE_SIZE);
+ keys.enckeylen -= CTR_RF
Re: [PATCH -next] hwrng: exynos - remove redundant dev_err call in exynos_trng_probe()
It was <2018-01-10 śro 14:30>, when Wei Yongjun wrote:
> There is a error message within devm_ioremap_resource
> already, so remove the dev_err call to avoid redundant
> error message.
>
> Signed-off-by: Wei Yongjun
Acked-by: Łukasz Stelmach
> ---
> drivers/char/hw_random/exynos-trng.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/char/hw_random/exynos-trng.c
> b/drivers/char/hw_random/exynos-trng.c
> index 34d6f51..4c8a2be 100644
> --- a/drivers/char/hw_random/exynos-trng.c
> +++ b/drivers/char/hw_random/exynos-trng.c
> @@ -129,10 +129,8 @@ static int exynos_trng_probe(struct platform_device
> *pdev)
>
> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> trng->mem = devm_ioremap_resource(&pdev->dev, res);
> - if (IS_ERR(trng->mem)) {
> - dev_err(&pdev->dev, "Could not map IO resources.\n");
> + if (IS_ERR(trng->mem))
> return PTR_ERR(trng->mem);
> - }
>
> pm_runtime_enable(&pdev->dev);
> ret = pm_runtime_get_sync(&pdev->dev);
>
>
>
>
--
Łukasz Stelmach
Samsung R&D Institute Poland
Samsung Electronics
signature.asc
Description: PGP signature
[PATCH -next] staging: ccree: remove redundant dev_err call in init_cc_resources()
There is a error message within devm_ioremap_resource
already, so remove the dev_err call to avoid redundant
error message.
Signed-off-by: Wei Yongjun
---
drivers/staging/ccree/cc_driver.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/staging/ccree/cc_driver.c
b/drivers/staging/ccree/cc_driver.c
index 6682d9d..c27d5a8 100644
--- a/drivers/staging/ccree/cc_driver.c
+++ b/drivers/staging/ccree/cc_driver.c
@@ -174,10 +174,8 @@ static int init_cc_resources(struct platform_device
*plat_dev)
req_mem_cc_regs = platform_get_resource(plat_dev, IORESOURCE_MEM, 0);
/* Map registers space */
new_drvdata->cc_base = devm_ioremap_resource(dev, req_mem_cc_regs);
- if (IS_ERR(new_drvdata->cc_base)) {
- dev_err(dev, "Failed to ioremap registers");
+ if (IS_ERR(new_drvdata->cc_base))
return PTR_ERR(new_drvdata->cc_base);
- }
dev_dbg(dev, "Got MEM resource (%s): %pR\n", req_mem_cc_regs->name,
req_mem_cc_regs);
[PATCH] staging: ccree: don't break lines unnecessarily
These lines are less than 80 characters so we don't need to break them
up into chunks.
Signed-off-by: Dan Carpenter
diff --git a/drivers/staging/ccree/cc_aead.c b/drivers/staging/ccree/cc_aead.c
index 265adffdab41..b58413172231 100644
--- a/drivers/staging/ccree/cc_aead.c
+++ b/drivers/staging/ccree/cc_aead.c
@@ -2600,8 +2600,7 @@ static struct cc_crypto_alg *cc_create_aead_alg(struct
cc_alg_template *tmpl,
alg = &tmpl->template_aead;
- snprintf(alg->base.cra_name, CRYPTO_MAX_ALG_NAME, "%s",
-tmpl->name);
+ snprintf(alg->base.cra_name, CRYPTO_MAX_ALG_NAME, "%s", tmpl->name);
snprintf(alg->base.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s",
tmpl->driver_name);
alg->base.cra_module = THIS_MODULE;
diff --git a/drivers/staging/ccree/cc_cipher.c
b/drivers/staging/ccree/cc_cipher.c
index 8afdbc120b13..5c7e91f1cde7 100644
--- a/drivers/staging/ccree/cc_cipher.c
+++ b/drivers/staging/ccree/cc_cipher.c
@@ -127,8 +127,7 @@ static int validate_data_size(struct cc_cipher_ctx *ctx_p,
static unsigned int get_max_keysize(struct crypto_tfm *tfm)
{
struct cc_crypto_alg *cc_alg =
- container_of(tfm->__crt_alg, struct cc_crypto_alg,
-crypto_alg);
+ container_of(tfm->__crt_alg, struct cc_crypto_alg, crypto_alg);
if ((cc_alg->crypto_alg.cra_flags & CRYPTO_ALG_TYPE_MASK) ==
CRYPTO_ALG_TYPE_ABLKCIPHER)
@@ -391,8 +390,7 @@ static void cc_setup_cipher_desc(struct crypto_tfm *tfm,
unsigned int du_size = nbytes;
struct cc_crypto_alg *cc_alg =
- container_of(tfm->__crt_alg, struct cc_crypto_alg,
-crypto_alg);
+ container_of(tfm->__crt_alg, struct cc_crypto_alg, crypto_alg);
if ((cc_alg->crypto_alg.cra_flags & CRYPTO_ALG_BULK_MASK) ==
CRYPTO_ALG_BULK_DU_512)
@@ -611,8 +609,7 @@ static void cc_cipher_complete(struct device *dev, void
*cc_req, int err)
kfree(req_ctx->backup_info);
} else if (!err) {
scatterwalk_map_and_copy(req->info, req->dst,
-(req->nbytes - ivsize),
-ivsize, 0);
+(req->nbytes - ivsize), ivsize, 0);
}
ablkcipher_request_complete(areq, err);
@@ -1096,8 +1093,7 @@ struct cc_crypto_alg *cc_cipher_create_alg(struct
cc_alg_template *template,
int cc_cipher_free(struct cc_drvdata *drvdata)
{
struct cc_crypto_alg *t_alg, *n;
- struct cc_cipher_handle *blkcipher_handle =
- drvdata->blkcipher_handle;
+ struct cc_cipher_handle *blkcipher_handle = drvdata->blkcipher_handle;
if (blkcipher_handle) {
/* Remove registered algs */
list_for_each_entry_safe(t_alg, n,
diff --git a/drivers/staging/ccree/cc_driver.c
b/drivers/staging/ccree/cc_driver.c
index 6682d9d93931..192b1759de45 100644
--- a/drivers/staging/ccree/cc_driver.c
+++ b/drivers/staging/ccree/cc_driver.c
@@ -216,8 +216,7 @@ static int init_cc_resources(struct platform_device
*plat_dev)
}
if (rc) {
- dev_err(dev, "Failed in dma_set_mask, mask=%par\n",
- &dma_mask);
+ dev_err(dev, "Failed in dma_set_mask, mask=%par\n", &dma_mask);
return rc;
}
diff --git a/drivers/staging/ccree/cc_fips.c b/drivers/staging/ccree/cc_fips.c
index b25c34e08717..de08af976b7f 100644
--- a/drivers/staging/ccree/cc_fips.c
+++ b/drivers/staging/ccree/cc_fips.c
@@ -53,8 +53,7 @@ void cc_fips_fini(struct cc_drvdata *drvdata)
void fips_handler(struct cc_drvdata *drvdata)
{
- struct cc_fips_handle *fips_handle_ptr =
- drvdata->fips_handle;
+ struct cc_fips_handle *fips_handle_ptr = drvdata->fips_handle;
tasklet_schedule(&fips_handle_ptr->tasklet);
}
diff --git a/drivers/staging/ccree/cc_hash.c b/drivers/staging/ccree/cc_hash.c
index 86f9ec711edc..8afc39f10bb3 100644
--- a/drivers/staging/ccree/cc_hash.c
+++ b/drivers/staging/ccree/cc_hash.c
@@ -1858,9 +1858,8 @@ int cc_init_hash_sram(struct cc_drvdata *drvdata)
hash_handle->larval_digest_sram_addr = sram_buff_ofs;
/* Copy-to-sram initial SHA* digests */
- cc_set_sram_desc(md5_init, sram_buff_ofs,
-ARRAY_SIZE(md5_init), larval_seq,
-&larval_seq_len);
+ cc_set_sram_desc(md5_init, sram_buff_ofs, ARRAY_SIZE(md5_init),
+larval_seq, &larval_seq_len);
rc = send_request_init(drvdata, larval_seq, larval_seq_len);
if (rc)
goto init_digest_const_err;
@@ -2004,8 +2003,7 @@ int cc_hash_alloc(struct cc_drvdata *drvdata)
kfree(t_alg);
goto fail;
} else {
- list_add_tail(&t_alg->entry
Re: [PATCH 3/7] crypto: ccree: add ablkcipher support
Am Donnerstag, 11. Januar 2018, 10:17:10 CET schrieb Gilad Ben-Yossef:
Hi Gilad,
> + // verify weak keys
> + if (ctx_p->flow_mode == S_DIN_to_DES) {
> + if (!des_ekey(tmp, key) &&
> + (crypto_tfm_get_flags(tfm) & CRYPTO_TFM_REQ_WEAK_KEY)) {
> + tfm->crt_flags |= CRYPTO_TFM_RES_WEAK_KEY;
> + dev_dbg(dev, "weak DES key");
> + return -EINVAL;
> + }
> + }
> + if (ctx_p->cipher_mode == DRV_CIPHER_XTS &&
> + xts_check_key(tfm, key, keylen)) {
> + dev_dbg(dev, "weak XTS key");
> + return -EINVAL;
> + }
> + if (ctx_p->flow_mode == S_DIN_to_DES &&
> + keylen == DES3_EDE_KEY_SIZE &&
> + cc_verify_3des_keys(key, keylen)) {
> + dev_dbg(dev, "weak 3DES key");
> + return -EINVAL;
> + }
For the DES key, wouldn't it make sense to use __des3_ede_setkey?
Note, I would plan to release a patch for review to change that function to
disallow key1 == key2 or key1 == key3 or key2 == key3 in FIPS mode.
Ciao
Stephan
Re: [PATCH 3/7] crypto: ccree: add ablkcipher support
On Thu, Jan 11, 2018 at 09:17:10AM +, Gilad Ben-Yossef wrote:
> Add CryptoCell ablkcipher support
>
Hello
I have some minor comments:
ablkcipher is deprecated, so you need to use skcipher instead.
> Signed-off-by: Gilad Ben-Yossef
> ---
> drivers/crypto/ccree/Makefile|2 +-
> drivers/crypto/ccree/cc_buffer_mgr.c | 125
> drivers/crypto/ccree/cc_buffer_mgr.h | 10 +
> drivers/crypto/ccree/cc_cipher.c | 1167
> ++
> drivers/crypto/ccree/cc_cipher.h | 74 +++
> drivers/crypto/ccree/cc_driver.c | 11 +
> drivers/crypto/ccree/cc_driver.h |2 +
> 7 files changed, 1390 insertions(+), 1 deletion(-)
> create mode 100644 drivers/crypto/ccree/cc_cipher.c
> create mode 100644 drivers/crypto/ccree/cc_cipher.h
>
[...]
> +
> +struct tdes_keys {
> + u8 key1[DES_KEY_SIZE];
> + u8 key2[DES_KEY_SIZE];
> + u8 key3[DES_KEY_SIZE];
> +};
> +
> +static const u8 zero_buff[] = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
> + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
> + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
> + 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
> +
This constant is used nowhere.
> +/* The function verifies that tdes keys are not weak.*/
> +static int cc_verify_3des_keys(const u8 *key, unsigned int keylen)
> +{
> + struct tdes_keys *tdes_key = (struct tdes_keys *)key;
> +
> + /* verify key1 != key2 and key3 != key2*/
> + if ((memcmp((u8 *)tdes_key->key1, (u8 *)tdes_key->key2,
> + sizeof(tdes_key->key1)) == 0) ||
> + (memcmp((u8 *)tdes_key->key3, (u8 *)tdes_key->key2,
> + sizeof(tdes_key->key3)) == 0)) {
> + return -ENOEXEC;
> + }
> +
> + return 0;
> +}
All driver testing 3des key also use des_ekey()
[...]
> +static void cc_cipher_complete(struct device *dev, void *cc_req, int err)
> +{
> + struct ablkcipher_request *areq = (struct ablkcipher_request *)cc_req;
> + struct scatterlist *dst = areq->dst;
> + struct scatterlist *src = areq->src;
> + struct blkcipher_req_ctx *req_ctx = ablkcipher_request_ctx(areq);
> + struct crypto_ablkcipher *tfm = crypto_ablkcipher_reqtfm(areq);
> + unsigned int ivsize = crypto_ablkcipher_ivsize(tfm);
> + struct ablkcipher_request *req = (struct ablkcipher_request *)areq;
> +
> + cc_unmap_blkcipher_request(dev, req_ctx, ivsize, src, dst);
> + kfree(req_ctx->iv);
kzfree for all stuff with IV/key
[...]
> +
> +#ifdef CRYPTO_TFM_REQ_HW_KEY
> +
> +static inline bool cc_is_hw_key(struct crypto_tfm *tfm)
> +{
> + return (crypto_tfm_get_flags(tfm) & CRYPTO_TFM_REQ_HW_KEY);
> +}
> +
> +#else
> +
> +struct arm_hw_key_info {
> + int hw_key1;
> + int hw_key2;
> +};
> +
> +static inline bool cc_is_hw_key(struct crypto_tfm *tfm)
> +{
> + return false;
> +}
> +
> +#endif /* CRYPTO_TFM_REQ_HW_KEY */
I see nowhere any use/documentation of CRYPTO_TFM_REQ_HW_KEY, so a cleaning
could be done
Regards
[PATCH 1/7] staging: ccree: remove ccree from staging tree
Remove the ccree driver from the staging tree in preparation to introducing it in the crypto tree. Signed-off-by: Gilad Ben-Yossef --- drivers/staging/Kconfig|2 - drivers/staging/Makefile |1 - .../devicetree/bindings/crypto/arm-cryptocell.txt | 27 - drivers/staging/ccree/Kconfig | 25 - drivers/staging/ccree/Makefile |3 - drivers/staging/ccree/TODO | 30 - drivers/staging/ccree/cc_crypto_ctx.h | 200 -- drivers/staging/ccree/cc_hw_queue_defs.h | 594 - drivers/staging/ccree/cc_lli_defs.h| 72 - drivers/staging/ccree/dx_crys_kernel.h | 180 -- drivers/staging/ccree/dx_host.h| 155 -- drivers/staging/ccree/dx_reg_common.h | 26 - drivers/staging/ccree/hash_defs.h | 36 - drivers/staging/ccree/ssi_aead.c | 2794 drivers/staging/ccree/ssi_aead.h | 117 - drivers/staging/ccree/ssi_buffer_mgr.c | 1776 - drivers/staging/ccree/ssi_buffer_mgr.h | 91 - drivers/staging/ccree/ssi_cipher.c | 1357 -- drivers/staging/ccree/ssi_cipher.h | 84 - drivers/staging/ccree/ssi_config.h | 36 - drivers/staging/ccree/ssi_driver.c | 538 drivers/staging/ccree/ssi_driver.h | 206 -- drivers/staging/ccree/ssi_fips.c | 126 - drivers/staging/ccree/ssi_fips.h | 49 - drivers/staging/ccree/ssi_hash.c | 2549 -- drivers/staging/ccree/ssi_hash.h | 103 - drivers/staging/ccree/ssi_ivgen.c | 299 --- drivers/staging/ccree/ssi_ivgen.h | 71 - drivers/staging/ccree/ssi_pm.c | 145 - drivers/staging/ccree/ssi_pm.h | 43 - drivers/staging/ccree/ssi_request_mgr.c| 610 - drivers/staging/ccree/ssi_request_mgr.h| 60 - drivers/staging/ccree/ssi_sram_mgr.c | 123 - drivers/staging/ccree/ssi_sram_mgr.h | 79 - drivers/staging/ccree/ssi_sysfs.c | 172 -- drivers/staging/ccree/ssi_sysfs.h | 55 - 36 files changed, 12834 deletions(-) delete mode 100644 drivers/staging/ccree/Documentation/devicetree/bindings/crypto/arm-cryptocell.txt delete mode 100644 drivers/staging/ccree/Kconfig delete mode 100644 drivers/staging/ccree/Makefile delete mode 100644 drivers/staging/ccree/TODO delete mode 100644 drivers/staging/ccree/cc_crypto_ctx.h delete mode 100644 drivers/staging/ccree/cc_hw_queue_defs.h delete mode 100644 drivers/staging/ccree/cc_lli_defs.h delete mode 100644 drivers/staging/ccree/dx_crys_kernel.h delete mode 100644 drivers/staging/ccree/dx_host.h delete mode 100644 drivers/staging/ccree/dx_reg_common.h delete mode 100644 drivers/staging/ccree/hash_defs.h delete mode 100644 drivers/staging/ccree/ssi_aead.c delete mode 100644 drivers/staging/ccree/ssi_aead.h delete mode 100644 drivers/staging/ccree/ssi_buffer_mgr.c delete mode 100644 drivers/staging/ccree/ssi_buffer_mgr.h delete mode 100644 drivers/staging/ccree/ssi_cipher.c delete mode 100644 drivers/staging/ccree/ssi_cipher.h delete mode 100644 drivers/staging/ccree/ssi_config.h delete mode 100644 drivers/staging/ccree/ssi_driver.c delete mode 100644 drivers/staging/ccree/ssi_driver.h delete mode 100644 drivers/staging/ccree/ssi_fips.c delete mode 100644 drivers/staging/ccree/ssi_fips.h delete mode 100644 drivers/staging/ccree/ssi_hash.c delete mode 100644 drivers/staging/ccree/ssi_hash.h delete mode 100644 drivers/staging/ccree/ssi_ivgen.c delete mode 100644 drivers/staging/ccree/ssi_ivgen.h delete mode 100644 drivers/staging/ccree/ssi_pm.c delete mode 100644 drivers/staging/ccree/ssi_pm.h delete mode 100644 drivers/staging/ccree/ssi_request_mgr.c delete mode 100644 drivers/staging/ccree/ssi_request_mgr.h delete mode 100644 drivers/staging/ccree/ssi_sram_mgr.c delete mode 100644 drivers/staging/ccree/ssi_sram_mgr.h delete mode 100644 drivers/staging/ccree/ssi_sysfs.c delete mode 100644 drivers/staging/ccree/ssi_sysfs.h diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig index 5546839..72946bf 100644 --- a/drivers/staging/Kconfig +++ b/drivers/staging/Kconfig @@ -110,8 +110,6 @@ source "drivers/staging/greybus/Kconfig" source "drivers/staging/vc04_services/Kconfig" -source "drivers/staging/ccree/Kconfig" - source "drivers/staging/typec/Kconfig" source "drivers/staging/vboxvideo/Kconfig" diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile index 6e53602..7612bee 100644 --- a/drivers/staging/Makefile +++ b/drivers/staging/Makefile @@ -47,6 +47,5 @@ obj-$(CONFIG_MOST)+= most/ obj-$(CONFIG_KS7010)
[PATCH 3/7] crypto: ccree: add ablkcipher support
Add CryptoCell ablkcipher support
Signed-off-by: Gilad Ben-Yossef
---
drivers/crypto/ccree/Makefile|2 +-
drivers/crypto/ccree/cc_buffer_mgr.c | 125
drivers/crypto/ccree/cc_buffer_mgr.h | 10 +
drivers/crypto/ccree/cc_cipher.c | 1167 ++
drivers/crypto/ccree/cc_cipher.h | 74 +++
drivers/crypto/ccree/cc_driver.c | 11 +
drivers/crypto/ccree/cc_driver.h |2 +
7 files changed, 1390 insertions(+), 1 deletion(-)
create mode 100644 drivers/crypto/ccree/cc_cipher.c
create mode 100644 drivers/crypto/ccree/cc_cipher.h
diff --git a/drivers/crypto/ccree/Makefile b/drivers/crypto/ccree/Makefile
index 6b204ab..a7fecad 100644
--- a/drivers/crypto/ccree/Makefile
+++ b/drivers/crypto/ccree/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_CRYPTO_DEV_CCREE) := ccree.o
-ccree-y := cc_driver.o cc_buffer_mgr.o cc_request_mgr.o cc_ivgen.o
cc_sram_mgr.o
+ccree-y := cc_driver.o cc_buffer_mgr.o cc_request_mgr.o cc_cipher.o cc_ivgen.o
cc_sram_mgr.o
ccree-$(CONFIG_DEBUG_FS) += cc_debugfs.o
ccree-$(CONFIG_PM) += cc_pm.o
diff --git a/drivers/crypto/ccree/cc_buffer_mgr.c
b/drivers/crypto/ccree/cc_buffer_mgr.c
index 4c67579..510993e 100644
--- a/drivers/crypto/ccree/cc_buffer_mgr.c
+++ b/drivers/crypto/ccree/cc_buffer_mgr.c
@@ -8,6 +8,7 @@
#include "cc_buffer_mgr.h"
#include "cc_lli_defs.h"
+#include "cc_cipher.h"
enum dma_buffer_type {
DMA_NULL_TYPE = -1,
@@ -347,6 +348,130 @@ static int cc_map_sg(struct device *dev, struct
scatterlist *sg,
return 0;
}
+void cc_unmap_blkcipher_request(struct device *dev, void *ctx,
+ unsigned int ivsize, struct scatterlist *src,
+ struct scatterlist *dst)
+{
+ struct blkcipher_req_ctx *req_ctx = (struct blkcipher_req_ctx *)ctx;
+
+ if (req_ctx->gen_ctx.iv_dma_addr) {
+ dev_dbg(dev, "Unmapped iv: iv_dma_addr=%pad iv_size=%u\n",
+ &req_ctx->gen_ctx.iv_dma_addr, ivsize);
+ dma_unmap_single(dev, req_ctx->gen_ctx.iv_dma_addr,
+ivsize,
+req_ctx->is_giv ? DMA_BIDIRECTIONAL :
+DMA_TO_DEVICE);
+ }
+ /* Release pool */
+ if (req_ctx->dma_buf_type == CC_DMA_BUF_MLLI &&
+ req_ctx->mlli_params.mlli_virt_addr) {
+ dma_pool_free(req_ctx->mlli_params.curr_pool,
+ req_ctx->mlli_params.mlli_virt_addr,
+ req_ctx->mlli_params.mlli_dma_addr);
+ }
+
+ dma_unmap_sg(dev, src, req_ctx->in_nents, DMA_BIDIRECTIONAL);
+ dev_dbg(dev, "Unmapped req->src=%pK\n", sg_virt(src));
+
+ if (src != dst) {
+ dma_unmap_sg(dev, dst, req_ctx->out_nents, DMA_BIDIRECTIONAL);
+ dev_dbg(dev, "Unmapped req->dst=%pK\n", sg_virt(dst));
+ }
+}
+
+int cc_map_blkcipher_request(struct cc_drvdata *drvdata, void *ctx,
+unsigned int ivsize, unsigned int nbytes,
+void *info, struct scatterlist *src,
+struct scatterlist *dst, gfp_t flags)
+{
+ struct blkcipher_req_ctx *req_ctx = (struct blkcipher_req_ctx *)ctx;
+ struct mlli_params *mlli_params = &req_ctx->mlli_params;
+ struct buff_mgr_handle *buff_mgr = drvdata->buff_mgr_handle;
+ struct device *dev = drvdata_to_dev(drvdata);
+ struct buffer_array sg_data;
+ u32 dummy = 0;
+ int rc = 0;
+ u32 mapped_nents = 0;
+
+ req_ctx->dma_buf_type = CC_DMA_BUF_DLLI;
+ mlli_params->curr_pool = NULL;
+ sg_data.num_of_buffers = 0;
+
+ /* Map IV buffer */
+ if (ivsize) {
+ dump_byte_array("iv", (u8 *)info, ivsize);
+ req_ctx->gen_ctx.iv_dma_addr =
+ dma_map_single(dev, (void *)info,
+ ivsize,
+ req_ctx->is_giv ? DMA_BIDIRECTIONAL :
+ DMA_TO_DEVICE);
+ if (dma_mapping_error(dev, req_ctx->gen_ctx.iv_dma_addr)) {
+ dev_err(dev, "Mapping iv %u B at va=%pK for DMA
failed\n",
+ ivsize, info);
+ return -ENOMEM;
+ }
+ dev_dbg(dev, "Mapped iv %u B at va=%pK to dma=%pad\n",
+ ivsize, info, &req_ctx->gen_ctx.iv_dma_addr);
+ } else {
+ req_ctx->gen_ctx.iv_dma_addr = 0;
+ }
+
+ /* Map the src SGL */
+ rc = cc_map_sg(dev, src, nbytes, DMA_BIDIRECTIONAL, &req_ctx->in_nents,
+ LLI_MAX_NUM_OF_DATA_ENTRIES, &dummy, &mapped_nents);
+ if (rc) {
+ rc = -ENOMEM;
+ goto ablkcipher_exit;
+ }
+ if (mapped_nents > 1)
+ req_ctx->dma_buf_type = CC_DMA_BUF_MLLI;
+
+ i
[PATCH 2/7] crypto: ccree: introduce CryptoCell driver
Introduce basic low level Arm TrustZone CryptoCell HW support. This first patch doesn't actually register any Crypto API transformations, these will follow up in the next patch. This first revision supports the CC 712 REE component. Signed-off-by: Gilad Ben-Yossef --- drivers/crypto/Kconfig | 27 ++ drivers/crypto/Makefile | 1 + drivers/crypto/ccree/Makefile | 6 + drivers/crypto/ccree/cc_buffer_mgr.c| 387 + drivers/crypto/ccree/cc_buffer_mgr.h| 60 +++ drivers/crypto/ccree/cc_crypto_ctx.h| 170 drivers/crypto/ccree/cc_debugfs.c | 101 + drivers/crypto/ccree/cc_debugfs.h | 32 ++ drivers/crypto/ccree/cc_driver.c| 418 +++ drivers/crypto/ccree/cc_driver.h| 186 + drivers/crypto/ccree/cc_host_regs.h | 142 +++ drivers/crypto/ccree/cc_hw_queue_defs.h | 590 ++ drivers/crypto/ccree/cc_ivgen.c | 280 + drivers/crypto/ccree/cc_ivgen.h | 55 +++ drivers/crypto/ccree/cc_kernel_regs.h | 167 drivers/crypto/ccree/cc_lli_defs.h | 59 +++ drivers/crypto/ccree/cc_pm.c| 119 ++ drivers/crypto/ccree/cc_pm.h| 57 +++ drivers/crypto/ccree/cc_request_mgr.c | 714 drivers/crypto/ccree/cc_request_mgr.h | 51 +++ drivers/crypto/ccree/cc_sram_mgr.c | 107 + drivers/crypto/ccree/cc_sram_mgr.h | 65 +++ 22 files changed, 3794 insertions(+) create mode 100644 drivers/crypto/ccree/Makefile create mode 100644 drivers/crypto/ccree/cc_buffer_mgr.c create mode 100644 drivers/crypto/ccree/cc_buffer_mgr.h create mode 100644 drivers/crypto/ccree/cc_crypto_ctx.h create mode 100644 drivers/crypto/ccree/cc_debugfs.c create mode 100644 drivers/crypto/ccree/cc_debugfs.h create mode 100644 drivers/crypto/ccree/cc_driver.c create mode 100644 drivers/crypto/ccree/cc_driver.h create mode 100644 drivers/crypto/ccree/cc_host_regs.h create mode 100644 drivers/crypto/ccree/cc_hw_queue_defs.h create mode 100644 drivers/crypto/ccree/cc_ivgen.c create mode 100644 drivers/crypto/ccree/cc_ivgen.h create mode 100644 drivers/crypto/ccree/cc_kernel_regs.h create mode 100644 drivers/crypto/ccree/cc_lli_defs.h create mode 100644 drivers/crypto/ccree/cc_pm.c create mode 100644 drivers/crypto/ccree/cc_pm.h create mode 100644 drivers/crypto/ccree/cc_request_mgr.c create mode 100644 drivers/crypto/ccree/cc_request_mgr.h create mode 100644 drivers/crypto/ccree/cc_sram_mgr.c create mode 100644 drivers/crypto/ccree/cc_sram_mgr.h diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 47ec920..ed912bf 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -731,4 +731,31 @@ config CRYPTO_DEV_ARTPEC6 To compile this driver as a module, choose M here. +config CRYPTO_DEV_CCREE + tristate "Support for ARM TrustZone CryptoCell family of security processors" + depends on CRYPTO && CRYPTO_HW && OF && HAS_DMA + default n + select CRYPTO_HASH + select CRYPTO_BLKCIPHER + select CRYPTO_DES + select CRYPTO_AEAD + select CRYPTO_AUTHENC + select CRYPTO_SHA1 + select CRYPTO_MD5 + select CRYPTO_SHA256 + select CRYPTO_SHA512 + select CRYPTO_HMAC + select CRYPTO_AES + select CRYPTO_CBC + select CRYPTO_ECB + select CRYPTO_CTR + select CRYPTO_XTS + help + Say 'Y' to enable a driver for the Arm TrustZone CryptoCell + family of processors. Currently only the CryptoCell 712 REE + is supported. + Choose this if you wish to use hardware acceleration of + cryptographic operations on the system REE. + If unsure say Y. + endif # CRYPTO_HW diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile index 2513d13..ee5ec5c9 100644 --- a/drivers/crypto/Makefile +++ b/drivers/crypto/Makefile @@ -6,6 +6,7 @@ obj-$(CONFIG_CRYPTO_DEV_ATMEL_ECC) += atmel-ecc.o obj-$(CONFIG_CRYPTO_DEV_BFIN_CRC) += bfin_crc.o obj-$(CONFIG_CRYPTO_DEV_CAVIUM_ZIP) += cavium/ obj-$(CONFIG_CRYPTO_DEV_CCP) += ccp/ +obj-$(CONFIG_CRYPTO_DEV_CCREE) += ccree/ obj-$(CONFIG_CRYPTO_DEV_CHELSIO) += chelsio/ obj-$(CONFIG_CRYPTO_DEV_CPT) += cavium/cpt/ obj-$(CONFIG_CRYPTO_DEV_NITROX) += cavium/nitrox/ diff --git a/drivers/crypto/ccree/Makefile b/drivers/crypto/ccree/Makefile new file mode 100644 index 000..6b204ab --- /dev/null +++ b/drivers/crypto/ccree/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-$(CONFIG_CRYPTO_DEV_CCREE) := ccree.o +ccree-y := cc_driver.o cc_buffer_mgr.o cc_request_mgr.o cc_ivgen.o cc_sram_mgr.o +ccree-$(CONFIG_DEBUG_FS) += cc_debugfs.o +ccree-$(CONFIG_PM) += cc_pm.o diff --git a/drivers/crypto/ccree/cc_buffer_mgr.c b/drivers/crypto/ccree/cc_buffer_mgr.c new file mode 100644 index 000..4c67579 --- /dev/null +++ b/drivers/crypto/ccree/cc_buffer_mgr.c @@ -0,0
[PATCH 6/7] crypto: ccree: add FIPS support
Add FIPS mode support to CryptoCell driver
Signed-off-by: Gilad Ben-Yossef
---
drivers/crypto/ccree/Makefile| 1 +
drivers/crypto/ccree/cc_driver.c | 29 +-
drivers/crypto/ccree/cc_driver.h | 1 +
drivers/crypto/ccree/cc_fips.c | 112 +++
drivers/crypto/ccree/cc_fips.h | 37 +
5 files changed, 178 insertions(+), 2 deletions(-)
create mode 100644 drivers/crypto/ccree/cc_fips.c
create mode 100644 drivers/crypto/ccree/cc_fips.h
diff --git a/drivers/crypto/ccree/Makefile b/drivers/crypto/ccree/Makefile
index 7cb3082..bdc2797 100644
--- a/drivers/crypto/ccree/Makefile
+++ b/drivers/crypto/ccree/Makefile
@@ -2,5 +2,6 @@
obj-$(CONFIG_CRYPTO_DEV_CCREE) := ccree.o
ccree-y := cc_driver.o cc_buffer_mgr.o cc_request_mgr.o cc_cipher.o cc_hash.o
cc_aead.o cc_ivgen.o cc_sram_mgr.o
+ccree-$(CONFIG_CRYPTO_FIPS) += cc_fips.o
ccree-$(CONFIG_DEBUG_FS) += cc_debugfs.o
ccree-$(CONFIG_PM) += cc_pm.o
diff --git a/drivers/crypto/ccree/cc_driver.c b/drivers/crypto/ccree/cc_driver.c
index 31140e3..b71dc70 100644
--- a/drivers/crypto/ccree/cc_driver.c
+++ b/drivers/crypto/ccree/cc_driver.c
@@ -25,6 +25,7 @@
#include "cc_ivgen.h"
#include "cc_sram_mgr.h"
#include "cc_pm.h"
+#include "cc_fips.h"
bool cc_dump_desc;
module_param_named(dump_desc, cc_dump_desc, bool, 0600);
@@ -78,7 +79,17 @@ static irqreturn_t cc_isr(int irq, void *dev_id)
irr &= ~CC_COMP_IRQ_MASK;
complete_request(drvdata);
}
-
+#ifdef CONFIG_CRYPTO_FIPS
+ /* TEE FIPS interrupt */
+ if (irr & CC_GPR0_IRQ_MASK) {
+ /* Mask interrupt - will be unmasked in Deferred service
+* handler
+*/
+ cc_iowrite(drvdata, CC_REG(HOST_IMR), imr | CC_GPR0_IRQ_MASK);
+ irr &= ~CC_GPR0_IRQ_MASK;
+ fips_handler(drvdata);
+ }
+#endif
/* AXI error interrupt */
if (irr & CC_AXI_ERR_IRQ_MASK) {
u32 axi_err;
@@ -244,10 +255,15 @@ static int init_cc_resources(struct platform_device
*plat_dev)
goto post_regs_err;
}
+ rc = cc_fips_init(new_drvdata);
+ if (rc) {
+ dev_err(dev, "CC_FIPS_INIT failed 0x%x\n", rc);
+ goto post_debugfs_err;
+ }
rc = cc_sram_mgr_init(new_drvdata);
if (rc) {
dev_err(dev, "cc_sram_mgr_init failed\n");
- goto post_debugfs_err;
+ goto post_fips_init_err;
}
new_drvdata->mlli_sram_addr =
@@ -302,6 +318,12 @@ static int init_cc_resources(struct platform_device
*plat_dev)
goto post_hash_err;
}
+ /* If we got here and FIPS mode is enabled
+* it means all FIPS test passed, so let TEE
+* know we're good.
+*/
+ cc_set_ree_fips_status(new_drvdata, true);
+
return 0;
post_hash_err:
@@ -318,6 +340,8 @@ static int init_cc_resources(struct platform_device
*plat_dev)
cc_req_mgr_fini(new_drvdata);
post_sram_mgr_err:
cc_sram_mgr_fini(new_drvdata);
+post_fips_init_err:
+ cc_fips_fini(new_drvdata);
post_debugfs_err:
cc_debugfs_fini(new_drvdata);
post_regs_err:
@@ -346,6 +370,7 @@ static void cleanup_cc_resources(struct platform_device
*plat_dev)
cc_buffer_mgr_fini(drvdata);
cc_req_mgr_fini(drvdata);
cc_sram_mgr_fini(drvdata);
+ cc_fips_fini(drvdata);
cc_debugfs_fini(drvdata);
fini_cc_regs(drvdata);
cc_clk_off(drvdata);
diff --git a/drivers/crypto/ccree/cc_driver.h b/drivers/crypto/ccree/cc_driver.h
index ab9a66f..12699f1 100644
--- a/drivers/crypto/ccree/cc_driver.h
+++ b/drivers/crypto/ccree/cc_driver.h
@@ -115,6 +115,7 @@ struct cc_drvdata {
void *aead_handle;
void *blkcipher_handle;
void *request_mgr_handle;
+ void *fips_handle;
void *ivgen_handle;
void *sram_mgr_handle;
void *debugfs;
diff --git a/drivers/crypto/ccree/cc_fips.c b/drivers/crypto/ccree/cc_fips.c
new file mode 100644
index 000..b25c34e
--- /dev/null
+++ b/drivers/crypto/ccree/cc_fips.c
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright (C) 2012-2018 ARM Limited or its affiliates. */
+
+#include
+#include
+
+#include "cc_driver.h"
+#include "cc_fips.h"
+
+static void fips_dsr(unsigned long devarg);
+
+struct cc_fips_handle {
+ struct tasklet_struct tasklet;
+};
+
+/* The function called once at driver entry point to check
+ * whether TEE FIPS error occurred.
+ */
+static bool cc_get_tee_fips_status(struct cc_drvdata *drvdata)
+{
+ u32 reg;
+
+ reg = cc_ioread(drvdata, CC_REG(GPR_HOST));
+ return (reg == (CC_FIPS_SYNC_TEE_STATUS | CC_FIPS_SYNC_MODULE_OK));
+}
+
+/*
+ * This function should push the FIPS REE library status towards the TEE
library
+ * by writing the error state to HOST_GPR0 register.
+ */
+void cc_set_ree_fips_status(struct cc_drvdata *drvdat
[PATCH 5/7] crypto: ccree: add AEAD support
Add CryptoCell AEAD support
Signed-off-by: Gilad Ben-Yossef
---
drivers/crypto/ccree/Makefile|2 +-
drivers/crypto/ccree/cc_aead.c | 2702 ++
drivers/crypto/ccree/cc_aead.h | 109 ++
drivers/crypto/ccree/cc_buffer_mgr.c | 882 +++
drivers/crypto/ccree/cc_buffer_mgr.h |4 +
drivers/crypto/ccree/cc_driver.c | 10 +
drivers/crypto/ccree/cc_driver.h |4 +
7 files changed, 3712 insertions(+), 1 deletion(-)
create mode 100644 drivers/crypto/ccree/cc_aead.c
create mode 100644 drivers/crypto/ccree/cc_aead.h
diff --git a/drivers/crypto/ccree/Makefile b/drivers/crypto/ccree/Makefile
index 1109480..7cb3082 100644
--- a/drivers/crypto/ccree/Makefile
+++ b/drivers/crypto/ccree/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_CRYPTO_DEV_CCREE) := ccree.o
-ccree-y := cc_driver.o cc_buffer_mgr.o cc_request_mgr.o cc_cipher.o cc_hash.o
cc_ivgen.o cc_sram_mgr.o
+ccree-y := cc_driver.o cc_buffer_mgr.o cc_request_mgr.o cc_cipher.o cc_hash.o
cc_aead.o cc_ivgen.o cc_sram_mgr.o
ccree-$(CONFIG_DEBUG_FS) += cc_debugfs.o
ccree-$(CONFIG_PM) += cc_pm.o
diff --git a/drivers/crypto/ccree/cc_aead.c b/drivers/crypto/ccree/cc_aead.c
new file mode 100644
index 000..265adff
--- /dev/null
+++ b/drivers/crypto/ccree/cc_aead.c
@@ -0,0 +1,2702 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright (C) 2012-2018 ARM Limited or its affiliates. */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include "cc_driver.h"
+#include "cc_buffer_mgr.h"
+#include "cc_aead.h"
+#include "cc_request_mgr.h"
+#include "cc_hash.h"
+#include "cc_sram_mgr.h"
+
+#define template_aead template_u.aead
+
+#define MAX_AEAD_SETKEY_SEQ 12
+#define MAX_AEAD_PROCESS_SEQ 23
+
+#define MAX_HMAC_DIGEST_SIZE (SHA256_DIGEST_SIZE)
+#define MAX_HMAC_BLOCK_SIZE (SHA256_BLOCK_SIZE)
+
+#define AES_CCM_RFC4309_NONCE_SIZE 3
+#define MAX_NONCE_SIZE CTR_RFC3686_NONCE_SIZE
+
+/* Value of each ICV_CMP byte (of 8) in case of success */
+#define ICV_VERIF_OK 0x01
+
+struct cc_aead_handle {
+ cc_sram_addr_t sram_workspace_addr;
+ struct list_head aead_list;
+};
+
+struct cc_hmac_s {
+ u8 *padded_authkey;
+ u8 *ipad_opad; /* IPAD, OPAD*/
+ dma_addr_t padded_authkey_dma_addr;
+ dma_addr_t ipad_opad_dma_addr;
+};
+
+struct cc_xcbc_s {
+ u8 *xcbc_keys; /* K1,K2,K3 */
+ dma_addr_t xcbc_keys_dma_addr;
+};
+
+struct cc_aead_ctx {
+ struct cc_drvdata *drvdata;
+ u8 ctr_nonce[MAX_NONCE_SIZE]; /* used for ctr3686 iv and aes ccm */
+ u8 *enckey;
+ dma_addr_t enckey_dma_addr;
+ union {
+ struct cc_hmac_s hmac;
+ struct cc_xcbc_s xcbc;
+ } auth_state;
+ unsigned int enc_keylen;
+ unsigned int auth_keylen;
+ unsigned int authsize; /* Actual (reduced?) size of the MAC/ICv */
+ enum drv_cipher_mode cipher_mode;
+ enum cc_flow_mode flow_mode;
+ enum drv_hash_mode auth_mode;
+};
+
+static inline bool valid_assoclen(struct aead_request *req)
+{
+ return ((req->assoclen == 16) || (req->assoclen == 20));
+}
+
+static void cc_aead_exit(struct crypto_aead *tfm)
+{
+ struct cc_aead_ctx *ctx = crypto_aead_ctx(tfm);
+ struct device *dev = drvdata_to_dev(ctx->drvdata);
+
+ dev_dbg(dev, "Clearing context @%p for %s\n", crypto_aead_ctx(tfm),
+ crypto_tfm_alg_name(&tfm->base));
+
+ /* Unmap enckey buffer */
+ if (ctx->enckey) {
+ dma_free_coherent(dev, AES_MAX_KEY_SIZE, ctx->enckey,
+ ctx->enckey_dma_addr);
+ dev_dbg(dev, "Freed enckey DMA buffer enckey_dma_addr=%pad\n",
+ &ctx->enckey_dma_addr);
+ ctx->enckey_dma_addr = 0;
+ ctx->enckey = NULL;
+ }
+
+ if (ctx->auth_mode == DRV_HASH_XCBC_MAC) { /* XCBC authetication */
+ struct cc_xcbc_s *xcbc = &ctx->auth_state.xcbc;
+
+ if (xcbc->xcbc_keys) {
+ dma_free_coherent(dev, CC_AES_128_BIT_KEY_SIZE * 3,
+ xcbc->xcbc_keys,
+ xcbc->xcbc_keys_dma_addr);
+ }
+ dev_dbg(dev, "Freed xcbc_keys DMA buffer
xcbc_keys_dma_addr=%pad\n",
+ &xcbc->xcbc_keys_dma_addr);
+ xcbc->xcbc_keys_dma_addr = 0;
+ xcbc->xcbc_keys = NULL;
+ } else if (ctx->auth_mode != DRV_HASH_NULL) { /* HMAC auth. */
+ struct cc_hmac_s *hmac = &ctx->auth_state.hmac;
+
+ if (hmac->ipad_opad) {
+ dma_free_coherent(dev, 2 * MAX_HMAC_DIGEST_SIZE,
+ hmac->ipad_opad,
+ hmac->ipad_opad_dma_addr);
+ dev_dbg(dev, "Freed ipad_opad DMA buffer
ipad_opad_dma_addr=%pad\n",
+
[PATCH 4/7] crypto: ccree: add ahash support
Add CryptoCell async. hash and HMAC support.
Signed-off-by: Gilad Ben-Yossef
---
drivers/crypto/ccree/Makefile|2 +-
drivers/crypto/ccree/cc_buffer_mgr.c | 257
drivers/crypto/ccree/cc_driver.c | 13 +
drivers/crypto/ccree/cc_driver.h |1 +
drivers/crypto/ccree/cc_hash.c | 2297 ++
drivers/crypto/ccree/cc_hash.h | 114 ++
drivers/crypto/ccree/cc_pm.c |4 +
7 files changed, 2687 insertions(+), 1 deletion(-)
create mode 100644 drivers/crypto/ccree/cc_hash.c
create mode 100644 drivers/crypto/ccree/cc_hash.h
diff --git a/drivers/crypto/ccree/Makefile b/drivers/crypto/ccree/Makefile
index a7fecad..1109480 100644
--- a/drivers/crypto/ccree/Makefile
+++ b/drivers/crypto/ccree/Makefile
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_CRYPTO_DEV_CCREE) := ccree.o
-ccree-y := cc_driver.o cc_buffer_mgr.o cc_request_mgr.o cc_cipher.o cc_ivgen.o
cc_sram_mgr.o
+ccree-y := cc_driver.o cc_buffer_mgr.o cc_request_mgr.o cc_cipher.o cc_hash.o
cc_ivgen.o cc_sram_mgr.o
ccree-$(CONFIG_DEBUG_FS) += cc_debugfs.o
ccree-$(CONFIG_PM) += cc_pm.o
diff --git a/drivers/crypto/ccree/cc_buffer_mgr.c
b/drivers/crypto/ccree/cc_buffer_mgr.c
index 510993e..1ff379b 100644
--- a/drivers/crypto/ccree/cc_buffer_mgr.c
+++ b/drivers/crypto/ccree/cc_buffer_mgr.c
@@ -9,6 +9,7 @@
#include "cc_buffer_mgr.h"
#include "cc_lli_defs.h"
#include "cc_cipher.h"
+#include "cc_hash.h"
enum dma_buffer_type {
DMA_NULL_TYPE = -1,
@@ -348,6 +349,30 @@ static int cc_map_sg(struct device *dev, struct
scatterlist *sg,
return 0;
}
+static int cc_set_hash_buf(struct device *dev, struct ahash_req_ctx *areq_ctx,
+ u8 *curr_buff, u32 curr_buff_cnt,
+ struct buffer_array *sg_data)
+{
+ dev_dbg(dev, " handle curr buff %x set to DLLI\n", curr_buff_cnt);
+ /* create sg for the current buffer */
+ sg_init_one(areq_ctx->buff_sg, curr_buff, curr_buff_cnt);
+ if (dma_map_sg(dev, areq_ctx->buff_sg, 1, DMA_TO_DEVICE) != 1) {
+ dev_err(dev, "dma_map_sg() src buffer failed\n");
+ return -ENOMEM;
+ }
+ dev_dbg(dev, "Mapped curr_buff: dma_address=%pad page=%p addr=%pK
offset=%u length=%u\n",
+ &sg_dma_address(areq_ctx->buff_sg), sg_page(areq_ctx->buff_sg),
+ sg_virt(areq_ctx->buff_sg), areq_ctx->buff_sg->offset,
+ areq_ctx->buff_sg->length);
+ areq_ctx->data_dma_buf_type = CC_DMA_BUF_DLLI;
+ areq_ctx->curr_sg = areq_ctx->buff_sg;
+ areq_ctx->in_nents = 0;
+ /* prepare for case of MLLI */
+ cc_add_sg_entry(dev, sg_data, 1, areq_ctx->buff_sg, curr_buff_cnt, 0,
+ false, NULL);
+ return 0;
+}
+
void cc_unmap_blkcipher_request(struct device *dev, void *ctx,
unsigned int ivsize, struct scatterlist *src,
struct scatterlist *dst)
@@ -472,6 +497,238 @@ int cc_map_blkcipher_request(struct cc_drvdata *drvdata,
void *ctx,
return rc;
}
+int cc_map_hash_request_final(struct cc_drvdata *drvdata, void *ctx,
+ struct scatterlist *src, unsigned int nbytes,
+ bool do_update, gfp_t flags)
+{
+ struct ahash_req_ctx *areq_ctx = (struct ahash_req_ctx *)ctx;
+ struct device *dev = drvdata_to_dev(drvdata);
+ u8 *curr_buff = cc_hash_buf(areq_ctx);
+ u32 *curr_buff_cnt = cc_hash_buf_cnt(areq_ctx);
+ struct mlli_params *mlli_params = &areq_ctx->mlli_params;
+ struct buffer_array sg_data;
+ struct buff_mgr_handle *buff_mgr = drvdata->buff_mgr_handle;
+ u32 dummy = 0;
+ u32 mapped_nents = 0;
+
+ dev_dbg(dev, "final params : curr_buff=%pK curr_buff_cnt=0x%X nbytes =
0x%X src=%pK curr_index=%u\n",
+ curr_buff, *curr_buff_cnt, nbytes, src, areq_ctx->buff_index);
+ /* Init the type of the dma buffer */
+ areq_ctx->data_dma_buf_type = CC_DMA_BUF_NULL;
+ mlli_params->curr_pool = NULL;
+ sg_data.num_of_buffers = 0;
+ areq_ctx->in_nents = 0;
+
+ if (nbytes == 0 && *curr_buff_cnt == 0) {
+ /* nothing to do */
+ return 0;
+ }
+
+ /*TODO: copy data in case that buffer is enough for operation */
+ /* map the previous buffer */
+ if (*curr_buff_cnt) {
+ if (cc_set_hash_buf(dev, areq_ctx, curr_buff, *curr_buff_cnt,
+ &sg_data)) {
+ return -ENOMEM;
+ }
+ }
+
+ if (src && nbytes > 0 && do_update) {
+ if (cc_map_sg(dev, src, nbytes, DMA_TO_DEVICE,
+ &areq_ctx->in_nents, LLI_MAX_NUM_OF_DATA_ENTRIES,
+ &dummy, &mapped_nents)) {
+ goto unmap_curr_buff;
+ }
+ if (src && mapped_ne
[PATCH 7/7] MAINTAINERS: update ccree entry
Update Arm TrustZone CryptoCell driver entry move into drivers/crypto/ Signed-off-by: Gilad Ben-Yossef --- MAINTAINERS | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 1082846..560e068 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3273,12 +3273,11 @@ F: drivers/net/ieee802154/cc2520.c F: include/linux/spi/cc2520.h F: Documentation/devicetree/bindings/net/ieee802154/cc2520.txt -CCREE ARM TRUSTZONE CRYPTOCELL 700 REE DRIVER +CCREE ARM TRUSTZONE CRYPTOCELL REE DRIVER M: Gilad Ben-Yossef L: linux-crypto@vger.kernel.org -L: driverdev-de...@linuxdriverproject.org S: Supported -F: drivers/staging/ccree/ +F: drivers/crypto/ccree/ W: https://developer.arm.com/products/system-ip/trustzone-cryptocell/cryptocell-700-family CEC FRAMEWORK -- 2.7.4
[PATCH 0/7] Introduce Arm TrustZone CryptoCell
Arm TrustZone CryptoCell is a security hardware IP that
includes support for hardware based hash, digest, cipher
and AEAD operations. This driver provides support for
these as part of the Linux Crypto sub-system.
The driver spent some time now in the staging tree being
cleaned up and is now submitted for review for the
purpose of moving into the crypto tree. The first patch
therefore delete it's copy in the staging directory
otherwise there is a build failure due to collisions
with it's other copy there.
Please note that the driver include some stubs for yet
unexposed functionality (ivgen and secure HW keys).
Signed-off-by: Gilad Ben-Yossef
Gilad Ben-Yossef (7):
staging: ccree: remove ccree from staging tree
crypto: ccree: introduce CryptoCell driver
crypto: ccree: add ablkcipher support
crypto: ccree: add ahash support
crypto: ccree: add AEAD support
crypto: ccree: add FIPS support
MAINTAINERS: update ccree entry
MAINTAINERS|5 +-
drivers/crypto/Kconfig | 27 +
drivers/crypto/Makefile|1 +
drivers/crypto/ccree/Makefile |7 +
.../ccree/ssi_aead.c => crypto/ccree/cc_aead.c}| 1120 ++--
.../ccree/ssi_aead.h => crypto/ccree/cc_aead.h}| 56 +-
.../ccree/cc_buffer_mgr.c} | 1085 ++--
drivers/crypto/ccree/cc_buffer_mgr.h | 74 +
.../ssi_cipher.c => crypto/ccree/cc_cipher.c} | 716 +++-
drivers/crypto/ccree/cc_cipher.h | 74 +
drivers/{staging => crypto}/ccree/cc_crypto_ctx.h | 38 +-
drivers/crypto/ccree/cc_debugfs.c | 101 ++
drivers/crypto/ccree/cc_debugfs.h | 32 +
drivers/crypto/ccree/cc_driver.c | 477 +
drivers/crypto/ccree/cc_driver.h | 194 +++
.../ccree/ssi_fips.c => crypto/ccree/cc_fips.c}| 44 +-
drivers/crypto/ccree/cc_fips.h | 37 +
.../ccree/ssi_hash.c => crypto/ccree/cc_hash.c}| 1818 +---
drivers/crypto/ccree/cc_hash.h | 114 ++
drivers/crypto/ccree/cc_host_regs.h| 142 ++
.../{staging => crypto}/ccree/cc_hw_queue_defs.h | 40 +-
.../ccree/ssi_ivgen.c => crypto/ccree/cc_ivgen.c} | 141 +-
drivers/crypto/ccree/cc_ivgen.h| 55 +
drivers/crypto/ccree/cc_kernel_regs.h | 167 ++
drivers/{staging => crypto}/ccree/cc_lli_defs.h| 19 +-
drivers/crypto/ccree/cc_pm.c | 123 ++
drivers/crypto/ccree/cc_pm.h | 57 +
drivers/crypto/ccree/cc_request_mgr.c | 714
drivers/crypto/ccree/cc_request_mgr.h | 51 +
.../ssi_sram_mgr.c => crypto/ccree/cc_sram_mgr.c} | 70 +-
drivers/crypto/ccree/cc_sram_mgr.h | 65 +
drivers/staging/Kconfig|2 -
drivers/staging/Makefile |1 -
.../devicetree/bindings/crypto/arm-cryptocell.txt | 27 -
drivers/staging/ccree/Kconfig | 25 -
drivers/staging/ccree/Makefile |3 -
drivers/staging/ccree/TODO | 30 -
drivers/staging/ccree/dx_crys_kernel.h | 180 --
drivers/staging/ccree/dx_host.h| 155 --
drivers/staging/ccree/dx_reg_common.h | 26 -
drivers/staging/ccree/hash_defs.h | 36 -
drivers/staging/ccree/ssi_buffer_mgr.h | 91 -
drivers/staging/ccree/ssi_cipher.h | 84 -
drivers/staging/ccree/ssi_config.h | 36 -
drivers/staging/ccree/ssi_driver.c | 538 --
drivers/staging/ccree/ssi_driver.h | 206 ---
drivers/staging/ccree/ssi_fips.h | 49 -
drivers/staging/ccree/ssi_hash.h | 103 --
drivers/staging/ccree/ssi_ivgen.h | 71 -
drivers/staging/ccree/ssi_pm.c | 145 --
drivers/staging/ccree/ssi_pm.h | 43 -
drivers/staging/ccree/ssi_request_mgr.c| 610 ---
drivers/staging/ccree/ssi_request_mgr.h| 60 -
drivers/staging/ccree/ssi_sram_mgr.h | 79 -
drivers/staging/ccree/ssi_sysfs.c | 172 --
drivers/staging/ccree/ssi_sysfs.h | 55 -
56 files changed, 4706 insertions(+), 5785 deletions(-)
create mode 100644 drivers/crypto/ccree/Makefile
rename drivers/{staging/ccree/ssi_aead.c => crypto/ccree/cc_aead.c} (70%)
rename drivers/{staging/ccree/ssi_aead.h => crypto/ccree/cc_aead.h} (64%)
rename drivers/{staging/ccree/ssi_buffer_mgr.c =>
crypto/ccree/cc_buffer_mgr.c} (56%)
create mode 100644 drivers/crypto/ccree/cc_buffer_mgr.h
rename drivers/{staging/ccree/ssi_cipher.c => crypto/ccree/cc_cipher.c} (58%)
create mode 100644 drivers/crypto/ccree/cc_cipher.h
rename d
Re: Getting the ccree driver out of staging
Here are my remaining Smatch warnings:
drivers/staging/ccree/cc_driver.c:219 init_cc_resources()
error: '%pa' can only be followed by one of [dp]
drivers/staging/ccree/cc_driver.c
217
218 if (rc) {
219 dev_err(dev, "Failed in dma_set_mask, mask=%par\n",
^
This 'r' is is treated as a 'p'. Not sure what was intended.
220 &dma_mask);
221 return rc;
222 }
223
drivers/staging/ccree/cc_buffer_mgr.c:1067 cc_aead_chain_data()
warn: inconsistent indenting
drivers/staging/ccree/cc_buffer_mgr.c
1064 if (src_mapped_nents > LLI_MAX_NUM_OF_DATA_ENTRIES) {
1065 dev_err(dev, "Too many fragments. current %d max %d\n",
1066 src_mapped_nents, LLI_MAX_NUM_OF_DATA_ENTRIES);
1067 return -ENOMEM;
^^
1068 }
drivers/staging/ccree/cc_cipher.c:373 cc_cipher_setkey()
warn: inconsistent indenting
drivers/staging/ccree/cc_cipher.c
369 dma_sync_single_for_device(dev, ctx_p->user.key_dma_addr,
370 max_key_buf_size, DMA_TO_DEVICE);
371 ctx_p->keylen = keylen;
372
373 dev_dbg(dev, "return safely");
^
One extra space.
374 return 0;
375 }
regards,
dan carpenter
