[PATCH v2] hw_random: omap3-rom-rng: convert timer to delayed work
We cannot put the HW RNG to idle using a timer because we cannot disable
clocks from atomic context. Use a delayed work instead.
Fixes a warning with CONFIG_DEBUG_MUTEXES on Nokia N900 during boot.
Reported-by: Sebastian Reichel <s...@kernel.org>
Signed-off-by: Aaro Koskinen <aaro.koski...@iki.fi>
---
v2: Include workqueue.h instead of timer.h.
drivers/char/hw_random/omap3-rom-rng.c | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/char/hw_random/omap3-rom-rng.c
b/drivers/char/hw_random/omap3-rom-rng.c
index a405cdc..8da14f1 100644
--- a/drivers/char/hw_random/omap3-rom-rng.c
+++ b/drivers/char/hw_random/omap3-rom-rng.c
@@ -17,7 +17,7 @@
#include
#include
#include
-#include
+#include
#include
#include
#include
@@ -29,11 +29,11 @@
/* param1: ptr, param2: count, param3: flag */
static u32 (*omap3_rom_rng_call)(u32, u32, u32);
-static struct timer_list idle_timer;
+static struct delayed_work idle_work;
static int rng_idle;
static struct clk *rng_clk;
-static void omap3_rom_rng_idle(unsigned long data)
+static void omap3_rom_rng_idle(struct work_struct *work)
{
int r;
@@ -51,7 +51,7 @@ static int omap3_rom_rng_get_random(void *buf, unsigned int
count)
u32 r;
u32 ptr;
- del_timer_sync(_timer);
+ cancel_delayed_work_sync(_work);
if (rng_idle) {
clk_prepare_enable(rng_clk);
r = omap3_rom_rng_call(0, 0, RNG_GEN_PRNG_HW_INIT);
@@ -65,7 +65,7 @@ static int omap3_rom_rng_get_random(void *buf, unsigned int
count)
ptr = virt_to_phys(buf);
r = omap3_rom_rng_call(ptr, count, RNG_GEN_HW);
- mod_timer(_timer, jiffies + msecs_to_jiffies(500));
+ schedule_delayed_work(_work, msecs_to_jiffies(500));
if (r != 0)
return -EINVAL;
return 0;
@@ -102,7 +102,7 @@ static int omap3_rom_rng_probe(struct platform_device *pdev)
return -EINVAL;
}
- setup_timer(_timer, omap3_rom_rng_idle, 0);
+ INIT_DELAYED_WORK(_work, omap3_rom_rng_idle);
rng_clk = devm_clk_get(>dev, "ick");
if (IS_ERR(rng_clk)) {
pr_err("unable to get RNG clock\n");
@@ -118,6 +118,7 @@ static int omap3_rom_rng_probe(struct platform_device *pdev)
static int omap3_rom_rng_remove(struct platform_device *pdev)
{
+ cancel_delayed_work_sync(_work);
hwrng_unregister(_rom_rng_ops);
clk_disable_unprepare(rng_clk);
return 0;
--
2.4.0
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[PATCH] hw_random: omap3-rom-rng: convert timer to delayed work
We cannot put the HW RNG to idle using a timer because we cannot disable
clocks from atomic context. Use a delayed work instead.
Fixes a warning with CONFIG_DEBUG_MUTEXES on Nokia N900 during boot.
Reported-by: Sebastian Reichel <s...@kernel.org>
Signed-off-by: Aaro Koskinen <aaro.koski...@iki.fi>
---
drivers/char/hw_random/omap3-rom-rng.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/char/hw_random/omap3-rom-rng.c
b/drivers/char/hw_random/omap3-rom-rng.c
index a405cdc..58191c6 100644
--- a/drivers/char/hw_random/omap3-rom-rng.c
+++ b/drivers/char/hw_random/omap3-rom-rng.c
@@ -29,11 +29,11 @@
/* param1: ptr, param2: count, param3: flag */
static u32 (*omap3_rom_rng_call)(u32, u32, u32);
-static struct timer_list idle_timer;
+static struct delayed_work idle_work;
static int rng_idle;
static struct clk *rng_clk;
-static void omap3_rom_rng_idle(unsigned long data)
+static void omap3_rom_rng_idle(struct work_struct *work)
{
int r;
@@ -51,7 +51,7 @@ static int omap3_rom_rng_get_random(void *buf, unsigned int
count)
u32 r;
u32 ptr;
- del_timer_sync(_timer);
+ cancel_delayed_work_sync(_work);
if (rng_idle) {
clk_prepare_enable(rng_clk);
r = omap3_rom_rng_call(0, 0, RNG_GEN_PRNG_HW_INIT);
@@ -65,7 +65,7 @@ static int omap3_rom_rng_get_random(void *buf, unsigned int
count)
ptr = virt_to_phys(buf);
r = omap3_rom_rng_call(ptr, count, RNG_GEN_HW);
- mod_timer(_timer, jiffies + msecs_to_jiffies(500));
+ schedule_delayed_work(_work, msecs_to_jiffies(500));
if (r != 0)
return -EINVAL;
return 0;
@@ -102,7 +102,7 @@ static int omap3_rom_rng_probe(struct platform_device *pdev)
return -EINVAL;
}
- setup_timer(_timer, omap3_rom_rng_idle, 0);
+ INIT_DELAYED_WORK(_work, omap3_rom_rng_idle);
rng_clk = devm_clk_get(>dev, "ick");
if (IS_ERR(rng_clk)) {
pr_err("unable to get RNG clock\n");
@@ -118,6 +118,7 @@ static int omap3_rom_rng_probe(struct platform_device *pdev)
static int omap3_rom_rng_remove(struct platform_device *pdev)
{
+ cancel_delayed_work_sync(_work);
hwrng_unregister(_rom_rng_ops);
clk_disable_unprepare(rng_clk);
return 0;
--
2.4.0
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[PATCH 1/7] crypto: octeon - don't disable bottom half in octeon-md5
Don't disable bottom half while the crypto engine is in use, as it should be unnecessary: All kernel crypto engine usage is wrapped with crypto engine state save/restore, so if we get interrupted by softirq that uses crypto they should save and restore our context. This actually fixes an issue when running OCTEON MD5 with interrupts disabled (tcrypt mode=302). There's a WARNING because the module is trying to enable the bottom half with irqs disabled: [ 52.656610] [ cut here ] [ 52.661439] WARNING: CPU: 1 PID: 428 at /home/aaro/git/linux/kernel/softirq.c:150 __local_bh_enable_ip+0x9c/0xd8() [ 52.671780] Modules linked in: tcrypt(+) [...] [ 52.763539] [8114082c] warn_slowpath_common+0x94/0xd8 [ 52.769465] [81144614] __local_bh_enable_ip+0x9c/0xd8 [ 52.775390] [81119574] octeon_md5_final+0x12c/0x1e8 [ 52.781144] [81337050] shash_compat_digest+0xd0/0x1b0 Signed-off-by: Aaro Koskinen aaro.koski...@iki.fi --- arch/mips/cavium-octeon/crypto/octeon-md5.c | 4 1 file changed, 4 deletions(-) diff --git a/arch/mips/cavium-octeon/crypto/octeon-md5.c b/arch/mips/cavium-octeon/crypto/octeon-md5.c index b909881..3dd8845 100644 --- a/arch/mips/cavium-octeon/crypto/octeon-md5.c +++ b/arch/mips/cavium-octeon/crypto/octeon-md5.c @@ -97,7 +97,6 @@ static int octeon_md5_update(struct shash_desc *desc, const u8 *data, memcpy((char *)mctx-block + (sizeof(mctx-block) - avail), data, avail); - local_bh_disable(); preempt_disable(); flags = octeon_crypto_enable(state); octeon_md5_store_hash(mctx); @@ -115,7 +114,6 @@ static int octeon_md5_update(struct shash_desc *desc, const u8 *data, octeon_md5_read_hash(mctx); octeon_crypto_disable(state, flags); preempt_enable(); - local_bh_enable(); memcpy(mctx-block, data, len); @@ -133,7 +131,6 @@ static int octeon_md5_final(struct shash_desc *desc, u8 *out) *p++ = 0x80; - local_bh_disable(); preempt_disable(); flags = octeon_crypto_enable(state); octeon_md5_store_hash(mctx); @@ -153,7 +150,6 @@ static int octeon_md5_final(struct shash_desc *desc, u8 *out) octeon_md5_read_hash(mctx); octeon_crypto_disable(state, flags); preempt_enable(); - local_bh_enable(); memcpy(out, mctx-hash, sizeof(mctx-hash)); memset(mctx, 0, sizeof(*mctx)); -- 2.2.0 -- To unsubscribe from this list: send the line unsubscribe linux-crypto in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/7] crypto: OCTEON MD5 bugfix + SHA modules
bytes per update, 256 updates): 1.86x faster test 14 ( 4096 byte blocks, 256 bytes per update, 16 updates): 6.12x faster test 15 ( 4096 byte blocks, 1024 bytes per update, 4 updates): 9.03x faster test 16 ( 4096 byte blocks, 4096 bytes per update, 1 updates): 10.31x faster test 17 ( 8192 byte blocks, 16 bytes per update, 512 updates): 1.85x faster test 18 ( 8192 byte blocks, 256 bytes per update, 32 updates): 6.18x faster test 19 ( 8192 byte blocks, 1024 bytes per update, 8 updates): 9.26x faster test 20 ( 8192 byte blocks, 4096 bytes per update, 2 updates): 10.64x faster test 21 ( 8192 byte blocks, 8192 bytes per update, 1 updates): 10.65x faster A. Aaro Koskinen (7): crypto: octeon - don't disable bottom half in octeon-md5 crypto: octeon - always disable preemption when using crypto engine crypto: octeon - add instruction definitions for SHA1/256/512 crypto: octeon - add SHA1 module crypto: octeon - add SHA256 module crypto: octeon - add SHA512 module crypto: octeon - enable OCTEON SHA1/256/512 module selection arch/mips/cavium-octeon/crypto/Makefile| 5 +- arch/mips/cavium-octeon/crypto/octeon-crypto.c | 4 +- arch/mips/cavium-octeon/crypto/octeon-crypto.h | 83 +++- arch/mips/cavium-octeon/crypto/octeon-md5.c| 8 - arch/mips/cavium-octeon/crypto/octeon-sha1.c | 241 + arch/mips/cavium-octeon/crypto/octeon-sha256.c | 280 + arch/mips/cavium-octeon/crypto/octeon-sha512.c | 277 crypto/Kconfig | 27 +++ 8 files changed, 911 insertions(+), 14 deletions(-) create mode 100644 arch/mips/cavium-octeon/crypto/octeon-sha1.c create mode 100644 arch/mips/cavium-octeon/crypto/octeon-sha256.c create mode 100644 arch/mips/cavium-octeon/crypto/octeon-sha512.c -- 2.2.0 -- To unsubscribe from this list: send the line unsubscribe linux-crypto in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/7] crypto: octeon - add instruction definitions for SHA1/256/512
Add instruction definitions for SHA1/256/512.
Signed-off-by: Aaro Koskinen aaro.koski...@iki.fi
---
arch/mips/cavium-octeon/crypto/octeon-crypto.h | 83 --
1 file changed, 79 insertions(+), 4 deletions(-)
diff --git a/arch/mips/cavium-octeon/crypto/octeon-crypto.h
b/arch/mips/cavium-octeon/crypto/octeon-crypto.h
index e2a4aec..3550725 100644
--- a/arch/mips/cavium-octeon/crypto/octeon-crypto.h
+++ b/arch/mips/cavium-octeon/crypto/octeon-crypto.h
@@ -5,7 +5,8 @@
*
* Copyright (C) 2012-2013 Cavium Inc., All Rights Reserved.
*
- * MD5 instruction definitions added by Aaro Koskinen aaro.koski...@iki.fi.
+ * MD5/SHA1/SHA256/SHA512 instruction definitions added by
+ * Aaro Koskinen aaro.koski...@iki.fi.
*
*/
#ifndef __LINUX_OCTEON_CRYPTO_H
@@ -21,11 +22,11 @@ extern void octeon_crypto_disable(struct octeon_cop2_state
*state,
unsigned long flags);
/*
- * Macros needed to implement MD5:
+ * Macros needed to implement MD5/SHA1/SHA256:
*/
/*
- * The index can be 0-1.
+ * The index can be 0-1 (MD5) or 0-2 (SHA1), 0-3 (SHA256).
*/
#define write_octeon_64bit_hash_dword(value, index)\
do { \
@@ -36,7 +37,7 @@ do { \
} while (0)
/*
- * The index can be 0-1.
+ * The index can be 0-1 (MD5) or 0-2 (SHA1), 0-3 (SHA256).
*/
#define read_octeon_64bit_hash_dword(index)\
({ \
@@ -72,4 +73,78 @@ do { \
: [rt] d (value));\
} while (0)
+/*
+ * The value is the final block dword (64-bit).
+ */
+#define octeon_sha1_start(value) \
+do { \
+ __asm__ __volatile__ ( \
+ dmtc2 %[rt],0x4057\
+ : \
+ : [rt] d (value));\
+} while (0)
+
+/*
+ * The value is the final block dword (64-bit).
+ */
+#define octeon_sha256_start(value) \
+do { \
+ __asm__ __volatile__ ( \
+ dmtc2 %[rt],0x404f\
+ : \
+ : [rt] d (value));\
+} while (0)
+
+/*
+ * Macros needed to implement SHA512:
+ */
+
+/*
+ * The index can be 0-7.
+ */
+#define write_octeon_64bit_hash_sha512(value, index) \
+do { \
+ __asm__ __volatile__ ( \
+ dmtc2 %[rt],0x0250+ STR(index)\
+ : \
+ : [rt] d (value));\
+} while (0)
+
+/*
+ * The index can be 0-7.
+ */
+#define read_octeon_64bit_hash_sha512(index) \
+({ \
+ u64 __value;\
+ \
+ __asm__ __volatile__ ( \
+ dmfc2 %[rt],0x0250+ STR(index)\
+ : [rt] =d (__value) \
+ : );\
+ \
+ __value;\
+})
+
+/*
+ * The index can be 0-14.
+ */
+#define write_octeon_64bit_block_sha512(value, index) \
+do { \
+ __asm__ __volatile__ ( \
+ dmtc2 %[rt],0x0240+ STR(index)\
+ : \
+ : [rt] d (value));\
+} while (0)
+
+/*
+ * The value is the final block word (64-bit).
+ */
+#define octeon_sha512_start(value) \
+do { \
+ __asm__ __volatile__ ( \
+ dmtc2 %[rt],0x424f\
+ : \
+ : [rt] d (value));\
+} while (0)
+
#endif /* __LINUX_OCTEON_CRYPTO_H */
--
2.2.0
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[PATCH 6/7] crypto: octeon - add SHA512 module
Add OCTEON SHA512 module.
Signed-off-by: Aaro Koskinen aaro.koski...@iki.fi
---
arch/mips/cavium-octeon/crypto/Makefile| 1 +
arch/mips/cavium-octeon/crypto/octeon-sha512.c | 277 +
2 files changed, 278 insertions(+)
create mode 100644 arch/mips/cavium-octeon/crypto/octeon-sha512.c
diff --git a/arch/mips/cavium-octeon/crypto/Makefile
b/arch/mips/cavium-octeon/crypto/Makefile
index 47806a5..f7aa9d5 100644
--- a/arch/mips/cavium-octeon/crypto/Makefile
+++ b/arch/mips/cavium-octeon/crypto/Makefile
@@ -7,3 +7,4 @@ obj-y += octeon-crypto.o
obj-$(CONFIG_CRYPTO_MD5_OCTEON)+= octeon-md5.o
obj-$(CONFIG_CRYPTO_SHA1_OCTEON) += octeon-sha1.o
obj-$(CONFIG_CRYPTO_SHA256_OCTEON) += octeon-sha256.o
+obj-$(CONFIG_CRYPTO_SHA512_OCTEON) += octeon-sha512.o
diff --git a/arch/mips/cavium-octeon/crypto/octeon-sha512.c
b/arch/mips/cavium-octeon/crypto/octeon-sha512.c
new file mode 100644
index 000..d5fb3c6
--- /dev/null
+++ b/arch/mips/cavium-octeon/crypto/octeon-sha512.c
@@ -0,0 +1,277 @@
+/*
+ * Cryptographic API.
+ *
+ * SHA-512 and SHA-384 Secure Hash Algorithm.
+ *
+ * Adapted for OCTEON by Aaro Koskinen aaro.koski...@iki.fi.
+ *
+ * Based on crypto/sha512_generic.c, which is:
+ *
+ * Copyright (c) Jean-Luc Cooke jlco...@certainkey.com
+ * Copyright (c) Andrew McDonald and...@mcdonald.org.uk
+ * Copyright (c) 2003 Kyle McMartin k...@debian.org
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2, or (at your option) any
+ * later version.
+ */
+
+#include linux/mm.h
+#include crypto/sha.h
+#include linux/init.h
+#include linux/types.h
+#include linux/module.h
+#include asm/byteorder.h
+#include asm/octeon/octeon.h
+#include crypto/internal/hash.h
+
+#include octeon-crypto.h
+
+/*
+ * We pass everything as 64-bit. OCTEON can handle misaligned data.
+ */
+
+static void octeon_sha512_store_hash(struct sha512_state *sctx)
+{
+ write_octeon_64bit_hash_sha512(sctx-state[0], 0);
+ write_octeon_64bit_hash_sha512(sctx-state[1], 1);
+ write_octeon_64bit_hash_sha512(sctx-state[2], 2);
+ write_octeon_64bit_hash_sha512(sctx-state[3], 3);
+ write_octeon_64bit_hash_sha512(sctx-state[4], 4);
+ write_octeon_64bit_hash_sha512(sctx-state[5], 5);
+ write_octeon_64bit_hash_sha512(sctx-state[6], 6);
+ write_octeon_64bit_hash_sha512(sctx-state[7], 7);
+}
+
+static void octeon_sha512_read_hash(struct sha512_state *sctx)
+{
+ sctx-state[0] = read_octeon_64bit_hash_sha512(0);
+ sctx-state[1] = read_octeon_64bit_hash_sha512(1);
+ sctx-state[2] = read_octeon_64bit_hash_sha512(2);
+ sctx-state[3] = read_octeon_64bit_hash_sha512(3);
+ sctx-state[4] = read_octeon_64bit_hash_sha512(4);
+ sctx-state[5] = read_octeon_64bit_hash_sha512(5);
+ sctx-state[6] = read_octeon_64bit_hash_sha512(6);
+ sctx-state[7] = read_octeon_64bit_hash_sha512(7);
+}
+
+static void octeon_sha512_transform(const void *_block)
+{
+ const u64 *block = _block;
+
+ write_octeon_64bit_block_sha512(block[0], 0);
+ write_octeon_64bit_block_sha512(block[1], 1);
+ write_octeon_64bit_block_sha512(block[2], 2);
+ write_octeon_64bit_block_sha512(block[3], 3);
+ write_octeon_64bit_block_sha512(block[4], 4);
+ write_octeon_64bit_block_sha512(block[5], 5);
+ write_octeon_64bit_block_sha512(block[6], 6);
+ write_octeon_64bit_block_sha512(block[7], 7);
+ write_octeon_64bit_block_sha512(block[8], 8);
+ write_octeon_64bit_block_sha512(block[9], 9);
+ write_octeon_64bit_block_sha512(block[10], 10);
+ write_octeon_64bit_block_sha512(block[11], 11);
+ write_octeon_64bit_block_sha512(block[12], 12);
+ write_octeon_64bit_block_sha512(block[13], 13);
+ write_octeon_64bit_block_sha512(block[14], 14);
+ octeon_sha512_start(block[15]);
+}
+
+static int octeon_sha512_init(struct shash_desc *desc)
+{
+ struct sha512_state *sctx = shash_desc_ctx(desc);
+
+ sctx-state[0] = SHA512_H0;
+ sctx-state[1] = SHA512_H1;
+ sctx-state[2] = SHA512_H2;
+ sctx-state[3] = SHA512_H3;
+ sctx-state[4] = SHA512_H4;
+ sctx-state[5] = SHA512_H5;
+ sctx-state[6] = SHA512_H6;
+ sctx-state[7] = SHA512_H7;
+ sctx-count[0] = sctx-count[1] = 0;
+
+ return 0;
+}
+
+static int octeon_sha384_init(struct shash_desc *desc)
+{
+ struct sha512_state *sctx = shash_desc_ctx(desc);
+
+ sctx-state[0] = SHA384_H0;
+ sctx-state[1] = SHA384_H1;
+ sctx-state[2] = SHA384_H2;
+ sctx-state[3] = SHA384_H3;
+ sctx-state[4] = SHA384_H4;
+ sctx-state[5] = SHA384_H5;
+ sctx-state[6] = SHA384_H6;
+ sctx-state[7] = SHA384_H7;
+ sctx-count[0] = sctx-count[1] = 0;
+
+ return 0;
+}
+
+static void __octeon_sha512_update
[PATCH 2/7] crypto: octeon - always disable preemption when using crypto engine
Always disable preemption on behalf of the drivers when crypto engine is taken into use. This will simplify the usage. Signed-off-by: Aaro Koskinen aaro.koski...@iki.fi --- arch/mips/cavium-octeon/crypto/octeon-crypto.c | 4 +++- arch/mips/cavium-octeon/crypto/octeon-md5.c| 4 2 files changed, 3 insertions(+), 5 deletions(-) diff --git a/arch/mips/cavium-octeon/crypto/octeon-crypto.c b/arch/mips/cavium-octeon/crypto/octeon-crypto.c index 7c82ff4..f66bd1a 100644 --- a/arch/mips/cavium-octeon/crypto/octeon-crypto.c +++ b/arch/mips/cavium-octeon/crypto/octeon-crypto.c @@ -17,7 +17,7 @@ * crypto operations in calls to octeon_crypto_enable/disable in order to make * sure the state of COP2 isn't corrupted if userspace is also performing * hardware crypto operations. Allocate the state parameter on the stack. - * Preemption must be disabled to prevent context switches. + * Returns with preemption disabled. * * @state: Pointer to state structure to store current COP2 state in. * @@ -28,6 +28,7 @@ unsigned long octeon_crypto_enable(struct octeon_cop2_state *state) int status; unsigned long flags; + preempt_disable(); local_irq_save(flags); status = read_c0_status(); write_c0_status(status | ST0_CU2); @@ -62,5 +63,6 @@ void octeon_crypto_disable(struct octeon_cop2_state *state, else write_c0_status(read_c0_status() ~ST0_CU2); local_irq_restore(flags); + preempt_enable(); } EXPORT_SYMBOL_GPL(octeon_crypto_disable); diff --git a/arch/mips/cavium-octeon/crypto/octeon-md5.c b/arch/mips/cavium-octeon/crypto/octeon-md5.c index 3dd8845..12dccdb 100644 --- a/arch/mips/cavium-octeon/crypto/octeon-md5.c +++ b/arch/mips/cavium-octeon/crypto/octeon-md5.c @@ -97,7 +97,6 @@ static int octeon_md5_update(struct shash_desc *desc, const u8 *data, memcpy((char *)mctx-block + (sizeof(mctx-block) - avail), data, avail); - preempt_disable(); flags = octeon_crypto_enable(state); octeon_md5_store_hash(mctx); @@ -113,7 +112,6 @@ static int octeon_md5_update(struct shash_desc *desc, const u8 *data, octeon_md5_read_hash(mctx); octeon_crypto_disable(state, flags); - preempt_enable(); memcpy(mctx-block, data, len); @@ -131,7 +129,6 @@ static int octeon_md5_final(struct shash_desc *desc, u8 *out) *p++ = 0x80; - preempt_disable(); flags = octeon_crypto_enable(state); octeon_md5_store_hash(mctx); @@ -149,7 +146,6 @@ static int octeon_md5_final(struct shash_desc *desc, u8 *out) octeon_md5_read_hash(mctx); octeon_crypto_disable(state, flags); - preempt_enable(); memcpy(out, mctx-hash, sizeof(mctx-hash)); memset(mctx, 0, sizeof(*mctx)); -- 2.2.0 -- To unsubscribe from this list: send the line unsubscribe linux-crypto in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 7/7] crypto: octeon - enable OCTEON SHA1/256/512 module selection
Enable user to select OCTEON SHA1/256/512 modules. Signed-off-by: Aaro Koskinen aaro.koski...@iki.fi --- crypto/Kconfig | 27 +++ 1 file changed, 27 insertions(+) diff --git a/crypto/Kconfig b/crypto/Kconfig index 50f4da4..38b2315 100644 --- a/crypto/Kconfig +++ b/crypto/Kconfig @@ -546,6 +546,15 @@ config CRYPTO_SHA512_SSSE3 Extensions version 1 (AVX1), or Advanced Vector Extensions version 2 (AVX2) instructions, when available. +config CRYPTO_SHA1_OCTEON + tristate SHA1 digest algorithm (OCTEON) + depends on CPU_CAVIUM_OCTEON + select CRYPTO_SHA1 + select CRYPTO_HASH + help + SHA-1 secure hash standard (FIPS 180-1/DFIPS 180-2) implemented + using OCTEON crypto instructions, when available. + config CRYPTO_SHA1_SPARC64 tristate SHA1 digest algorithm (SPARC64) depends on SPARC64 @@ -610,6 +619,15 @@ config CRYPTO_SHA256 This code also includes SHA-224, a 224 bit hash with 112 bits of security against collision attacks. +config CRYPTO_SHA256_OCTEON + tristate SHA224 and SHA256 digest algorithm (OCTEON) + depends on CPU_CAVIUM_OCTEON + select CRYPTO_SHA256 + select CRYPTO_HASH + help + SHA-256 secure hash standard (DFIPS 180-2) implemented + using OCTEON crypto instructions, when available. + config CRYPTO_SHA256_SPARC64 tristate SHA224 and SHA256 digest algorithm (SPARC64) depends on SPARC64 @@ -631,6 +649,15 @@ config CRYPTO_SHA512 This code also includes SHA-384, a 384 bit hash with 192 bits of security against collision attacks. +config CRYPTO_SHA512_OCTEON + tristate SHA384 and SHA512 digest algorithms (OCTEON) + depends on CPU_CAVIUM_OCTEON + select CRYPTO_SHA512 + select CRYPTO_HASH + help + SHA-512 secure hash standard (DFIPS 180-2) implemented + using OCTEON crypto instructions, when available. + config CRYPTO_SHA512_SPARC64 tristate SHA384 and SHA512 digest algorithm (SPARC64) depends on SPARC64 -- 2.2.0 -- To unsubscribe from this list: send the line unsubscribe linux-crypto in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 00/10] omap3 crypto fixes
Hi, On Fri, Feb 27, 2015 at 01:40:44PM +0100, Pali Rohár wrote: However I get these when CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set: alg: hash: Chunking test 1 failed for omap-sha1 alg: hash: Chunking test 1 failed for omap-md5 alg: hash: Chunking test 1 failed for omap-hmac-sha1 alg: hash: Chunking test 1 failed for omap-hmac-md5 BTW, it seems these errors are reported to be introduced possibly somewhere between 3.11 and 3.15: https://lists.fedoraproject.org/pipermail/arm/2014-August/008240.html A. -- To unsubscribe from this list: send the line unsubscribe linux-crypto in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 00/10] omap3 crypto fixes
Hi, On Fri, Mar 06, 2015 at 10:36:32AM -0800, Tony Lindgren wrote: Are there any fixes in this series that should go into v4.0-rc series, or can it all wait for v4.1? I think these all should wait for v4.1. A. -- To unsubscribe from this list: send the line unsubscribe linux-crypto in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 00/10] omap3 crypto fixes
Hi, On Thu, Feb 26, 2015 at 02:49:50PM +0100, Pali Rohár wrote: This patch series fix crypto support for omap3 devices which use DT. It enables AES and SHAM on N9/N950 and SHAM on N900. AES is still disabled for N900. (Please format your lines somewhere near 76 chars, especially in commit logs, otherwise git log looks ugly on 80 char terminals.) I tested these with stock bootloaders, and devices boot normally and I can now modprobe omap-aes (on N9 and N950) and omap-sham (on all three): omap-aes 480c5000.aes: OMAP AES hw accel rev: 2.6 omap-sham 480c3000.sham: hw accel on OMAP rev 0.9 However I get these when CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set: alg: hash: Chunking test 1 failed for omap-sha1 alg: hash: Chunking test 1 failed for omap-md5 alg: hash: Chunking test 1 failed for omap-hmac-sha1 alg: hash: Chunking test 1 failed for omap-hmac-md5 But that's probably unrelated to this series. For patches 1-8, feel free to add: Tested-by: Aaro Koskinen aaro.koski...@iki.fi A. -- To unsubscribe from this list: send the line unsubscribe linux-crypto in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 0/5] MIPS/crypto: MD5 for OCTEON
Hi, This adds accelerated MD5 cryptoapi module for OCTEON. Tested with 3.19-rc1 on EdgeRouter Lite (OCTEON+) and EdgeRouter Pro (OCTEON2) by running selftest, tcrypt and also by sending TCP MD5SIG traffic between OCTEON - X86 box. Below figures show the improvement on ER Lite compared to md5-generic (calculated from output of tcrypt mode=402). test 0 ( 16 byte blocks, 16 bytes per update, 1 updates): 1.20x faster test 1 ( 64 byte blocks, 16 bytes per update, 4 updates): 1.17x faster test 2 ( 64 byte blocks, 64 bytes per update, 1 updates): 1.30x faster test 3 ( 256 byte blocks, 16 bytes per update, 16 updates): 1.14x faster test 4 ( 256 byte blocks, 64 bytes per update, 4 updates): 1.29x faster test 5 ( 256 byte blocks, 256 bytes per update, 1 updates): 1.84x faster test 6 ( 1024 byte blocks, 16 bytes per update, 64 updates): 1.13x faster test 7 ( 1024 byte blocks, 256 bytes per update, 4 updates): 2.01x faster test 8 ( 1024 byte blocks, 1024 bytes per update, 1 updates): 2.49x faster test 9 ( 2048 byte blocks, 16 bytes per update, 128 updates): 1.13x faster test 10 ( 2048 byte blocks, 256 bytes per update, 8 updates): 2.05x faster test 11 ( 2048 byte blocks, 1024 bytes per update, 2 updates): 2.57x faster test 12 ( 2048 byte blocks, 2048 bytes per update, 1 updates): 2.71x faster test 13 ( 4096 byte blocks, 16 bytes per update, 256 updates): 1.15x faster test 14 ( 4096 byte blocks, 256 bytes per update, 16 updates): 2.08x faster test 15 ( 4096 byte blocks, 1024 bytes per update, 4 updates): 2.63x faster test 16 ( 4096 byte blocks, 4096 bytes per update, 1 updates): 2.83x faster test 17 ( 8192 byte blocks, 16 bytes per update, 512 updates): 1.13x faster test 18 ( 8192 byte blocks, 256 bytes per update, 32 updates): 2.09x faster test 19 ( 8192 byte blocks, 1024 bytes per update, 8 updates): 2.66x faster test 20 ( 8192 byte blocks, 4096 bytes per update, 2 updates): 2.87x faster test 21 ( 8192 byte blocks, 8192 bytes per update, 1 updates): 2.87x faster A. Aaro Koskinen (5): MIPS: OCTEON: add crypto helper functions MIPS: OCTEON: crypto: add instruction definitions for MD5 MIPS: OCTEON: reintroduce crypto features check MIPS: OCTEON: crypto: add MD5 module crypto: enable OCTEON MD5 module selection arch/mips/cavium-octeon/Makefile | 1 + arch/mips/cavium-octeon/crypto/Makefile | 7 + arch/mips/cavium-octeon/crypto/octeon-crypto.c | 66 +++ arch/mips/cavium-octeon/crypto/octeon-crypto.h | 75 arch/mips/cavium-octeon/crypto/octeon-md5.c | 216 +++ arch/mips/cavium-octeon/executive/octeon-model.c | 6 + arch/mips/include/asm/octeon/octeon-feature.h| 17 +- arch/mips/include/asm/octeon/octeon.h| 5 - crypto/Kconfig | 9 + 9 files changed, 395 insertions(+), 7 deletions(-) create mode 100644 arch/mips/cavium-octeon/crypto/Makefile create mode 100644 arch/mips/cavium-octeon/crypto/octeon-crypto.c create mode 100644 arch/mips/cavium-octeon/crypto/octeon-crypto.h create mode 100644 arch/mips/cavium-octeon/crypto/octeon-md5.c -- 2.2.0 -- To unsubscribe from this list: send the line unsubscribe linux-crypto in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 3/5] MIPS: OCTEON: reintroduce crypto features check
Reintroduce run-time check for crypto features. The old one was deleted
because it was unreliable, now decide the crypto availability on early
boot when the model string is constructed.
Signed-off-by: Aaro Koskinen aaro.koski...@iki.fi
---
arch/mips/cavium-octeon/executive/octeon-model.c | 6 ++
arch/mips/include/asm/octeon/octeon-feature.h| 17 +++--
2 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/arch/mips/cavium-octeon/executive/octeon-model.c
b/arch/mips/cavium-octeon/executive/octeon-model.c
index e15b049..b2104bd 100644
--- a/arch/mips/cavium-octeon/executive/octeon-model.c
+++ b/arch/mips/cavium-octeon/executive/octeon-model.c
@@ -27,6 +27,9 @@
#include asm/octeon/octeon.h
+enum octeon_feature_bits __octeon_feature_bits __read_mostly;
+EXPORT_SYMBOL_GPL(__octeon_feature_bits);
+
/**
* Read a byte of fuse data
* @byte_addr: address to read
@@ -103,6 +106,9 @@ static const char *__init
octeon_model_get_string_buffer(uint32_t chip_id,
else
suffix = NSP;
+ if (!fus_dat2.s.nocrypto)
+ __octeon_feature_bits |= OCTEON_HAS_CRYPTO;
+
/*
* Assume pass number is encoded using 5:32:0. Exceptions
* will be fixed later.
diff --git a/arch/mips/include/asm/octeon/octeon-feature.h
b/arch/mips/include/asm/octeon/octeon-feature.h
index c4fe81f..8ebd3f57 100644
--- a/arch/mips/include/asm/octeon/octeon-feature.h
+++ b/arch/mips/include/asm/octeon/octeon-feature.h
@@ -46,8 +46,6 @@ enum octeon_feature {
OCTEON_FEATURE_SAAD,
/* Does this Octeon support the ZIP offload engine? */
OCTEON_FEATURE_ZIP,
- /* Does this Octeon support crypto acceleration using COP2? */
- OCTEON_FEATURE_CRYPTO,
OCTEON_FEATURE_DORM_CRYPTO,
/* Does this Octeon support PCI express? */
OCTEON_FEATURE_PCIE,
@@ -86,6 +84,21 @@ enum octeon_feature {
OCTEON_MAX_FEATURE
};
+enum octeon_feature_bits {
+ OCTEON_HAS_CRYPTO = 0x0001, /* Crypto acceleration using COP2 */
+};
+extern enum octeon_feature_bits __octeon_feature_bits;
+
+/**
+ * octeon_has_crypto() - Check if this OCTEON has crypto acceleration support.
+ *
+ * Returns: Non-zero if the feature exists. Zero if the feature does not exist.
+ */
+static inline int octeon_has_crypto(void)
+{
+ return __octeon_feature_bits OCTEON_HAS_CRYPTO;
+}
+
/**
* Determine if the current Octeon supports a specific feature. These
* checks have been optimized to be fairly quick, but they should still
--
2.2.0
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[PATCH 4/5] MIPS: OCTEON: crypto: add MD5 module
Add OCTEON MD5 module.
Signed-off-by: Aaro Koskinen aaro.koski...@iki.fi
---
arch/mips/cavium-octeon/crypto/Makefile| 2 +
arch/mips/cavium-octeon/crypto/octeon-crypto.h | 2 +
arch/mips/cavium-octeon/crypto/octeon-md5.c| 216 +
3 files changed, 220 insertions(+)
create mode 100644 arch/mips/cavium-octeon/crypto/octeon-md5.c
diff --git a/arch/mips/cavium-octeon/crypto/Makefile
b/arch/mips/cavium-octeon/crypto/Makefile
index 739b803..a74f76d 100644
--- a/arch/mips/cavium-octeon/crypto/Makefile
+++ b/arch/mips/cavium-octeon/crypto/Makefile
@@ -3,3 +3,5 @@
#
obj-y += octeon-crypto.o
+
+obj-$(CONFIG_CRYPTO_MD5_OCTEON) += octeon-md5.o
diff --git a/arch/mips/cavium-octeon/crypto/octeon-crypto.h
b/arch/mips/cavium-octeon/crypto/octeon-crypto.h
index 3f65bc6..e2a4aec 100644
--- a/arch/mips/cavium-octeon/crypto/octeon-crypto.h
+++ b/arch/mips/cavium-octeon/crypto/octeon-crypto.h
@@ -14,6 +14,8 @@
#include linux/sched.h
#include asm/mipsregs.h
+#define OCTEON_CR_OPCODE_PRIORITY 300
+
extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state);
extern void octeon_crypto_disable(struct octeon_cop2_state *state,
unsigned long flags);
diff --git a/arch/mips/cavium-octeon/crypto/octeon-md5.c
b/arch/mips/cavium-octeon/crypto/octeon-md5.c
new file mode 100644
index 000..b909881
--- /dev/null
+++ b/arch/mips/cavium-octeon/crypto/octeon-md5.c
@@ -0,0 +1,216 @@
+/*
+ * Cryptographic API.
+ *
+ * MD5 Message Digest Algorithm (RFC1321).
+ *
+ * Adapted for OCTEON by Aaro Koskinen aaro.koski...@iki.fi.
+ *
+ * Based on crypto/md5.c, which is:
+ *
+ * Derived from cryptoapi implementation, originally based on the
+ * public domain implementation written by Colin Plumb in 1993.
+ *
+ * Copyright (c) Cryptoapi developers.
+ * Copyright (c) 2002 James Morris jmor...@intercode.com.au
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include crypto/md5.h
+#include linux/init.h
+#include linux/types.h
+#include linux/module.h
+#include linux/string.h
+#include asm/byteorder.h
+#include linux/cryptohash.h
+#include asm/octeon/octeon.h
+#include crypto/internal/hash.h
+
+#include octeon-crypto.h
+
+/*
+ * We pass everything as 64-bit. OCTEON can handle misaligned data.
+ */
+
+static void octeon_md5_store_hash(struct md5_state *ctx)
+{
+ u64 *hash = (u64 *)ctx-hash;
+
+ write_octeon_64bit_hash_dword(hash[0], 0);
+ write_octeon_64bit_hash_dword(hash[1], 1);
+}
+
+static void octeon_md5_read_hash(struct md5_state *ctx)
+{
+ u64 *hash = (u64 *)ctx-hash;
+
+ hash[0] = read_octeon_64bit_hash_dword(0);
+ hash[1] = read_octeon_64bit_hash_dword(1);
+}
+
+static void octeon_md5_transform(const void *_block)
+{
+ const u64 *block = _block;
+
+ write_octeon_64bit_block_dword(block[0], 0);
+ write_octeon_64bit_block_dword(block[1], 1);
+ write_octeon_64bit_block_dword(block[2], 2);
+ write_octeon_64bit_block_dword(block[3], 3);
+ write_octeon_64bit_block_dword(block[4], 4);
+ write_octeon_64bit_block_dword(block[5], 5);
+ write_octeon_64bit_block_dword(block[6], 6);
+ octeon_md5_start(block[7]);
+}
+
+static int octeon_md5_init(struct shash_desc *desc)
+{
+ struct md5_state *mctx = shash_desc_ctx(desc);
+
+ mctx-hash[0] = cpu_to_le32(0x67452301);
+ mctx-hash[1] = cpu_to_le32(0xefcdab89);
+ mctx-hash[2] = cpu_to_le32(0x98badcfe);
+ mctx-hash[3] = cpu_to_le32(0x10325476);
+ mctx-byte_count = 0;
+
+ return 0;
+}
+
+static int octeon_md5_update(struct shash_desc *desc, const u8 *data,
+unsigned int len)
+{
+ struct md5_state *mctx = shash_desc_ctx(desc);
+ const u32 avail = sizeof(mctx-block) - (mctx-byte_count 0x3f);
+ struct octeon_cop2_state state;
+ unsigned long flags;
+
+ mctx-byte_count += len;
+
+ if (avail len) {
+ memcpy((char *)mctx-block + (sizeof(mctx-block) - avail),
+ data, len);
+ return 0;
+ }
+
+ memcpy((char *)mctx-block + (sizeof(mctx-block) - avail), data,
+ avail);
+
+ local_bh_disable();
+ preempt_disable();
+ flags = octeon_crypto_enable(state);
+ octeon_md5_store_hash(mctx);
+
+ octeon_md5_transform(mctx-block);
+ data += avail;
+ len -= avail;
+
+ while (len = sizeof(mctx-block)) {
+ octeon_md5_transform(data);
+ data += sizeof(mctx-block);
+ len -= sizeof(mctx-block);
+ }
+
+ octeon_md5_read_hash(mctx);
+ octeon_crypto_disable(state, flags);
+ preempt_enable();
+ local_bh_enable();
+
+ memcpy(mctx-block, data
[PATCH 2/5] MIPS: OCTEON: crypto: add instruction definitions for MD5
Add instruction definitions for MD5. Based on information extracted
from EdgeRouter Pro GPL source tarball.
Signed-off-by: Aaro Koskinen aaro.koski...@iki.fi
---
arch/mips/cavium-octeon/crypto/octeon-crypto.h | 56 ++
1 file changed, 56 insertions(+)
diff --git a/arch/mips/cavium-octeon/crypto/octeon-crypto.h
b/arch/mips/cavium-octeon/crypto/octeon-crypto.h
index 5ca86d4..3f65bc6 100644
--- a/arch/mips/cavium-octeon/crypto/octeon-crypto.h
+++ b/arch/mips/cavium-octeon/crypto/octeon-crypto.h
@@ -4,14 +4,70 @@
* for more details.
*
* Copyright (C) 2012-2013 Cavium Inc., All Rights Reserved.
+ *
+ * MD5 instruction definitions added by Aaro Koskinen aaro.koski...@iki.fi.
+ *
*/
#ifndef __LINUX_OCTEON_CRYPTO_H
#define __LINUX_OCTEON_CRYPTO_H
#include linux/sched.h
+#include asm/mipsregs.h
extern unsigned long octeon_crypto_enable(struct octeon_cop2_state *state);
extern void octeon_crypto_disable(struct octeon_cop2_state *state,
unsigned long flags);
+/*
+ * Macros needed to implement MD5:
+ */
+
+/*
+ * The index can be 0-1.
+ */
+#define write_octeon_64bit_hash_dword(value, index)\
+do { \
+ __asm__ __volatile__ ( \
+ dmtc2 %[rt],0x0048+ STR(index)\
+ : \
+ : [rt] d (value));\
+} while (0)
+
+/*
+ * The index can be 0-1.
+ */
+#define read_octeon_64bit_hash_dword(index)\
+({ \
+ u64 __value;\
+ \
+ __asm__ __volatile__ ( \
+ dmfc2 %[rt],0x0048+ STR(index)\
+ : [rt] =d (__value) \
+ : );\
+ \
+ __value;\
+})
+
+/*
+ * The index can be 0-6.
+ */
+#define write_octeon_64bit_block_dword(value, index) \
+do { \
+ __asm__ __volatile__ ( \
+ dmtc2 %[rt],0x0040+ STR(index)\
+ : \
+ : [rt] d (value));\
+} while (0)
+
+/*
+ * The value is the final block dword (64-bit).
+ */
+#define octeon_md5_start(value)\
+do { \
+ __asm__ __volatile__ ( \
+ dmtc2 %[rt],0x4047\
+ : \
+ : [rt] d (value));\
+} while (0)
+
#endif /* __LINUX_OCTEON_CRYPTO_H */
--
2.2.0
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