Re: [PATCH 3/9] dt-bindings: crypto: Add DT bindings documentation for sun8i-ce Crypto Engine
On Thu, Sep 12, 2019 at 9:33 PM Maxime Ripard wrote: > > On Thu, Sep 12, 2019 at 09:26:27PM +0100, Chen-Yu Tsai wrote: > > > > > > > > clock-names: > > > > items: > > > > - const: ahb > > > > - const: mod > > > > - const: mbus > > > > > > And here as well > > > > > > Something I missed earlier though was that we've tried to unify as > > > much as possible the ahb / apb / axi clocks around the bus name, it > > > would be great if you could do it. > > > > I think we also want to standardize "mbus" as "dram"? > > Do we? The only user so far seems to be sun9i-de, while mbus has more > users. I don't really care though, both mbus and dram are pretty > generic to me. What makes you prefer dram over mbus? Argh... it's actually "ram" we use the most. Both "dram" and "mbus" have only one instance each. ChenYu
Re: [PATCH 3/9] dt-bindings: crypto: Add DT bindings documentation for sun8i-ce Crypto Engine
On Thu, Sep 12, 2019 at 10:37 AM Maxime Ripard wrote: > > Hi Corentin, > > On Wed, Sep 11, 2019 at 08:31:58PM +0200, Corentin Labbe wrote: > > On Sat, Sep 07, 2019 at 07:01:16AM +0300, Maxime Ripard wrote: > > > On Fri, Sep 06, 2019 at 08:45:45PM +0200, Corentin Labbe wrote: > > > > This patch adds documentation for Device-Tree bindings for the > > > > Crypto Engine cryptographic accelerator driver. > > > > > > > > Signed-off-by: Corentin Labbe > > > > --- > > > > .../bindings/crypto/allwinner,sun8i-ce.yaml | 84 +++ > > > > 1 file changed, 84 insertions(+) > > > > create mode 100644 > > > > Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml > > > > > > > > diff --git > > > > a/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml > > > > b/Documentation/devicetree/bindings/crypto/allwinner,sun8i-ce.yaml > > [...] > > > > +else: > > > > + clocks: > > > > +items: > > > > + - description: Bus clock > > > > + - description: Module clock > > > > + > > > > + clock-names: > > > > +items: > > > > + - const: ahb > > > > + - const: mod > > > > + > > > > + resets: > > > > +maxItems: 1 > > > > + > > > > + reset-names: > > > > +const: ahb > > > > > > This prevents the usage of the additionalProperties property, which > > > you should really use. > > > > > > What you can do instead is moving the clocks and clock-names > > > description under properties, with a minItems of 2 and a maxItems of > > > 3. Then you can restrict the length of that property to either 2 or 3 > > > depending on the case here. > > > > > > > Hello > > > > I fail to do this. > > I do the following (keeped only clock stuff) > > properties: > > > > clocks: > > items: > > - description: Bus clock > > - description: Module clock > > - description: MBus clock > > Add minItems: 2 and maxItems: 3 at the same level than items > > > > > clock-names: > > items: > > - const: ahb > > - const: mod > > - const: mbus > > And here as well > > Something I missed earlier though was that we've tried to unify as > much as possible the ahb / apb / axi clocks around the bus name, it > would be great if you could do it. I think we also want to standardize "mbus" as "dram"? ChenYu > > > > if: > > properties: > > compatible: > > items: > > const: allwinner,sun50i-h6-crypto > > then: > > properties: > > clocks: > > minItems: 3 > > maxItems: 3 > > clock-names: > > minItems: 3 > > maxItems: 3 > > You don't need to duplicate the min and maxItems here > > Maxime
Re: [PATCH] crypto: sun4i-ss: add missing statesize
On Thu, Nov 5, 2015 at 3:48 PM, LABBE Corentin
wrote:
> sun4i-ss implementaton of md5/sha1 is via ahash algorithms.
> A recent change make impossible to load them without giving statesize.
> This patch specifiy statesize for sha1 and md5.
>
> Signed-off-by: LABBE Corentin
> Cc: sta...@vger.kernel.org
Confirmed the driver properly loads again.
Tested-by: Chen-Yu Tsai
> ---
> drivers/crypto/sunxi-ss/sun4i-ss-core.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/crypto/sunxi-ss/sun4i-ss-core.c
> b/drivers/crypto/sunxi-ss/sun4i-ss-core.c
> index eab6fe2..107cd2a 100644
> --- a/drivers/crypto/sunxi-ss/sun4i-ss-core.c
> +++ b/drivers/crypto/sunxi-ss/sun4i-ss-core.c
> @@ -39,6 +39,7 @@ static struct sun4i_ss_alg_template ss_algs[] = {
> .import = sun4i_hash_import_md5,
> .halg = {
> .digestsize = MD5_DIGEST_SIZE,
> + .statesize = sizeof(struct md5_state),
> .base = {
> .cra_name = "md5",
> .cra_driver_name = "md5-sun4i-ss",
> @@ -66,6 +67,7 @@ static struct sun4i_ss_alg_template ss_algs[] = {
> .import = sun4i_hash_import_sha1,
> .halg = {
> .digestsize = SHA1_DIGEST_SIZE,
> + .statesize = sizeof(struct sha1_state),
> .base = {
> .cra_name = "sha1",
> .cra_driver_name = "sha1-sun4i-ss",
> --
> 2.4.10
>
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[PATCH 3/3] ARM: dts: sun6i: Add security system crypto engine clock and device nodes
A31/A31s have the same "Security System" crypto engine as A10/A20,
but with a separate reset control.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun6i-a31.dtsi | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 39953e76bbfc..7afb80f07dad 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -346,6 +346,14 @@
"mmc3_sample";
};
+ ss_clk: clk@01c2009c {
+ #clock-cells = <0>;
+ compatible = "allwinner,sun4i-a10-mod0-clk";
+ reg = <0x01c2009c 0x4>;
+ clocks = <&osc24M>, <&pll6 0>;
+ clock-output-names = "ss";
+ };
+
spi0_clk: clk@01c200a0 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-a10-mod0-clk";
@@ -882,6 +890,16 @@
#size-cells = <0>;
};
+ crypto: crypto-engine@01c15000 {
+ compatible = "allwinner,sun4i-a10-crypto";
+ reg = <0x01c15000 0x1000>;
+ interrupts = ;
+ clocks = <&ahb1_gates 5>, <&ss_clk>;
+ clock-names = "ahb", "mod";
+ resets = <&ahb1_rst 5>;
+ reset-names = "ahb";
+ };
+
timer@01c6 {
compatible = "allwinner,sun6i-a31-hstimer",
"allwinner,sun7i-a20-hstimer";
--
2.5.0
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[PATCH 1/3] crypto: sunxi-ss: Document optional reset control bindings
Later Allwinner SoCs split out the reset controls for individual modules
out of the clock gate controls. The "Security System" crypto engine is
no different.
Signed-off-by: Chen-Yu Tsai
---
Documentation/devicetree/bindings/crypto/sun4i-ss.txt | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/crypto/sun4i-ss.txt
b/Documentation/devicetree/bindings/crypto/sun4i-ss.txt
index 1e02d177fea6..5d38e9b7033f 100644
--- a/Documentation/devicetree/bindings/crypto/sun4i-ss.txt
+++ b/Documentation/devicetree/bindings/crypto/sun4i-ss.txt
@@ -9,6 +9,10 @@ Required properties:
* "ahb" : AHB gating clock
* "mod" : SS controller clock
+Optional properties:
+ - resets : phandle + reset specifier pair
+ - reset-names : must contain "ahb"
+
Example:
crypto: crypto-engine@01c15000 {
compatible = "allwinner,sun4i-a10-crypto";
--
2.5.0
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[PATCH 0/3] ARM: sun6i: Support Security System crypto engine
Hi everyone, This series enables support for the crypto engine found in sun6i, or Allwinner A31/A31s SoCs. The crypto engine is the same hardware as on earlier sun4i/sun7i (A10/A20), with the only difference being the reset control is separated out of the clock gate control. The same hardware is also available on the A33, but not the A23. Support for this requires additions to the clock driver, and will be submitted separately once things are clear on how to proceed. I already have a proof of concept working. Patch 1 adds an optional reset control property to the sunxi-ss binding. Patch 2 adds optional reset control support to the sunxi-ss driver. Patch 3 enables the crypto engine on sun6i, by adding the module clock and device node. Regards ChenYu Chen-Yu Tsai (3): crypto: sunxi-ss: Document optional reset control bindings crypto: sunxi-ss: Add optional reset control support ARM: dts: sun6i: Add security system crypto engine clock and device nodes .../devicetree/bindings/crypto/sun4i-ss.txt| 4 arch/arm/boot/dts/sun6i-a31.dtsi | 18 ++ drivers/crypto/sunxi-ss/sun4i-ss-core.c| 22 ++ drivers/crypto/sunxi-ss/sun4i-ss.h | 2 ++ 4 files changed, 46 insertions(+) -- 2.5.0 -- To unsubscribe from this list: send the line "unsubscribe linux-crypto" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/3] crypto: sunxi-ss: Add optional reset control support
On sun6i and later platforms, the reset control is split out of the
clock gates. Add support for an optional reset control.
Signed-off-by: Chen-Yu Tsai
---
drivers/crypto/sunxi-ss/sun4i-ss-core.c | 22 ++
drivers/crypto/sunxi-ss/sun4i-ss.h | 2 ++
2 files changed, 24 insertions(+)
diff --git a/drivers/crypto/sunxi-ss/sun4i-ss-core.c
b/drivers/crypto/sunxi-ss/sun4i-ss-core.c
index 0b79b58c913b..eab6fe227fa0 100644
--- a/drivers/crypto/sunxi-ss/sun4i-ss-core.c
+++ b/drivers/crypto/sunxi-ss/sun4i-ss-core.c
@@ -22,6 +22,7 @@
#include
#include
#include
+#include
#include "sun4i-ss.h"
@@ -253,6 +254,14 @@ static int sun4i_ss_probe(struct platform_device *pdev)
}
dev_dbg(&pdev->dev, "clock ahb_ss acquired\n");
+ ss->reset = devm_reset_control_get_optional(&pdev->dev, "ahb");
+ if (IS_ERR(ss->reset)) {
+ if (PTR_ERR(ss->reset) == -EPROBE_DEFER)
+ return PTR_ERR(ss->reset);
+ dev_info(&pdev->dev, "no reset control found\n");
+ ss->reset = NULL;
+ }
+
/* Enable both clocks */
err = clk_prepare_enable(ss->busclk);
if (err != 0) {
@@ -275,6 +284,15 @@ static int sun4i_ss_probe(struct platform_device *pdev)
goto error_clk;
}
+ /* Deassert reset if we have a reset control */
+ if (ss->reset) {
+ err = reset_control_deassert(ss->reset);
+ if (err) {
+ dev_err(&pdev->dev, "Cannot deassert reset control\n");
+ goto error_clk;
+ }
+ }
+
/*
* The only impact on clocks below requirement are bad performance,
* so do not print "errors"
@@ -352,6 +370,8 @@ error_alg:
break;
}
}
+ if (ss->reset)
+ reset_control_assert(ss->reset);
error_clk:
clk_disable_unprepare(ss->ssclk);
error_ssclk:
@@ -376,6 +396,8 @@ static int sun4i_ss_remove(struct platform_device *pdev)
}
writel(0, ss->base + SS_CTL);
+ if (ss->reset)
+ reset_control_assert(ss->reset);
clk_disable_unprepare(ss->busclk);
clk_disable_unprepare(ss->ssclk);
return 0;
diff --git a/drivers/crypto/sunxi-ss/sun4i-ss.h
b/drivers/crypto/sunxi-ss/sun4i-ss.h
index db18b2554e6f..8e9c05f6e4d4 100644
--- a/drivers/crypto/sunxi-ss/sun4i-ss.h
+++ b/drivers/crypto/sunxi-ss/sun4i-ss.h
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -129,6 +130,7 @@ struct sun4i_ss_ctx {
int irq;
struct clk *busclk;
struct clk *ssclk;
+ struct reset_control *reset;
struct device *dev;
struct resource *res;
spinlock_t slock; /* control the use of the device */
--
2.5.0
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Re: [linux-sunxi] [PATCH v2 1/4] crypto: Add Allwinner Security System crypto accelerator
Hi, On Mon, Jun 9, 2014 at 6:59 PM, LABBE Corentin wrote: > Add support for the Security System included in Allwinner SoC A20. > The Security System is a hardware cryptographic accelerator that support > AES/MD5/SHA1/DES/3DES/PRNG algorithms. > > Signed-off-by: LABBE Corentin > --- > drivers/crypto/sunxi-ss/Makefile | 16 ++ > drivers/crypto/sunxi-ss/sunxi-ss-cipher-3des.c | 118 > drivers/crypto/sunxi-ss/sunxi-ss-cipher-aes.c | 130 + > drivers/crypto/sunxi-ss/sunxi-ss-cipher-des.c | 118 > drivers/crypto/sunxi-ss/sunxi-ss-cipher.c | 362 > + > drivers/crypto/sunxi-ss/sunxi-ss-cipher.h | 8 + > drivers/crypto/sunxi-ss/sunxi-ss-hash-md5.c| 69 + > drivers/crypto/sunxi-ss/sunxi-ss-hash-sha1.c | 69 + > drivers/crypto/sunxi-ss/sunxi-ss-hash.c| 228 > drivers/crypto/sunxi-ss/sunxi-ss-hash.h| 9 + > drivers/crypto/sunxi-ss/sunxi-ss-rng.c | 115 > drivers/crypto/sunxi-ss/sunxi-ss.c | 190 + > drivers/crypto/sunxi-ss/sunxi-ss.h | 161 +++ > 13 files changed, 1593 insertions(+) > create mode 100644 drivers/crypto/sunxi-ss/Makefile > create mode 100644 drivers/crypto/sunxi-ss/sunxi-ss-cipher-3des.c > create mode 100644 drivers/crypto/sunxi-ss/sunxi-ss-cipher-aes.c > create mode 100644 drivers/crypto/sunxi-ss/sunxi-ss-cipher-des.c > create mode 100644 drivers/crypto/sunxi-ss/sunxi-ss-cipher.c > create mode 100644 drivers/crypto/sunxi-ss/sunxi-ss-cipher.h > create mode 100644 drivers/crypto/sunxi-ss/sunxi-ss-hash-md5.c > create mode 100644 drivers/crypto/sunxi-ss/sunxi-ss-hash-sha1.c > create mode 100644 drivers/crypto/sunxi-ss/sunxi-ss-hash.c > create mode 100644 drivers/crypto/sunxi-ss/sunxi-ss-hash.h > create mode 100644 drivers/crypto/sunxi-ss/sunxi-ss-rng.c > create mode 100644 drivers/crypto/sunxi-ss/sunxi-ss.c > create mode 100644 drivers/crypto/sunxi-ss/sunxi-ss.h > > diff --git a/drivers/crypto/sunxi-ss/Makefile > b/drivers/crypto/sunxi-ss/Makefile > new file mode 100644 > index 000..de4556b > --- /dev/null > +++ b/drivers/crypto/sunxi-ss/Makefile > @@ -0,0 +1,16 @@ > +obj-$(CONFIG_CRYPTO_DEV_SUNXI_SS) += sunxi-ss.o > + > +obj-$(CONFIG_CRYPTO_DEV_SUNXI_SS_PRNG) += sunxi-ss-rng.o > + > +obj-$(CONFIG_CRYPTO_DEV_SUNXI_SS_DES) += sunxi-ss-des.o > +sunxi-ss-des-y += sunxi-ss-cipher-des.o sunxi-ss-cipher.o > +obj-$(CONFIG_CRYPTO_DEV_SUNXI_SS_3DES) += sunxi-ss-3des.o > +sunxi-ss-3des-y += sunxi-ss-cipher-3des.o sunxi-ss-cipher.o > + > +obj-$(CONFIG_CRYPTO_DEV_SUNXI_SS_AES) += sunxi-ss-aes.o > +sunxi-ss-aes-y += sunxi-ss-cipher-aes.o sunxi-ss-cipher.o I just tried building Hans' (CC-ed) sunxi-devel branch, which includes this series, with all the Security System options enabled. It doesn't build: LD drivers/crypto/sunxi-ss/built-in.o drivers/crypto/sunxi-ss/sunxi-ss-3des.o: In function `sunxi_cipher_init': /home/wens/sunxi/linux/drivers/crypto/sunxi-ss/sunxi-ss-cipher.c:24: multiple definition of `sunxi_cipher_init' drivers/crypto/sunxi-ss/sunxi-ss-des.o:/home/wens/sunxi/linux/drivers/crypto/sunxi-ss/sunxi-ss-cipher.c:24: first defined here drivers/crypto/sunxi-ss/sunxi-ss-3des.o: In function `sunxi_des_poll': /home/wens/sunxi/linux/drivers/crypto/sunxi-ss/sunxi-ss-cipher.c:218: multiple definition of `sunxi_des_poll' drivers/crypto/sunxi-ss/sunxi-ss-des.o:/home/wens/sunxi/linux/drivers/crypto/sunxi-ss/sunxi-ss-cipher.c:218: first defined here drivers/crypto/sunxi-ss/sunxi-ss-3des.o: In function `sunxi_aes_poll': /home/wens/sunxi/linux/drivers/crypto/sunxi-ss/sunxi-ss-cipher.c:33: multiple definition of `sunxi_aes_poll' drivers/crypto/sunxi-ss/sunxi-ss-des.o:/home/wens/sunxi/linux/drivers/crypto/sunxi-ss/sunxi-ss-cipher.c:33: first defined here drivers/crypto/sunxi-ss/sunxi-ss-3des.o: In function `sunxi_cipher_exit': /home/wens/sunxi/linux/drivers/crypto/sunxi-ss/sunxi-ss-cipher.c:29: multiple definition of `sunxi_cipher_exit' drivers/crypto/sunxi-ss/sunxi-ss-des.o:/home/wens/sunxi/linux/drivers/crypto/sunxi-ss/sunxi-ss-cipher.c:29: first defined here drivers/crypto/sunxi-ss/sunxi-ss-aes.o: In function `sunxi_cipher_init': /home/wens/sunxi/linux/drivers/crypto/sunxi-ss/sunxi-ss-cipher.c:24: multiple definition of `sunxi_cipher_init' drivers/crypto/sunxi-ss/sunxi-ss-des.o:/home/wens/sunxi/linux/drivers/crypto/sunxi-ss/sunxi-ss-cipher.c:24: first defined here drivers/crypto/sunxi-ss/sunxi-ss-aes.o: In function `sunxi_des_poll': /home/wens/sunxi/linux/drivers/crypto/sunxi-ss/sunxi-ss-cipher.c:218: multiple definition of `sunxi_des_poll' drivers/crypto/sunxi-ss/sunxi-ss-des.o:/home/wens/sunxi/linux/drivers/crypto/sunxi-ss/sunxi-ss-cipher.c:218: first defined here drivers/crypto/sunxi-ss/sunxi-ss-aes.o: In function `sunxi_aes_poll': /home/wens/sunxi/linux/drivers/crypto/sunxi-ss/sunxi-ss-cipher.c:33: multiple definition of `sunxi_aes_poll' drivers/crypto/sunxi-ss/sunxi-ss-des.o:/home/wens/sunxi/linu
