[PATCH V2] staging: ccree: - style fix, spaces and tabs
Changed code indent to be tabs across whole driver
Found using checkpatch
Signed-off-by: Derek Robson
V1 had vague subject.
---
drivers/staging/ccree/ssi_cipher.c | 45 +-
drivers/staging/ccree/ssi_driver.c | 6 ++---
drivers/staging/ccree/ssi_driver.h | 6 ++---
drivers/staging/ccree/ssi_fips.h | 8 +++---
drivers/staging/ccree/ssi_fips_ext.c | 4 +--
drivers/staging/ccree/ssi_fips_ll.c| 40 +++---
drivers/staging/ccree/ssi_fips_local.c | 28 ++---
drivers/staging/ccree/ssi_fips_local.h | 12 -
8 files changed, 75 insertions(+), 74 deletions(-)
diff --git a/drivers/staging/ccree/ssi_cipher.c
b/drivers/staging/ccree/ssi_cipher.c
index 2dfc6a3bd4c1..34450a5e6573 100644
--- a/drivers/staging/ccree/ssi_cipher.c
+++ b/drivers/staging/ccree/ssi_cipher.c
@@ -258,45 +258,45 @@ static void ssi_blkcipher_exit(struct crypto_tfm *tfm)
typedef struct tdes_keys{
-u8 key1[DES_KEY_SIZE];
-u8 key2[DES_KEY_SIZE];
-u8 key3[DES_KEY_SIZE];
+ u8 key1[DES_KEY_SIZE];
+ u8 key2[DES_KEY_SIZE];
+ u8 key3[DES_KEY_SIZE];
}tdes_keys_t;
-static const u8 zero_buff[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
- 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
- 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
- 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+static const u8 zero_buff[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
/* The function verifies that tdes keys are not weak.*/
static int ssi_fips_verify_3des_keys(const u8 *key, unsigned int keylen)
{
#ifdef CCREE_FIPS_SUPPORT
-tdes_keys_t *tdes_key = (tdes_keys_t*)key;
+ tdes_keys_t *tdes_key = (tdes_keys_t*)key;
/* verify key1 != key2 and key3 != key2*/
-if (unlikely( (memcmp((u8*)tdes_key->key1, (u8*)tdes_key->key2,
sizeof(tdes_key->key1)) == 0) ||
+ if (unlikely( (memcmp((u8*)tdes_key->key1, (u8*)tdes_key->key2,
sizeof(tdes_key->key1)) == 0) ||
(memcmp((u8*)tdes_key->key3, (u8*)tdes_key->key2,
sizeof(tdes_key->key3)) == 0) )) {
-return -ENOEXEC;
-}
+ return -ENOEXEC;
+ }
#endif /* CCREE_FIPS_SUPPORT */
-return 0;
+ return 0;
}
/* The function verifies that xts keys are not weak.*/
static int ssi_fips_verify_xts_keys(const u8 *key, unsigned int keylen)
{
#ifdef CCREE_FIPS_SUPPORT
-/* Weak key is define as key that its first half (128/256 lsb) equals
its second half (128/256 msb) */
-int singleKeySize = keylen >> 1;
+ /* Weak key is define as key that its first half (128/256 lsb) equals
its second half (128/256 msb) */
+ int singleKeySize = keylen >> 1;
if (unlikely(memcmp(key, &key[singleKeySize], singleKeySize) == 0)) {
return -ENOEXEC;
}
#endif /* CCREE_FIPS_SUPPORT */
-return 0;
+ return 0;
}
static enum cc_hw_crypto_key hw_key_to_cc_hw_key(int slot_num)
@@ -720,12 +720,13 @@ ssi_blkcipher_create_data_desc(
}
static int ssi_blkcipher_complete(struct device *dev,
- struct ssi_ablkcipher_ctx *ctx_p,
- struct blkcipher_req_ctx *req_ctx,
- struct scatterlist *dst, struct scatterlist
*src,
- unsigned int ivsize,
- void *areq,
- void __iomem *cc_base)
+ struct ssi_ablkcipher_ctx *ctx_p,
+ struct blkcipher_req_ctx *req_ctx,
+ struct scatterlist *dst,
+ struct scatterlist *src,
+ unsigned int ivsize,
+ void *areq,
+ void __iomem *cc_base)
{
int completion_error = 0;
u32 inflight_counter;
@@ -779,7 +780,7 @@ static int ssi_blkcipher_process(
/* No data to process is valid */
return 0;
}
-/*For CTS in case of data size aligned to 16 use CBC mode*/
+ /*For CTS in case of data size aligned to 16 use CBC mode*/
if (((nbytes % AES_BLOCK_SIZE) == 0) && (ctx_p->cipher_mode ==
DRV_CIPHER_CBC_CTS)){
ctx_p->cipher_mode = DRV_CIPHER_CBC;
diff --git a/drivers/staging/ccree/ssi_driver.c
b/drivers/staging/ccree/ssi_driver.c
index 190922970bf0..b9d0dd27e853 100644
--- a/drivers/staging/ccree/ssi_driver.c
+++ b/drivers/staging/ccree/ssi_driver.c
@@
[PATCH] Drivers: ccree - style fix
Align block comments
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/cc_hw_queue_defs.h | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/staging/ccree/cc_hw_queue_defs.h
b/drivers/staging/ccree/cc_hw_queue_defs.h
index aaa56c85bda2..0e6416ed9a58 100644
--- a/drivers/staging/ccree/cc_hw_queue_defs.h
+++ b/drivers/staging/ccree/cc_hw_queue_defs.h
@@ -23,8 +23,8 @@
#include
/**
-* DEFINITIONS
-**/
+ * DEFINITIONS
+
**/
#define HW_DESC_SIZE_WORDS 6
#define HW_QUEUE_SLOTS_MAX 15 /* Max. available slots in HW queue
*/
@@ -70,8 +70,8 @@
#define WORD5_DOUT_ADDR_HIGH CC_GENMASK(5, DOUT_ADDR_HIGH)
/**
-* TYPE DEFINITIONS
-**/
+ * TYPE DEFINITIONS
+
**/
struct cc_hw_desc {
union {
--
2.13.0
[PATCH] Drivers: ccree - style fix, spaces and tabs
Changed code indent to be tabs across whole driver
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/ssi_cipher.c | 45 +-
drivers/staging/ccree/ssi_driver.c | 6 ++---
drivers/staging/ccree/ssi_driver.h | 6 ++---
drivers/staging/ccree/ssi_fips.h | 8 +++---
drivers/staging/ccree/ssi_fips_ext.c | 4 +--
drivers/staging/ccree/ssi_fips_ll.c| 40 +++---
drivers/staging/ccree/ssi_fips_local.c | 28 ++---
drivers/staging/ccree/ssi_fips_local.h | 12 -
8 files changed, 75 insertions(+), 74 deletions(-)
diff --git a/drivers/staging/ccree/ssi_cipher.c
b/drivers/staging/ccree/ssi_cipher.c
index 2dfc6a3bd4c1..34450a5e6573 100644
--- a/drivers/staging/ccree/ssi_cipher.c
+++ b/drivers/staging/ccree/ssi_cipher.c
@@ -258,45 +258,45 @@ static void ssi_blkcipher_exit(struct crypto_tfm *tfm)
typedef struct tdes_keys{
-u8 key1[DES_KEY_SIZE];
-u8 key2[DES_KEY_SIZE];
-u8 key3[DES_KEY_SIZE];
+ u8 key1[DES_KEY_SIZE];
+ u8 key2[DES_KEY_SIZE];
+ u8 key3[DES_KEY_SIZE];
}tdes_keys_t;
-static const u8 zero_buff[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
- 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
- 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
- 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
+static const u8 zero_buff[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
/* The function verifies that tdes keys are not weak.*/
static int ssi_fips_verify_3des_keys(const u8 *key, unsigned int keylen)
{
#ifdef CCREE_FIPS_SUPPORT
-tdes_keys_t *tdes_key = (tdes_keys_t*)key;
+ tdes_keys_t *tdes_key = (tdes_keys_t*)key;
/* verify key1 != key2 and key3 != key2*/
-if (unlikely( (memcmp((u8*)tdes_key->key1, (u8*)tdes_key->key2,
sizeof(tdes_key->key1)) == 0) ||
+ if (unlikely( (memcmp((u8*)tdes_key->key1, (u8*)tdes_key->key2,
sizeof(tdes_key->key1)) == 0) ||
(memcmp((u8*)tdes_key->key3, (u8*)tdes_key->key2,
sizeof(tdes_key->key3)) == 0) )) {
-return -ENOEXEC;
-}
+ return -ENOEXEC;
+ }
#endif /* CCREE_FIPS_SUPPORT */
-return 0;
+ return 0;
}
/* The function verifies that xts keys are not weak.*/
static int ssi_fips_verify_xts_keys(const u8 *key, unsigned int keylen)
{
#ifdef CCREE_FIPS_SUPPORT
-/* Weak key is define as key that its first half (128/256 lsb) equals
its second half (128/256 msb) */
-int singleKeySize = keylen >> 1;
+ /* Weak key is define as key that its first half (128/256 lsb) equals
its second half (128/256 msb) */
+ int singleKeySize = keylen >> 1;
if (unlikely(memcmp(key, &key[singleKeySize], singleKeySize) == 0)) {
return -ENOEXEC;
}
#endif /* CCREE_FIPS_SUPPORT */
-return 0;
+ return 0;
}
static enum cc_hw_crypto_key hw_key_to_cc_hw_key(int slot_num)
@@ -720,12 +720,13 @@ ssi_blkcipher_create_data_desc(
}
static int ssi_blkcipher_complete(struct device *dev,
- struct ssi_ablkcipher_ctx *ctx_p,
- struct blkcipher_req_ctx *req_ctx,
- struct scatterlist *dst, struct scatterlist
*src,
- unsigned int ivsize,
- void *areq,
- void __iomem *cc_base)
+ struct ssi_ablkcipher_ctx *ctx_p,
+ struct blkcipher_req_ctx *req_ctx,
+ struct scatterlist *dst,
+ struct scatterlist *src,
+ unsigned int ivsize,
+ void *areq,
+ void __iomem *cc_base)
{
int completion_error = 0;
u32 inflight_counter;
@@ -779,7 +780,7 @@ static int ssi_blkcipher_process(
/* No data to process is valid */
return 0;
}
-/*For CTS in case of data size aligned to 16 use CBC mode*/
+ /*For CTS in case of data size aligned to 16 use CBC mode*/
if (((nbytes % AES_BLOCK_SIZE) == 0) && (ctx_p->cipher_mode ==
DRV_CIPHER_CBC_CTS)){
ctx_p->cipher_mode = DRV_CIPHER_CBC;
diff --git a/drivers/staging/ccree/ssi_driver.c
b/drivers/staging/ccree/ssi_driver.c
index 190922970bf0..b9d0dd27e853 100644
--- a/drivers/staging/ccree/ssi_driver.c
+++ b/drivers/staging/ccree/ssi_driver.c
@@ -437,9 +437,9 @
[PATCH V2 23/27] Drivers: ccree: ssi_aead.c - align block comments
Fixed block comment alignment, Style fix only
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/ssi_aead.c | 45 ++--
1 file changed, 29 insertions(+), 16 deletions(-)
diff --git a/drivers/staging/ccree/ssi_aead.c b/drivers/staging/ccree/ssi_aead.c
index 26afa8794668..ecf9ff2ae336 100644
--- a/drivers/staging/ccree/ssi_aead.c
+++ b/drivers/staging/ccree/ssi_aead.c
@@ -250,7 +250,8 @@ static void ssi_aead_complete(struct device *dev, void
*ssi_req, void __iomem *c
"(auth-size=%d, cipher=%d).\n",
ctx->authsize, ctx->cipher_mode);
/* In case of payload authentication failure, MUST NOT
- revealed the decrypted message --> zero its memory.
*/
+* revealed the decrypted message --> zero its memory.
+*/
ssi_buffer_mgr_zero_sgl(areq->dst, areq_ctx->cryptlen);
err = -EBADMSG;
}
@@ -279,7 +280,8 @@ static int xcbc_setkey(struct cc_hw_desc *desc, struct
ssi_aead_ctx *ctx)
/* Load the AES key */
HW_DESC_INIT(&desc[0]);
/* We are using for the source/user key the same buffer as for the
output keys,
- because after this key loading it is not needed anymore */
+* because after this key loading it is not needed anymore
+*/
HW_DESC_SET_DIN_TYPE(&desc[0], DMA_DLLI,
ctx->auth_state.xcbc.xcbc_keys_dma_addr, ctx->auth_keylen, NS_BIT);
HW_DESC_SET_CIPHER_MODE(&desc[0], DRV_CIPHER_ECB);
HW_DESC_SET_CIPHER_CONFIG0(&desc[0], DRV_CRYPTO_DIRECTION_ENCRYPT);
@@ -420,8 +422,9 @@ static int validate_keys_sizes(struct ssi_aead_ctx *ctx)
return 0; /* All tests of keys sizes passed */
}
-/*This function prepers the user key so it can pass to the hmac processing
- (copy to intenral buffer or hash in case of key longer than block */
+/* This function prepers the user key so it can pass to the hmac processing
+ * (copy to intenral buffer or hash in case of key longer than block
+ */
static int
ssi_get_plain_hmac_key(struct crypto_aead *tfm, const u8 *key, unsigned int
keylen)
{
@@ -600,7 +603,8 @@ ssi_aead_setkey(struct crypto_aead *tfm, const u8 *key,
unsigned int keylen)
(AES_MIN_KEY_SIZE + CTR_RFC3686_NONCE_SIZE))
goto badkey;
/* Copy nonce from last 4 bytes in CTR key to
- * first 4 bytes in CTR IV */
+* first 4 bytes in CTR IV
+*/
memcpy(ctx->ctr_nonce, key + ctx->auth_keylen +
ctx->enc_keylen -
CTR_RFC3686_NONCE_SIZE, CTR_RFC3686_NONCE_SIZE);
/* Set CTR key size */
@@ -829,7 +833,8 @@ ssi_aead_process_authenc_data_desc(
{
/* DOUBLE-PASS flow (as default)
* assoc. + iv + data -compact in one table
-* if assoclen is ZERO only IV perform */
+* if assoclen is ZERO only IV perform
+*/
ssi_sram_addr_t mlli_addr = areq_ctx->assoc.sram_addr;
u32 mlli_nents = areq_ctx->assoc.mlli_nents;
@@ -1287,7 +1292,8 @@ static inline void ssi_aead_hmac_authenc(
/**
* Double-pass flow
* Fallback for unsupported single-pass modes,
-* i.e. using assoc. data of non-word-multiple */
+* i.e. using assoc. data of non-word-multiple
+*/
if (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) {
/* encrypt first.. */
ssi_aead_process_cipher(req, desc, seq_size, data_flow_mode);
@@ -1305,7 +1311,8 @@ static inline void ssi_aead_hmac_authenc(
/* decrypt after.. */
ssi_aead_process_cipher(req, desc, seq_size, data_flow_mode);
/* read the digest result with setting the completion bit
- must be after the cipher operation */
+* must be after the cipher operation
+*/
ssi_aead_process_digest_result_desc(req, desc, seq_size);
}
}
@@ -1338,7 +1345,8 @@ ssi_aead_xcbc_authenc(
/**
* Double-pass flow
* Fallback for unsupported single-pass modes,
-* i.e. using assoc. data of non-word-multiple */
+* i.e. using assoc. data of non-word-multiple
+*/
if (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) {
/* encrypt first.. */
ssi_aead_process_cipher(req, desc, seq_size, data_flow_mode);
@@ -1353,7 +1361,8 @@ ssi_aead_xcbc_authenc(
/* decrypt after..*/
ssi_aead_process_cipher(req, desc, seq_size, data_flow_mode);
/* read the digest result with setting the com
[PATCH V2 27/27] Drivers: ccree: cc_crypto_ctx.h - align block comments
Fixed block comment alignment, Style fix only
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/cc_crypto_ctx.h | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/staging/ccree/cc_crypto_ctx.h
b/drivers/staging/ccree/cc_crypto_ctx.h
index ac39d349060d..191f92f0ef22 100644
--- a/drivers/staging/ccree/cc_crypto_ctx.h
+++ b/drivers/staging/ccree/cc_crypto_ctx.h
@@ -219,7 +219,8 @@ struct drv_ctx_hash {
};
/* drv_ctx_hmac should have the same structure as drv_ctx_hash except
- k0, k0_size fields */
+ * k0, k0_size fields
+ */
struct drv_ctx_hmac {
enum drv_crypto_alg alg; /* DRV_CRYPTO_ALG_HMAC */
enum drv_hash_mode mode;
@@ -240,9 +241,10 @@ struct drv_ctx_cipher {
u32 key_size; /* numeric value in bytes */
u32 data_unit_size; /* required for XTS */
/* block_state is the AES engine block state.
- * It is used by the host to pass IV or counter at initialization.
- * It is used by SeP for intermediate block chaining state and for
- * returning MAC algorithms results. */
+* It is used by the host to pass IV or counter at initialization.
+* It is used by SeP for intermediate block chaining state and for
+* returning MAC algorithms results.
+ */
u8 block_state[CC_AES_BLOCK_SIZE];
u8 key[CC_AES_KEY_SIZE_MAX];
u8 xex_key[CC_AES_KEY_SIZE_MAX];
@@ -279,9 +281,10 @@ struct drv_ctx_aead {
/* Get the address of a @member within a given @ctx address
- @ctx: The context address
- @type: Type of context structure
- @member: Associated context field */
+ * @ctx: The context address
+ * @type: Type of context structure
+ * @member: Associated context field
+ */
#define GET_CTX_FIELD_ADDR(ctx, type, member) (ctx + offsetof(type, member))
#endif /* _CC_CRYPTO_CTX_H_ */
--
2.13.0
[PATCH V2 26/27] Drivers: ccree: cc_hw_queue_defs.h - align block comments
Fixed block comment alignment, Style fix only
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/cc_hw_queue_defs.h | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/staging/ccree/cc_hw_queue_defs.h
b/drivers/staging/ccree/cc_hw_queue_defs.h
index 71381760566d..bb64fddc371d 100644
--- a/drivers/staging/ccree/cc_hw_queue_defs.h
+++ b/drivers/staging/ccree/cc_hw_queue_defs.h
@@ -23,8 +23,8 @@
#include "dx_crys_kernel.h"
/**
-* DEFINITIONS
-**/
+ * DEFINITIONS
+
**/
/* Dma AXI Secure bit */
#defineAXI_SECURE 0
@@ -36,8 +36,8 @@
#define _HW_DESC_MONITOR_KICK 0x7FFFC00
/**
-* TYPE DEFINITIONS
-**/
+ * TYPE DEFINITIONS
+
**/
struct cc_hw_desc {
u32 word[HW_DESC_SIZE_WORDS];
@@ -400,7 +400,7 @@ enum cc_hw_des_key_size {
*
* \param pDesc pointer HW descriptor struct
* \param numRounds number of rounds for Multi2
-*/
+ */
#define HW_DESC_SET_MULTI2_NUM_ROUNDS(pDesc, numRounds)
\
do {
\
CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE,
(pDesc)->word[2], (u32)(numRounds)); \
@@ -411,7 +411,7 @@ enum cc_hw_des_key_size {
*
* \param pDesc pointer HW descriptor struct
* \param flowMode Any one of the modes defined in [CC7x-DESC]
-*/
+ */
#define HW_DESC_SET_FLOW_MODE(pDesc, flowMode)
\
do {
\
@@ -423,7 +423,7 @@ enum cc_hw_des_key_size {
*
* \param pDesc pointer HW descriptor struct
* \param cipherMode Any one of the modes defined in [CC7x-DESC]
-*/
+ */
#define HW_DESC_SET_CIPHER_MODE(pDesc, cipherMode)
\
do {
\
CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_MODE,
(pDesc)->word[4], (cipherMode)); \
@@ -434,7 +434,7 @@ enum cc_hw_des_key_size {
*
* \param pDesc pointer HW descriptor struct
* \param cipherConfig Any one of the modes defined in [CC7x-DESC]
-*/
+ */
#define HW_DESC_SET_CIPHER_CONFIG0(pDesc, cipherConfig)
\
do {
\
CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_CONF0,
(pDesc)->word[4], (cipherConfig));\
@@ -445,7 +445,7 @@ enum cc_hw_des_key_size {
*
* \param pDesc pointer HW descriptor struct
* \param cipherConfig Any one of the modes defined in [CC7x-DESC]
-*/
+ */
#define HW_DESC_SET_CIPHER_CONFIG1(pDesc, cipherConfig)
\
do {
\
CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_CONF1,
(pDesc)->word[4], (cipherConfig));\
@@ -456,7 +456,7 @@ enum cc_hw_des_key_size {
*
* \param pDesc pointer HW descriptor struct
* \param hwKey The hw key number as in enun HwCryptoKey
-*/
+ */
#define HW_DESC_SET_HW_CRYPTO_KEY(pDesc, hwKey)
\
do {
\
CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_DO,
(pDesc)->word[4], (hwKey) & HW_KEY_MASK_CIPHER_DO); \
@@ -468,7 +468,7 @@ enum cc_hw_des_key_size {
*
* \param pDesc pointer HW descriptor struct
* \param swapConfig Any one of the modes defined in [CC7x-DESC]
-*/
+ */
#define HW_DESC_SET_BYTES_SWAP(pDesc, swapConfig)
\
do {
\
CC_REG_FLD_SET(CR
[PATCH V2 24/27] Drivers: ccree: hash_defs.h - align block comments
Fixed block comment alignment, Style fix only
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/hash_defs.h | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/staging/ccree/hash_defs.h
b/drivers/staging/ccree/hash_defs.h
index 613897038f6d..3f2b2d1521c2 100644
--- a/drivers/staging/ccree/hash_defs.h
+++ b/drivers/staging/ccree/hash_defs.h
@@ -59,13 +59,14 @@ enum HashCipherDoPadding {
typedef struct SepHashPrivateContext {
/* The current length is placed at the end of the context buffer
because the hash
- context is used for all HMAC operations as well. HMAC context
includes a 64 bytes
- K0 field. The size of struct drv_ctx_hash reserved field is 88/184
bytes depend if t
- he SHA512 is supported ( in this case teh context size is 256 bytes).
- The size of struct drv_ctx_hash reseved field is 20 or 52 depend if
the SHA512 is supported.
- This means that this structure size (without the reserved field can
be up to 20 bytes ,
- in case sha512 is not suppported it is 20 bytes
(SEP_HASH_LENGTH_WORDS define to 2 ) and in the other
- case it is 28 (SEP_HASH_LENGTH_WORDS define to 4) */
+* context is used for all HMAC operations as well. HMAC context
includes a 64 bytes
+* K0 field. The size of struct drv_ctx_hash reserved field is
88/184 bytes depend if t
+* he SHA512 is supported ( in this case teh context size is 256
bytes).
+* The size of struct drv_ctx_hash reseved field is 20 or 52 depend if
the SHA512 is supported.
+* This means that this structure size (without the reserved field can
be up to 20 bytes ,
+* in case sha512 is not suppported it is 20 bytes
(SEP_HASH_LENGTH_WORDS define to 2 ) and in the other
+* case it is 28 (SEP_HASH_LENGTH_WORDS define to 4)
+*/
u32 reserved[(sizeof(struct drv_ctx_hash)/sizeof(u32)) -
SEP_HASH_LENGTH_WORDS - 3];
u32 CurrentDigestedLength[SEP_HASH_LENGTH_WORDS];
u32 KeyType;
--
2.13.0
[PATCH V2 25/27] Drivers: ccree: cc_regs.h - align block comments
Fixed block comment alignment, Style fix only
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/cc_regs.h | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/staging/ccree/cc_regs.h b/drivers/staging/ccree/cc_regs.h
index 8b89f0603f16..51b01609838e 100644
--- a/drivers/staging/ccree/cc_regs.h
+++ b/drivers/staging/ccree/cc_regs.h
@@ -55,8 +55,9 @@ do {
\
BITFIELD_GET(reg_val, CC_ ## reg_name ## _ ## fld_name ## _BIT_SHIFT, \
CC_ ## reg_name ## _ ## fld_name ## _BIT_SIZE))
-/* yael TBD !!! -*
-* all HW includes should start with CC_ and not DX_ !! */
+/* yael TBD !!!
+ * all HW includes should start with CC_ and not DX_ !!
+ */
/*! Bit fields set */
@@ -86,10 +87,10 @@ do {
\
} while (0)
/* Usage example:
- u32 reg_shadow = READ_REGISTER(CC_REG_ADDR(CRY_KERNEL,AES_CONTROL));
- CC_REG_FLD_SET(CRY_KERNEL,AES_CONTROL,NK_KEY0,reg_shadow, 3);
- CC_REG_FLD_SET(CRY_KERNEL,AES_CONTROL,NK_KEY1,reg_shadow, 1);
- WRITE_REGISTER(CC_REG_ADDR(CRY_KERNEL,AES_CONTROL), reg_shadow);
+ * u32 reg_shadow = READ_REGISTER(CC_REG_ADDR(CRY_KERNEL,AES_CONTROL));
+ * CC_REG_FLD_SET(CRY_KERNEL,AES_CONTROL,NK_KEY0,reg_shadow, 3);
+ * CC_REG_FLD_SET(CRY_KERNEL,AES_CONTROL,NK_KEY1,reg_shadow, 1);
+ * WRITE_REGISTER(CC_REG_ADDR(CRY_KERNEL,AES_CONTROL), reg_shadow);
*/
#endif /*_CC_REGS_H_*/
--
2.13.0
[PATCH V2 21/27] Drivers: ccree: ssi_buffer_mgr.c - align block comments
Fixed block comment alignment, Style fix only
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/ssi_buffer_mgr.c | 87 +++---
1 file changed, 49 insertions(+), 38 deletions(-)
diff --git a/drivers/staging/ccree/ssi_buffer_mgr.c
b/drivers/staging/ccree/ssi_buffer_mgr.c
index 04515e70d2d3..edb88441e90d 100644
--- a/drivers/staging/ccree/ssi_buffer_mgr.c
+++ b/drivers/staging/ccree/ssi_buffer_mgr.c
@@ -330,7 +330,8 @@ static int ssi_buffer_mgr_generate_mlli(
/* set last bit in the current table */
if (sg_data->mlli_nents[i] != NULL) {
/*Calculate the current MLLI table length for the
- length field in the descriptor*/
+*length field in the descriptor
+*/
*(sg_data->mlli_nents[i]) +=
(total_nents - prev_total_nents);
prev_total_nents = total_nents;
@@ -463,7 +464,8 @@ static int ssi_buffer_mgr_map_scatterlist(
}
if (!is_chained) {
/* In case of mmu the number of mapped nents might
- be changed from the original sgl nents */
+* be changed from the original sgl nents
+*/
*mapped_nents = dma_map_sg(dev, sg, *nents, direction);
if (unlikely(*mapped_nents == 0)){
*nents = 0;
@@ -472,7 +474,8 @@ static int ssi_buffer_mgr_map_scatterlist(
}
} else {
/*In this case the driver maps entry by entry so it
- must have the same nents before and after map */
+* must have the same nents before and after map
+*/
*mapped_nents = ssi_buffer_mgr_dma_map_sg(dev,
sg,
*nents,
@@ -764,7 +767,8 @@ void ssi_buffer_mgr_unmap_aead_request(
}
/*In case a pool was set, a table was
- allocated and should be released */
+*allocated and should be released
+*/
if (areq_ctx->mlli_params.curr_pool != NULL) {
SSI_LOG_DEBUG("free MLLI buffer: dma=0x%08llX virt=%pK\n",
(unsigned long long)areq_ctx->mlli_params.mlli_dma_addr,
@@ -801,7 +805,8 @@ void ssi_buffer_mgr_unmap_aead_request(
size_to_skip += crypto_aead_ivsize(tfm);
}
/* copy mac to a temporary location to deal with possible
- data memory overriding that caused by cache coherence
problem. */
+* data memory overriding that caused by cache coherence
problem.
+*/
ssi_buffer_mgr_copy_scatterlist_portion(
areq_ctx->backup_mac, req->src,
size_to_skip+ req->cryptlen - areq_ctx->req_authsize,
@@ -965,7 +970,8 @@ static inline int ssi_buffer_mgr_aead_chain_assoc(
areq_ctx->assoc.nents = mapped_nents;
/* in CCM case we have additional entry for
- * ccm header configurations */
+* ccm header configurations
+*/
if (areq_ctx->ccm_hdr_size != ccm_header_size_null) {
if (unlikely((mapped_nents + 1) >
LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES)) {
@@ -1068,13 +1074,15 @@ static inline int ssi_buffer_mgr_prepare_aead_data_mlli(
if (unlikely(areq_ctx->is_icv_fragmented == true)) {
/* Backup happens only when ICV is fragmented, ICV
- verification is made by CPU compare in order to
simplify
- MAC verification upon request completion */
+* verification is made by CPU compare in order to
simplify
+* MAC verification upon request completion
+*/
if (direct == DRV_CRYPTO_DIRECTION_DECRYPT) {
#if !DX_HAS_ACP
/* In ACP platform we already copying ICV
- for any INPLACE-DECRYPT operation, hence
- we must neglect this code. */
+* for any INPLACE-DECRYPT operation, hence
+* we must neglect this code.
+*/
u32 size_to_skip = req->assoclen;
if (areq_ctx->is_gcm4543) {
size_to_skip += crypto_aead_ivsize(tfm);
@@ -1120,8 +1128,9 @@ static inline int ssi_buffer_mgr_prepare_aead_data_mlli(
[PATCH V2 22/27] Drivers: ccree: ssi_aead.h - align block comments
Fixed block comment alignment, Style fix only
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/ssi_aead.h | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/staging/ccree/ssi_aead.h b/drivers/staging/ccree/ssi_aead.h
index 654a181729d7..00a3680cb8ab 100644
--- a/drivers/staging/ccree/ssi_aead.h
+++ b/drivers/staging/ccree/ssi_aead.h
@@ -15,7 +15,7 @@
*/
/* \file ssi_aead.h
- ARM CryptoCell AEAD Crypto API
+ * ARM CryptoCell AEAD Crypto API
*/
#ifndef __SSI_AEAD_H__
@@ -62,8 +62,9 @@ enum aead_ccm_header_size {
struct aead_req_ctx {
/* Allocate cache line although only 4 bytes are needed to
- * assure next field falls @ cache line
- * Used for both: digest HW compare and CCM/GCM MAC value */
+* assure next field falls @ cache line
+* Used for both: digest HW compare and CCM/GCM MAC value
+*/
u8 mac_buf[MAX_MAC_SIZE] cacheline_aligned;
u8 ctr_iv[AES_BLOCK_SIZE] cacheline_aligned;
--
2.13.0
[PATCH V2 19/27] Drivers: ccree: ssi_cipher.h - align block comments
Fixed block comment alignment, Style fix only Found using checkpatch Signed-off-by: Derek Robson --- drivers/staging/ccree/ssi_cipher.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/ccree/ssi_cipher.h b/drivers/staging/ccree/ssi_cipher.h index 7d58b56fc2c7..22d7b431edb9 100644 --- a/drivers/staging/ccree/ssi_cipher.h +++ b/drivers/staging/ccree/ssi_cipher.h @@ -15,7 +15,7 @@ */ /* \file ssi_cipher.h - ARM CryptoCell Cipher Crypto API + * ARM CryptoCell Cipher Crypto API */ #ifndef __SSI_CIPHER_H__ -- 2.13.0
[PATCH V2 20/27] Drivers: ccree: ssi_buffer_mgr.h - align block comments
Fixed block comment alignment, Style fix only Found using checkpatch Signed-off-by: Derek Robson --- drivers/staging/ccree/ssi_buffer_mgr.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/ccree/ssi_buffer_mgr.h b/drivers/staging/ccree/ssi_buffer_mgr.h index 4acbb4b6afc9..98355dd789e5 100644 --- a/drivers/staging/ccree/ssi_buffer_mgr.h +++ b/drivers/staging/ccree/ssi_buffer_mgr.h @@ -15,7 +15,7 @@ */ /* \file buffer_mgr.h - Buffer Manager + * Buffer Manager */ #ifndef __SSI_BUFFER_MGR_H__ -- 2.13.0
[PATCH V2 18/27] Drivers: ccree: ssi_config.h - align block comments
Fixed block comment alignment, Style fix only Found using checkpatch Signed-off-by: Derek Robson --- drivers/staging/ccree/ssi_config.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/staging/ccree/ssi_config.h b/drivers/staging/ccree/ssi_config.h index 431b518d893a..9feb692fff0d 100644 --- a/drivers/staging/ccree/ssi_config.h +++ b/drivers/staging/ccree/ssi_config.h @@ -15,7 +15,7 @@ */ /* \file ssi_config.h - Definitions for ARM CryptoCell Linux Crypto Driver + * Definitions for ARM CryptoCell Linux Crypto Driver */ #ifndef __SSI_CONFIG_H__ @@ -49,7 +49,8 @@ #define SSI_CACHE_PARAMS (0x000) /* CC attached to NONE-ACP such as HPP/ACE/AMBA4. * The customer is responsible to enable/disable this feature -* according to his platform type. */ +* according to his platform type. +*/ #define DX_HAS_ACP 0 #else #define SSI_CACHE_PARAMS (0xEEE) -- 2.13.0
[PATCH V2 17/27] Drivers: ccree: ssi_driver.h - align block comments
Fixed block comment alignment, Style fix only
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/ssi_driver.h | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/staging/ccree/ssi_driver.h
b/drivers/staging/ccree/ssi_driver.h
index 45fc23fe169f..e034b0987137 100644
--- a/drivers/staging/ccree/ssi_driver.h
+++ b/drivers/staging/ccree/ssi_driver.h
@@ -15,7 +15,7 @@
*/
/* \file ssi_driver.h
- ARM CryptoCell Linux Crypto Driver
+ * ARM CryptoCell Linux Crypto Driver
*/
#ifndef __SSI_DRIVER_H__
@@ -86,7 +86,8 @@
#define NS_BIT 1
#define AXI_ID 0
/* AXI_ID is not actually the AXI ID of the transaction but the value of AXI_ID
- field in the HW descriptor. The DMA engine +8 that value. */
+ * field in the HW descriptor. The DMA engine +8 that value.
+ */
/* Logging macros */
#define SSI_LOG(level, format, ...) \
@@ -108,9 +109,11 @@
struct ssi_crypto_req {
void (*user_cb)(struct device *dev, void *req, void __iomem *cc_base);
void *user_arg;
- dma_addr_t ivgen_dma_addr[SSI_MAX_IVGEN_DMA_ADDRESSES]; /* For the
first 'ivgen_dma_addr_len' addresses of this array,
-generated IV would be placed in it by
send_request().
-Same generated IV for all addresses! */
+ dma_addr_t ivgen_dma_addr[SSI_MAX_IVGEN_DMA_ADDRESSES];
+ /* For the first 'ivgen_dma_addr_len' addresses of this array,
+* generated IV would be placed in it by send_request().
+* Same generated IV for all addresses!
+*/
unsigned int ivgen_dma_addr_len; /* Amount of 'ivgen_dma_addr' elements
to be filled. */
unsigned int ivgen_size; /* The generated IV size required, 8/16 B
allowed. */
struct completion seq_compl; /* request completion */
@@ -136,7 +139,8 @@ struct ssi_drvdata {
u32 irq_mask;
u32 fw_ver;
/* Calibration time of start/stop
- * monitor descriptors */
+* monitor descriptors
+*/
u32 monitor_null_cycles;
struct platform_device *plat_dev;
ssi_sram_addr_t mlli_sram_addr;
--
2.13.0
[PATCH V2 16/27] Drivers: ccree: ssi_fips.c - align block comments
Fixed block comment alignment, Style fix only
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/ssi_fips.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/staging/ccree/ssi_fips.c b/drivers/staging/ccree/ssi_fips.c
index 25ee23a1cecf..60a2452f7b0b 100644
--- a/drivers/staging/ccree/ssi_fips.c
+++ b/drivers/staging/ccree/ssi_fips.c
@@ -16,8 +16,8 @@
/**
-This file defines the driver FIPS APIs
*
-***/
+ * This file defines the driver FIPS APIs *
+ **/
#include
#include "ssi_fips.h"
@@ -27,9 +27,9 @@ extern int ssi_fips_ext_get_state(ssi_fips_state_t *p_state);
extern int ssi_fips_ext_get_error(ssi_fips_error_t *p_err);
/*
-This function returns the REE FIPS state.
-It should be called by kernel module.
-*/
+ * This function returns the REE FIPS state.
+ * It should be called by kernel module.
+ */
int ssi_fips_get_state(ssi_fips_state_t *p_state)
{
int rc = 0;
@@ -46,9 +46,9 @@ int ssi_fips_get_state(ssi_fips_state_t *p_state)
EXPORT_SYMBOL(ssi_fips_get_state);
/*
-This function returns the REE FIPS error.
-It should be called by kernel module.
-*/
+ * This function returns the REE FIPS error.
+ * It should be called by kernel module.
+ */
int ssi_fips_get_error(ssi_fips_error_t *p_err)
{
int rc = 0;
--
2.13.0
[PATCH V2 15/27] Drivers: ccree: ssi_fips.h - align block comments
Fixed block comment alignment, Style fix only
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/ssi_fips.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/staging/ccree/ssi_fips.h b/drivers/staging/ccree/ssi_fips.h
index 607c64b8c458..e108d89ef98c 100644
--- a/drivers/staging/ccree/ssi_fips.h
+++ b/drivers/staging/ccree/ssi_fips.h
@@ -18,9 +18,9 @@
#define __SSI_FIPS_H__
/*!
-@file
-@brief This file contains FIPS related defintions and APIs.
-*/
+ * @file
+ * @brief This file contains FIPS related defintions and APIs.
+ */
typedef enum ssi_fips_state {
CC_FIPS_STATE_NOT_SUPPORTED = 0,
--
2.13.0
[PATCH V2 14/27] Drivers: ccree: ssi_fips_data.h - align block comments
Fixed block comment alignment, Style fix only Found using checkpatch Signed-off-by: Derek Robson --- drivers/staging/ccree/ssi_fips_data.h | 93 +-- 1 file changed, 46 insertions(+), 47 deletions(-) diff --git a/drivers/staging/ccree/ssi_fips_data.h b/drivers/staging/ccree/ssi_fips_data.h index a4b78f1b4d48..fa6bf41c27e5 100644 --- a/drivers/staging/ccree/ssi_fips_data.h +++ b/drivers/staging/ccree/ssi_fips_data.h @@ -15,53 +15,52 @@ */ /* -The test vectors were taken from: - -* AES -NIST Special Publication 800-38A 2001 Edition -Recommendation for Block Cipher Modes of Operation -http://csrc.nist.gov/publications/nistpubs/800-38a/sp800-38a.pdf -Appendix F: Example Vectors for Modes of Operation of the AES - -* AES CTS -Advanced Encryption Standard (AES) Encryption for Kerberos 5 -February 2005 -https://tools.ietf.org/html/rfc3962#appendix-B -B. Sample Test Vectors - -* AES XTS -http://csrc.nist.gov/groups/STM/cavp/#08 -http://csrc.nist.gov/groups/STM/cavp/documents/aes/XTSTestVectors.zip - -* AES CMAC -http://csrc.nist.gov/groups/STM/cavp/index.html#07 -http://csrc.nist.gov/groups/STM/cavp/documents/mac/cmactestvectors.zip - -* AES-CCM -http://csrc.nist.gov/groups/STM/cavp/#07 -http://csrc.nist.gov/groups/STM/cavp/documents/mac/ccmtestvectors.zip - -* AES-GCM -http://csrc.nist.gov/groups/STM/cavp/documents/mac/gcmtestvectors.zip - -* Triple-DES -NIST Special Publication 800-67 January 2012 -Recommendation for the Triple Data Encryption Algorithm (TDEA) Block Cipher -http://csrc.nist.gov/publications/nistpubs/800-67-Rev1/SP-800-67-Rev1.pdf -APPENDIX B: EXAMPLE OF TDEA FORWARD AND INVERSE CIPHER OPERATIONS -and -http://csrc.nist.gov/groups/STM/cavp/#01 -http://csrc.nist.gov/groups/STM/cavp/documents/des/tdesmct_intermediate.zip - -* HASH -http://csrc.nist.gov/groups/STM/cavp/#03 -http://csrc.nist.gov/groups/STM/cavp/documents/shs/shabytetestvectors.zip - -* HMAC -http://csrc.nist.gov/groups/STM/cavp/#07 -http://csrc.nist.gov/groups/STM/cavp/documents/mac/hmactestvectors.zip - -*/ + * The test vectors were taken from: + * + * * AES + * NIST Special Publication 800-38A 2001 Edition + * Recommendation for Block Cipher Modes of Operation + * http://csrc.nist.gov/publications/nistpubs/800-38a/sp800-38a.pdf + * Appendix F: Example Vectors for Modes of Operation of the AES + * + * * AES CTS + * Advanced Encryption Standard (AES) Encryption for Kerberos 5 + * February 2005 + * https://tools.ietf.org/html/rfc3962#appendix-B + * B. Sample Test Vectors + * + * * AES XTS + * http://csrc.nist.gov/groups/STM/cavp/#08 + * http://csrc.nist.gov/groups/STM/cavp/documents/aes/XTSTestVectors.zip + * + * * AES CMAC + * http://csrc.nist.gov/groups/STM/cavp/index.html#07 + * http://csrc.nist.gov/groups/STM/cavp/documents/mac/cmactestvectors.zip + * + * * AES-CCM + * http://csrc.nist.gov/groups/STM/cavp/#07 + * http://csrc.nist.gov/groups/STM/cavp/documents/mac/ccmtestvectors.zip + * + * * AES-GCM + * http://csrc.nist.gov/groups/STM/cavp/documents/mac/gcmtestvectors.zip + * + * * Triple-DES + * NIST Special Publication 800-67 January 2012 + * Recommendation for the Triple Data Encryption Algorithm (TDEA) Block Cipher + * http://csrc.nist.gov/publications/nistpubs/800-67-Rev1/SP-800-67-Rev1.pdf + * APPENDIX B: EXAMPLE OF TDEA FORWARD AND INVERSE CIPHER OPERATIONS + * and + * http://csrc.nist.gov/groups/STM/cavp/#01 + * http://csrc.nist.gov/groups/STM/cavp/documents/des/tdesmct_intermediate.zip + * + * * HASH + * http://csrc.nist.gov/groups/STM/cavp/#03 + * http://csrc.nist.gov/groups/STM/cavp/documents/shs/shabytetestvectors.zip + * + * * HMAC + * http://csrc.nist.gov/groups/STM/cavp/#07 + * http://csrc.nist.gov/groups/STM/cavp/documents/mac/hmactestvectors.zip + */ /* NIST AES */ #define AES_128_BIT_KEY_SIZE16 -- 2.13.0
[PATCH V2 13/27] Drivers: ccree: ssi_fips_ext.c - align block comments
Fixed block comment alignment, Style fix only
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/ssi_fips_ext.c | 46 ++--
1 file changed, 23 insertions(+), 23 deletions(-)
diff --git a/drivers/staging/ccree/ssi_fips_ext.c
b/drivers/staging/ccree/ssi_fips_ext.c
index 291a880f567c..0f53a4bc43de 100644
--- a/drivers/staging/ccree/ssi_fips_ext.c
+++ b/drivers/staging/ccree/ssi_fips_ext.c
@@ -15,9 +15,9 @@
*/
/**
-This file defines the driver FIPS functions that should be
-implemented by the driver user. Current implementation is sample code only.
-***/
+ * This file defines the driver FIPS functions that should be
+ * implemented by the driver user. Current implementation is sample code only.
+ ***/
#include
#include "ssi_fips_local.h"
@@ -32,11 +32,11 @@ static ssi_fips_state_t fips_state =
CC_FIPS_STATE_NOT_SUPPORTED;
static ssi_fips_error_t fips_error = CC_REE_FIPS_ERROR_OK;
/*
-This function returns the FIPS REE state.
-The function should be implemented by the driver user, depends on where
.
-the state value is stored.
-The reference code uses global variable.
-*/
+ * This function returns the FIPS REE state.
+ * The function should be implemented by the driver user, depends on where
+ * the state value is stored.
+ * The reference code uses global variable.
+ */
int ssi_fips_ext_get_state(ssi_fips_state_t *p_state)
{
int rc = 0;
@@ -51,11 +51,11 @@ int ssi_fips_ext_get_state(ssi_fips_state_t *p_state)
}
/*
-This function returns the FIPS REE error.
-The function should be implemented by the driver user, depends on where
.
-the error value is stored.
-The reference code uses global variable.
-*/
+ * This function returns the FIPS REE error.
+ * The function should be implemented by the driver user, depends on where
+ * the error value is stored.
+ * The reference code uses global variable.
+ */
int ssi_fips_ext_get_error(ssi_fips_error_t *p_err)
{
int rc = 0;
@@ -70,11 +70,11 @@ int ssi_fips_ext_get_error(ssi_fips_error_t *p_err)
}
/*
-This function sets the FIPS REE state.
-The function should be implemented by the driver user, depends on where
.
-the state value is stored.
-The reference code uses global variable.
-*/
+ * This function sets the FIPS REE state.
+ * The function should be implemented by the driver user, depends on where
+ * the state value is stored.
+ * The reference code uses global variable.
+ */
int ssi_fips_ext_set_state(ssi_fips_state_t state)
{
fips_state = state;
@@ -82,11 +82,11 @@ int ssi_fips_ext_set_state(ssi_fips_state_t state)
}
/*
-This function sets the FIPS REE error.
-The function should be implemented by the driver user, depends on where
.
-the error value is stored.
-The reference code uses global variable.
-*/
+ * This function sets the FIPS REE error.
+ * The function should be implemented by the driver user, depends on where
+ * the error value is stored.
+ * The reference code uses global variable.
+ */
int ssi_fips_ext_set_error(ssi_fips_error_t err)
{
fips_error = err;
--
2.13.0
[PATCH V2 12/27] Drivers: ccree: ssi_fips_ll.c - align block comments
Fixed block comment alignment, Style fix only
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/ssi_fips_ll.c | 21 -
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/drivers/staging/ccree/ssi_fips_ll.c
b/drivers/staging/ccree/ssi_fips_ll.c
index 7c7c922f0788..ef0a9a580560 100644
--- a/drivers/staging/ccree/ssi_fips_ll.c
+++ b/drivers/staging/ccree/ssi_fips_ll.c
@@ -15,9 +15,9 @@
*/
/**
-This file defines the driver FIPS Low Level implmentaion functions,
-that executes the KAT.
-***/
+ * This file defines the driver FIPS Low Level implmentaion functions,
+ * that executes the KAT.
+ ***/
#include
#include "ssi_driver.h"
@@ -816,7 +816,8 @@ ssi_hmac_fips_run_test(struct ssi_drvdata *drvdata,
dma_addr_t digest_bytes_len_dma_addr)
{
/* The implemented flow is not the same as the one implemented in
ssi_hash.c (setkey + digest flows).
- In this flow, there is no need to store and reload some of the
intermidiate results. */
+* In this flow, there is no need to store and reload some of the
intermidiate results.
+*/
/* max number of descriptors used for the flow */
#define FIPS_HMAC_MAX_SEQ_LEN 12
@@ -948,9 +949,9 @@ ssi_hmac_fips_run_test(struct ssi_drvdata *drvdata,
idx++;
/* at this point:
- tmp_digest = H(o_key_pad)
- k0 = H(i_key_pad || m)
- */
+* tmp_digest = H(o_key_pad)
+* k0 = H(i_key_pad || m)
+*/
/* Loading hash opad xor key state */
HW_DESC_INIT(&desc[idx]);
@@ -1413,8 +1414,10 @@ ssi_gcm_fips_run_test(struct ssi_drvdata *drvdata,
idx++;
/* Configure Hash Engine to work with GHASH.
- Since it was not possible to extend HASH submodes to add GHASH,
- The following command is necessary in order to select GHASH
(according to HW designers)*/
+* Since it was not possible to extend HASH submodes to add GHASH,
+* The following command is necessary in order to
+* select GHASH (according to HW designers)
+*/
HW_DESC_INIT(&desc[idx]);
HW_DESC_SET_DIN_NO_DMA(&desc[idx], 0, 0xf0);
HW_DESC_SET_DOUT_NO_DMA(&desc[idx], 0, 0, 1);
--
2.13.0
[PATCH V2 11/27] Drivers: ccree: ssi_fips_local.c - align block comments
Fixed block comment alignment, Style fix only
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/ssi_fips_local.c | 21 -
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/drivers/staging/ccree/ssi_fips_local.c
b/drivers/staging/ccree/ssi_fips_local.c
index 316507d88b4e..8076c771f750 100644
--- a/drivers/staging/ccree/ssi_fips_local.c
+++ b/drivers/staging/ccree/ssi_fips_local.c
@@ -15,8 +15,8 @@
*/
/**
-This file defines the driver FIPS internal function, used by the driver itself.
-***/
+ * This file defines the driver FIPS internal function, used by the driver
itself.
+ ***/
#include
#include
#include
@@ -80,10 +80,10 @@ static enum ssi_fips_error ssi_fips_get_tee_error(struct
ssi_drvdata *drvdata)
/*
- This function should push the FIPS REE library status towards the TEE library.
- By writing the error state to HOST_GPR0 register. The function is called from
.
- driver entry point so no need to protect by mutex.
-*/
+ * This function should push the FIPS REE library status towards the TEE
library.
+ * By writing the error state to HOST_GPR0 register. The function is called
from
+ * driver entry point so no need to protect by mutex.
+ */
static void ssi_fips_update_tee_upon_ree_status(struct ssi_drvdata *drvdata,
ssi_fips_error_t err)
{
void __iomem *cc_base = drvdata->cc_base;
@@ -232,7 +232,8 @@ ssi_fips_error_t cc_fips_run_power_up_tests(struct
ssi_drvdata *drvdata)
/* The function checks if FIPS supported and FIPS error exists.*
-* It should be used in every driver API.*/
+ * It should be used in every driver API.
+ */
int ssi_fips_check_fips_error(void)
{
ssi_fips_state_t fips_state;
@@ -250,14 +251,16 @@ int ssi_fips_check_fips_error(void)
/* The function sets the REE FIPS state.*
-* It should be used while driver is being loaded .*/
+ * It should be used while driver is being loaded.
+ */
int ssi_fips_set_state(ssi_fips_state_t state)
{
return ssi_fips_ext_set_state(state);
}
/* The function sets the REE FIPS error, and pushes the error to TEE library. *
-* It should be used when any of the KAT tests fails .*/
+ * It should be used when any of the KAT tests fails.
+ */
int ssi_fips_set_error(struct ssi_drvdata *p_drvdata, ssi_fips_error_t err)
{
int rc = 0;
--
2.13.0
[PATCH V2 10/27] Drivers: ccree: ssi_hash.c - align block comments
Fixed block comment alignment, Style fix only
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/ssi_hash.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/staging/ccree/ssi_hash.c b/drivers/staging/ccree/ssi_hash.c
index 8585f73161b3..da5915e4ce48 100644
--- a/drivers/staging/ccree/ssi_hash.c
+++ b/drivers/staging/ccree/ssi_hash.c
@@ -97,7 +97,8 @@ struct hash_key_req_ctx {
struct ssi_hash_ctx {
struct ssi_drvdata *drvdata;
/* holds the origin digest; the digest after "setkey" if HMAC,*
- the initial digest if HASH. */
+* the initial digest if HASH.
+*/
u8 digest_buff[SSI_MAX_HASH_DIGEST_SIZE] cacheline_aligned;
u8 opad_tmp_keys_buff[SSI_MAX_HASH_OPAD_TMP_KEYS_SIZE]
cacheline_aligned;
dma_addr_t opad_tmp_keys_dma_addr cacheline_aligned;
@@ -250,7 +251,8 @@ static int ssi_hash_map_request(struct device *dev,
}
} else { /*hash*/
/* Copy the initial digests if hash flow. The SRAM contains the
- initial digests in the expected order for all SHA* */
+* initial digests in the expected order for all SHA*
+*/
HW_DESC_INIT(&desc);
HW_DESC_SET_DIN_SRAM(&desc, larval_digest_addr,
ctx->inter_digestsize);
HW_DESC_SET_DOUT_DLLI(&desc, state->digest_buff_dma_addr,
ctx->inter_digestsize, NS_BIT, 0);
@@ -1027,7 +1029,8 @@ static int ssi_hash_setkey(void *hash,
ctx->drvdata, ctx->hash_mode);
/* The keylen value distinguishes HASH in case keylen is ZERO bytes,
- any NON-ZERO value utilizes HMAC flow */
+* any NON-ZERO value utilizes HMAC flow
+*/
ctx->key_params.keylen = keylen;
ctx->key_params.key_dma_addr = 0;
ctx->is_hmac = true;
--
2.13.0
[PATCH V2 08/27] Drivers: ccree: ssi_ivgen.c - align block comments
Fixed block comment alignment, Style fix only Found using checkpatch Signed-off-by: Derek Robson --- drivers/staging/ccree/ssi_ivgen.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/staging/ccree/ssi_ivgen.c b/drivers/staging/ccree/ssi_ivgen.c index 1bb6f8919101..db4b831e82a3 100644 --- a/drivers/staging/ccree/ssi_ivgen.c +++ b/drivers/staging/ccree/ssi_ivgen.c @@ -26,7 +26,8 @@ /* The max. size of pool *MUST* be <= SRAM total size */ #define SSI_IVPOOL_SIZE 1024 /* The first 32B fraction of pool are dedicated to the - next encryption "key" & "IV" for pool regeneration */ + * next encryption "key" & "IV" for pool regeneration + */ #define SSI_IVPOOL_META_SIZE (CC_AES_IV_SIZE + AES_KEYSIZE_128) #define SSI_IVPOOL_GEN_SEQ_LEN 4 @@ -278,7 +279,8 @@ int ssi_ivgen_getiv( } /* Bypass operation is proceeded by crypto sequence, hence must - * assure bypass-write-transaction by a memory barrier */ +* assure bypass-write-transaction by a memory barrier +*/ HW_DESC_INIT(&iv_seq[idx]); HW_DESC_SET_DIN_NO_DMA(&iv_seq[idx], 0, 0xf0); HW_DESC_SET_DOUT_NO_DMA(&iv_seq[idx], 0, 0, 1); -- 2.13.0
[PATCH V2 09/27] Drivers: ccree: ssi_hash.h - align block comments
Fixed block comment alignment, Style fix only Found using checkpatch Signed-off-by: Derek Robson --- drivers/staging/ccree/ssi_hash.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/ccree/ssi_hash.h b/drivers/staging/ccree/ssi_hash.h index b821d0c854b5..7c946614a1f9 100644 --- a/drivers/staging/ccree/ssi_hash.h +++ b/drivers/staging/ccree/ssi_hash.h @@ -15,7 +15,7 @@ */ /* \file ssi_hash.h - ARM CryptoCell Hash Crypto API + * ARM CryptoCell Hash Crypto API */ #ifndef __SSI_HASH_H__ -- 2.13.0
[PATCH V2 07/27] Drivers: ccree: ssi_pm.h - align block comments
Fixed block comment alignment, Style fix only Found using checkpatch Signed-off-by: Derek Robson --- drivers/staging/ccree/ssi_pm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/ccree/ssi_pm.h b/drivers/staging/ccree/ssi_pm.h index f1fe1777c04a..8b0d8be95199 100644 --- a/drivers/staging/ccree/ssi_pm.h +++ b/drivers/staging/ccree/ssi_pm.h @@ -15,7 +15,7 @@ */ /* \file ssi_pm.h -*/ + */ #ifndef __SSI_POWER_MGR_H__ #define __SSI_POWER_MGR_H__ -- 2.13.0
[PATCH V2 06/27] Drivers: ccree: ssi_pm_ext.c - align block comments
Fixed block comment alignment, Style fix only
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/ssi_pm_ext.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/staging/ccree/ssi_pm_ext.c
b/drivers/staging/ccree/ssi_pm_ext.c
index 5889d9f97479..453151cdd6b2 100644
--- a/drivers/staging/ccree/ssi_pm_ext.c
+++ b/drivers/staging/ccree/ssi_pm_ext.c
@@ -26,10 +26,10 @@
#include "ssi_pm_ext.h"
/*
-This function should suspend the HW (if possiable), It should be implemented by
-the driver user.
-The reference code clears the internal SRAM to imitate lose of state.
-*/
+ * This function should suspend the HW (if possiable), It should be
implemented by
+ * the driver user.
+ * The reference code clears the internal SRAM to imitate lose of state.
+ */
void ssi_pm_ext_hw_suspend(struct device *dev)
{
struct ssi_drvdata *drvdata =
@@ -50,9 +50,9 @@ void ssi_pm_ext_hw_suspend(struct device *dev)
}
/*
-This function should resume the HW (if possiable).It should be implemented by
-the driver user.
-*/
+ * This function should resume the HW (if possiable).It should be implemented
by
+ * the driver user.
+ */
void ssi_pm_ext_hw_resume(struct device *dev)
{
return;
--
2.13.0
[PATCH V2 05/27] Drivers: ccree: ssi_pm_ext.h - align block comments
Fixed block comment alignment, Style fix only Found using checkpatch Signed-off-by: Derek Robson --- drivers/staging/ccree/ssi_pm_ext.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/ccree/ssi_pm_ext.h b/drivers/staging/ccree/ssi_pm_ext.h index 9049e6ffa8d3..dbe658b530bf 100644 --- a/drivers/staging/ccree/ssi_pm_ext.h +++ b/drivers/staging/ccree/ssi_pm_ext.h @@ -15,7 +15,7 @@ */ /* \file ssi_pm_ext.h -*/ + */ #ifndef __PM_EXT_H__ #define __PM_EXT_H__ -- 2.13.0
[PATCH V2 04/27] Drivers: ccree: ssi_request_mgr.c - align block comments
Fixed block comment alignment, Style fix only
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/ssi_request_mgr.c | 37 -
1 file changed, 22 insertions(+), 15 deletions(-)
diff --git a/drivers/staging/ccree/ssi_request_mgr.c
b/drivers/staging/ccree/ssi_request_mgr.c
index 48c2450d65c6..1bc6811d63c5 100644
--- a/drivers/staging/ccree/ssi_request_mgr.c
+++ b/drivers/staging/ccree/ssi_request_mgr.c
@@ -300,8 +300,9 @@ static inline int request_mgr_queues_status_check(
unsigned long poll_queue;
/* SW queue is checked only once as it will not
- be chaned during the poll becasue the spinlock_bh
- is held by the thread */
+* be chaned during the poll becasue the spinlock_bh
+* is held by the thread
+*/
if (unlikely(((req_mgr_h->req_queue_head + 1) &
(MAX_REQUEST_QUEUE_SIZE - 1)) ==
req_mgr_h->req_queue_tail)) {
@@ -384,8 +385,9 @@ int send_request(
spin_lock_bh(&req_mgr_h->hw_lock);
/* Check if there is enough place in the SW/HW queues
- in case iv gen add the max size and in case of no dout add 1
- for the internal completion descriptor */
+* in case iv gen add the max size and in case of no dout add 1
+* for the internal completion descriptor
+*/
rc = request_mgr_queues_status_check(req_mgr_h,
cc_base,
max_required_seq_len);
@@ -397,7 +399,8 @@ int send_request(
if (rc != -EAGAIN) {
/* Any error other than HW queue full
- (SW queue is full) */
+* (SW queue is full)
+*/
#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP)
ssi_power_mgr_runtime_put_suspend(&drvdata->plat_dev->dev);
#endif
@@ -409,7 +412,8 @@ int send_request(
} while (1);
/* Additional completion descriptor is needed incase caller did not
- enabled any DLLI/MLLI DOUT bit in the given sequence */
+* enabled any DLLI/MLLI DOUT bit in the given sequence
+*/
if (!is_dout) {
init_completion(&ssi_req->seq_compl);
ssi_req->user_cb = request_mgr_complete;
@@ -481,7 +485,8 @@ int send_request(
if (!is_dout) {
/* Wait upon sequence completion.
- * Return "0" -Operation done successfully. */
+* Return "0" -Operation done successfully.
+*/
return wait_for_completion_interruptible(&ssi_req->seq_compl);
} else {
/* Operation still in process */
@@ -633,7 +638,8 @@ static void comp_handler(unsigned long devarg)
/* ISR-to-Tasklet latency */
if (request_mgr_handle->axi_completed) {
/* Only if actually reflects ISR-to-completion-handling
latency, i.e.,
- not duplicate as a result of interrupt after
AXIM_MON_ERR clear, before end of loop */
+* not duplicate as a result of interrupt after
AXIM_MON_ERR clear, before end of loop
+*/
END_CYCLE_COUNT_AT(drvdata->isr_exit_cycles,
STAT_OP_TYPE_GENERIC, STAT_PHASE_1);
}
@@ -641,7 +647,8 @@ static void comp_handler(unsigned long devarg)
do {
proc_completions(drvdata);
/* At this point (after proc_completions()),
request_mgr_handle->axi_completed is always 0.
- The following assignment was changed to =
(previously was +=) to conform KW restrictions. */
+* The following assignment was changed to =
(previously was +=) to conform KW restrictions.
+*/
request_mgr_handle->axi_completed =
CC_REG_FLD_GET(CRY_KERNEL, AXIM_MON_COMP, VALUE,
CC_HAL_READ_REGISTER(AXIM_MON_BASE_OFFSET));
} while (request_mgr_handle->axi_completed > 0);
@@ -663,9 +670,9 @@ static void comp_handler(unsigned long devarg)
}
/*
-resume the queue configuration - no need to take the lock as this happens
inside
-the spin lock protection
-*/
+ * resume the queue configuration - no need to take the lock as this happens
inside
+ * the spin lock protection
+ */
#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP)
int ssi_request_mgr_runtime_resume_queue(struct ssi_drvdata *drvdata)
{
@@ -679,9 +686,9 @@ int ssi_request_mgr_runtime_resume_queue(struct ssi_drvdata
*drvdata)
}
/*
-susp
[PATCH V2 03/27] Drivers: ccree: ssi_request_mgr.h - align block comments
Fixed block comment alignment, Style fix only Found using checkpatch Signed-off-by: Derek Robson --- drivers/staging/ccree/ssi_request_mgr.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/ccree/ssi_request_mgr.h b/drivers/staging/ccree/ssi_request_mgr.h index ea685bb7fa2b..c4036ab715f1 100644 --- a/drivers/staging/ccree/ssi_request_mgr.h +++ b/drivers/staging/ccree/ssi_request_mgr.h @@ -15,7 +15,7 @@ */ /* \file request_mgr.h - Request Manager + * Request Manager */ #ifndef __REQUEST_MGR_H__ -- 2.13.0
[PATCH V2 01/27] Drivers: ccree: ssi_sysfs.h - align block comments
Fixed block comment alignment, Style fix only Found using checkpatch Signed-off-by: Derek Robson --- drivers/staging/ccree/ssi_sysfs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/ccree/ssi_sysfs.h b/drivers/staging/ccree/ssi_sysfs.h index cd456c5dccc4..4893e014adf7 100644 --- a/drivers/staging/ccree/ssi_sysfs.h +++ b/drivers/staging/ccree/ssi_sysfs.h @@ -15,7 +15,7 @@ */ /* \file ssi_sysfs.h - ARM CryptoCell sysfs APIs + * ARM CryptoCell sysfs APIs */ #ifndef __SSI_SYSFS_H__ -- 2.13.0
[PATCH V2 00/27] Drivers: ccree - align block comments
Fixed block comments across whole ccree driver Version #1 has some trailing white space issue in a few patches Derek Robson (27): Drivers: ccree: ssi_sysfs.h - align block comments Drivers: ccree: ssi_sysfs.c - align block comments Drivers: ccree: ssi_request_mgr.h - align block comments Drivers: ccree: ssi_request_mgr.c - align block comments Drivers: ccree: ssi_pm_ext.h - align block comments Drivers: ccree: ssi_pm_ext.c - align block comments Drivers: ccree: ssi_pm.h - align block comments Drivers: ccree: ssi_ivgen.c - align block comments Drivers: ccree: ssi_hash.h - align block comments Drivers: ccree: ssi_hash.c - align block comments Drivers: ccree: ssi_fips_local.c - align block comments Drivers: ccree: ssi_fips_ll.c - align block comments Drivers: ccree: ssi_fips_ext.c - align block comments Drivers: ccree: ssi_fips_data.h - align block comments Drivers: ccree: ssi_fips.h - align block comments Drivers: ccree: ssi_fips.c - align block comments Drivers: ccree: ssi_driver.h - align block comments Drivers: ccree: ssi_config.h - align block comments Drivers: ccree: ssi_cipher.h - align block comments Drivers: ccree: ssi_buffer_mgr.h - align block comments Drivers: ccree: ssi_buffer_mgr.c - align block comments Drivers: ccree: ssi_aead.h - align block comments Drivers: ccree: ssi_aead.c - align block comments Drivers: ccree: hash_defs.h - align block comments Drivers: ccree: cc_regs.h - align block comments Drivers: ccree: cc_hw_queue_defs.h - align block comments Drivers: ccree: cc_crypto_ctx.h - align block comments drivers/staging/ccree/cc_crypto_ctx.h| 17 +++--- drivers/staging/ccree/cc_hw_queue_defs.h | 32 +-- drivers/staging/ccree/cc_regs.h | 13 ++--- drivers/staging/ccree/hash_defs.h| 15 +++--- drivers/staging/ccree/ssi_aead.c | 45 ++-- drivers/staging/ccree/ssi_aead.h | 7 +-- drivers/staging/ccree/ssi_buffer_mgr.c | 87 +- drivers/staging/ccree/ssi_buffer_mgr.h | 2 +- drivers/staging/ccree/ssi_cipher.h | 2 +- drivers/staging/ccree/ssi_config.h | 5 +- drivers/staging/ccree/ssi_driver.h | 16 +++--- drivers/staging/ccree/ssi_fips.c | 16 +++--- drivers/staging/ccree/ssi_fips.h | 6 +-- drivers/staging/ccree/ssi_fips_data.h| 93 drivers/staging/ccree/ssi_fips_ext.c | 46 drivers/staging/ccree/ssi_fips_ll.c | 21 drivers/staging/ccree/ssi_fips_local.c | 21 drivers/staging/ccree/ssi_hash.c | 9 ++-- drivers/staging/ccree/ssi_hash.h | 2 +- drivers/staging/ccree/ssi_ivgen.c| 6 ++- drivers/staging/ccree/ssi_pm.h | 2 +- drivers/staging/ccree/ssi_pm_ext.c | 14 ++--- drivers/staging/ccree/ssi_pm_ext.h | 2 +- drivers/staging/ccree/ssi_request_mgr.c | 37 +++-- drivers/staging/ccree/ssi_request_mgr.h | 2 +- drivers/staging/ccree/ssi_sysfs.c| 3 +- drivers/staging/ccree/ssi_sysfs.h| 2 +- 27 files changed, 288 insertions(+), 235 deletions(-) -- 2.13.0
[PATCH V2 02/27] Drivers: ccree: ssi_sysfs.c - align block comments
Fixed block comment alignment, Style fix only
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/ssi_sysfs.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/staging/ccree/ssi_sysfs.c
b/drivers/staging/ccree/ssi_sysfs.c
index 89021c009872..69e1ae491098 100644
--- a/drivers/staging/ccree/ssi_sysfs.c
+++ b/drivers/staging/ccree/ssi_sysfs.c
@@ -355,7 +355,8 @@ static struct ssi_drvdata *sys_get_drvdata(void)
{
/* TODO: supporting multiple SeP devices would require avoiding
* global "top_dir" and finding associated "top_dir" by traversing
-* up the tree to the kobject which matches one of the top_dir's */
+* up the tree to the kobject which matches one of the top_dir's
+*/
return sys_top_dir.drvdata;
}
--
2.13.0
[PATCH 27/27] Drivers: ccree: cc_crypto_ctx.h - align block comments
Fixed block comment alignment, Style fix only
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/cc_crypto_ctx.h | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/staging/ccree/cc_crypto_ctx.h
b/drivers/staging/ccree/cc_crypto_ctx.h
index 216d24791d5d..dcec9a649a84 100644
--- a/drivers/staging/ccree/cc_crypto_ctx.h
+++ b/drivers/staging/ccree/cc_crypto_ctx.h
@@ -219,7 +219,8 @@ struct drv_ctx_hash {
};
/* drv_ctx_hmac should have the same structure as drv_ctx_hash except
- k0, k0_size fields */
+ * k0, k0_size fields
+ */
struct drv_ctx_hmac {
enum drv_crypto_alg alg; /* DRV_CRYPTO_ALG_HMAC */
enum drv_hash_mode mode;
@@ -240,9 +241,10 @@ struct drv_ctx_cipher {
u32 key_size; /* numeric value in bytes */
u32 data_unit_size; /* required for XTS */
/* block_state is the AES engine block state.
- * It is used by the host to pass IV or counter at initialization.
- * It is used by SeP for intermediate block chaining state and for
- * returning MAC algorithms results. */
+* It is used by the host to pass IV or counter at initialization.
+* It is used by SeP for intermediate block chaining state and for
+* returning MAC algorithms results.
+ */
u8 block_state[CC_AES_BLOCK_SIZE];
u8 key[CC_AES_KEY_SIZE_MAX];
u8 xex_key[CC_AES_KEY_SIZE_MAX];
@@ -279,9 +281,10 @@ struct drv_ctx_aead {
/* Get the address of a @member within a given @ctx address
- @ctx: The context address
- @type: Type of context structure
- @member: Associated context field */
+ * @ctx: The context address
+ * @type: Type of context structure
+ * @member: Associated context field
+ */
#define GET_CTX_FIELD_ADDR(ctx, type, member) (ctx + offsetof(type, member))
#endif /* _CC_CRYPTO_CTX_H_ */
--
2.12.2
[PATCH 26/27] Drivers: ccree: cc_hw_queue_defs.h - align block comments
Fixed block comment alignment, Style fix only
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/cc_hw_queue_defs.h | 32
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/staging/ccree/cc_hw_queue_defs.h
b/drivers/staging/ccree/cc_hw_queue_defs.h
index 71381760566d..bb64fddc371d 100644
--- a/drivers/staging/ccree/cc_hw_queue_defs.h
+++ b/drivers/staging/ccree/cc_hw_queue_defs.h
@@ -23,8 +23,8 @@
#include "dx_crys_kernel.h"
/**
-* DEFINITIONS
-**/
+ * DEFINITIONS
+
**/
/* Dma AXI Secure bit */
#defineAXI_SECURE 0
@@ -36,8 +36,8 @@
#define _HW_DESC_MONITOR_KICK 0x7FFFC00
/**
-* TYPE DEFINITIONS
-**/
+ * TYPE DEFINITIONS
+
**/
struct cc_hw_desc {
u32 word[HW_DESC_SIZE_WORDS];
@@ -400,7 +400,7 @@ enum cc_hw_des_key_size {
*
* \param pDesc pointer HW descriptor struct
* \param numRounds number of rounds for Multi2
-*/
+ */
#define HW_DESC_SET_MULTI2_NUM_ROUNDS(pDesc, numRounds)
\
do {
\
CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD2, VALUE,
(pDesc)->word[2], (u32)(numRounds)); \
@@ -411,7 +411,7 @@ enum cc_hw_des_key_size {
*
* \param pDesc pointer HW descriptor struct
* \param flowMode Any one of the modes defined in [CC7x-DESC]
-*/
+ */
#define HW_DESC_SET_FLOW_MODE(pDesc, flowMode)
\
do {
\
@@ -423,7 +423,7 @@ enum cc_hw_des_key_size {
*
* \param pDesc pointer HW descriptor struct
* \param cipherMode Any one of the modes defined in [CC7x-DESC]
-*/
+ */
#define HW_DESC_SET_CIPHER_MODE(pDesc, cipherMode)
\
do {
\
CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_MODE,
(pDesc)->word[4], (cipherMode)); \
@@ -434,7 +434,7 @@ enum cc_hw_des_key_size {
*
* \param pDesc pointer HW descriptor struct
* \param cipherConfig Any one of the modes defined in [CC7x-DESC]
-*/
+ */
#define HW_DESC_SET_CIPHER_CONFIG0(pDesc, cipherConfig)
\
do {
\
CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_CONF0,
(pDesc)->word[4], (cipherConfig));\
@@ -445,7 +445,7 @@ enum cc_hw_des_key_size {
*
* \param pDesc pointer HW descriptor struct
* \param cipherConfig Any one of the modes defined in [CC7x-DESC]
-*/
+ */
#define HW_DESC_SET_CIPHER_CONFIG1(pDesc, cipherConfig)
\
do {
\
CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_CONF1,
(pDesc)->word[4], (cipherConfig));\
@@ -456,7 +456,7 @@ enum cc_hw_des_key_size {
*
* \param pDesc pointer HW descriptor struct
* \param hwKey The hw key number as in enun HwCryptoKey
-*/
+ */
#define HW_DESC_SET_HW_CRYPTO_KEY(pDesc, hwKey)
\
do {
\
CC_REG_FLD_SET(CRY_KERNEL, DSCRPTR_QUEUE_WORD4, CIPHER_DO,
(pDesc)->word[4], (hwKey) & HW_KEY_MASK_CIPHER_DO); \
@@ -468,7 +468,7 @@ enum cc_hw_des_key_size {
*
* \param pDesc pointer HW descriptor struct
* \param swapConfig Any one of the modes defined in [CC7x-DESC]
-*/
+ */
#define HW_DESC_SET_BYTES_SWAP(pDesc, swapConfig)
\
do {
\
CC_REG_FLD_SET(CR
[PATCH 23/27] Drivers: ccree: ssi_aead.c - align block comments
Fixed block comment alignment, Style fix only
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/ssi_aead.c | 45 ++--
1 file changed, 29 insertions(+), 16 deletions(-)
diff --git a/drivers/staging/ccree/ssi_aead.c b/drivers/staging/ccree/ssi_aead.c
index 26afa8794668..ecf9ff2ae336 100644
--- a/drivers/staging/ccree/ssi_aead.c
+++ b/drivers/staging/ccree/ssi_aead.c
@@ -250,7 +250,8 @@ static void ssi_aead_complete(struct device *dev, void
*ssi_req, void __iomem *c
"(auth-size=%d, cipher=%d).\n",
ctx->authsize, ctx->cipher_mode);
/* In case of payload authentication failure, MUST NOT
- revealed the decrypted message --> zero its memory.
*/
+* revealed the decrypted message --> zero its memory.
+*/
ssi_buffer_mgr_zero_sgl(areq->dst, areq_ctx->cryptlen);
err = -EBADMSG;
}
@@ -279,7 +280,8 @@ static int xcbc_setkey(struct cc_hw_desc *desc, struct
ssi_aead_ctx *ctx)
/* Load the AES key */
HW_DESC_INIT(&desc[0]);
/* We are using for the source/user key the same buffer as for the
output keys,
- because after this key loading it is not needed anymore */
+* because after this key loading it is not needed anymore
+*/
HW_DESC_SET_DIN_TYPE(&desc[0], DMA_DLLI,
ctx->auth_state.xcbc.xcbc_keys_dma_addr, ctx->auth_keylen, NS_BIT);
HW_DESC_SET_CIPHER_MODE(&desc[0], DRV_CIPHER_ECB);
HW_DESC_SET_CIPHER_CONFIG0(&desc[0], DRV_CRYPTO_DIRECTION_ENCRYPT);
@@ -420,8 +422,9 @@ static int validate_keys_sizes(struct ssi_aead_ctx *ctx)
return 0; /* All tests of keys sizes passed */
}
-/*This function prepers the user key so it can pass to the hmac processing
- (copy to intenral buffer or hash in case of key longer than block */
+/* This function prepers the user key so it can pass to the hmac processing
+ * (copy to intenral buffer or hash in case of key longer than block
+ */
static int
ssi_get_plain_hmac_key(struct crypto_aead *tfm, const u8 *key, unsigned int
keylen)
{
@@ -600,7 +603,8 @@ ssi_aead_setkey(struct crypto_aead *tfm, const u8 *key,
unsigned int keylen)
(AES_MIN_KEY_SIZE + CTR_RFC3686_NONCE_SIZE))
goto badkey;
/* Copy nonce from last 4 bytes in CTR key to
- * first 4 bytes in CTR IV */
+* first 4 bytes in CTR IV
+*/
memcpy(ctx->ctr_nonce, key + ctx->auth_keylen +
ctx->enc_keylen -
CTR_RFC3686_NONCE_SIZE, CTR_RFC3686_NONCE_SIZE);
/* Set CTR key size */
@@ -829,7 +833,8 @@ ssi_aead_process_authenc_data_desc(
{
/* DOUBLE-PASS flow (as default)
* assoc. + iv + data -compact in one table
-* if assoclen is ZERO only IV perform */
+* if assoclen is ZERO only IV perform
+*/
ssi_sram_addr_t mlli_addr = areq_ctx->assoc.sram_addr;
u32 mlli_nents = areq_ctx->assoc.mlli_nents;
@@ -1287,7 +1292,8 @@ static inline void ssi_aead_hmac_authenc(
/**
* Double-pass flow
* Fallback for unsupported single-pass modes,
-* i.e. using assoc. data of non-word-multiple */
+* i.e. using assoc. data of non-word-multiple
+*/
if (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) {
/* encrypt first.. */
ssi_aead_process_cipher(req, desc, seq_size, data_flow_mode);
@@ -1305,7 +1311,8 @@ static inline void ssi_aead_hmac_authenc(
/* decrypt after.. */
ssi_aead_process_cipher(req, desc, seq_size, data_flow_mode);
/* read the digest result with setting the completion bit
- must be after the cipher operation */
+* must be after the cipher operation
+*/
ssi_aead_process_digest_result_desc(req, desc, seq_size);
}
}
@@ -1338,7 +1345,8 @@ ssi_aead_xcbc_authenc(
/**
* Double-pass flow
* Fallback for unsupported single-pass modes,
-* i.e. using assoc. data of non-word-multiple */
+* i.e. using assoc. data of non-word-multiple
+*/
if (direct == DRV_CRYPTO_DIRECTION_ENCRYPT) {
/* encrypt first.. */
ssi_aead_process_cipher(req, desc, seq_size, data_flow_mode);
@@ -1353,7 +1361,8 @@ ssi_aead_xcbc_authenc(
/* decrypt after..*/
ssi_aead_process_cipher(req, desc, seq_size, data_flow_mode);
/* read the digest result with setting the com
[PATCH 25/27] Drivers: ccree: cc_regs.h - align block comments
Fixed block comment alignment, Style fix only
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/cc_regs.h | 13 +++--
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/staging/ccree/cc_regs.h b/drivers/staging/ccree/cc_regs.h
index 8b89f0603f16..f4b3b5a23ae2 100644
--- a/drivers/staging/ccree/cc_regs.h
+++ b/drivers/staging/ccree/cc_regs.h
@@ -55,8 +55,9 @@ do {
\
BITFIELD_GET(reg_val, CC_ ## reg_name ## _ ## fld_name ## _BIT_SHIFT, \
CC_ ## reg_name ## _ ## fld_name ## _BIT_SIZE))
-/* yael TBD !!! -*
-* all HW includes should start with CC_ and not DX_ !! */
+/* yael TBD !!!
+ * all HW includes should start with CC_ and not DX_ !!
+ */
/*! Bit fields set */
@@ -86,10 +87,10 @@ do {
\
} while (0)
/* Usage example:
- u32 reg_shadow = READ_REGISTER(CC_REG_ADDR(CRY_KERNEL,AES_CONTROL));
- CC_REG_FLD_SET(CRY_KERNEL,AES_CONTROL,NK_KEY0,reg_shadow, 3);
- CC_REG_FLD_SET(CRY_KERNEL,AES_CONTROL,NK_KEY1,reg_shadow, 1);
- WRITE_REGISTER(CC_REG_ADDR(CRY_KERNEL,AES_CONTROL), reg_shadow);
+ * u32 reg_shadow = READ_REGISTER(CC_REG_ADDR(CRY_KERNEL,AES_CONTROL));
+ * CC_REG_FLD_SET(CRY_KERNEL,AES_CONTROL,NK_KEY0,reg_shadow, 3);
+ * CC_REG_FLD_SET(CRY_KERNEL,AES_CONTROL,NK_KEY1,reg_shadow, 1);
+ * WRITE_REGISTER(CC_REG_ADDR(CRY_KERNEL,AES_CONTROL), reg_shadow);
*/
#endif /*_CC_REGS_H_*/
--
2.12.2
[PATCH 24/27] Drivers: ccree: hash_defs.h - align block comments
Fixed block comment alignment, Style fix only
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/hash_defs.h | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/staging/ccree/hash_defs.h
b/drivers/staging/ccree/hash_defs.h
index 613897038f6d..3f2b2d1521c2 100644
--- a/drivers/staging/ccree/hash_defs.h
+++ b/drivers/staging/ccree/hash_defs.h
@@ -59,13 +59,14 @@ enum HashCipherDoPadding {
typedef struct SepHashPrivateContext {
/* The current length is placed at the end of the context buffer
because the hash
- context is used for all HMAC operations as well. HMAC context
includes a 64 bytes
- K0 field. The size of struct drv_ctx_hash reserved field is 88/184
bytes depend if t
- he SHA512 is supported ( in this case teh context size is 256 bytes).
- The size of struct drv_ctx_hash reseved field is 20 or 52 depend if
the SHA512 is supported.
- This means that this structure size (without the reserved field can
be up to 20 bytes ,
- in case sha512 is not suppported it is 20 bytes
(SEP_HASH_LENGTH_WORDS define to 2 ) and in the other
- case it is 28 (SEP_HASH_LENGTH_WORDS define to 4) */
+* context is used for all HMAC operations as well. HMAC context
includes a 64 bytes
+* K0 field. The size of struct drv_ctx_hash reserved field is
88/184 bytes depend if t
+* he SHA512 is supported ( in this case teh context size is 256
bytes).
+* The size of struct drv_ctx_hash reseved field is 20 or 52 depend if
the SHA512 is supported.
+* This means that this structure size (without the reserved field can
be up to 20 bytes ,
+* in case sha512 is not suppported it is 20 bytes
(SEP_HASH_LENGTH_WORDS define to 2 ) and in the other
+* case it is 28 (SEP_HASH_LENGTH_WORDS define to 4)
+*/
u32 reserved[(sizeof(struct drv_ctx_hash)/sizeof(u32)) -
SEP_HASH_LENGTH_WORDS - 3];
u32 CurrentDigestedLength[SEP_HASH_LENGTH_WORDS];
u32 KeyType;
--
2.12.2
[PATCH 22/27] Drivers: ccree: ssi_aead.h - align block comments
Fixed block comment alignment, Style fix only
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/ssi_aead.h | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/staging/ccree/ssi_aead.h b/drivers/staging/ccree/ssi_aead.h
index 654a181729d7..00a3680cb8ab 100644
--- a/drivers/staging/ccree/ssi_aead.h
+++ b/drivers/staging/ccree/ssi_aead.h
@@ -15,7 +15,7 @@
*/
/* \file ssi_aead.h
- ARM CryptoCell AEAD Crypto API
+ * ARM CryptoCell AEAD Crypto API
*/
#ifndef __SSI_AEAD_H__
@@ -62,8 +62,9 @@ enum aead_ccm_header_size {
struct aead_req_ctx {
/* Allocate cache line although only 4 bytes are needed to
- * assure next field falls @ cache line
- * Used for both: digest HW compare and CCM/GCM MAC value */
+* assure next field falls @ cache line
+* Used for both: digest HW compare and CCM/GCM MAC value
+*/
u8 mac_buf[MAX_MAC_SIZE] cacheline_aligned;
u8 ctr_iv[AES_BLOCK_SIZE] cacheline_aligned;
--
2.12.2
[PATCH 21/27] Drivers: ccree: ssi_buffer_mgr.c - align block comments
Fixed block comment alignment, Style fix only
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/ssi_buffer_mgr.c | 87 +++---
1 file changed, 49 insertions(+), 38 deletions(-)
diff --git a/drivers/staging/ccree/ssi_buffer_mgr.c
b/drivers/staging/ccree/ssi_buffer_mgr.c
index 77e490968db9..db6333ae5612 100644
--- a/drivers/staging/ccree/ssi_buffer_mgr.c
+++ b/drivers/staging/ccree/ssi_buffer_mgr.c
@@ -330,7 +330,8 @@ static int ssi_buffer_mgr_generate_mlli(
/* set last bit in the current table */
if (sg_data->mlli_nents[i] != NULL) {
/*Calculate the current MLLI table length for the
- length field in the descriptor*/
+*length field in the descriptor
+*/
*(sg_data->mlli_nents[i]) +=
(total_nents - prev_total_nents);
prev_total_nents = total_nents;
@@ -463,7 +464,8 @@ static int ssi_buffer_mgr_map_scatterlist(
}
if (!is_chained) {
/* In case of mmu the number of mapped nents might
- be changed from the original sgl nents */
+* be changed from the original sgl nents
+*/
*mapped_nents = dma_map_sg(dev, sg, *nents, direction);
if (unlikely(*mapped_nents == 0)){
*nents = 0;
@@ -472,7 +474,8 @@ static int ssi_buffer_mgr_map_scatterlist(
}
} else {
/*In this case the driver maps entry by entry so it
- must have the same nents before and after map */
+* must have the same nents before and after map
+*/
*mapped_nents = ssi_buffer_mgr_dma_map_sg(dev,
sg,
*nents,
@@ -764,7 +767,8 @@ void ssi_buffer_mgr_unmap_aead_request(
}
/*In case a pool was set, a table was
- allocated and should be released */
+*allocated and should be released
+*/
if (areq_ctx->mlli_params.curr_pool != NULL) {
SSI_LOG_DEBUG("free MLLI buffer: dma=0x%08llX virt=%pK\n",
(unsigned long long)areq_ctx->mlli_params.mlli_dma_addr,
@@ -801,7 +805,8 @@ void ssi_buffer_mgr_unmap_aead_request(
size_to_skip += crypto_aead_ivsize(tfm);
}
/* copy mac to a temporary location to deal with possible
- data memory overriding that caused by cache coherence
problem. */
+* data memory overriding that caused by cache coherence
problem.
+*/
ssi_buffer_mgr_copy_scatterlist_portion(
areq_ctx->backup_mac, req->src,
size_to_skip+ req->cryptlen - areq_ctx->req_authsize,
@@ -965,7 +970,8 @@ static inline int ssi_buffer_mgr_aead_chain_assoc(
areq_ctx->assoc.nents = mapped_nents;
/* in CCM case we have additional entry for
- * ccm header configurations */
+* ccm header configurations
+*/
if (areq_ctx->ccm_hdr_size != ccm_header_size_null) {
if (unlikely((mapped_nents + 1) >
LLI_MAX_NUM_OF_ASSOC_DATA_ENTRIES)) {
@@ -1068,13 +1074,15 @@ static inline int ssi_buffer_mgr_prepare_aead_data_mlli(
if (unlikely(areq_ctx->is_icv_fragmented == true)) {
/* Backup happens only when ICV is fragmented, ICV
- verification is made by CPU compare in order to
simplify
- MAC verification upon request completion */
+* verification is made by CPU compare in order to
simplify
+* MAC verification upon request completion
+*/
if (direct == DRV_CRYPTO_DIRECTION_DECRYPT) {
#if !DX_HAS_ACP
/* In ACP platform we already copying ICV
- for any INPLACE-DECRYPT operation, hence
- we must neglect this code. */
+* for any INPLACE-DECRYPT operation, hence
+* we must neglect this code.
+*/
u32 size_to_skip = req->assoclen;
if (areq_ctx->is_gcm4543) {
size_to_skip += crypto_aead_ivsize(tfm);
@@ -1120,8 +1128,9 @@ static inline int ssi_buffer_mgr_prepare_aead_data_mlli(
[PATCH 20/27] Drivers: ccree: ssi_buffer_mgr.h - align block comments
Fixed block comment alignment, Style fix only Found using checkpatch Signed-off-by: Derek Robson --- drivers/staging/ccree/ssi_buffer_mgr.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/ccree/ssi_buffer_mgr.h b/drivers/staging/ccree/ssi_buffer_mgr.h index 4acbb4b6afc9..98355dd789e5 100644 --- a/drivers/staging/ccree/ssi_buffer_mgr.h +++ b/drivers/staging/ccree/ssi_buffer_mgr.h @@ -15,7 +15,7 @@ */ /* \file buffer_mgr.h - Buffer Manager + * Buffer Manager */ #ifndef __SSI_BUFFER_MGR_H__ -- 2.12.2
[PATCH 18/27] Drivers: ccree: ssi_config.h - align block comments
Fixed block comment alignment, Style fix only Found using checkpatch Signed-off-by: Derek Robson --- drivers/staging/ccree/ssi_config.h | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/staging/ccree/ssi_config.h b/drivers/staging/ccree/ssi_config.h index 431b518d893a..9feb692fff0d 100644 --- a/drivers/staging/ccree/ssi_config.h +++ b/drivers/staging/ccree/ssi_config.h @@ -15,7 +15,7 @@ */ /* \file ssi_config.h - Definitions for ARM CryptoCell Linux Crypto Driver + * Definitions for ARM CryptoCell Linux Crypto Driver */ #ifndef __SSI_CONFIG_H__ @@ -49,7 +49,8 @@ #define SSI_CACHE_PARAMS (0x000) /* CC attached to NONE-ACP such as HPP/ACE/AMBA4. * The customer is responsible to enable/disable this feature -* according to his platform type. */ +* according to his platform type. +*/ #define DX_HAS_ACP 0 #else #define SSI_CACHE_PARAMS (0xEEE) -- 2.12.2
[PATCH 16/27] Drivers: ccree: ssi_fips.c - align block comments
Fixed block comment alignment, Style fix only
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/ssi_fips.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/staging/ccree/ssi_fips.c b/drivers/staging/ccree/ssi_fips.c
index 25ee23a1cecf..60a2452f7b0b 100644
--- a/drivers/staging/ccree/ssi_fips.c
+++ b/drivers/staging/ccree/ssi_fips.c
@@ -16,8 +16,8 @@
/**
-This file defines the driver FIPS APIs
*
-***/
+ * This file defines the driver FIPS APIs *
+ **/
#include
#include "ssi_fips.h"
@@ -27,9 +27,9 @@ extern int ssi_fips_ext_get_state(ssi_fips_state_t *p_state);
extern int ssi_fips_ext_get_error(ssi_fips_error_t *p_err);
/*
-This function returns the REE FIPS state.
-It should be called by kernel module.
-*/
+ * This function returns the REE FIPS state.
+ * It should be called by kernel module.
+ */
int ssi_fips_get_state(ssi_fips_state_t *p_state)
{
int rc = 0;
@@ -46,9 +46,9 @@ int ssi_fips_get_state(ssi_fips_state_t *p_state)
EXPORT_SYMBOL(ssi_fips_get_state);
/*
-This function returns the REE FIPS error.
-It should be called by kernel module.
-*/
+ * This function returns the REE FIPS error.
+ * It should be called by kernel module.
+ */
int ssi_fips_get_error(ssi_fips_error_t *p_err)
{
int rc = 0;
--
2.12.2
[PATCH 19/27] Drivers: ccree: ssi_cipher.h - align block comments
Fixed block comment alignment, Style fix only Found using checkpatch Signed-off-by: Derek Robson --- drivers/staging/ccree/ssi_cipher.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/ccree/ssi_cipher.h b/drivers/staging/ccree/ssi_cipher.h index 7d58b56fc2c7..22d7b431edb9 100644 --- a/drivers/staging/ccree/ssi_cipher.h +++ b/drivers/staging/ccree/ssi_cipher.h @@ -15,7 +15,7 @@ */ /* \file ssi_cipher.h - ARM CryptoCell Cipher Crypto API + * ARM CryptoCell Cipher Crypto API */ #ifndef __SSI_CIPHER_H__ -- 2.12.2
[PATCH 17/27] Drivers: ccree: ssi_driver.h - align block comments
Fixed block comment alignment, Style fix only
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/ssi_driver.h | 16 ++--
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/staging/ccree/ssi_driver.h
b/drivers/staging/ccree/ssi_driver.h
index 45fc23fe169f..e034b0987137 100644
--- a/drivers/staging/ccree/ssi_driver.h
+++ b/drivers/staging/ccree/ssi_driver.h
@@ -15,7 +15,7 @@
*/
/* \file ssi_driver.h
- ARM CryptoCell Linux Crypto Driver
+ * ARM CryptoCell Linux Crypto Driver
*/
#ifndef __SSI_DRIVER_H__
@@ -86,7 +86,8 @@
#define NS_BIT 1
#define AXI_ID 0
/* AXI_ID is not actually the AXI ID of the transaction but the value of AXI_ID
- field in the HW descriptor. The DMA engine +8 that value. */
+ * field in the HW descriptor. The DMA engine +8 that value.
+ */
/* Logging macros */
#define SSI_LOG(level, format, ...) \
@@ -108,9 +109,11 @@
struct ssi_crypto_req {
void (*user_cb)(struct device *dev, void *req, void __iomem *cc_base);
void *user_arg;
- dma_addr_t ivgen_dma_addr[SSI_MAX_IVGEN_DMA_ADDRESSES]; /* For the
first 'ivgen_dma_addr_len' addresses of this array,
-generated IV would be placed in it by
send_request().
-Same generated IV for all addresses! */
+ dma_addr_t ivgen_dma_addr[SSI_MAX_IVGEN_DMA_ADDRESSES];
+ /* For the first 'ivgen_dma_addr_len' addresses of this array,
+* generated IV would be placed in it by send_request().
+* Same generated IV for all addresses!
+*/
unsigned int ivgen_dma_addr_len; /* Amount of 'ivgen_dma_addr' elements
to be filled. */
unsigned int ivgen_size; /* The generated IV size required, 8/16 B
allowed. */
struct completion seq_compl; /* request completion */
@@ -136,7 +139,8 @@ struct ssi_drvdata {
u32 irq_mask;
u32 fw_ver;
/* Calibration time of start/stop
- * monitor descriptors */
+* monitor descriptors
+*/
u32 monitor_null_cycles;
struct platform_device *plat_dev;
ssi_sram_addr_t mlli_sram_addr;
--
2.12.2
[PATCH 14/27] Drivers: ccree: ssi_fips_data.h - align block comments
Fixed block comment alignment, Style fix only Found using checkpatch Signed-off-by: Derek Robson --- drivers/staging/ccree/ssi_fips_data.h | 93 +-- 1 file changed, 46 insertions(+), 47 deletions(-) diff --git a/drivers/staging/ccree/ssi_fips_data.h b/drivers/staging/ccree/ssi_fips_data.h index a4b78f1b4d48..a2aaa925ba38 100644 --- a/drivers/staging/ccree/ssi_fips_data.h +++ b/drivers/staging/ccree/ssi_fips_data.h @@ -15,53 +15,52 @@ */ /* -The test vectors were taken from: - -* AES -NIST Special Publication 800-38A 2001 Edition -Recommendation for Block Cipher Modes of Operation -http://csrc.nist.gov/publications/nistpubs/800-38a/sp800-38a.pdf -Appendix F: Example Vectors for Modes of Operation of the AES - -* AES CTS -Advanced Encryption Standard (AES) Encryption for Kerberos 5 -February 2005 -https://tools.ietf.org/html/rfc3962#appendix-B -B. Sample Test Vectors - -* AES XTS -http://csrc.nist.gov/groups/STM/cavp/#08 -http://csrc.nist.gov/groups/STM/cavp/documents/aes/XTSTestVectors.zip - -* AES CMAC -http://csrc.nist.gov/groups/STM/cavp/index.html#07 -http://csrc.nist.gov/groups/STM/cavp/documents/mac/cmactestvectors.zip - -* AES-CCM -http://csrc.nist.gov/groups/STM/cavp/#07 -http://csrc.nist.gov/groups/STM/cavp/documents/mac/ccmtestvectors.zip - -* AES-GCM -http://csrc.nist.gov/groups/STM/cavp/documents/mac/gcmtestvectors.zip - -* Triple-DES -NIST Special Publication 800-67 January 2012 -Recommendation for the Triple Data Encryption Algorithm (TDEA) Block Cipher -http://csrc.nist.gov/publications/nistpubs/800-67-Rev1/SP-800-67-Rev1.pdf -APPENDIX B: EXAMPLE OF TDEA FORWARD AND INVERSE CIPHER OPERATIONS -and -http://csrc.nist.gov/groups/STM/cavp/#01 -http://csrc.nist.gov/groups/STM/cavp/documents/des/tdesmct_intermediate.zip - -* HASH -http://csrc.nist.gov/groups/STM/cavp/#03 -http://csrc.nist.gov/groups/STM/cavp/documents/shs/shabytetestvectors.zip - -* HMAC -http://csrc.nist.gov/groups/STM/cavp/#07 -http://csrc.nist.gov/groups/STM/cavp/documents/mac/hmactestvectors.zip - -*/ + * The test vectors were taken from: + * + * * AES + * NIST Special Publication 800-38A 2001 Edition + * Recommendation for Block Cipher Modes of Operation + * http://csrc.nist.gov/publications/nistpubs/800-38a/sp800-38a.pdf + * Appendix F: Example Vectors for Modes of Operation of the AES + * + * * AES CTS + * Advanced Encryption Standard (AES) Encryption for Kerberos 5 + * February 2005 + * https://tools.ietf.org/html/rfc3962#appendix-B + * B. Sample Test Vectors + * + * * AES XTS + * http://csrc.nist.gov/groups/STM/cavp/#08 + * http://csrc.nist.gov/groups/STM/cavp/documents/aes/XTSTestVectors.zip + * + * * AES CMAC + * http://csrc.nist.gov/groups/STM/cavp/index.html#07 + * http://csrc.nist.gov/groups/STM/cavp/documents/mac/cmactestvectors.zip + * + * * AES-CCM + * http://csrc.nist.gov/groups/STM/cavp/#07 + * http://csrc.nist.gov/groups/STM/cavp/documents/mac/ccmtestvectors.zip + * + * * AES-GCM + * http://csrc.nist.gov/groups/STM/cavp/documents/mac/gcmtestvectors.zip + * + * * Triple-DES + * NIST Special Publication 800-67 January 2012 + * Recommendation for the Triple Data Encryption Algorithm (TDEA) Block Cipher + * http://csrc.nist.gov/publications/nistpubs/800-67-Rev1/SP-800-67-Rev1.pdf + * APPENDIX B: EXAMPLE OF TDEA FORWARD AND INVERSE CIPHER OPERATIONS + * and + * http://csrc.nist.gov/groups/STM/cavp/#01 + * http://csrc.nist.gov/groups/STM/cavp/documents/des/tdesmct_intermediate.zip + * + * * HASH + * http://csrc.nist.gov/groups/STM/cavp/#03 + * http://csrc.nist.gov/groups/STM/cavp/documents/shs/shabytetestvectors.zip + * + * * HMAC + * http://csrc.nist.gov/groups/STM/cavp/#07 + * http://csrc.nist.gov/groups/STM/cavp/documents/mac/hmactestvectors.zip + */ /* NIST AES */ #define AES_128_BIT_KEY_SIZE16 -- 2.12.2
[PATCH 15/27] Drivers: ccree: ssi_fips.h - align block comments
Fixed block comment alignment, Style fix only
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/ssi_fips.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/staging/ccree/ssi_fips.h b/drivers/staging/ccree/ssi_fips.h
index 607c64b8c458..e108d89ef98c 100644
--- a/drivers/staging/ccree/ssi_fips.h
+++ b/drivers/staging/ccree/ssi_fips.h
@@ -18,9 +18,9 @@
#define __SSI_FIPS_H__
/*!
-@file
-@brief This file contains FIPS related defintions and APIs.
-*/
+ * @file
+ * @brief This file contains FIPS related defintions and APIs.
+ */
typedef enum ssi_fips_state {
CC_FIPS_STATE_NOT_SUPPORTED = 0,
--
2.12.2
[PATCH 13/27] Drivers: ccree: ssi_fips_ext.c - align block comments
Fixed block comment alignment, Style fix only
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/ssi_fips_ext.c | 46 ++--
1 file changed, 23 insertions(+), 23 deletions(-)
diff --git a/drivers/staging/ccree/ssi_fips_ext.c
b/drivers/staging/ccree/ssi_fips_ext.c
index 291a880f567c..0f53a4bc43de 100644
--- a/drivers/staging/ccree/ssi_fips_ext.c
+++ b/drivers/staging/ccree/ssi_fips_ext.c
@@ -15,9 +15,9 @@
*/
/**
-This file defines the driver FIPS functions that should be
-implemented by the driver user. Current implementation is sample code only.
-***/
+ * This file defines the driver FIPS functions that should be
+ * implemented by the driver user. Current implementation is sample code only.
+ ***/
#include
#include "ssi_fips_local.h"
@@ -32,11 +32,11 @@ static ssi_fips_state_t fips_state =
CC_FIPS_STATE_NOT_SUPPORTED;
static ssi_fips_error_t fips_error = CC_REE_FIPS_ERROR_OK;
/*
-This function returns the FIPS REE state.
-The function should be implemented by the driver user, depends on where
.
-the state value is stored.
-The reference code uses global variable.
-*/
+ * This function returns the FIPS REE state.
+ * The function should be implemented by the driver user, depends on where
+ * the state value is stored.
+ * The reference code uses global variable.
+ */
int ssi_fips_ext_get_state(ssi_fips_state_t *p_state)
{
int rc = 0;
@@ -51,11 +51,11 @@ int ssi_fips_ext_get_state(ssi_fips_state_t *p_state)
}
/*
-This function returns the FIPS REE error.
-The function should be implemented by the driver user, depends on where
.
-the error value is stored.
-The reference code uses global variable.
-*/
+ * This function returns the FIPS REE error.
+ * The function should be implemented by the driver user, depends on where
+ * the error value is stored.
+ * The reference code uses global variable.
+ */
int ssi_fips_ext_get_error(ssi_fips_error_t *p_err)
{
int rc = 0;
@@ -70,11 +70,11 @@ int ssi_fips_ext_get_error(ssi_fips_error_t *p_err)
}
/*
-This function sets the FIPS REE state.
-The function should be implemented by the driver user, depends on where
.
-the state value is stored.
-The reference code uses global variable.
-*/
+ * This function sets the FIPS REE state.
+ * The function should be implemented by the driver user, depends on where
+ * the state value is stored.
+ * The reference code uses global variable.
+ */
int ssi_fips_ext_set_state(ssi_fips_state_t state)
{
fips_state = state;
@@ -82,11 +82,11 @@ int ssi_fips_ext_set_state(ssi_fips_state_t state)
}
/*
-This function sets the FIPS REE error.
-The function should be implemented by the driver user, depends on where
.
-the error value is stored.
-The reference code uses global variable.
-*/
+ * This function sets the FIPS REE error.
+ * The function should be implemented by the driver user, depends on where
+ * the error value is stored.
+ * The reference code uses global variable.
+ */
int ssi_fips_ext_set_error(ssi_fips_error_t err)
{
fips_error = err;
--
2.12.2
[PATCH 12/27] Drivers: ccree: ssi_fips_ll.c - align block comments
Fixed block comment alignment, Style fix only
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/ssi_fips_ll.c | 21 -
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/drivers/staging/ccree/ssi_fips_ll.c
b/drivers/staging/ccree/ssi_fips_ll.c
index 7c7c922f0788..cb487d747ee8 100644
--- a/drivers/staging/ccree/ssi_fips_ll.c
+++ b/drivers/staging/ccree/ssi_fips_ll.c
@@ -15,9 +15,9 @@
*/
/**
-This file defines the driver FIPS Low Level implmentaion functions,
-that executes the KAT.
-***/
+ * This file defines the driver FIPS Low Level implmentaion functions,
+ * that executes the KAT.
+ ***/
#include
#include "ssi_driver.h"
@@ -816,7 +816,8 @@ ssi_hmac_fips_run_test(struct ssi_drvdata *drvdata,
dma_addr_t digest_bytes_len_dma_addr)
{
/* The implemented flow is not the same as the one implemented in
ssi_hash.c (setkey + digest flows).
- In this flow, there is no need to store and reload some of the
intermidiate results. */
+* In this flow, there is no need to store and reload some of the
intermidiate results.
+*/
/* max number of descriptors used for the flow */
#define FIPS_HMAC_MAX_SEQ_LEN 12
@@ -948,9 +949,9 @@ ssi_hmac_fips_run_test(struct ssi_drvdata *drvdata,
idx++;
/* at this point:
- tmp_digest = H(o_key_pad)
- k0 = H(i_key_pad || m)
- */
+* tmp_digest = H(o_key_pad)
+* k0 = H(i_key_pad || m)
+*/
/* Loading hash opad xor key state */
HW_DESC_INIT(&desc[idx]);
@@ -1413,8 +1414,10 @@ ssi_gcm_fips_run_test(struct ssi_drvdata *drvdata,
idx++;
/* Configure Hash Engine to work with GHASH.
- Since it was not possible to extend HASH submodes to add GHASH,
- The following command is necessary in order to select GHASH
(according to HW designers)*/
+* Since it was not possible to extend HASH submodes to add GHASH,
+* The following command is necessary in order to
+* select GHASH (according to HW designers)
+*/
HW_DESC_INIT(&desc[idx]);
HW_DESC_SET_DIN_NO_DMA(&desc[idx], 0, 0xf0);
HW_DESC_SET_DOUT_NO_DMA(&desc[idx], 0, 0, 1);
--
2.12.2
[PATCH 11/27] Drivers: ccree: ssi_fips_local.c - align block comments
Fixed block comment alignment, Style fix only
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/ssi_fips_local.c | 21 -
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/drivers/staging/ccree/ssi_fips_local.c
b/drivers/staging/ccree/ssi_fips_local.c
index 316507d88b4e..8076c771f750 100644
--- a/drivers/staging/ccree/ssi_fips_local.c
+++ b/drivers/staging/ccree/ssi_fips_local.c
@@ -15,8 +15,8 @@
*/
/**
-This file defines the driver FIPS internal function, used by the driver itself.
-***/
+ * This file defines the driver FIPS internal function, used by the driver
itself.
+ ***/
#include
#include
#include
@@ -80,10 +80,10 @@ static enum ssi_fips_error ssi_fips_get_tee_error(struct
ssi_drvdata *drvdata)
/*
- This function should push the FIPS REE library status towards the TEE library.
- By writing the error state to HOST_GPR0 register. The function is called from
.
- driver entry point so no need to protect by mutex.
-*/
+ * This function should push the FIPS REE library status towards the TEE
library.
+ * By writing the error state to HOST_GPR0 register. The function is called
from
+ * driver entry point so no need to protect by mutex.
+ */
static void ssi_fips_update_tee_upon_ree_status(struct ssi_drvdata *drvdata,
ssi_fips_error_t err)
{
void __iomem *cc_base = drvdata->cc_base;
@@ -232,7 +232,8 @@ ssi_fips_error_t cc_fips_run_power_up_tests(struct
ssi_drvdata *drvdata)
/* The function checks if FIPS supported and FIPS error exists.*
-* It should be used in every driver API.*/
+ * It should be used in every driver API.
+ */
int ssi_fips_check_fips_error(void)
{
ssi_fips_state_t fips_state;
@@ -250,14 +251,16 @@ int ssi_fips_check_fips_error(void)
/* The function sets the REE FIPS state.*
-* It should be used while driver is being loaded .*/
+ * It should be used while driver is being loaded.
+ */
int ssi_fips_set_state(ssi_fips_state_t state)
{
return ssi_fips_ext_set_state(state);
}
/* The function sets the REE FIPS error, and pushes the error to TEE library. *
-* It should be used when any of the KAT tests fails .*/
+ * It should be used when any of the KAT tests fails.
+ */
int ssi_fips_set_error(struct ssi_drvdata *p_drvdata, ssi_fips_error_t err)
{
int rc = 0;
--
2.12.2
[PATCH 10/27] Drivers: ccree: ssi_hash.c - align block comments
Fixed block comment alignment, Style fix only
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/ssi_hash.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/staging/ccree/ssi_hash.c b/drivers/staging/ccree/ssi_hash.c
index 162d17dee2cd..11b5eae1c55e 100644
--- a/drivers/staging/ccree/ssi_hash.c
+++ b/drivers/staging/ccree/ssi_hash.c
@@ -97,7 +97,8 @@ struct hash_key_req_ctx {
struct ssi_hash_ctx {
struct ssi_drvdata *drvdata;
/* holds the origin digest; the digest after "setkey" if HMAC,*
- the initial digest if HASH. */
+* the initial digest if HASH.
+*/
u8 digest_buff[SSI_MAX_HASH_DIGEST_SIZE] cacheline_aligned;
u8 opad_tmp_keys_buff[SSI_MAX_HASH_OPAD_TMP_KEYS_SIZE]
cacheline_aligned;
dma_addr_t opad_tmp_keys_dma_addr cacheline_aligned;
@@ -250,7 +251,8 @@ static int ssi_hash_map_request(struct device *dev,
}
} else { /*hash*/
/* Copy the initial digests if hash flow. The SRAM contains the
- initial digests in the expected order for all SHA* */
+* initial digests in the expected order for all SHA*
+*/
HW_DESC_INIT(&desc);
HW_DESC_SET_DIN_SRAM(&desc, larval_digest_addr,
ctx->inter_digestsize);
HW_DESC_SET_DOUT_DLLI(&desc, state->digest_buff_dma_addr,
ctx->inter_digestsize, NS_BIT, 0);
@@ -1027,7 +1029,8 @@ static int ssi_hash_setkey(void *hash,
ctx->drvdata, ctx->hash_mode);
/* The keylen value distinguishes HASH in case keylen is ZERO bytes,
- any NON-ZERO value utilizes HMAC flow */
+* any NON-ZERO value utilizes HMAC flow
+*/
ctx->key_params.keylen = keylen;
ctx->key_params.key_dma_addr = 0;
ctx->is_hmac = true;
--
2.12.2
[PATCH 08/27] Drivers: ccree: ssi_ivgen.c - align block comments
Fixed block comment alignment, Style fix only Found using checkpatch Signed-off-by: Derek Robson --- drivers/staging/ccree/ssi_ivgen.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/staging/ccree/ssi_ivgen.c b/drivers/staging/ccree/ssi_ivgen.c index 1bb6f8919101..db4b831e82a3 100644 --- a/drivers/staging/ccree/ssi_ivgen.c +++ b/drivers/staging/ccree/ssi_ivgen.c @@ -26,7 +26,8 @@ /* The max. size of pool *MUST* be <= SRAM total size */ #define SSI_IVPOOL_SIZE 1024 /* The first 32B fraction of pool are dedicated to the - next encryption "key" & "IV" for pool regeneration */ + * next encryption "key" & "IV" for pool regeneration + */ #define SSI_IVPOOL_META_SIZE (CC_AES_IV_SIZE + AES_KEYSIZE_128) #define SSI_IVPOOL_GEN_SEQ_LEN 4 @@ -278,7 +279,8 @@ int ssi_ivgen_getiv( } /* Bypass operation is proceeded by crypto sequence, hence must - * assure bypass-write-transaction by a memory barrier */ +* assure bypass-write-transaction by a memory barrier +*/ HW_DESC_INIT(&iv_seq[idx]); HW_DESC_SET_DIN_NO_DMA(&iv_seq[idx], 0, 0xf0); HW_DESC_SET_DOUT_NO_DMA(&iv_seq[idx], 0, 0, 1); -- 2.12.2
[PATCH 07/27] Drivers: ccree: ssi_pm.h - align block comments
Fixed block comment alignment, Style fix only Found using checkpatch Signed-off-by: Derek Robson --- drivers/staging/ccree/ssi_pm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/ccree/ssi_pm.h b/drivers/staging/ccree/ssi_pm.h index f1fe1777c04a..8b0d8be95199 100644 --- a/drivers/staging/ccree/ssi_pm.h +++ b/drivers/staging/ccree/ssi_pm.h @@ -15,7 +15,7 @@ */ /* \file ssi_pm.h -*/ + */ #ifndef __SSI_POWER_MGR_H__ #define __SSI_POWER_MGR_H__ -- 2.12.2
[PATCH 09/27] Drivers: ccree: ssi_hash.h - align block comments
Fixed block comment alignment, Style fix only Found using checkpatch Signed-off-by: Derek Robson --- drivers/staging/ccree/ssi_hash.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/ccree/ssi_hash.h b/drivers/staging/ccree/ssi_hash.h index b821d0c854b5..7c946614a1f9 100644 --- a/drivers/staging/ccree/ssi_hash.h +++ b/drivers/staging/ccree/ssi_hash.h @@ -15,7 +15,7 @@ */ /* \file ssi_hash.h - ARM CryptoCell Hash Crypto API + * ARM CryptoCell Hash Crypto API */ #ifndef __SSI_HASH_H__ -- 2.12.2
[PATCH 06/27] Drivers: ccree: ssi_pm_ext.c - align block comments
Fixed block comment alignment, Style fix only
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/ssi_pm_ext.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/drivers/staging/ccree/ssi_pm_ext.c
b/drivers/staging/ccree/ssi_pm_ext.c
index 5889d9f97479..453151cdd6b2 100644
--- a/drivers/staging/ccree/ssi_pm_ext.c
+++ b/drivers/staging/ccree/ssi_pm_ext.c
@@ -26,10 +26,10 @@
#include "ssi_pm_ext.h"
/*
-This function should suspend the HW (if possiable), It should be implemented by
-the driver user.
-The reference code clears the internal SRAM to imitate lose of state.
-*/
+ * This function should suspend the HW (if possiable), It should be
implemented by
+ * the driver user.
+ * The reference code clears the internal SRAM to imitate lose of state.
+ */
void ssi_pm_ext_hw_suspend(struct device *dev)
{
struct ssi_drvdata *drvdata =
@@ -50,9 +50,9 @@ void ssi_pm_ext_hw_suspend(struct device *dev)
}
/*
-This function should resume the HW (if possiable).It should be implemented by
-the driver user.
-*/
+ * This function should resume the HW (if possiable).It should be implemented
by
+ * the driver user.
+ */
void ssi_pm_ext_hw_resume(struct device *dev)
{
return;
--
2.12.2
[PATCH 05/27] Drivers: ccree: ssi_pm_ext.h - align block comments
Fixed block comment alignment, Style fix only Found using checkpatch Signed-off-by: Derek Robson --- drivers/staging/ccree/ssi_pm_ext.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/ccree/ssi_pm_ext.h b/drivers/staging/ccree/ssi_pm_ext.h index 9049e6ffa8d3..dbe658b530bf 100644 --- a/drivers/staging/ccree/ssi_pm_ext.h +++ b/drivers/staging/ccree/ssi_pm_ext.h @@ -15,7 +15,7 @@ */ /* \file ssi_pm_ext.h -*/ + */ #ifndef __PM_EXT_H__ #define __PM_EXT_H__ -- 2.12.2
[PATCH 04/27] Drivers: ccree: ssi_request_mgr.c - align block comments
Fixed block comment alignment, Style fix only
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/ssi_request_mgr.c | 37 -
1 file changed, 22 insertions(+), 15 deletions(-)
diff --git a/drivers/staging/ccree/ssi_request_mgr.c
b/drivers/staging/ccree/ssi_request_mgr.c
index 48c2450d65c6..1bc6811d63c5 100644
--- a/drivers/staging/ccree/ssi_request_mgr.c
+++ b/drivers/staging/ccree/ssi_request_mgr.c
@@ -300,8 +300,9 @@ static inline int request_mgr_queues_status_check(
unsigned long poll_queue;
/* SW queue is checked only once as it will not
- be chaned during the poll becasue the spinlock_bh
- is held by the thread */
+* be chaned during the poll becasue the spinlock_bh
+* is held by the thread
+*/
if (unlikely(((req_mgr_h->req_queue_head + 1) &
(MAX_REQUEST_QUEUE_SIZE - 1)) ==
req_mgr_h->req_queue_tail)) {
@@ -384,8 +385,9 @@ int send_request(
spin_lock_bh(&req_mgr_h->hw_lock);
/* Check if there is enough place in the SW/HW queues
- in case iv gen add the max size and in case of no dout add 1
- for the internal completion descriptor */
+* in case iv gen add the max size and in case of no dout add 1
+* for the internal completion descriptor
+*/
rc = request_mgr_queues_status_check(req_mgr_h,
cc_base,
max_required_seq_len);
@@ -397,7 +399,8 @@ int send_request(
if (rc != -EAGAIN) {
/* Any error other than HW queue full
- (SW queue is full) */
+* (SW queue is full)
+*/
#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP)
ssi_power_mgr_runtime_put_suspend(&drvdata->plat_dev->dev);
#endif
@@ -409,7 +412,8 @@ int send_request(
} while (1);
/* Additional completion descriptor is needed incase caller did not
- enabled any DLLI/MLLI DOUT bit in the given sequence */
+* enabled any DLLI/MLLI DOUT bit in the given sequence
+*/
if (!is_dout) {
init_completion(&ssi_req->seq_compl);
ssi_req->user_cb = request_mgr_complete;
@@ -481,7 +485,8 @@ int send_request(
if (!is_dout) {
/* Wait upon sequence completion.
- * Return "0" -Operation done successfully. */
+* Return "0" -Operation done successfully.
+*/
return wait_for_completion_interruptible(&ssi_req->seq_compl);
} else {
/* Operation still in process */
@@ -633,7 +638,8 @@ static void comp_handler(unsigned long devarg)
/* ISR-to-Tasklet latency */
if (request_mgr_handle->axi_completed) {
/* Only if actually reflects ISR-to-completion-handling
latency, i.e.,
- not duplicate as a result of interrupt after
AXIM_MON_ERR clear, before end of loop */
+* not duplicate as a result of interrupt after
AXIM_MON_ERR clear, before end of loop
+*/
END_CYCLE_COUNT_AT(drvdata->isr_exit_cycles,
STAT_OP_TYPE_GENERIC, STAT_PHASE_1);
}
@@ -641,7 +647,8 @@ static void comp_handler(unsigned long devarg)
do {
proc_completions(drvdata);
/* At this point (after proc_completions()),
request_mgr_handle->axi_completed is always 0.
- The following assignment was changed to =
(previously was +=) to conform KW restrictions. */
+* The following assignment was changed to =
(previously was +=) to conform KW restrictions.
+*/
request_mgr_handle->axi_completed =
CC_REG_FLD_GET(CRY_KERNEL, AXIM_MON_COMP, VALUE,
CC_HAL_READ_REGISTER(AXIM_MON_BASE_OFFSET));
} while (request_mgr_handle->axi_completed > 0);
@@ -663,9 +670,9 @@ static void comp_handler(unsigned long devarg)
}
/*
-resume the queue configuration - no need to take the lock as this happens
inside
-the spin lock protection
-*/
+ * resume the queue configuration - no need to take the lock as this happens
inside
+ * the spin lock protection
+ */
#if defined (CONFIG_PM_RUNTIME) || defined (CONFIG_PM_SLEEP)
int ssi_request_mgr_runtime_resume_queue(struct ssi_drvdata *drvdata)
{
@@ -679,9 +686,9 @@ int ssi_request_mgr_runtime_resume_queue(struct ssi_drvdata
*drvdata)
}
/*
-susp
[PATCH 02/27] Drivers: ccree: ssi_sysfs.c - align block comments
Fixed block comment alignment, Style fix only
Found using checkpatch
Signed-off-by: Derek Robson
---
drivers/staging/ccree/ssi_sysfs.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/staging/ccree/ssi_sysfs.c
b/drivers/staging/ccree/ssi_sysfs.c
index 89021c009872..69e1ae491098 100644
--- a/drivers/staging/ccree/ssi_sysfs.c
+++ b/drivers/staging/ccree/ssi_sysfs.c
@@ -355,7 +355,8 @@ static struct ssi_drvdata *sys_get_drvdata(void)
{
/* TODO: supporting multiple SeP devices would require avoiding
* global "top_dir" and finding associated "top_dir" by traversing
-* up the tree to the kobject which matches one of the top_dir's */
+* up the tree to the kobject which matches one of the top_dir's
+*/
return sys_top_dir.drvdata;
}
--
2.12.2
[PATCH 03/27] Drivers: ccree: ssi_request_mgr.h - align block comments
Fixed block comment alignment, Style fix only Found using checkpatch Signed-off-by: Derek Robson --- drivers/staging/ccree/ssi_request_mgr.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/ccree/ssi_request_mgr.h b/drivers/staging/ccree/ssi_request_mgr.h index ea685bb7fa2b..c4036ab715f1 100644 --- a/drivers/staging/ccree/ssi_request_mgr.h +++ b/drivers/staging/ccree/ssi_request_mgr.h @@ -15,7 +15,7 @@ */ /* \file request_mgr.h - Request Manager + * Request Manager */ #ifndef __REQUEST_MGR_H__ -- 2.12.2
[PATCH 01/27] Drivers: ccree: ssi_sysfs.h - align block comments
Fixed block comment alignment, Style fix only Found using checkpatch Signed-off-by: Derek Robson --- drivers/staging/ccree/ssi_sysfs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/ccree/ssi_sysfs.h b/drivers/staging/ccree/ssi_sysfs.h index cd456c5dccc4..4893e014adf7 100644 --- a/drivers/staging/ccree/ssi_sysfs.h +++ b/drivers/staging/ccree/ssi_sysfs.h @@ -15,7 +15,7 @@ */ /* \file ssi_sysfs.h - ARM CryptoCell sysfs APIs + * ARM CryptoCell sysfs APIs */ #ifndef __SSI_SYSFS_H__ -- 2.12.2
[PATCH 00/27] Drivers: ccree - align block comments
Fixed block comments across whole ccree driver Derek Robson (27): Drivers: ccree: ssi_sysfs.h - align block comments Drivers: ccree: ssi_sysfs.c - align block comments Drivers: ccree: ssi_request_mgr.h - align block comments Drivers: ccree: ssi_request_mgr.c - align block comments Drivers: ccree: ssi_pm_ext.h - align block comments Drivers: ccree: ssi_pm_ext.c - align block comments Drivers: ccree: ssi_pm.h - align block comments Drivers: ccree: ssi_ivgen.c - align block comments Drivers: ccree: ssi_hash.h - align block comments Drivers: ccree: ssi_hash.c - align block comments Drivers: ccree: ssi_fips_local.c - align block comments Drivers: ccree: ssi_fips_ll.c - align block comments Drivers: ccree: ssi_fips_ext.c - align block comments Drivers: ccree: ssi_fips_data.h - align block comments Drivers: ccree: ssi_fips.h - align block comments Drivers: ccree: ssi_fips.c - align block comments Drivers: ccree: ssi_driver.h - align block comments Drivers: ccree: ssi_config.h - align block comments Drivers: ccree: ssi_cipher.h - align block comments Drivers: ccree: ssi_buffer_mgr.h - align block comments Drivers: ccree: ssi_buffer_mgr.c - align block comments Drivers: ccree: ssi_aead.h - align block comments Drivers: ccree: ssi_aead.c - align block comments Drivers: ccree: hash_defs.h - align block comments Drivers: ccree: cc_regs.h - align block comments Drivers: ccree: cc_hw_queue_defs.h - align block comments Drivers: ccree: cc_crypto_ctx.h - align block comments drivers/staging/ccree/cc_crypto_ctx.h| 17 +++--- drivers/staging/ccree/cc_hw_queue_defs.h | 32 +-- drivers/staging/ccree/cc_regs.h | 13 ++--- drivers/staging/ccree/hash_defs.h| 15 +++--- drivers/staging/ccree/ssi_aead.c | 45 ++-- drivers/staging/ccree/ssi_aead.h | 7 +-- drivers/staging/ccree/ssi_buffer_mgr.c | 87 +- drivers/staging/ccree/ssi_buffer_mgr.h | 2 +- drivers/staging/ccree/ssi_cipher.h | 2 +- drivers/staging/ccree/ssi_config.h | 5 +- drivers/staging/ccree/ssi_driver.h | 16 +++--- drivers/staging/ccree/ssi_fips.c | 16 +++--- drivers/staging/ccree/ssi_fips.h | 6 +-- drivers/staging/ccree/ssi_fips_data.h| 93 drivers/staging/ccree/ssi_fips_ext.c | 46 drivers/staging/ccree/ssi_fips_ll.c | 21 drivers/staging/ccree/ssi_fips_local.c | 21 drivers/staging/ccree/ssi_hash.c | 9 ++-- drivers/staging/ccree/ssi_hash.h | 2 +- drivers/staging/ccree/ssi_ivgen.c| 6 ++- drivers/staging/ccree/ssi_pm.h | 2 +- drivers/staging/ccree/ssi_pm_ext.c | 14 ++--- drivers/staging/ccree/ssi_pm_ext.h | 2 +- drivers/staging/ccree/ssi_request_mgr.c | 37 +++-- drivers/staging/ccree/ssi_request_mgr.h | 2 +- drivers/staging/ccree/ssi_sysfs.c| 3 +- drivers/staging/ccree/ssi_sysfs.h| 2 +- 27 files changed, 288 insertions(+), 235 deletions(-) -- 2.12.2
