Re: [PATCH v3 2/2] crypto: sahara: Add driver for SAHARA2 accelerator.
Hi Herbert,
would you please merge this driver or is there anything else you want
me to address first?
Regards.
On 1 March 2013 12:37, Javier Martin wrote:
> SAHARA2 HW module is included in the i.MX27 SoC from
> Freescale. It is capable of performing cipher algorithms
> such as AES, 3DES..., hashing and RNG too.
>
> This driver provides support for AES-CBC and AES-ECB
> by now.
>
> Reviewed-by: Arnd Bergmann
> Signed-off-by: Javier Martin
> ---
> .../devicetree/bindings/crypto/fsl-imx-sahara.txt | 15 +
> drivers/crypto/Kconfig | 10 +
> drivers/crypto/Makefile|1 +
> drivers/crypto/sahara.c| 1070
>
> 4 files changed, 1096 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/crypto/fsl-imx-sahara.txt
> create mode 100644 drivers/crypto/sahara.c
>
> diff --git a/Documentation/devicetree/bindings/crypto/fsl-imx-sahara.txt
> b/Documentation/devicetree/bindings/crypto/fsl-imx-sahara.txt
> new file mode 100644
> index 000..5c65ecc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/crypto/fsl-imx-sahara.txt
> @@ -0,0 +1,15 @@
> +Freescale SAHARA Cryptographic Accelerator included in some i.MX chips.
> +Currently only i.MX27 is supported.
> +
> +Required properties:
> +- compatible : Should be "fsl,-sahara"
> +- reg : Should contain SAHARA registers location and length
> +- interrupts : Should contain SAHARA interrupt number
> +
> +Example:
> +
> +sah@10025000 {
> + compatible = "fsl,imx27-sahara";
> + reg = < 0x10025000 0x800>;
> + interrupts = <75>;
> +};
> diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
> index 87ec4d0..8458e63 100644
> --- a/drivers/crypto/Kconfig
> +++ b/drivers/crypto/Kconfig
> @@ -276,6 +276,16 @@ config CRYPTO_DEV_PICOXCELL
>
> Saying m here will build a module named pipcoxcell_crypto.
>
> +config CRYPTO_DEV_SAHARA
> + tristate "Support for SAHARA crypto accelerator"
> + depends on ARCH_MXC && EXPERIMENTAL && OF
> + select CRYPTO_BLKCIPHER
> + select CRYPTO_AES
> + select CRYPTO_ECB
> + help
> + This option enables support for the SAHARA HW crypto accelerator
> + found in some Freescale i.MX chips.
> +
> config CRYPTO_DEV_S5P
> tristate "Support for Samsung S5PV210 crypto accelerator"
> depends on ARCH_S5PV210
> diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
> index 880a47b..38ce13d 100644
> --- a/drivers/crypto/Makefile
> +++ b/drivers/crypto/Makefile
> @@ -12,6 +12,7 @@ obj-$(CONFIG_CRYPTO_DEV_PPC4XX) += amcc/
> obj-$(CONFIG_CRYPTO_DEV_OMAP_SHAM) += omap-sham.o
> obj-$(CONFIG_CRYPTO_DEV_OMAP_AES) += omap-aes.o
> obj-$(CONFIG_CRYPTO_DEV_PICOXCELL) += picoxcell_crypto.o
> +obj-$(CONFIG_CRYPTO_DEV_SAHARA) += sahara.o
> obj-$(CONFIG_CRYPTO_DEV_S5P) += s5p-sss.o
> obj-$(CONFIG_CRYPTO_DEV_TEGRA_AES) += tegra-aes.o
> obj-$(CONFIG_CRYPTO_DEV_UX500) += ux500/
> diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c
> new file mode 100644
> index 000..a97bb6c
> --- /dev/null
> +++ b/drivers/crypto/sahara.c
> @@ -0,0 +1,1070 @@
> +/*
> + * Cryptographic API.
> + *
> + * Support for SAHARA cryptographic accelerator.
> + *
> + * Copyright (c) 2013 Vista Silicon S.L.
> + * Author: Javier Martin
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> published
> + * by the Free Software Foundation.
> + *
> + * Based on omap-aes.c and tegra-aes.c
> + */
> +
> +#include
> +#include
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#define SAHARA_NAME "sahara"
> +#define SAHARA_VERSION_3 3
> +#define SAHARA_TIMEOUT_MS 1000
> +#define SAHARA_MAX_HW_DESC 2
> +#define SAHARA_MAX_HW_LINK 20
> +
> +#define FLAGS_MODE_MASK0x000f
> +#define FLAGS_ENCRYPT BIT(0)
> +#define FLAGS_CBC BIT(1)
> +#define FLAGS_NEW_KEY BIT(3)
> +#define FLAGS_BUSY 4
> +
> +#define SAHARA_HDR_BASE0x0080
> +#define SAHARA_HDR_SKHA_ALG_AES0
> +#define SAHARA_HDR_SKHA_OP_ENC (1 << 2)
> +#define SAHARA_HDR_SKHA_MODE_ECB (0 << 3)
> +#define SAHARA_HDR_SKHA_MODE_CBC (1 << 3)
> +#define SAHARA_HDR_FORM_DATA (5 << 16)
Re: [PATCH v3 1/2] i.MX27: Add clock support for SAHARA2.
Hi, On 11 March 2013 08:42, Sascha Hauer wrote: > On Mon, Mar 11, 2013 at 09:19:26AM +0800, Herbert Xu wrote: >> On Mon, Mar 11, 2013 at 12:08:56AM +0100, Sascha Hauer wrote: >> > On Sun, Mar 10, 2013 at 04:34:01PM +0800, Herbert Xu wrote: >> > > > > >> > > > > https://patchwork.kernel.org/patch/1817741/ >> > > > > >> > > > > So the change above becomes unnecessary >> > > > >> > > > Very good. Then this patch can be safely dropped. >> > > >> > > So should I take this patch or not? >> > >> > This clk patch, no. The sahara patch, yes, if it is fine for you. >> >> But will the second patch work fine without the first? > > It will work once a device is registered. The necessary clocks for it > will be provided by the devicetree then. As Sascha stated you can safely drop this first patch: [PATCH v3 1/2] i.MX27: Add clock support for SAHARA2. And merge the second one: [PATCH v3 2/2] crypto: sahara: Add driver for SAHARA2 accelerator. Regards. -- Javier Martin Vista Silicon S.L. CDTUC - FASE C - Oficina S-345 Avda de los Castros s/n 39005- Santander. Cantabria. Spain +34 942 25 32 60 www.vista-silicon.com -- To unsubscribe from this list: send the line "unsubscribe linux-crypto" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v3 1/2] i.MX27: Add clock support for SAHARA2.
Hi Sascha, On 4 March 2013 08:53, Sascha Hauer wrote: > On Fri, Mar 01, 2013 at 12:37:52PM +0100, Javier Martin wrote: >> >> Signed-off-by: Javier Martin >> --- >> arch/arm/mach-imx/clk-imx27.c |2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c >> index 4c1d1e4..0b9664a 100644 >> --- a/arch/arm/mach-imx/clk-imx27.c >> +++ b/arch/arm/mach-imx/clk-imx27.c >> @@ -253,6 +253,8 @@ int __init mx27_clocks_init(unsigned long fref) >> clk_register_clkdev(clk[nfc_baud_gate], NULL, "imx27-nand.0"); >> clk_register_clkdev(clk[vpu_baud_gate], "per", "coda-imx27.0"); >> clk_register_clkdev(clk[vpu_ahb_gate], "ahb", "coda-imx27.0"); >> + clk_register_clkdev(clk[sahara_ahb_gate], "ahb", "sahara-imx27.0"); >> + clk_register_clkdev(clk[sahara_ipg_gate], "ipg", "sahara-imx27.0"); > > One of the first patches I want to push upstream for the next merge > window is this one: > > https://patchwork.kernel.org/patch/1817741/ > > So the change above becomes unnecessary Very good. Then this patch can be safely dropped. -- Javier Martin Vista Silicon S.L. CDTUC - FASE C - Oficina S-345 Avda de los Castros s/n 39005- Santander. Cantabria. Spain +34 942 25 32 60 www.vista-silicon.com -- To unsubscribe from this list: send the line "unsubscribe linux-crypto" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 2/2] crypto: sahara: Add driver for SAHARA2 accelerator.
SAHARA2 HW module is included in the i.MX27 SoC from
Freescale. It is capable of performing cipher algorithms
such as AES, 3DES..., hashing and RNG too.
This driver provides support for AES-CBC and AES-ECB
by now.
Reviewed-by: Arnd Bergmann
Signed-off-by: Javier Martin
---
.../devicetree/bindings/crypto/fsl-imx-sahara.txt | 15 +
drivers/crypto/Kconfig | 10 +
drivers/crypto/Makefile|1 +
drivers/crypto/sahara.c| 1070
4 files changed, 1096 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/fsl-imx-sahara.txt
create mode 100644 drivers/crypto/sahara.c
diff --git a/Documentation/devicetree/bindings/crypto/fsl-imx-sahara.txt
b/Documentation/devicetree/bindings/crypto/fsl-imx-sahara.txt
new file mode 100644
index 000..5c65ecc
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/fsl-imx-sahara.txt
@@ -0,0 +1,15 @@
+Freescale SAHARA Cryptographic Accelerator included in some i.MX chips.
+Currently only i.MX27 is supported.
+
+Required properties:
+- compatible : Should be "fsl,-sahara"
+- reg : Should contain SAHARA registers location and length
+- interrupts : Should contain SAHARA interrupt number
+
+Example:
+
+sah@10025000 {
+ compatible = "fsl,imx27-sahara";
+ reg = < 0x10025000 0x800>;
+ interrupts = <75>;
+};
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index 87ec4d0..8458e63 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -276,6 +276,16 @@ config CRYPTO_DEV_PICOXCELL
Saying m here will build a module named pipcoxcell_crypto.
+config CRYPTO_DEV_SAHARA
+ tristate "Support for SAHARA crypto accelerator"
+ depends on ARCH_MXC && EXPERIMENTAL && OF
+ select CRYPTO_BLKCIPHER
+ select CRYPTO_AES
+ select CRYPTO_ECB
+ help
+ This option enables support for the SAHARA HW crypto accelerator
+ found in some Freescale i.MX chips.
+
config CRYPTO_DEV_S5P
tristate "Support for Samsung S5PV210 crypto accelerator"
depends on ARCH_S5PV210
diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile
index 880a47b..38ce13d 100644
--- a/drivers/crypto/Makefile
+++ b/drivers/crypto/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_CRYPTO_DEV_PPC4XX) += amcc/
obj-$(CONFIG_CRYPTO_DEV_OMAP_SHAM) += omap-sham.o
obj-$(CONFIG_CRYPTO_DEV_OMAP_AES) += omap-aes.o
obj-$(CONFIG_CRYPTO_DEV_PICOXCELL) += picoxcell_crypto.o
+obj-$(CONFIG_CRYPTO_DEV_SAHARA) += sahara.o
obj-$(CONFIG_CRYPTO_DEV_S5P) += s5p-sss.o
obj-$(CONFIG_CRYPTO_DEV_TEGRA_AES) += tegra-aes.o
obj-$(CONFIG_CRYPTO_DEV_UX500) += ux500/
diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c
new file mode 100644
index 000..a97bb6c
--- /dev/null
+++ b/drivers/crypto/sahara.c
@@ -0,0 +1,1070 @@
+/*
+ * Cryptographic API.
+ *
+ * Support for SAHARA cryptographic accelerator.
+ *
+ * Copyright (c) 2013 Vista Silicon S.L.
+ * Author: Javier Martin
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ *
+ * Based on omap-aes.c and tegra-aes.c
+ */
+
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define SAHARA_NAME "sahara"
+#define SAHARA_VERSION_3 3
+#define SAHARA_TIMEOUT_MS 1000
+#define SAHARA_MAX_HW_DESC 2
+#define SAHARA_MAX_HW_LINK 20
+
+#define FLAGS_MODE_MASK0x000f
+#define FLAGS_ENCRYPT BIT(0)
+#define FLAGS_CBC BIT(1)
+#define FLAGS_NEW_KEY BIT(3)
+#define FLAGS_BUSY 4
+
+#define SAHARA_HDR_BASE0x0080
+#define SAHARA_HDR_SKHA_ALG_AES0
+#define SAHARA_HDR_SKHA_OP_ENC (1 << 2)
+#define SAHARA_HDR_SKHA_MODE_ECB (0 << 3)
+#define SAHARA_HDR_SKHA_MODE_CBC (1 << 3)
+#define SAHARA_HDR_FORM_DATA (5 << 16)
+#define SAHARA_HDR_FORM_KEY(8 << 16)
+#define SAHARA_HDR_LLO (1 << 24)
+#define SAHARA_HDR_CHA_SKHA(1 << 28)
+#define SAHARA_HDR_CHA_MDHA(2 << 28)
+#define SAHARA_HDR_PARITY_BIT (1 << 31)
+
+/* SAHARA can only process one request at a time */
+#define SAHARA_QUEUE_LENGTH1
+
+#define SAHARA_REG_VERSION 0x00
+#define SAHARA_REG_DAR 0x04
+#define SAHARA_REG_CONTROL 0x08
+#defineSAHARA_CONTROL_SET_THROTTLE(x) (((x) & 0xff) << 24)
+#defineSAHARA_CONTROL_SET_MAXBURST(x) (((x) & 0xff) << 16)
+#defineSAHARA_CONTROL_RNG_AUTORSD (1 << 7)
+#defineSAHARA_CONTROL_ENABLE_INT (1 << 4)
+#define SA
[PATCH v3 1/2] i.MX27: Add clock support for SAHARA2.
Signed-off-by: Javier Martin --- arch/arm/mach-imx/clk-imx27.c |2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c index 4c1d1e4..0b9664a 100644 --- a/arch/arm/mach-imx/clk-imx27.c +++ b/arch/arm/mach-imx/clk-imx27.c @@ -253,6 +253,8 @@ int __init mx27_clocks_init(unsigned long fref) clk_register_clkdev(clk[nfc_baud_gate], NULL, "imx27-nand.0"); clk_register_clkdev(clk[vpu_baud_gate], "per", "coda-imx27.0"); clk_register_clkdev(clk[vpu_ahb_gate], "ahb", "coda-imx27.0"); + clk_register_clkdev(clk[sahara_ahb_gate], "ahb", "sahara-imx27.0"); + clk_register_clkdev(clk[sahara_ipg_gate], "ipg", "sahara-imx27.0"); clk_register_clkdev(clk[dma_ahb_gate], "ahb", "imx27-dma"); clk_register_clkdev(clk[dma_ipg_gate], "ipg", "imx27-dma"); clk_register_clkdev(clk[fec_ipg_gate], "ipg", "imx27-fec.0"); -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-crypto" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v3 0/2] crypto: sahara: Add support for SAHARA in i.MX27.
Hi, the following changes since v2: - Merge device tree binding with the driver code in the same patch. - Specify that currently, only i.MX27 is supported in device tree binding. - Replace MACH_MX27 by ARCH_MXC in Kconfig. - Remove __devexit_p from sahara_remove(). I haven't finally included support for i.MX51 submitted by Arnaud. I'd rather it to be included in a separate patch later if you don't mind. [PATCH v3 1/2] i.MX27: Add clock support for SAHARA2. [PATCH v3 2/2] crypto: sahara: Add driver for SAHARA2 accelerator. -- To unsubscribe from this list: send the line "unsubscribe linux-crypto" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH v2 2/3] crypto: sahara: Add driver for SAHARA2 accelerator.
Hi Arnaud,
On 28 February 2013 12:07, Arnaud Patard wrote:
> Javier Martin writes:
>
> Hi,
>
>> SAHARA2 HW module is included in the i.MX27 SoC from
>> Freescale. It is capable of performing cipher algorithms
>> such as AES, 3DES..., hashing and RNG too.
>
> The rmmod oops is gone with this version, thanks.
>
>>
>> This driver provides support for AES-CBC and AES-ECB
>> by now.
>>
>> Signed-off-by: Javier Martin
>> ---
>> drivers/crypto/Kconfig | 10 +
>> drivers/crypto/Makefile |1 +
>> drivers/crypto/sahara.c | 1070
>> +++
>> 3 files changed, 1081 insertions(+)
>> create mode 100644 drivers/crypto/sahara.c
>>
>> diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
>> index 87ec4d0..7d73f5a 100644
>> --- a/drivers/crypto/Kconfig
>> +++ b/drivers/crypto/Kconfig
>> @@ -276,6 +276,16 @@ config CRYPTO_DEV_PICOXCELL
>>
>> Saying m here will build a module named pipcoxcell_crypto.
>>
>> +config CRYPTO_DEV_SAHARA
>> + tristate "Support for SAHARA crypto accelerator"
>> + depends on MACH_MX27 && EXPERIMENTAL && OF
>
> maybe switch to ARCH_MXC instead of MAC_MX27 ?
>
> [...]
>
>> +static struct platform_driver sahara_driver = {
>> + .probe = sahara_probe,
>> + .remove = __devexit_p(sahara_remove),
>
> Please remove the __devexit_p too.
>
>
> For information, you'll find below what I've changed to test the driver on my
> imx51. It's not perfect but it's enough for testing things.
>
>
Since I have to send v3 anyway to comply with Sascha's request maybe
it would be worth to include your changes to provide support for
i.mx51 too.
Regards.
--
Javier Martin
Vista Silicon S.L.
CDTUC - FASE C - Oficina S-345
Avda de los Castros s/n
39005- Santander. Cantabria. Spain
+34 942 25 32 60
www.vista-silicon.com
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Re: [PATCH v2 3/3] crypto: sahara: Add device tree binding for SAHARA2.
On 27 February 2013 21:05, Sascha Hauer wrote: > Hi Javier, > > On Wed, Feb 27, 2013 at 11:41:51AM +0100, Javier Martin wrote: >> >> Signed-off-by: Javier Martin >> --- >> .../devicetree/bindings/crypto/fsl-imx-sahara.txt | 14 ++ >> 1 file changed, 14 insertions(+) >> create mode 100644 >> Documentation/devicetree/bindings/crypto/fsl-imx-sahara.txt >> >> diff --git a/Documentation/devicetree/bindings/crypto/fsl-imx-sahara.txt >> b/Documentation/devicetree/bindings/crypto/fsl-imx-sahara.txt >> new file mode 100644 >> index 000..44abf11 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/crypto/fsl-imx-sahara.txt >> @@ -0,0 +1,14 @@ >> +* Freescale i.MX SAHARA Cryptographic Accelerator >> + >> +Required properties: >> +- compatible : Should be "fsl,-sahara" > > Please add explicitly which SoCs are supported. > > You can fold this patch into the driver patch. This way people reading > the commit history have a direct cross link between the driver and the > documentation. OK Sascha. Thanks. As we discussed previously it seems only i.MX27 is supported right now. -- Javier Martin Vista Silicon S.L. CDTUC - FASE C - Oficina S-345 Avda de los Castros s/n 39005- Santander. Cantabria. Spain +34 942 25 32 60 www.vista-silicon.com -- To unsubscribe from this list: send the line "unsubscribe linux-crypto" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 3/3] crypto: sahara: Add device tree binding for SAHARA2.
Signed-off-by: Javier Martin
---
.../devicetree/bindings/crypto/fsl-imx-sahara.txt | 14 ++
1 file changed, 14 insertions(+)
create mode 100644 Documentation/devicetree/bindings/crypto/fsl-imx-sahara.txt
diff --git a/Documentation/devicetree/bindings/crypto/fsl-imx-sahara.txt
b/Documentation/devicetree/bindings/crypto/fsl-imx-sahara.txt
new file mode 100644
index 000..44abf11
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/fsl-imx-sahara.txt
@@ -0,0 +1,14 @@
+* Freescale i.MX SAHARA Cryptographic Accelerator
+
+Required properties:
+- compatible : Should be "fsl,-sahara"
+- reg : Should contain SAHARA registers location and length
+- interrupts : Should contain SAHARA interrupt number
+
+Example:
+
+sah@10025000 {
+ compatible = "fsl,imx27-sahara";
+ reg = < 0x10025000 0x800>;
+ interrupts = <75>;
+};
--
1.7.9.5
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[PATCH v2 2/3] crypto: sahara: Add driver for SAHARA2 accelerator.
SAHARA2 HW module is included in the i.MX27 SoC from Freescale. It is capable of performing cipher algorithms such as AES, 3DES..., hashing and RNG too. This driver provides support for AES-CBC and AES-ECB by now. Signed-off-by: Javier Martin --- drivers/crypto/Kconfig | 10 + drivers/crypto/Makefile |1 + drivers/crypto/sahara.c | 1070 +++ 3 files changed, 1081 insertions(+) create mode 100644 drivers/crypto/sahara.c diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 87ec4d0..7d73f5a 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -276,6 +276,16 @@ config CRYPTO_DEV_PICOXCELL Saying m here will build a module named pipcoxcell_crypto. +config CRYPTO_DEV_SAHARA + tristate "Support for SAHARA crypto accelerator" + depends on MACH_MX27 && EXPERIMENTAL && OF + select CRYPTO_BLKCIPHER + select CRYPTO_AES + select CRYPTO_ECB + help + This option enables support for the SAHARA HW crypto accelerator + found in some Freescale i.MX chips. + config CRYPTO_DEV_S5P tristate "Support for Samsung S5PV210 crypto accelerator" depends on ARCH_S5PV210 diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile index 880a47b..38ce13d 100644 --- a/drivers/crypto/Makefile +++ b/drivers/crypto/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_CRYPTO_DEV_PPC4XX) += amcc/ obj-$(CONFIG_CRYPTO_DEV_OMAP_SHAM) += omap-sham.o obj-$(CONFIG_CRYPTO_DEV_OMAP_AES) += omap-aes.o obj-$(CONFIG_CRYPTO_DEV_PICOXCELL) += picoxcell_crypto.o +obj-$(CONFIG_CRYPTO_DEV_SAHARA) += sahara.o obj-$(CONFIG_CRYPTO_DEV_S5P) += s5p-sss.o obj-$(CONFIG_CRYPTO_DEV_TEGRA_AES) += tegra-aes.o obj-$(CONFIG_CRYPTO_DEV_UX500) += ux500/ diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c new file mode 100644 index 000..691983b --- /dev/null +++ b/drivers/crypto/sahara.c @@ -0,0 +1,1070 @@ +/* + * Cryptographic API. + * + * Support for SAHARA cryptographic accelerator. + * + * Copyright (c) 2013 Vista Silicon S.L. + * Author: Javier Martin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Based on omap-aes.c and tegra-aes.c + */ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SAHARA_NAME "sahara" +#define SAHARA_VERSION_3 3 +#define SAHARA_TIMEOUT_MS 1000 +#define SAHARA_MAX_HW_DESC 2 +#define SAHARA_MAX_HW_LINK 20 + +#define FLAGS_MODE_MASK0x000f +#define FLAGS_ENCRYPT BIT(0) +#define FLAGS_CBC BIT(1) +#define FLAGS_NEW_KEY BIT(3) +#define FLAGS_BUSY 4 + +#define SAHARA_HDR_BASE0x0080 +#define SAHARA_HDR_SKHA_ALG_AES0 +#define SAHARA_HDR_SKHA_OP_ENC (1 << 2) +#define SAHARA_HDR_SKHA_MODE_ECB (0 << 3) +#define SAHARA_HDR_SKHA_MODE_CBC (1 << 3) +#define SAHARA_HDR_FORM_DATA (5 << 16) +#define SAHARA_HDR_FORM_KEY(8 << 16) +#define SAHARA_HDR_LLO (1 << 24) +#define SAHARA_HDR_CHA_SKHA(1 << 28) +#define SAHARA_HDR_CHA_MDHA(2 << 28) +#define SAHARA_HDR_PARITY_BIT (1 << 31) + +/* SAHARA can only process one request at a time */ +#define SAHARA_QUEUE_LENGTH1 + +#define SAHARA_REG_VERSION 0x00 +#define SAHARA_REG_DAR 0x04 +#define SAHARA_REG_CONTROL 0x08 +#defineSAHARA_CONTROL_SET_THROTTLE(x) (((x) & 0xff) << 24) +#defineSAHARA_CONTROL_SET_MAXBURST(x) (((x) & 0xff) << 16) +#defineSAHARA_CONTROL_RNG_AUTORSD (1 << 7) +#defineSAHARA_CONTROL_ENABLE_INT (1 << 4) +#define SAHARA_REG_CMD 0x0C +#defineSAHARA_CMD_RESET(1 << 0) +#defineSAHARA_CMD_CLEAR_INT(1 << 8) +#defineSAHARA_CMD_CLEAR_ERR(1 << 9) +#defineSAHARA_CMD_SINGLE_STEP (1 << 10) +#defineSAHARA_CMD_MODE_BATCH (1 << 16) +#defineSAHARA_CMD_MODE_DEBUG (1 << 18) +#defineSAHARA_REG_STATUS 0x10 +#defineSAHARA_STATUS_GET_STATE(x) ((x) & 0x7) +#defineSAHARA_STATE_IDLE 0 +#defineSAHARA_STATE_BUSY 1 +#defineSAHARA_STATE_ERR2 +#defineSAHARA_STATE_FAULT 3 +#defineSAHARA_STATE_COMPLETE 4 +#defineSAHARA_STATE_COMP_FLAG (1 << 2) +#defineS
[PATCH v2 1/3] i.MX27: Add clock support for SAHARA2.
Signed-off-by: Javier Martin --- arch/arm/mach-imx/clk-imx27.c |2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c index 4c1d1e4..0b9664a 100644 --- a/arch/arm/mach-imx/clk-imx27.c +++ b/arch/arm/mach-imx/clk-imx27.c @@ -253,6 +253,8 @@ int __init mx27_clocks_init(unsigned long fref) clk_register_clkdev(clk[nfc_baud_gate], NULL, "imx27-nand.0"); clk_register_clkdev(clk[vpu_baud_gate], "per", "coda-imx27.0"); clk_register_clkdev(clk[vpu_ahb_gate], "ahb", "coda-imx27.0"); + clk_register_clkdev(clk[sahara_ahb_gate], "ahb", "sahara-imx27.0"); + clk_register_clkdev(clk[sahara_ipg_gate], "ipg", "sahara-imx27.0"); clk_register_clkdev(clk[dma_ahb_gate], "ahb", "imx27-dma"); clk_register_clkdev(clk[dma_ipg_gate], "ipg", "imx27-dma"); clk_register_clkdev(clk[fec_ipg_gate], "ipg", "imx27-fec.0"); -- 1.7.9.5 -- To unsubscribe from this list: send the line "unsubscribe linux-crypto" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH v2 0/3] crypto: sahara: Add support for SAHARA in i.MX27.
Hi, this v2 of the series solves several issues pointed out by Arnd Bergmann and Arnaud Patard. Moreover, it drops platform support and relies only on device tree (compile tested only). [PATCH v2 1/3] i.MX27: Add clock support for SAHARA2. [PATCH v2 2/3] crypto: sahara: Add driver for SAHARA2 accelerator. [PATCH v2 3/3] crypto: sahara: Add device tree binding for SAHARA2. -- To unsubscribe from this list: send the line "unsubscribe linux-crypto" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/3] crypto: sahara: Add driver for SAHARA2 accelerator.
Hi Arnaud,
thank you for your feedback. Sorry, I always forget to test my drivers
as modules.
I'll address the issues you pointed out, as well as the improvements
suggested by Arnd, for v2.
Regards.
On 23 February 2013 21:16, Arnaud Patard wrote:
> Javier Martin writes:
>
> Hi,
>
>> SAHARA2 HW module is included in the i.MX27 SoC from
>> Freescale. It is capable of performing cipher algorithms
>> such as AES, 3DES..., hashing and RNG too.
>>
>> This driver provides support for AES-CBC and AES-ECB
>> by now.
>>
>
> [...]
>
>> + int irq;
>> + int err;
>> + int i;
>> +
>> + dev = devm_kzalloc(&pdev->dev, sizeof(struct sahara_dev), GFP_KERNEL);
>> + if (dev == NULL) {
>> + dev_err(&pdev->dev, "unable to alloc data struct.\n");
>> + return -ENOMEM;
>> + }
>> +
>> + dev->device = &pdev->dev;
>> + platform_set_drvdata(pdev, dev);
>> +
>> + /* Get the base address */
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + if (!res) {
>> + dev_err(&pdev->dev, "failed to get memory region resource\n");
>> + return -ENODEV;
>> + }
>> +
>> + if (devm_request_mem_region(&pdev->dev, res->start,
>> + resource_size(res), SAHARA_NAME) == NULL) {
>> + dev_err(&pdev->dev, "failed to request memory region\n");
>> + return -ENOENT;
>> + }
>> + dev->regs_base = devm_ioremap(&pdev->dev, res->start,
>> + resource_size(res));
>> + if (!dev->regs_base) {
>> + dev_err(&pdev->dev, "failed to ioremap address region\n");
>> + return -ENOENT;
>> + }
>> +
>> + /* Get the IRQ */
>> + irq = platform_get_irq(pdev, 0);
>> + if (irq < 0) {
>> + dev_err(&pdev->dev, "failed to get irq resource\n");
>> + return irq;
>> + }
>> +
>> + if (devm_request_irq(&pdev->dev, irq, sahara_irq_handler,
>> + 0, SAHARA_NAME, dev) < 0) {
>> + dev_err(&pdev->dev, "failed to request irq\n");
>> + return -ENOENT;
>> + }
>> +
>> + /* clocks */
>> + dev->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
>> + if (IS_ERR(dev->clk_ipg)) {
>> + dev_err(&pdev->dev, "Could not get ipg clock\n");
>> + return PTR_ERR(dev->clk_ipg);
>> + }
>> +
>> + dev->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
>> + if (IS_ERR(dev->clk_ahb)) {
>> + dev_err(&pdev->dev, "Could not get ahb clock\n");
>> + return PTR_ERR(dev->clk_ahb);
>> + }
>> +
>> + /* Allocate HW descriptors */
>> + dev->hw_desc[0] = dma_alloc_coherent(&pdev->dev,
>> + SAHARA_MAX_HW_DESC * sizeof(struct sahara_hw_desc),
>> + &dev->hw_phys_desc[0], GFP_KERNEL);
>> + if (!dev->hw_desc[0]) {
>> + dev_err(&pdev->dev, "Could not allocate hw descriptors\n");
>> + return -ENOMEM;
>> + }
>> + dev->hw_desc[1] = dev->hw_desc[0] + 1;
>> + dev->hw_phys_desc[1] = dev->hw_phys_desc[0] +
>> + sizeof(struct sahara_hw_desc);
>> +
>> + /* Allocate space for iv and key */
>> + dev->key_base = dma_alloc_coherent(&pdev->dev, 2 * AES_KEYSIZE_128,
>> + &dev->key_phys_base, GFP_KERNEL);
>> + if (!dev->key_base) {
>> + dev_err(&pdev->dev, "Could not allocate memory for key\n");
>> + err = -ENOMEM;
>> + goto err_key;
>> + }
>> + dev->iv_base = dev->key_base + AES_KEYSIZE_128;
>> + dev->iv_phys_base = dev->key_phys_base + AES_KEYSIZE_128;
>> +
>> + /* Allocate space for HW links */
>> + dev->hw_link[0] = dma_alloc_coherent(&pdev->dev,
>> + SAHARA_MAX_HW_LINK * sizeof(struct sahara_hw_link),
>> + &dev->hw_phys_link[0], GFP_KERNEL);
>> + if (!dev->hw_link) {
>> + dev_err(&pdev->dev, "Could not allocate hw links\n");
>> + err = -ENOMEM;
&g
Re: [PATCH 0/3] crypto: sahara: Add support for SAHARA in i.MX27.
On 21 February 2013 16:18, Sascha Hauer wrote: > On Thu, Feb 21, 2013 at 03:18:36PM +0100, javier Martin wrote: >> Hi Arnd, >> >> On 21 February 2013 13:59, Arnd Bergmann wrote: >> > On Thursday 21 February 2013, Javier Martin wrote: >> >> This series of patches provide AES-ECB and AES-CBC support >> >> for the SAHARA2 cryptographic accelerator which is inside the i.MX27 SoC. >> >> It is expected that more algorithms will be supported in the future. >> >> >> >> For testing, a Visstrim M10 board has been used and the code related >> >> to this platform has been included too. >> > >> > As a new device driver, this needs to be supported on the DT based imx27 >> > machines, while support for the individual board files seems unnecessary. >> > >> > How about converting the Visstrim M10 board file over to DT so you don't >> > have to add any more infrastructure for imx that we will just have to >> > remove again one day? >> >> We know about the existence of DT and the constant migration process >> that is taking place towards it. >> >> Moreover we are strongly interested in converting the Visstrim SM10 >> platform to DT. Unfortunately, there are several issues that need to >> be solved so that Visstrim M10 can be fully converted to DT: >> - full SoC camera DT support >> - DT support for ov7670 >> - pinctrl support for i.MX27 > > For the pinctrl stuff I suggest doing what we have done for the newer > i.MX SoCs before we had pinctrl: Match by board compatible string and > call into the board code for using the static pinctrl tables which are > already there. I would like to have propert pinctrl support for the > older i.MX, but probably the motivation for writing it is quite low for > the older SoCs. OK, I take a look at it. > We have a patch in the queue converting the clock lookups for i.MX27 to > dt which should be ready for posting soon. Great. > Then the main road blockers should be out of the way to get rid of the > bulk of the board code. -- Javier Martin Vista Silicon S.L. CDTUC - FASE C - Oficina S-345 Avda de los Castros s/n 39005- Santander. Cantabria. Spain +34 942 25 32 60 www.vista-silicon.com -- To unsubscribe from this list: send the line "unsubscribe linux-crypto" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 0/3] crypto: sahara: Add support for SAHARA in i.MX27.
On 21 February 2013 15:40, Arnd Bergmann wrote: > On Thursday 21 February 2013, javier Martin wrote: >> We know about the existence of DT and the constant migration process >> that is taking place towards it. >> >> Moreover we are strongly interested in converting the Visstrim SM10 >> platform to DT. Unfortunately, there are several issues that need to >> be solved so that Visstrim M10 can be fully converted to DT: >> - full SoC camera DT support >> - DT support for ov7670 >> - pinctrl support for i.MX27 > > Ok, I see. Full device tree support is certainly asking too much then. > >> Furthermore, we have limited resources at the moment and we have to >> decide priorities. But having an hybrid platform-DT support is our >> next task for Visstrim M10. > > Ok, cool. > >> However, I understand your concern about new drivers having DT >> support. Maybe a good approach could be that I added compile-tested >> only DT support for this driver and remove platform support for >> mainline submission (although we maintain it internally in our >> repositories). >> >> What do you think? > > Sounds good. Since it sounds like the hardware is available in all > imx27 device, maybe someone else can test your driver on an imx27 > board that already has partial DT support when you add it to > arch/arm/boot/dts/imx27.dtsi? Yes, since the module is integrated in i.MX27 that seems the way to go. > Is there any reason why an imx27 based board would not support this > driver? Are there any other chips that could use it, e.g. imx25 or > imx6? No, there's no reason for an i.mx27 board not to support this driver since the module doesn't have any external interfaces. I think other i.MX chips have similar devices but I am not sure to what extent they are compatible or not. Probably Sascha Hauer or Shawn Guo (already in CC) could tell better than me since they have a wider view on the i.MX range. Regards. -- Javier Martin Vista Silicon S.L. CDTUC - FASE C - Oficina S-345 Avda de los Castros s/n 39005- Santander. Cantabria. Spain +34 942 25 32 60 www.vista-silicon.com -- To unsubscribe from this list: send the line "unsubscribe linux-crypto" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Re: [PATCH 2/3] crypto: sahara: Add driver for SAHARA2 accelerator.
Hi Arnd,
thanks for your review.
On 21 February 2013 14:13, Arnd Bergmann wrote:
> On Thursday 21 February 2013, Javier Martin wrote:
>> +
>> +struct sahara_dev {
>> + struct device *device;
>> + void __iomem*regs_base;
>> + struct clk *clk_ipg;
>> + struct clk *clk_ahb;
>> +
>> + struct sahara_ctx *ctx;
>> + spinlock_t lock;
>> + struct crypto_queue queue;
>> + unsigned long flags;
>> +
>> + struct tasklet_struct done_task;
>> + struct tasklet_struct queue_task;
>> +
>> + struct sahara_hw_desc *hw_desc[SAHARA_MAX_HW_DESC];
>> + dma_addr_t hw_phys_desc[SAHARA_MAX_HW_DESC];
>> +
>> + u8 *key_base;
>> + dma_addr_t key_phys_base;
>> +
>> + u8 *iv_base;
>> + dma_addr_t iv_phys_base;
>> +
>> + struct sahara_hw_link *hw_link[SAHARA_MAX_HW_LINK];
>> + dma_addr_t hw_phys_link[SAHARA_MAX_HW_LINK];
>> +
>> + struct ablkcipher_request *req;
>> + size_t total;
>> + struct scatterlist *in_sg;
>> + unsigned intnb_in_sg;
>> + struct scatterlist *out_sg;
>> + unsigned intnb_out_sg;
>> +
>> + u32 error;
>> + struct timer_list watchdog;
>> +};
>> +
>> +static struct sahara_dev *dev_ptr;
>
> Please remove this global device pointer, it should not be needed, since you
> can store the pointer in the context object.
Ok. Looks cleaner this way.
>
>> +#ifdef DEBUG
>> +
>> +static char *sahara_state[4] = { "Idle", "Busy", "Error", "HW Fault" };
>> +
>> +static void sahara_decode_status(struct sahara_dev *dev, unsigned int
>> status)
>> +{
>> + u8 state = SAHARA_STATUS_GET_STATE(status);
>
> You can simplify the code a lot if you replace the #ifdef around the function
> with an
>
> if (!IS_ENBLED(DEBUG))
> return;
>
> at the start of the function. That will lead to gcc completely removing the
> code an everything referenced by it.
>
Great. Thank you for the tip.
>> +static void sahara_aes_done_task(unsigned long data)
>> +{
>> + struct sahara_dev *dev = (struct sahara_dev *)data;
>> + unsigned long flags;
>> +
>> + dma_unmap_sg(dev->device, dev->out_sg, dev->nb_out_sg,
>> + DMA_TO_DEVICE);
>> + dma_unmap_sg(dev->device, dev->in_sg, dev->nb_in_sg,
>> + DMA_FROM_DEVICE);
>> +
>> + spin_lock_irqsave(&dev->lock, flags);
>> + clear_bit(FLAGS_BUSY, &dev->flags);
>> + spin_unlock_irqrestore(&dev->lock, flags);
>> +
>> + dev->req->base.complete(&dev->req->base, dev->error);
>> +}
>
> Does dev->lock have to be irq-disabled? You don't seem to take it
> from an interrupt handler.
>
> Also, when you know that code is called without irqs enabled and
> you just want to disable them, you can use the cheaper spin_lock_irq()
> rather than spin_lock_irqsave().
>
> In short, use either spin_lock_irq or spin_lock here. When protecting
> against a tasklet, you will need spin_lock_bh.
You are right, dev->lock is only held by encrypt()/decrypt() callbacks
and some tasklets so spin_lock() and spin_lock_bh() seem suitable
here.
>> +
>> +void sahara_watchdog(unsigned long data)
>> +{
>> + struct sahara_dev *dev = (struct sahara_dev *)data;
>> + unsigned int err = sahara_read(dev, SAHARA_REG_ERRSTATUS);
>> +#ifdef DEBUG
>> + unsigned int stat = sahara_read(dev, SAHARA_REG_STATUS);
>> + sahara_decode_status(dev, stat);
>> +#endif
>
> When you kill off the #ifdef, you should move this sahara_read()
> call into the sahara_decode_status() function so it gets
> compiled conditionally.
>
All right.
>> +static struct platform_device_id sahara_platform_ids[] = {
>> + { .name = "sahara-imx27" },
>> + { /* sentinel */ }
>> +};
>> +MODULE_DEVICE_TABLE(platform, sahara_platform_ids);
>
> You are missing the of_device_ids here. We probably don't even
> need the platform_device_id list and can instead mandate that
> this is only used by platforms that are already converted to
> DT booting.
>
> Please also add a DT binding document for this driver that mentions
> the name and the resources that need to be provided.
Please, take a look at 0/3 to discuss about this matter.
Regards.
--
Javier Martin
Vista Silicon S.L.
CDTUC - FASE C - Oficina S-345
Avda de los Castros s/n
39005- Santander. Cantabria. Spain
+34 942 25 32 60
www.vista-silicon.com
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Re: [PATCH 0/3] crypto: sahara: Add support for SAHARA in i.MX27.
Hi Arnd, On 21 February 2013 13:59, Arnd Bergmann wrote: > On Thursday 21 February 2013, Javier Martin wrote: >> This series of patches provide AES-ECB and AES-CBC support >> for the SAHARA2 cryptographic accelerator which is inside the i.MX27 SoC. >> It is expected that more algorithms will be supported in the future. >> >> For testing, a Visstrim M10 board has been used and the code related >> to this platform has been included too. > > As a new device driver, this needs to be supported on the DT based imx27 > machines, while support for the individual board files seems unnecessary. > > How about converting the Visstrim M10 board file over to DT so you don't > have to add any more infrastructure for imx that we will just have to > remove again one day? We know about the existence of DT and the constant migration process that is taking place towards it. Moreover we are strongly interested in converting the Visstrim SM10 platform to DT. Unfortunately, there are several issues that need to be solved so that Visstrim M10 can be fully converted to DT: - full SoC camera DT support - DT support for ov7670 - pinctrl support for i.MX27 Furthermore, we have limited resources at the moment and we have to decide priorities. But having an hybrid platform-DT support is our next task for Visstrim M10. However, I understand your concern about new drivers having DT support. Maybe a good approach could be that I added compile-tested only DT support for this driver and remove platform support for mainline submission (although we maintain it internally in our repositories). What do you think? Regards. -- Javier Martin Vista Silicon S.L. CDTUC - FASE C - Oficina S-345 Avda de los Castros s/n 39005- Santander. Cantabria. Spain +34 942 25 32 60 www.vista-silicon.com -- To unsubscribe from this list: send the line "unsubscribe linux-crypto" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
[PATCH 2/3] crypto: sahara: Add driver for SAHARA2 accelerator.
SAHARA2 HW module is included in the i.MX27 SoC from Freescale. It is capable of performing cipher algorithms such as AES, 3DES..., hashing and RNG too. This driver provides support for AES-CBC and AES-ECB by now. Signed-off-by: Javier Martin --- drivers/crypto/Kconfig | 10 + drivers/crypto/Makefile |1 + drivers/crypto/sahara.c | 1050 +++ 3 files changed, 1061 insertions(+) create mode 100644 drivers/crypto/sahara.c diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig index 87ec4d0..3a5c597 100644 --- a/drivers/crypto/Kconfig +++ b/drivers/crypto/Kconfig @@ -276,6 +276,16 @@ config CRYPTO_DEV_PICOXCELL Saying m here will build a module named pipcoxcell_crypto. +config CRYPTO_DEV_SAHARA + tristate "Support for SAHARA crypto accelerator" + depends on MACH_MX27 && EXPERIMENTAL + select CRYPTO_BLKCIPHER + select CRYPTO_AES + select CRYPTO_ECB + help + This option enables support for the SAHARA HW crypto accelerator + found in some Freescale i.MX chips. + config CRYPTO_DEV_S5P tristate "Support for Samsung S5PV210 crypto accelerator" depends on ARCH_S5PV210 diff --git a/drivers/crypto/Makefile b/drivers/crypto/Makefile index 880a47b..38ce13d 100644 --- a/drivers/crypto/Makefile +++ b/drivers/crypto/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_CRYPTO_DEV_PPC4XX) += amcc/ obj-$(CONFIG_CRYPTO_DEV_OMAP_SHAM) += omap-sham.o obj-$(CONFIG_CRYPTO_DEV_OMAP_AES) += omap-aes.o obj-$(CONFIG_CRYPTO_DEV_PICOXCELL) += picoxcell_crypto.o +obj-$(CONFIG_CRYPTO_DEV_SAHARA) += sahara.o obj-$(CONFIG_CRYPTO_DEV_S5P) += s5p-sss.o obj-$(CONFIG_CRYPTO_DEV_TEGRA_AES) += tegra-aes.o obj-$(CONFIG_CRYPTO_DEV_UX500) += ux500/ diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c new file mode 100644 index 000..e880029 --- /dev/null +++ b/drivers/crypto/sahara.c @@ -0,0 +1,1050 @@ +/* + * Cryptographic API. + * + * Support for SAHARA cryptographic accelerator. + * + * Copyright (c) 2013 Vista Silicon S.L. + * Author: Javier Martin + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as published + * by the Free Software Foundation. + * + * Based on omap-aes.c and tegra-aes.c + */ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#define SAHARA_NAME "sahara" +#define SAHARA_VERSION_3 3 +#define SAHARA_TIMEOUT_MS 1000 +#define SAHARA_MAX_HW_DESC 2 +#define SAHARA_MAX_HW_LINK 20 + +#define FLAGS_MODE_MASK0x000f +#define FLAGS_ENCRYPT BIT(0) +#define FLAGS_CBC BIT(1) +#define FLAGS_NEW_KEY BIT(3) +#define FLAGS_BUSY 4 + +#define SAHARA_HDR_BASE0x0080 +#define SAHARA_HDR_SKHA_ALG_AES0 +#define SAHARA_HDR_SKHA_OP_ENC (1 << 2) +#define SAHARA_HDR_SKHA_MODE_ECB (0 << 3) +#define SAHARA_HDR_SKHA_MODE_CBC (1 << 3) +#define SAHARA_HDR_FORM_DATA (5 << 16) +#define SAHARA_HDR_FORM_KEY(8 << 16) +#define SAHARA_HDR_LLO (1 << 24) +#define SAHARA_HDR_CHA_SKHA(1 << 28) +#define SAHARA_HDR_CHA_MDHA(2 << 28) +#define SAHARA_HDR_PARITY_BIT (1 << 31) + +/* SAHARA can only process one request at a time */ +#define SAHARA_QUEUE_LENGTH1 + +#define SAHARA_REG_VERSION 0x00 +#define SAHARA_REG_DAR 0x04 +#define SAHARA_REG_CONTROL 0x08 +#defineSAHARA_CONTROL_SET_THROTTLE(x) (((x) & 0xff) << 24) +#defineSAHARA_CONTROL_SET_MAXBURST(x) (((x) & 0xff) << 16) +#defineSAHARA_CONTROL_RNG_AUTORSD (1 << 7) +#defineSAHARA_CONTROL_ENABLE_INT (1 << 4) +#define SAHARA_REG_CMD 0x0C +#defineSAHARA_CMD_RESET(1 << 0) +#defineSAHARA_CMD_CLEAR_INT(1 << 8) +#defineSAHARA_CMD_CLEAR_ERR(1 << 9) +#defineSAHARA_CMD_SINGLE_STEP (1 << 10) +#defineSAHARA_CMD_MODE_BATCH (1 << 16) +#defineSAHARA_CMD_MODE_DEBUG (1 << 18) +#defineSAHARA_REG_STATUS 0x10 +#defineSAHARA_STATUS_GET_STATE(x) ((x) & 0x7) +#defineSAHARA_STATE_IDLE 0 +#defineSAHARA_STATE_BUSY 1 +#defineSAHARA_STATE_ERR2 +#defineSAHARA_STATE_FAULT 3 +#defineSAHARA_STATE_COMPLETE 4 +#defineSAHARA_STATE_COMP_FLAG (1 << 2) +#defineSAHARA_STATUS_DAR_FULL (1 <<
[PATCH 3/3] Visstrim M10: Add support for SAHARA2 module.
Signed-off-by: Javier Martin
---
arch/arm/mach-imx/Kconfig |1 +
arch/arm/mach-imx/mach-imx27_visstrim_m10.c |1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 1ad0d76..d232a56 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -402,6 +402,7 @@ config MACH_IMX27_VISSTRIM_M10
select IMX_HAVE_PLATFORM_IMX_UART
select IMX_HAVE_PLATFORM_MX2_CAMERA
select IMX_HAVE_PLATFORM_MX2_EMMA
+ select IMX_HAVE_PLATFORM_IMX27_SAHARA
select IMX_HAVE_PLATFORM_MXC_EHCI
select IMX_HAVE_PLATFORM_MXC_MMC
select LEDS_GPIO_REGISTER
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index 318bd8d..b051592 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -565,6 +565,7 @@ static void __init visstrim_m10_board_init(void)
imx27_add_mxc_mmc(0, &visstrim_m10_sdhc_pdata);
imx27_add_mxc_ehci_otg(&visstrim_m10_usbotg_pdata);
imx27_add_fec(NULL);
+ imx27_add_sahara();
imx_add_gpio_keys(&visstrim_gpio_keys_platform_data);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
imx_add_platform_device("mx27vis", 0, NULL, 0, &snd_mx27vis_pdata,
--
1.7.9.5
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[PATCH 1/3] i.MX27: Add platform support for SAHARA2.
i.MX27 devices include this HW cryptographic
accelerator.
Signed-off-by: Javier Martin
---
arch/arm/mach-imx/clk-imx27.c |2 ++
arch/arm/mach-imx/devices-imx27.h |4 +++
arch/arm/mach-imx/devices/Kconfig |4 +++
arch/arm/mach-imx/devices/Makefile|1 +
arch/arm/mach-imx/devices/devices-common.h|8 +
arch/arm/mach-imx/devices/platform-imx27-sahara.c | 37 +
6 files changed, 56 insertions(+)
create mode 100644 arch/arm/mach-imx/devices/platform-imx27-sahara.c
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index 4c1d1e4..0b9664a 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -253,6 +253,8 @@ int __init mx27_clocks_init(unsigned long fref)
clk_register_clkdev(clk[nfc_baud_gate], NULL, "imx27-nand.0");
clk_register_clkdev(clk[vpu_baud_gate], "per", "coda-imx27.0");
clk_register_clkdev(clk[vpu_ahb_gate], "ahb", "coda-imx27.0");
+ clk_register_clkdev(clk[sahara_ahb_gate], "ahb", "sahara-imx27.0");
+ clk_register_clkdev(clk[sahara_ipg_gate], "ipg", "sahara-imx27.0");
clk_register_clkdev(clk[dma_ahb_gate], "ahb", "imx27-dma");
clk_register_clkdev(clk[dma_ipg_gate], "ipg", "imx27-dma");
clk_register_clkdev(clk[fec_ipg_gate], "ipg", "imx27-fec.0");
diff --git a/arch/arm/mach-imx/devices-imx27.h
b/arch/arm/mach-imx/devices-imx27.h
index 1309625..3bc95d8 100644
--- a/arch/arm/mach-imx/devices-imx27.h
+++ b/arch/arm/mach-imx/devices-imx27.h
@@ -20,6 +20,10 @@ extern const struct imx_imx27_coda_data imx27_coda_data;
#define imx27_add_coda() \
imx_add_imx27_coda(&imx27_coda_data)
+extern const struct imx_imx27_sahara_data imx27_sahara_data;
+#define imx27_add_sahara() \
+ imx_add_imx27_sahara(&imx27_sahara_data)
+
extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data;
#define imx27_add_imx2_wdt() \
imx_add_imx2_wdt(&imx27_imx2_wdt_data)
diff --git a/arch/arm/mach-imx/devices/Kconfig
b/arch/arm/mach-imx/devices/Kconfig
index 9a8f1ca..3edaa8d 100644
--- a/arch/arm/mach-imx/devices/Kconfig
+++ b/arch/arm/mach-imx/devices/Kconfig
@@ -20,6 +20,10 @@ config IMX_HAVE_PLATFORM_IMX27_CODA
bool
default y if SOC_IMX27
+config IMX_HAVE_PLATFORM_IMX27_SAHARA
+ bool
+ default y if SOC_IMX27
+
config IMX_HAVE_PLATFORM_IMX2_WDT
bool
diff --git a/arch/arm/mach-imx/devices/Makefile
b/arch/arm/mach-imx/devices/Makefile
index 6acf37e..f5534a2 100644
--- a/arch/arm/mach-imx/devices/Makefile
+++ b/arch/arm/mach-imx/devices/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) +=
platform-gpio_keys.o
obj-y += platform-gpio-mxc.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX27_CODA) += platform-imx27-coda.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX27_SAHARA) += platform-imx27-sahara.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMXDI_RTC) += platform-imxdi_rtc.o
obj-y += platform-imx-dma.o
diff --git a/arch/arm/mach-imx/devices/devices-common.h
b/arch/arm/mach-imx/devices/devices-common.h
index 6277baf..48065b2 100644
--- a/arch/arm/mach-imx/devices/devices-common.h
+++ b/arch/arm/mach-imx/devices/devices-common.h
@@ -91,6 +91,14 @@ struct imx_imx27_coda_data {
struct platform_device *__init imx_add_imx27_coda(
const struct imx_imx27_coda_data *data);
+struct imx_imx27_sahara_data {
+ resource_size_t iobase;
+ resource_size_t iosize;
+ resource_size_t irq;
+};
+struct platform_device *__init imx_add_imx27_sahara(
+ const struct imx_imx27_sahara_data *data);
+
struct imx_imx2_wdt_data {
int id;
resource_size_t iobase;
diff --git a/arch/arm/mach-imx/devices/platform-imx27-sahara.c
b/arch/arm/mach-imx/devices/platform-imx27-sahara.c
new file mode 100644
index 000..94288f4
--- /dev/null
+++ b/arch/arm/mach-imx/devices/platform-imx27-sahara.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2012 Vista Silicon
+ * Javier Martin
+ *
+ * This program is free software; you can redistribute it and/or modify it
under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+
+#include "../hardware.h"
+#include "devices-common.h"
+
+#ifdef CONFIG_SOC_IMX27
+const struct imx_imx27_sahara_data imx27_sahara_data __initconst = {
+ .iobase = MX27_SAHARA_BASE_ADDR,
+ .iosize = SZ_2K,
+ .irq = MX27_INT_SAHARA,
+};
+#endif
+
+struct platform_device *__init imx_add_imx27_sahara(
+ const struct imx_imx27_sahara_data *data)
+{
+ struct resource res[
[PATCH 0/3] crypto: sahara: Add support for SAHARA in i.MX27.
This series of patches provide AES-ECB and AES-CBC support for the SAHARA2 cryptographic accelerator which is inside the i.MX27 SoC. It is expected that more algorithms will be supported in the future. For testing, a Visstrim M10 board has been used and the code related to this platform has been included too. [PATCH 1/3] i.MX27: Add platform support for SAHARA2. [PATCH 2/3] crypto: sahara: Add driver for SAHARA2 accelerator. [PATCH 3/3] Visstrim M10: Add support for SAHARA2 module. -- To unsubscribe from this list: send the line "unsubscribe linux-crypto" in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
