[PATCH v2 2/3] dmaengine: xgene-dma: Add support for CRC32C computations via DMA engine

2015-11-16 Thread rsahu 
From: Rameshwar Prasad Sahu 

This patch implements CRC32C support to APM X-Gene SoC DMA engine driver.
Basically we have DMA engine in SoC capable of doing CRC32C computations.

Signed-off-by: Rameshwar Prasad Sahu 
---
 drivers/dma/xgene-dma.c |  314 ---
 1 files changed, 299 insertions(+), 15 deletions(-)

diff --git a/drivers/dma/xgene-dma.c b/drivers/dma/xgene-dma.c
index 9dfa2b0..d95dc72 100644
--- a/drivers/dma/xgene-dma.c
+++ b/drivers/dma/xgene-dma.c
@@ -22,6 +22,7 @@
  */

 #include 
+#include 
 #include 
 #include 
 #include 
@@ -39,6 +40,7 @@
 #define XGENE_DMA_RING_ENABLE  BIT(31)
 #define XGENE_DMA_RING_ID  0x08
 #define XGENE_DMA_RING_ID_SETUP(v) ((v) | BIT(31))
+#define XGENE_DMA_RING_IS_BUFPOOL  BIT(20)
 #define XGENE_DMA_RING_ID_BUF  0x0C
 #define XGENE_DMA_RING_ID_BUF_SETUP(v) (((v) << 9) | BIT(21))
 #define XGENE_DMA_RING_THRESLD0_SET1   0x30
@@ -69,6 +71,8 @@
(((u32 *)(m))[2] |= (((v) >> 8) << 5))
 #define XGENE_DMA_RING_ADDRH_SET(m, v) \
(((u32 *)(m))[3] |= ((v) >> 35))
+#define XGENE_DMA_RING_BUFMODE_SET(m)  \
+   (((u32 *)(m))[3] |= ((0x3) << 20))
 #define XGENE_DMA_RING_ACCEPTLERR_SET(m)   \
(((u32 *)(m))[3] |= BIT(19))
 #define XGENE_DMA_RING_SIZE_SET(m, v)  \
@@ -106,6 +110,7 @@
 #define XGENE_DMA_RING_INT2_MASK   0x90B0
 #define XGENE_DMA_RING_INT3_MASK   0x90B8
 #define XGENE_DMA_RING_INT4_MASK   0x90C0
+#define XGENE_DMA_CFG_RING_FQ_ASSOC0x90DC
 #define XGENE_DMA_CFG_RING_WQ_ASSOC0x90E0
 #define XGENE_DMA_ASSOC_RING_MNGR1 0x
 #define XGENE_DMA_MEM_RAM_SHUTDOWN 0xD070
@@ -127,6 +132,10 @@
 #define XGENE_DMA_DESC_LERR_POS60
 #define XGENE_DMA_DESC_BUFLEN_POS  48
 #define XGENE_DMA_DESC_HOENQ_NUM_POS   48
+#define XGENE_DMA_DESC_BD_BIT  BIT(0)
+#define XGENE_DMA_DESC_SD_BIT  BIT(1)
+#define XGENE_DMA_DESC_CRCSEED_POS 8
+#define XGENE_DMA_DESC_FPQ_NUM_POS 32
 #define XGENE_DMA_DESC_ELERR_RD(m) \
(((m) >> XGENE_DMA_DESC_ELERR_POS) & 0x3)
 #define XGENE_DMA_DESC_LERR_RD(m)  \
@@ -140,20 +149,25 @@
 /* X-Gene DMA configurable parameters defines */
 #define XGENE_DMA_RING_NUM 512
 #define XGENE_DMA_BUFNUM   0x0
+#define XGENE_DMA_BUFPOOL_BUFNUM   0x20
 #define XGENE_DMA_CPU_BUFNUM   0x18
 #define XGENE_DMA_RING_OWNER_DMA   0x03
 #define XGENE_DMA_RING_OWNER_CPU   0x0F
 #define XGENE_DMA_RING_TYPE_REGULAR0x01
+#define XGENE_DMA_RING_TYPE_BUFPOOL0x02
 #define XGENE_DMA_RING_WQ_DESC_SIZE32  /* 32 Bytes */
+#define XGENE_DMA_BUFPOOL_DESC_SIZE16  /* 16 Bytes */
 #define XGENE_DMA_RING_NUM_CONFIG  5
 #define XGENE_DMA_MAX_CHANNEL  4
 #define XGENE_DMA_XOR_CHANNEL  0
 #define XGENE_DMA_PQ_CHANNEL   1
+#define XGENE_DMA_FLYBY_CHANNEL2
 #define XGENE_DMA_MAX_BYTE_CNT 0x4000  /* 16 KB */
 #define XGENE_DMA_MAX_64B_DESC_BYTE_CNT0x14000 /* 80 KB */
 #define XGENE_DMA_MAX_XOR_SRC  5
 #define XGENE_DMA_16K_BUFFER_LEN_CODE  0x0
 #define XGENE_DMA_INVALID_LEN_CODE 0x7800ULL
+#define XGENE_DMA_MAX_FLYBY_BYTE_CNT   0x7FFF  /* (32 KB - 1) */

 /* X-Gene DMA descriptor error codes */
 #define ERR_DESC_AXI   0x01
@@ -187,9 +201,14 @@
 #define FLYBY_3SRC_XOR 0x90
 #define FLYBY_4SRC_XOR 0xA0
 #define FLYBY_5SRC_XOR 0xB0
+#define FLYBY_CRC160x10
+#define FLYBY_CRC32C   0x20
+#define FLYBY_CRC320x30
+#define FLYBY_CHECKSUM 0x40

 /* X-Gene DMA SW descriptor flags */
 #define XGENE_DMA_FLAG_64B_DESCBIT(0)
+#define XGENE_DMA_FLAG_FLYBY_ACTIVEBIT(1)

 /* Define to dump X-Gene DMA descriptor */
 #define XGENE_DMA_DESC_DUMP(desc, m)   \
@@ -206,6 +225,11 @@
 #define chan_err(chan, fmt, arg...)\
dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)

+struct xgene_dma_desc16 {
+   __le64 m0;
+   __le64 m1;
+};
+
 struct xgene_dma_desc_hw {
__le64 m0;
__le64 m1;
@@ -232,6 +256,7 @@ struct xgene_dma_ring {
u16 slots;
u16 dst_ring_num;
u32 size;
+   bool is_bufpool;
void __iomem *cmd;
void __iomem *cmd_base;
dma_addr_t desc_paddr;
@@ -239,6 +264,7 @@ struct xgene_dma_ring {
enum xgene_dma_ring_cfgsize cfgsize;
union {
void *desc_vaddr;
+   struct xgene_dma_desc16 *desc16;
struct xgene_dma_desc_hw *desc_hw;
};
 };
@@ -247,6 +273,7 @@ struct xgene_dma_desc_sw {
struct xgene_dma_desc_hw desc1;
struct

[PATCH v2 2/3] dmaengine: xgene-dma: Add support for CRC32C computations via DMA engine

2015-11-07 Thread Rameshwar Prasad Sahu 
This patch implements CRC32C support to APM X-Gene SoC DMA engine driver.
Basically we have DMA engine in SoC capable of doing CRC32C computations.

Signed-off-by: Rameshwar Prasad Sahu 
---
 drivers/dma/xgene-dma.c |  314 ---
 1 files changed, 299 insertions(+), 15 deletions(-)

diff --git a/drivers/dma/xgene-dma.c b/drivers/dma/xgene-dma.c
index 9dfa2b0..d95dc72 100644
--- a/drivers/dma/xgene-dma.c
+++ b/drivers/dma/xgene-dma.c
@@ -22,6 +22,7 @@
  */

 #include 
+#include 
 #include 
 #include 
 #include 
@@ -39,6 +40,7 @@
 #define XGENE_DMA_RING_ENABLE  BIT(31)
 #define XGENE_DMA_RING_ID  0x08
 #define XGENE_DMA_RING_ID_SETUP(v) ((v) | BIT(31))
+#define XGENE_DMA_RING_IS_BUFPOOL  BIT(20)
 #define XGENE_DMA_RING_ID_BUF  0x0C
 #define XGENE_DMA_RING_ID_BUF_SETUP(v) (((v) << 9) | BIT(21))
 #define XGENE_DMA_RING_THRESLD0_SET1   0x30
@@ -69,6 +71,8 @@
(((u32 *)(m))[2] |= (((v) >> 8) << 5))
 #define XGENE_DMA_RING_ADDRH_SET(m, v) \
(((u32 *)(m))[3] |= ((v) >> 35))
+#define XGENE_DMA_RING_BUFMODE_SET(m)  \
+   (((u32 *)(m))[3] |= ((0x3) << 20))
 #define XGENE_DMA_RING_ACCEPTLERR_SET(m)   \
(((u32 *)(m))[3] |= BIT(19))
 #define XGENE_DMA_RING_SIZE_SET(m, v)  \
@@ -106,6 +110,7 @@
 #define XGENE_DMA_RING_INT2_MASK   0x90B0
 #define XGENE_DMA_RING_INT3_MASK   0x90B8
 #define XGENE_DMA_RING_INT4_MASK   0x90C0
+#define XGENE_DMA_CFG_RING_FQ_ASSOC0x90DC
 #define XGENE_DMA_CFG_RING_WQ_ASSOC0x90E0
 #define XGENE_DMA_ASSOC_RING_MNGR1 0x
 #define XGENE_DMA_MEM_RAM_SHUTDOWN 0xD070
@@ -127,6 +132,10 @@
 #define XGENE_DMA_DESC_LERR_POS60
 #define XGENE_DMA_DESC_BUFLEN_POS  48
 #define XGENE_DMA_DESC_HOENQ_NUM_POS   48
+#define XGENE_DMA_DESC_BD_BIT  BIT(0)
+#define XGENE_DMA_DESC_SD_BIT  BIT(1)
+#define XGENE_DMA_DESC_CRCSEED_POS 8
+#define XGENE_DMA_DESC_FPQ_NUM_POS 32
 #define XGENE_DMA_DESC_ELERR_RD(m) \
(((m) >> XGENE_DMA_DESC_ELERR_POS) & 0x3)
 #define XGENE_DMA_DESC_LERR_RD(m)  \
@@ -140,20 +149,25 @@
 /* X-Gene DMA configurable parameters defines */
 #define XGENE_DMA_RING_NUM 512
 #define XGENE_DMA_BUFNUM   0x0
+#define XGENE_DMA_BUFPOOL_BUFNUM   0x20
 #define XGENE_DMA_CPU_BUFNUM   0x18
 #define XGENE_DMA_RING_OWNER_DMA   0x03
 #define XGENE_DMA_RING_OWNER_CPU   0x0F
 #define XGENE_DMA_RING_TYPE_REGULAR0x01
+#define XGENE_DMA_RING_TYPE_BUFPOOL0x02
 #define XGENE_DMA_RING_WQ_DESC_SIZE32  /* 32 Bytes */
+#define XGENE_DMA_BUFPOOL_DESC_SIZE16  /* 16 Bytes */
 #define XGENE_DMA_RING_NUM_CONFIG  5
 #define XGENE_DMA_MAX_CHANNEL  4
 #define XGENE_DMA_XOR_CHANNEL  0
 #define XGENE_DMA_PQ_CHANNEL   1
+#define XGENE_DMA_FLYBY_CHANNEL2
 #define XGENE_DMA_MAX_BYTE_CNT 0x4000  /* 16 KB */
 #define XGENE_DMA_MAX_64B_DESC_BYTE_CNT0x14000 /* 80 KB */
 #define XGENE_DMA_MAX_XOR_SRC  5
 #define XGENE_DMA_16K_BUFFER_LEN_CODE  0x0
 #define XGENE_DMA_INVALID_LEN_CODE 0x7800ULL
+#define XGENE_DMA_MAX_FLYBY_BYTE_CNT   0x7FFF  /* (32 KB - 1) */

 /* X-Gene DMA descriptor error codes */
 #define ERR_DESC_AXI   0x01
@@ -187,9 +201,14 @@
 #define FLYBY_3SRC_XOR 0x90
 #define FLYBY_4SRC_XOR 0xA0
 #define FLYBY_5SRC_XOR 0xB0
+#define FLYBY_CRC160x10
+#define FLYBY_CRC32C   0x20
+#define FLYBY_CRC320x30
+#define FLYBY_CHECKSUM 0x40

 /* X-Gene DMA SW descriptor flags */
 #define XGENE_DMA_FLAG_64B_DESCBIT(0)
+#define XGENE_DMA_FLAG_FLYBY_ACTIVEBIT(1)

 /* Define to dump X-Gene DMA descriptor */
 #define XGENE_DMA_DESC_DUMP(desc, m)   \
@@ -206,6 +225,11 @@
 #define chan_err(chan, fmt, arg...)\
dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)

+struct xgene_dma_desc16 {
+   __le64 m0;
+   __le64 m1;
+};
+
 struct xgene_dma_desc_hw {
__le64 m0;
__le64 m1;
@@ -232,6 +256,7 @@ struct xgene_dma_ring {
u16 slots;
u16 dst_ring_num;
u32 size;
+   bool is_bufpool;
void __iomem *cmd;
void __iomem *cmd_base;
dma_addr_t desc_paddr;
@@ -239,6 +264,7 @@ struct xgene_dma_ring {
enum xgene_dma_ring_cfgsize cfgsize;
union {
void *desc_vaddr;
+   struct xgene_dma_desc16 *desc16;
struct xgene_dma_desc_hw *desc_hw;
};
 };
@@ -247,6 +273,7 @@ struct xgene_dma_desc_sw {
struct xgene_dma_desc_hw desc1;
struct xgene_dma_desc_hw desc2;
u32 flags;
+   u8