Re: [PATCH Documentation/memory-barriers.txt] Clarify limited control-dependency scope

[Paul E. McKenney]

On Fri, Jun 17, 2016 at 09:53:50AM +0200, Ingo Molnar wrote:
> 
> * Paul E. McKenney  wrote:
> 
> > Nothing in the control-dependencies section of memory-barriers.txt
> > says that control dependencies don't extend beyond the end of the
> > if-statement containing the control dependency.  Worse yet, in many
> > situations, they do extend beyond that if-statement.  In particular,
> > the compiler cannot destroy the control dependency given proper use of
> > READ_ONCE() and WRITE_ONCE().  However, a weakly ordered system having
> > a conditional-move instruction provides the control-dependency guarantee
> > only to code within the scope of the if-statement itself.
> > 
> > This commit therefore adds words and an example demonstrating this
> > limitation of control dependencies.
> > 
> > Reported-by: Will Deacon 
> > Signed-off-by: Paul E. McKenney 
> > Acked-by: Peter Zijlstra (Intel) 
> > 
> > diff --git a/Documentation/memory-barriers.txt 
> > b/Documentation/memory-barriers.txt
> > index 147ae8ec836f..a4d0a99de04d 100644
> > --- a/Documentation/memory-barriers.txt
> > +++ b/Documentation/memory-barriers.txt
> > @@ -806,6 +806,41 @@ out-guess your code.  More generally, although 
> > READ_ONCE() does force
> >  the compiler to actually emit code for a given load, it does not force
> >  the compiler to use the results.
> >  
> > +In addition, control dependencies apply only to the then-clause and
> > +else-clause of the if-statement in question.  In particular, it does
> > +not necessarily apply to code following the if-statement:
> > +
> > +   q = READ_ONCE(a);
> > +   if (q) {
> > +   WRITE_ONCE(b, p);
> > +   } else {
> > +   WRITE_ONCE(b, r);
> > +   }
> > +   WRITE_ONCE(c, 1);  /* BUG: No ordering against the read from "a". */
> > +
> > +It is tempting to argue that there in fact is ordering because the
> > +compiler cannot reorder volatile accesses and also cannot reorder
> > +the writes to "b" with the condition.  Unfortunately for this line
> > +of reasoning, the compiler might compile the two writes to "b" as
> > +conditional-move instructions, as in this fanciful pseudo-assembly
> > +language:
> 
> While CMOV would be the typical situation, even without CMOV the compiler 
> could 
> also internally transform it to:
> 
> > +   if (q)
> > +   WRITE_ONCE(b, p);
> > +   if (!q)
> > +   WRITE_ONCE(b, r);
> 
> ... and CPU speculation flow could get past the two branches without seeing 
> any 
> ordering constraint with the writes to 'b'.
> 
> I.e. conditions are not 'atomic', they can be 'torn' by the compiler just as 
> much 
> as reads or writes can be torn.

That is an interesting test case!

PowerPC prohibits speculating the writes in your transformed case, that is,
prohibits the writes to "b" from being reordered with the read from "a".
I believe that ARM also prohibits it in that case, but must defer to
Will Deacon.  Not sure about MIPS.

Or am I misunderstanding your intent with that example?

Thanx, Paul

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[RFC nowrap: PATCH v7 00/19] ILP32 for ARM64

[Yury Norov]

This series enables aarch64 with ilp32 mode, and as supporting work,
introduces ARCH_32BIT_OFF_T configuration option that is enabled for
existing 32-bit architectures but disabled for new arches (so 64-bit
off_t is is used by new userspace).

This version is based on kernel v4.7-rc3.
It works with glibc-2.23, and tested with LTP.

This is RFC because there is no solid understanding what type of registers
top-halves delousing we prefer. In this patchset, w0-w7 are cleared for each
syscall in assembler entry. The alternative approach is in introducing compat
wrappers which is little faster for natively routed syscalls (~2.6% for syscall
with no payload) but much more complicated.

v3: https://lkml.org/lkml/2014/9/3/704
v4: https://lkml.org/lkml/2015/4/13/691
v5: https://lkml.org/lkml/2015/9/29/911
v6: https://lkml.org/lkml/2016/5/23/661
v7: RFC nowrap:
 - wrappers removed, unconditional register delousing is introduced.
 - ino_t, off_t etc are turned to 64-bit.
 - added is_compat_thread(),
 - fixed ilp32 ELF_PLATFORM MACRO,
 - fixed ilp32 ELF_DYN_BASE,
 - ptrace redirected to compat version.
 - stat, statfs - related syscalls are redirected to native handlers.
 - elf_greg_t and elf_gregset_t types are taken from lp64.
 - Documentation updated.

Links:
This series:https://github.com/norov/linux/commits/ilp32-nowrap
v7 with wrappers:   https://github.com/norov/linux/commits/ilp32
glibc (dirty):  https://github.com/norov/glibc/commits/ilp32-nowrap
glibc with wrappers:https://github.com/norov/glibc/commits/ilp32-dev

Andrew Pinski (6):
  arm64: ensure the kernel is compiled for LP64
  arm64: rename COMPAT to AARCH32_EL0 in Kconfig
  arm64:uapi: set __BITS_PER_LONG correctly for ILP32 and LP64
  arm64: ilp32: add sys_ilp32.c and a separate table (in entry.S) to use it
  arm64: ilp32: introduce ilp32-specific handlers for sigframe and ucontext
  arm64:ilp32: add ARM64_ILP32 to Kconfig

Philipp Tomsich (1):
  arm64:ilp32: add vdso-ilp32 and use for signal return

Yury Norov (12):
  compat ABI: use non-compat openat and open_by_handle_at variants
  32-bit ABI: introduce ARCH_32BIT_OFF_T config option
  arm64: ilp32: add documentation on the ILP32 ABI for ARM64
  thread: move thread bits accessors to separated file
  arm64: introduce is_a32_task and is_a32_thread (for AArch32 compat)
  arm64: ilp32: add is_ilp32_compat_{task,thread} and TIF_32BIT_AARCH64
  arm64: introduce binfmt_elf32.c
  arm64: ilp32: introduce binfmt_ilp32.c
  arm64: ptrace: handle ptrace_request differently for aarch32 and ilp32
  arm64: ilp32: share aarch32 syscall handlers
  arm64: signal: share lp64 signal routines to ilp32
  arm64: signal32: move ilp32 and aarch32 common code to separated file

 Documentation/arm64/ilp32.txt |  54 +++
 arch/Kconfig  |   4 +
 arch/arc/Kconfig  |   1 +
 arch/arm/Kconfig  |   1 +
 arch/arm64/Kconfig|  19 ++-
 arch/arm64/Makefile   |   5 +
 arch/arm64/include/asm/compat.h   |  19 +--
 arch/arm64/include/asm/elf.h  |  29 +++-
 arch/arm64/include/asm/fpsimd.h   |   2 +-
 arch/arm64/include/asm/ftrace.h   |   2 +-
 arch/arm64/include/asm/hwcap.h|   6 +-
 arch/arm64/include/asm/is_compat.h|  90 
 arch/arm64/include/asm/memory.h   |   5 +-
 arch/arm64/include/asm/processor.h|  11 +-
 arch/arm64/include/asm/ptrace.h   |   2 +-
 arch/arm64/include/asm/signal32.h |   6 +-
 arch/arm64/include/asm/signal32_common.h  |  25 
 arch/arm64/include/asm/signal_common.h|  33 +
 arch/arm64/include/asm/signal_ilp32.h |  34 +
 arch/arm64/include/asm/syscall.h  |   2 +-
 arch/arm64/include/asm/thread_info.h  |   4 +-
 arch/arm64/include/asm/unistd.h   |   6 +-
 arch/arm64/include/asm/unistd32.h |   2 +-
 arch/arm64/include/asm/vdso.h |   6 +
 arch/arm64/include/uapi/asm/bitsperlong.h |   9 +-
 arch/arm64/kernel/Makefile|  14 +-
 arch/arm64/kernel/asm-offsets.c   |   9 +-
 arch/arm64/kernel/binfmt_elf32.c  |  31 
 arch/arm64/kernel/binfmt_ilp32.c  |  96 +
 arch/arm64/kernel/cpufeature.c|   8 +-
 arch/arm64/kernel/cpuinfo.c   |  20 +--
 arch/arm64/kernel/entry.S |  35 -
 arch/arm64/kernel/entry32.S   |  65 -
 arch/arm64/kernel/entry32_common.S|  93 
 arch/arm64/kernel/entry_ilp32.S   |  23 +++
 arch/arm64/kernel/head.S  |   2 +-
 arch/arm64/kernel/hw_breakpoint.c |  10 +-
 arch/arm64/kernel/perf_regs.c |   2 +-
 arch/arm64/kernel/process.c  

[PATCH 02/19] 32-bit ABI: introduce ARCH_32BIT_OFF_T config option

[Yury Norov]

All new 32-bit architectures should have 64-bit off_t type, but existing
architectures has 32-bit ones.

To handle it, new config option is added to arch/Kconfig that defaults
ARCH_32BIT_OFF_T to be disabled for non-64 bit architectures. All existing
32-bit architectures enable it explicitly here.

New option affects force_o_largefile() behaviour. Namely, if off_t is
64-bits long, we have no reason to reject user to open big files.

Note that even if architectures has only 64-bit off_t in the kernel
(arc, c6x, h8300, hexagon, metag, nios2, openrisc, tile32 and unicore32),
a libc may use 32-bit off_t, and therefore want to limit the file size
to 4GB unless specified differently in the open flags.

Signed-off-by: Yury Norov 
---
 arch/Kconfig| 4 
 arch/arc/Kconfig| 1 +
 arch/arm/Kconfig| 1 +
 arch/blackfin/Kconfig   | 1 +
 arch/cris/Kconfig   | 1 +
 arch/frv/Kconfig| 1 +
 arch/h8300/Kconfig  | 1 +
 arch/hexagon/Kconfig| 1 +
 arch/m32r/Kconfig   | 1 +
 arch/m68k/Kconfig   | 1 +
 arch/metag/Kconfig  | 1 +
 arch/microblaze/Kconfig | 1 +
 arch/mips/Kconfig   | 1 +
 arch/mn10300/Kconfig| 1 +
 arch/nios2/Kconfig  | 1 +
 arch/openrisc/Kconfig   | 1 +
 arch/parisc/Kconfig | 1 +
 arch/powerpc/Kconfig| 1 +
 arch/score/Kconfig  | 1 +
 arch/sh/Kconfig | 1 +
 arch/sparc/Kconfig  | 1 +
 arch/tile/Kconfig   | 1 +
 arch/unicore32/Kconfig  | 1 +
 arch/x86/Kconfig| 1 +
 arch/x86/um/Kconfig | 1 +
 arch/xtensa/Kconfig | 1 +
 include/linux/fcntl.h   | 2 +-
 27 files changed, 30 insertions(+), 1 deletion(-)

diff --git a/arch/Kconfig b/arch/Kconfig
index d794384..fdfc4ad 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -234,6 +234,10 @@ config ARCH_THREAD_INFO_ALLOCATOR
 config ARCH_WANTS_DYNAMIC_TASK_STRUCT
bool
 
+config ARCH_32BIT_OFF_T
+   bool
+   depends on !64BIT
+
 config HAVE_REGS_AND_STACK_ACCESS_API
bool
help
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 0d3e59f..d5ca749 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -9,6 +9,7 @@
 config ARC
def_bool y
select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
+   select ARCH_32BIT_OFF_T
select BUILDTIME_EXTABLE_SORT
select CLKSRC_OF
select CLONE_BACKWARDS
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 90542db..d84122a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1,6 +1,7 @@
 config ARM
bool
default y
+   select ARCH_32BIT_OFF_T
select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
select ARCH_HAS_DEVMEM_IS_ALLOWED
select ARCH_HAS_ELF_RANDOMIZE
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index 28c63fe..097e7a5 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -12,6 +12,7 @@ config RWSEM_XCHGADD_ALGORITHM
 
 config BLACKFIN
def_bool y
+   select ARCH_32BIT_OFF_T
select HAVE_ARCH_KGDB
select HAVE_ARCH_TRACEHOOK
select HAVE_DYNAMIC_FTRACE
diff --git a/arch/cris/Kconfig b/arch/cris/Kconfig
index deba266..b1376a9 100644
--- a/arch/cris/Kconfig
+++ b/arch/cris/Kconfig
@@ -50,6 +50,7 @@ config LOCKDEP_SUPPORT
 config CRIS
bool
default y
+   select ARCH_32BIT_OFF_T
select HAVE_IDE
select GENERIC_ATOMIC64
select HAVE_UID16
diff --git a/arch/frv/Kconfig b/arch/frv/Kconfig
index eefd9a4..2f14904 100644
--- a/arch/frv/Kconfig
+++ b/arch/frv/Kconfig
@@ -1,6 +1,7 @@
 config FRV
bool
default y
+   select ARCH_32BIT_OFF_T
select HAVE_IDE
select HAVE_ARCH_TRACEHOOK
select HAVE_PERF_EVENTS
diff --git a/arch/h8300/Kconfig b/arch/h8300/Kconfig
index 3ae8525..29bbcb1 100644
--- a/arch/h8300/Kconfig
+++ b/arch/h8300/Kconfig
@@ -1,5 +1,6 @@
 config H8300
 def_bool y
+   select ARCH_32BIT_OFF_T
select GENERIC_ATOMIC64
select HAVE_UID16
select VIRT_TO_BUS
diff --git a/arch/hexagon/Kconfig b/arch/hexagon/Kconfig
index 57298e7..df84602 100644
--- a/arch/hexagon/Kconfig
+++ b/arch/hexagon/Kconfig
@@ -3,6 +3,7 @@ comment "Linux Kernel Configuration for Hexagon"
 
 config HEXAGON
def_bool y
+   select ARCH_32BIT_OFF_T
select HAVE_OPROFILE
# Other pending projects/to-do items.
# select HAVE_REGS_AND_STACK_ACCESS_API
diff --git a/arch/m32r/Kconfig b/arch/m32r/Kconfig
index 3cc8498..efa10d3 100644
--- a/arch/m32r/Kconfig
+++ b/arch/m32r/Kconfig
@@ -1,6 +1,7 @@
 config M32R
bool
default y
+   select ARCH_32BIT_OFF_T
select HAVE_IDE
select HAVE_OPROFILE
select INIT_ALL_POSSIBLE
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index 498b567..e9897e4 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -1,6 +1,7 @@
 config M68K
bool
default y
+   select ARCH_32BIT_OFF_T
select ARCH_MIGHT_HAVE_PC_PARPORT if ISA
select 

[PATCH 05/19] arm64: rename COMPAT to AARCH32_EL0 in Kconfig

[Yury Norov]

From: Andrew Pinski 

In this patchset  ILP32 ABI support is added. Additionally to AARCH32,
which is binary-compatible with ARM, ILP32 is (mostly) ABI-compatible.

>From now, AARCH32_EL0 (former COMPAT) config option means the support of
AARCH32 userspace, ARM64_ILP32 - support of ILP32 ABI (see next patches),
and COMPAT indicates that one of them, or both, is enabled.

Where needed, CONFIG_COMPAT is changed over to use CONFIG_AARCH32_EL0 instead

Reviewed-by: David Daney 
Signed-off-by: Andrew Pinski 
Signed-off-by: Philipp Tomsich 
Signed-off-by: Christoph Muellner 
Signed-off-by: Bamvor Jian Zhang 
Signed-off-by: Yury Norov 
---
 arch/arm64/Kconfig   | 10 --
 arch/arm64/include/asm/fpsimd.h  |  2 +-
 arch/arm64/include/asm/hwcap.h   |  4 ++--
 arch/arm64/include/asm/processor.h   |  6 +++---
 arch/arm64/include/asm/ptrace.h  |  2 +-
 arch/arm64/include/asm/signal32.h|  6 --
 arch/arm64/include/asm/unistd.h  |  2 +-
 arch/arm64/kernel/Makefile   |  2 +-
 arch/arm64/kernel/asm-offsets.c  |  2 +-
 arch/arm64/kernel/cpufeature.c   |  8 
 arch/arm64/kernel/cpuinfo.c  | 20 +++-
 arch/arm64/kernel/entry.S|  6 +++---
 arch/arm64/kernel/head.S |  2 +-
 arch/arm64/kernel/ptrace.c   |  8 
 arch/arm64/kernel/traps.c|  2 +-
 arch/arm64/kernel/vdso.c |  4 ++--
 drivers/clocksource/arm_arch_timer.c |  2 +-
 17 files changed, 49 insertions(+), 39 deletions(-)

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 5a0a691..aea8e61 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -385,7 +385,7 @@ config ARM64_ERRATUM_834220
 
 config ARM64_ERRATUM_845719
bool "Cortex-A53: 845719: a load might read incorrect data"
-   depends on COMPAT
+   depends on AARCH32_EL0
default y
help
  This option adds an alternative code sequence to work around ARM
@@ -701,7 +701,7 @@ config FORCE_MAX_ZONEORDER
 
 menuconfig ARMV8_DEPRECATED
bool "Emulate deprecated/obsolete ARMv8 instructions"
-   depends on COMPAT
+   depends on AARCH32_EL0
help
  Legacy software support may require certain instructions
  that have been deprecated or obsoleted in the architecture.
@@ -971,8 +971,14 @@ menu "Userspace binary formats"
 source "fs/Kconfig.binfmt"
 
 config COMPAT
+   bool
+   depends on AARCH32_EL0
+
+config AARCH32_EL0
bool "Kernel support for 32-bit EL0"
+   def_bool y
depends on ARM64_4K_PAGES || EXPERT
+   select COMPAT
select COMPAT_BINFMT_ELF
select HAVE_UID16
select OLD_SIGSUSPEND3
diff --git a/arch/arm64/include/asm/fpsimd.h b/arch/arm64/include/asm/fpsimd.h
index 50f559f..63b19f1 100644
--- a/arch/arm64/include/asm/fpsimd.h
+++ b/arch/arm64/include/asm/fpsimd.h
@@ -52,7 +52,7 @@ struct fpsimd_partial_state {
 };
 
 
-#if defined(__KERNEL__) && defined(CONFIG_COMPAT)
+#if defined(__KERNEL__) && defined(CONFIG_AARCH32_EL0)
 /* Masks for extracting the FPSR and FPCR from the FPSCR */
 #define VFP_FPSCR_STAT_MASK0xf89f
 #define VFP_FPSCR_CTRL_MASK0x07f79f00
diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h
index 400b80b..2c7fc5d 100644
--- a/arch/arm64/include/asm/hwcap.h
+++ b/arch/arm64/include/asm/hwcap.h
@@ -46,7 +46,7 @@
  */
 #define ELF_HWCAP  (elf_hwcap)
 
-#ifdef CONFIG_COMPAT
+#ifdef CONFIG_AARCH32_EL0
 #define COMPAT_ELF_HWCAP   (compat_elf_hwcap)
 #define COMPAT_ELF_HWCAP2  (compat_elf_hwcap2)
 extern unsigned int compat_elf_hwcap, compat_elf_hwcap2;
@@ -54,7 +54,7 @@ extern unsigned int compat_elf_hwcap, compat_elf_hwcap2;
 
 enum {
CAP_HWCAP = 1,
-#ifdef CONFIG_COMPAT
+#ifdef CONFIG_AARCH32_EL0
CAP_COMPAT_HWCAP,
CAP_COMPAT_HWCAP2,
 #endif
diff --git a/arch/arm64/include/asm/processor.h 
b/arch/arm64/include/asm/processor.h
index cef1cf3..5bbdbb4 100644
--- a/arch/arm64/include/asm/processor.h
+++ b/arch/arm64/include/asm/processor.h
@@ -81,7 +81,7 @@ struct cpu_context {
 struct thread_struct {
struct cpu_context  cpu_context;/* cpu context */
unsigned long   tp_value;   /* TLS register */
-#ifdef CONFIG_COMPAT
+#ifdef CONFIG_AARCH32_EL0
unsigned long   tp2_value;
 #endif
struct fpsimd_state fpsimd_state;
@@ -90,7 +90,7 @@ struct thread_struct {
struct debug_info   debug;  /* debugging */
 };
 
-#ifdef CONFIG_COMPAT
+#ifdef CONFIG_AARCH32_EL0
 #define task_user_tls(t)   \
 ({ \
unsigned long *__tls;  

[PATCH 07/19] thread: move thread bits accessors to separated file

[Yury Norov]

They may be accessed from low-level code, so isolating is a measure to
avoid circular dependencies in header files.

The exact reason for circular dependency is WARN_ON() macro added by Al
Viro in patch [edd63a27] "set_restore_sigmask() is never called without
SIGPENDING (and never should be)"

Signed-off-by: Yury Norov 
---
 include/linux/thread_bits.h | 55 +
 include/linux/thread_info.h | 44 +---
 2 files changed, 56 insertions(+), 43 deletions(-)
 create mode 100644 include/linux/thread_bits.h

diff --git a/include/linux/thread_bits.h b/include/linux/thread_bits.h
new file mode 100644
index 000..0d05d16
--- /dev/null
+++ b/include/linux/thread_bits.h
@@ -0,0 +1,55 @@
+
+/* thread_bits.h: common low-level thread bits accessors */
+
+#ifndef _LINUX_THREAD_BITS_H
+#define _LINUX_THREAD_BITS_H
+
+#ifndef __ASSEMBLY__
+
+#include 
+#include 
+
+/*
+ * flag set/clear/test wrappers
+ * - pass TIF_ constants to these functions
+ */
+
+static inline void set_ti_thread_flag(struct thread_info *ti, int flag)
+{
+   set_bit(flag, (unsigned long *)>flags);
+}
+
+static inline void clear_ti_thread_flag(struct thread_info *ti, int flag)
+{
+   clear_bit(flag, (unsigned long *)>flags);
+}
+
+static inline int test_and_set_ti_thread_flag(struct thread_info *ti, int flag)
+{
+   return test_and_set_bit(flag, (unsigned long *)>flags);
+}
+
+static inline int test_and_clear_ti_thread_flag(struct thread_info *ti, int 
flag)
+{
+   return test_and_clear_bit(flag, (unsigned long *)>flags);
+}
+
+static inline int test_ti_thread_flag(struct thread_info *ti, int flag)
+{
+   return test_bit(flag, (unsigned long *)>flags);
+}
+
+#define set_thread_flag(flag) \
+   set_ti_thread_flag(current_thread_info(), flag)
+#define clear_thread_flag(flag) \
+   clear_ti_thread_flag(current_thread_info(), flag)
+#define test_and_set_thread_flag(flag) \
+   test_and_set_ti_thread_flag(current_thread_info(), flag)
+#define test_and_clear_thread_flag(flag) \
+   test_and_clear_ti_thread_flag(current_thread_info(), flag)
+#define test_thread_flag(flag) \
+   test_ti_thread_flag(current_thread_info(), flag)
+
+#endif /* !__ASSEMBLY__ */
+#endif /* _LINUX_THREAD_BITS_H */
+
diff --git a/include/linux/thread_info.h b/include/linux/thread_info.h
index b4c2a48..b094aed 100644
--- a/include/linux/thread_info.h
+++ b/include/linux/thread_info.h
@@ -50,8 +50,7 @@ struct restart_block {
 
 extern long do_no_restart_syscall(struct restart_block *parm);
 
-#include 
-#include 
+#include 
 
 #ifdef __KERNEL__
 
@@ -62,47 +61,6 @@ extern long do_no_restart_syscall(struct restart_block 
*parm);
 # define THREADINFO_GFP(GFP_KERNEL_ACCOUNT | __GFP_NOTRACK)
 #endif
 
-/*
- * flag set/clear/test wrappers
- * - pass TIF_ constants to these functions
- */
-
-static inline void set_ti_thread_flag(struct thread_info *ti, int flag)
-{
-   set_bit(flag, (unsigned long *)>flags);
-}
-
-static inline void clear_ti_thread_flag(struct thread_info *ti, int flag)
-{
-   clear_bit(flag, (unsigned long *)>flags);
-}
-
-static inline int test_and_set_ti_thread_flag(struct thread_info *ti, int flag)
-{
-   return test_and_set_bit(flag, (unsigned long *)>flags);
-}
-
-static inline int test_and_clear_ti_thread_flag(struct thread_info *ti, int 
flag)
-{
-   return test_and_clear_bit(flag, (unsigned long *)>flags);
-}
-
-static inline int test_ti_thread_flag(struct thread_info *ti, int flag)
-{
-   return test_bit(flag, (unsigned long *)>flags);
-}
-
-#define set_thread_flag(flag) \
-   set_ti_thread_flag(current_thread_info(), flag)
-#define clear_thread_flag(flag) \
-   clear_ti_thread_flag(current_thread_info(), flag)
-#define test_and_set_thread_flag(flag) \
-   test_and_set_ti_thread_flag(current_thread_info(), flag)
-#define test_and_clear_thread_flag(flag) \
-   test_and_clear_ti_thread_flag(current_thread_info(), flag)
-#define test_thread_flag(flag) \
-   test_ti_thread_flag(current_thread_info(), flag)
-
 #define tif_need_resched() test_thread_flag(TIF_NEED_RESCHED)
 
 #if defined TIF_RESTORE_SIGMASK && !defined HAVE_SET_RESTORE_SIGMASK
-- 
2.7.4

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[PATCH 04/19] arm64: ensure the kernel is compiled for LP64

[Yury Norov]

From: Andrew Pinski 

The kernel needs to be compiled as a LP64 binary for ARM64, even when
using a compiler that defaults to code-generation for the ILP32 ABI.
Consequently, we need to explicitly pass '-mabi=lp64' (supported on
gcc-4.9 and newer).

Signed-off-by: Andrew Pinski 
Signed-off-by: Philipp Tomsich 
Signed-off-by: Christoph Muellner 
Signed-off-by: Yury Norov 
Reviewed-by: David Daney 
---
 arch/arm64/Makefile | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
index 7085e32..51c5293 100644
--- a/arch/arm64/Makefile
+++ b/arch/arm64/Makefile
@@ -35,14 +35,19 @@ KBUILD_CFLAGS   += -fno-asynchronous-unwind-tables
 KBUILD_CFLAGS  += $(call cc-option, -mpc-relative-literal-loads)
 KBUILD_AFLAGS  += $(lseinstr)
 
+KBUILD_CFLAGS  += $(call cc-option,-mabi=lp64)
+KBUILD_AFLAGS  += $(call cc-option,-mabi=lp64)
+
 ifeq ($(CONFIG_CPU_BIG_ENDIAN), y)
 KBUILD_CPPFLAGS+= -mbig-endian
 AS += -EB
 LD += -EB
+LDFLAGS+= -maarch64linuxb
 else
 KBUILD_CPPFLAGS+= -mlittle-endian
 AS += -EL
 LD += -EL
+LDFLAGS+= -maarch64linux
 endif
 
 CHECKFLAGS += -D__aarch64__
-- 
2.7.4

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[PATCH 09/19] arm64: ilp32: add is_ilp32_compat_{task,thread} and TIF_32BIT_AARCH64

[Yury Norov]

ILP32 tasks are needed to be distinguished from lp64 and aarch32.
This patch adds helper functions is_ilp32_compat_{task,thread} and
thread flag TIF_32BIT_AARCH64 to address it. This is a preparation
for following patches in ilp32 patchset.

For consistency, SET_PERSONALITY is changed here accordingly.

Signed-off-by: Andrew Pinski 
Signed-off-by: Philipp Tomsich 
Signed-off-by: Christoph Muellner 
Signed-off-by: Yury Norov 
Reviewed-by: David Daney 
---
 arch/arm64/include/asm/elf.h | 13 +++--
 arch/arm64/include/asm/is_compat.h   | 30 --
 arch/arm64/include/asm/thread_info.h |  2 ++
 3 files changed, 41 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/include/asm/elf.h b/arch/arm64/include/asm/elf.h
index bef2d90..a967726 100644
--- a/arch/arm64/include/asm/elf.h
+++ b/arch/arm64/include/asm/elf.h
@@ -142,7 +142,11 @@ typedef struct user_fpsimd_state elf_fpregset_t;
  */
 #define ELF_PLAT_INIT(_r, load_addr)   (_r)->regs[0] = 0
 
-#define SET_PERSONALITY(ex)clear_thread_flag(TIF_32BIT);
+#define SET_PERSONALITY(ex)\
+do {   \
+   clear_thread_flag(TIF_32BIT_AARCH64);   \
+   clear_thread_flag(TIF_32BIT);   \
+} while (0)
 
 #define ARCH_DLINFO\
 do {   \
@@ -182,7 +186,12 @@ typedef compat_elf_greg_t  
compat_elf_gregset_t[COMPAT_ELF_NGREG];
 ((x)->e_flags & EF_ARM_EABI_MASK))
 
 #define compat_start_threadcompat_start_thread
-#define COMPAT_SET_PERSONALITY(ex) set_thread_flag(TIF_32BIT);
+#define COMPAT_SET_PERSONALITY(ex) \
+do {   \
+   clear_thread_flag(TIF_32BIT_AARCH64);   \
+   set_thread_flag(TIF_32BIT); \
+} while (0)
+
 #define COMPAT_ARCH_DLINFO
 extern int aarch32_setup_vectors_page(struct linux_binprm *bprm,
  int uses_interp);
diff --git a/arch/arm64/include/asm/is_compat.h 
b/arch/arm64/include/asm/is_compat.h
index 8dba5ca..7726beb 100644
--- a/arch/arm64/include/asm/is_compat.h
+++ b/arch/arm64/include/asm/is_compat.h
@@ -45,18 +45,44 @@ static inline int is_a32_compat_thread(struct thread_info 
*thread)
 
 #endif /* CONFIG_AARCH32_EL0 */
 
+#ifdef CONFIG_ARM64_ILP32
+
+static inline int is_ilp32_compat_task(void)
+{
+   return test_thread_flag(TIF_32BIT_AARCH64);
+}
+
+static inline int is_ilp32_compat_thread(struct thread_info *thread)
+{
+   return test_ti_thread_flag(thread, TIF_32BIT_AARCH64);
+}
+
+#else
+
+static inline int is_ilp32_compat_task(void)
+{
+   return 0;
+}
+
+static inline int is_ilp32_compat_thread(struct thread_info *thread)
+{
+   return 0;
+}
+
+#endif /* CONFIG_ARM64_ILP32 */
+
 #ifdef CONFIG_COMPAT
 
 static inline int is_compat_task(void)
 {
-   return is_a32_compat_task();
+   return is_a32_compat_task() || is_ilp32_compat_task();
 }
 
 #endif /* CONFIG_COMPAT */
 
 static inline int is_compat_thread(struct thread_info *thread)
 {
-   return is_a32_compat_thread(thread);
+   return is_a32_compat_thread(thread) || is_ilp32_compat_thread(thread);
 }
 
 
diff --git a/arch/arm64/include/asm/thread_info.h 
b/arch/arm64/include/asm/thread_info.h
index 4daa559..8802645 100644
--- a/arch/arm64/include/asm/thread_info.h
+++ b/arch/arm64/include/asm/thread_info.h
@@ -119,6 +119,7 @@ static inline struct thread_info *current_thread_info(void)
 #define TIF_RESTORE_SIGMASK20
 #define TIF_SINGLESTEP 21
 #define TIF_32BIT  22  /* AARCH32 process */
+#define TIF_32BIT_AARCH64  23  /* 32 bit process on AArch64(ILP32) */
 
 #define _TIF_SIGPENDING(1 << TIF_SIGPENDING)
 #define _TIF_NEED_RESCHED  (1 << TIF_NEED_RESCHED)
@@ -130,6 +131,7 @@ static inline struct thread_info *current_thread_info(void)
 #define _TIF_SYSCALL_TRACEPOINT(1 << TIF_SYSCALL_TRACEPOINT)
 #define _TIF_SECCOMP   (1 << TIF_SECCOMP)
 #define _TIF_32BIT (1 << TIF_32BIT)
+#define _TIF_32BIT_AARCH64 (1 << TIF_32BIT_AARCH64)
 
 #define _TIF_WORK_MASK (_TIF_NEED_RESCHED | _TIF_SIGPENDING | \
 _TIF_NOTIFY_RESUME | _TIF_FOREIGN_FPSTATE)
-- 
2.7.4

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[PATCH 08/19] arm64: introduce is_a32_task and is_a32_thread (for AArch32 compat)

[Yury Norov]

Based on patch of Andrew Pinski.

This patch introduces is_a32_compat_task and is_a32_thread so it is
easier to say this is a a32 specific thread or a generic compat thread/task.
Corresponding functions are located in  to avoid mess in
headers.

Some files include both  and ,
and this is wrong because  has  already
included. It was fixed too.

Signed-off-by: Yury Norov 
Signed-off-by: Philipp Tomsich 
Signed-off-by: Christoph Muellner 
Signed-off-by: Andrew Pinski 
Reviewed-by: David Daney 
---
 arch/arm64/include/asm/compat.h  | 19 ++-
 arch/arm64/include/asm/elf.h | 10 +++---
 arch/arm64/include/asm/ftrace.h  |  2 +-
 arch/arm64/include/asm/is_compat.h   | 64 
 arch/arm64/include/asm/memory.h  |  5 +--
 arch/arm64/include/asm/processor.h   |  5 +--
 arch/arm64/include/asm/syscall.h |  2 +-
 arch/arm64/include/asm/thread_info.h |  2 +-
 arch/arm64/kernel/hw_breakpoint.c| 10 +++---
 arch/arm64/kernel/perf_regs.c|  2 +-
 arch/arm64/kernel/process.c  |  7 ++--
 arch/arm64/kernel/ptrace.c   | 11 +++
 arch/arm64/kernel/signal.c   |  4 +--
 arch/arm64/kernel/traps.c|  3 +-
 14 files changed, 98 insertions(+), 48 deletions(-)
 create mode 100644 arch/arm64/include/asm/is_compat.h

diff --git a/arch/arm64/include/asm/compat.h b/arch/arm64/include/asm/compat.h
index eb8432b..df2f72d 100644
--- a/arch/arm64/include/asm/compat.h
+++ b/arch/arm64/include/asm/compat.h
@@ -24,6 +24,8 @@
 #include 
 #include 
 
+#include 
+
 #define COMPAT_USER_HZ 100
 #ifdef __AARCH64EB__
 #define COMPAT_UTS_MACHINE "armv8b\0\0"
@@ -298,23 +300,6 @@ struct compat_shmid64_ds {
compat_ulong_t __unused5;
 };
 
-static inline int is_compat_task(void)
-{
-   return test_thread_flag(TIF_32BIT);
-}
-
-static inline int is_compat_thread(struct thread_info *thread)
-{
-   return test_ti_thread_flag(thread, TIF_32BIT);
-}
-
-#else /* !CONFIG_COMPAT */
-
-static inline int is_compat_thread(struct thread_info *thread)
-{
-   return 0;
-}
-
 #endif /* CONFIG_COMPAT */
 #endif /* __KERNEL__ */
 #endif /* __ASM_COMPAT_H */
diff --git a/arch/arm64/include/asm/elf.h b/arch/arm64/include/asm/elf.h
index 579b6e6..bef2d90 100644
--- a/arch/arm64/include/asm/elf.h
+++ b/arch/arm64/include/asm/elf.h
@@ -16,6 +16,10 @@
 #ifndef __ASM_ELF_H
 #define __ASM_ELF_H
 
+#ifndef __ASSEMBLY__
+#include 
+#endif
+
 #include 
 
 /*
@@ -152,13 +156,9 @@ extern int arch_setup_additional_pages(struct linux_binprm 
*bprm,
   int uses_interp);
 
 /* 1GB of VA */
-#ifdef CONFIG_COMPAT
-#define STACK_RND_MASK (test_thread_flag(TIF_32BIT) ? \
+#define STACK_RND_MASK (is_compat_task() ? \
0x7ff >> (PAGE_SHIFT - 12) : \
0x3 >> (PAGE_SHIFT - 12))
-#else
-#define STACK_RND_MASK (0x3 >> (PAGE_SHIFT - 12))
-#endif
 
 #ifdef __AARCH64EB__
 #define COMPAT_ELF_PLATFORM("v8b")
diff --git a/arch/arm64/include/asm/ftrace.h b/arch/arm64/include/asm/ftrace.h
index caa955f..0feb28a 100644
--- a/arch/arm64/include/asm/ftrace.h
+++ b/arch/arm64/include/asm/ftrace.h
@@ -54,7 +54,7 @@ static inline unsigned long ftrace_call_adjust(unsigned long 
addr)
 #define ARCH_TRACE_IGNORE_COMPAT_SYSCALLS
 static inline bool arch_trace_is_compat_syscall(struct pt_regs *regs)
 {
-   return is_compat_task();
+   return is_a32_compat_task();
 }
 #endif /* ifndef __ASSEMBLY__ */
 
diff --git a/arch/arm64/include/asm/is_compat.h 
b/arch/arm64/include/asm/is_compat.h
new file mode 100644
index 000..8dba5ca
--- /dev/null
+++ b/arch/arm64/include/asm/is_compat.h
@@ -0,0 +1,64 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+#ifndef __ASM_IS_COMPAT_H
+#define __ASM_IS_COMPAT_H
+#ifndef __ASSEMBLY__
+
+#include 
+
+#ifdef CONFIG_AARCH32_EL0
+
+static inline int is_a32_compat_task(void)
+{
+   return test_thread_flag(TIF_32BIT);
+}
+
+static inline int is_a32_compat_thread(struct thread_info *thread)
+{
+   return test_ti_thread_flag(thread, TIF_32BIT);
+}
+
+#else
+
+static inline int is_a32_compat_task(void)
+
+{
+   return 0;
+}
+

[PATCH 13/19] arm64: ilp32: share aarch32 syscall handlers

[Yury Norov]

off_t is  passed in register pair just like in aarch32.
In this patch corresponding aarch32 handlers are shared to
ilp32 code.

Signed-off-by: Yury Norov 
---
 arch/arm64/kernel/Makefile |  1 +
 arch/arm64/kernel/entry32.S| 65 --
 arch/arm64/kernel/entry32_common.S | 93 ++
 3 files changed, 94 insertions(+), 65 deletions(-)
 create mode 100644 arch/arm64/kernel/entry32_common.S

diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index bcdd4b2..d11572d 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -29,6 +29,7 @@ arm64-obj-$(CONFIG_AARCH32_EL0)   += sys32.o 
kuser32.o signal32.o \
   sys_compat.o entry32.o   
\
   ../../arm/kernel/opcodes.o 
binfmt_elf32.o
 arm64-obj-$(CONFIG_ARM64_ILP32)+= binfmt_ilp32.o
+arm64-obj-$(CONFIG_COMPAT) += entry32_common.o
 arm64-obj-$(CONFIG_FUNCTION_TRACER)+= ftrace.o entry-ftrace.o
 arm64-obj-$(CONFIG_MODULES)+= arm64ksyms.o module.o
 arm64-obj-$(CONFIG_ARM64_MODULE_PLTS)  += module-plts.o
diff --git a/arch/arm64/kernel/entry32.S b/arch/arm64/kernel/entry32.S
index f332d5d..fd2b0d5 100644
--- a/arch/arm64/kernel/entry32.S
+++ b/arch/arm64/kernel/entry32.S
@@ -54,68 +54,3 @@ ENTRY(compat_sys_fstatfs64_wrapper)
b   compat_sys_fstatfs64
 ENDPROC(compat_sys_fstatfs64_wrapper)
 
-/*
- * Note: off_4k (w5) is always in units of 4K. If we can't do the
- * requested offset because it is not page-aligned, we return -EINVAL.
- */
-ENTRY(compat_sys_mmap2_wrapper)
-#if PAGE_SHIFT > 12
-   tst w5, #~PAGE_MASK >> 12
-   b.ne1f
-   lsr w5, w5, #PAGE_SHIFT - 12
-#endif
-   b   sys_mmap_pgoff
-1: mov x0, #-EINVAL
-   ret
-ENDPROC(compat_sys_mmap2_wrapper)
-
-/*
- * Wrappers for AArch32 syscalls that either take 64-bit parameters
- * in registers or that take 32-bit parameters which require sign
- * extension.
- */
-ENTRY(compat_sys_pread64_wrapper)
-   regs_to_64  x3, x4, x5
-   b   sys_pread64
-ENDPROC(compat_sys_pread64_wrapper)
-
-ENTRY(compat_sys_pwrite64_wrapper)
-   regs_to_64  x3, x4, x5
-   b   sys_pwrite64
-ENDPROC(compat_sys_pwrite64_wrapper)
-
-ENTRY(compat_sys_truncate64_wrapper)
-   regs_to_64  x1, x2, x3
-   b   sys_truncate
-ENDPROC(compat_sys_truncate64_wrapper)
-
-ENTRY(compat_sys_ftruncate64_wrapper)
-   regs_to_64  x1, x2, x3
-   b   sys_ftruncate
-ENDPROC(compat_sys_ftruncate64_wrapper)
-
-ENTRY(compat_sys_readahead_wrapper)
-   regs_to_64  x1, x2, x3
-   mov w2, w4
-   b   sys_readahead
-ENDPROC(compat_sys_readahead_wrapper)
-
-ENTRY(compat_sys_fadvise64_64_wrapper)
-   mov w6, w1
-   regs_to_64  x1, x2, x3
-   regs_to_64  x2, x4, x5
-   mov w3, w6
-   b   sys_fadvise64_64
-ENDPROC(compat_sys_fadvise64_64_wrapper)
-
-ENTRY(compat_sys_sync_file_range2_wrapper)
-   regs_to_64  x2, x2, x3
-   regs_to_64  x3, x4, x5
-   b   sys_sync_file_range2
-ENDPROC(compat_sys_sync_file_range2_wrapper)
-
-ENTRY(compat_sys_fallocate_wrapper)
-   regs_to_64  x2, x2, x3
-   regs_to_64  x3, x4, x5
-   b   sys_fallocate
-ENDPROC(compat_sys_fallocate_wrapper)
diff --git a/arch/arm64/kernel/entry32_common.S 
b/arch/arm64/kernel/entry32_common.S
new file mode 100644
index 000..261cd97
--- /dev/null
+++ b/arch/arm64/kernel/entry32_common.S
@@ -0,0 +1,93 @@
+/*
+ * Compat system call wrappers
+ *
+ * Copyright (C) 2012 ARM Ltd.
+ * Authors: Will Deacon 
+ * Catalin Marinas 
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+
+/*
+ * Note: off_4k (w5) is always in units of 4K. If we can't do the
+ * requested offset because it is not page-aligned, we return -EINVAL.
+ */
+ENTRY(compat_sys_mmap2_wrapper)
+#if PAGE_SHIFT > 12
+   tst w5, #~PAGE_MASK >> 12
+   b.ne1f
+   lsr w5, w5, #PAGE_SHIFT - 12
+#endif
+   b   sys_mmap_pgoff
+1: mov x0, #-EINVAL
+   ret
+ENDPROC(compat_sys_mmap2_wrapper)
+
+/*
+ * Wrappers for AArch32 syscalls that either take 64-bit 

[PATCH 12/19] arm64: ptrace: handle ptrace_request differently for aarch32 and ilp32

[Yury Norov]

Here new aarch32 ptrace syscall handler is introsuced to avoid run-time
detection of the task type.

Signed-off-by: Yury Norov 
---
 arch/arm64/include/asm/unistd32.h |  2 +-
 arch/arm64/kernel/ptrace.c| 50 ++-
 arch/arm64/kernel/sys32.c |  1 +
 include/linux/ptrace.h|  6 +
 kernel/ptrace.c   | 10 
 5 files changed, 62 insertions(+), 7 deletions(-)

diff --git a/arch/arm64/include/asm/unistd32.h 
b/arch/arm64/include/asm/unistd32.h
index b7e8ef1..6da7cbd 100644
--- a/arch/arm64/include/asm/unistd32.h
+++ b/arch/arm64/include/asm/unistd32.h
@@ -74,7 +74,7 @@ __SYSCALL(__NR_getuid, sys_getuid16)
/* 25 was sys_stime */
 __SYSCALL(25, sys_ni_syscall)
 #define __NR_ptrace 26
-__SYSCALL(__NR_ptrace, compat_sys_ptrace)
+__SYSCALL(__NR_ptrace, compat_sys_aarch32_ptrace)
/* 27 was sys_alarm */
 __SYSCALL(27, sys_ni_syscall)
/* 28 was sys_fstat */
diff --git a/arch/arm64/kernel/ptrace.c b/arch/arm64/kernel/ptrace.c
index 38a09338..a861105 100644
--- a/arch/arm64/kernel/ptrace.c
+++ b/arch/arm64/kernel/ptrace.c
@@ -29,6 +29,7 @@
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -1114,7 +1115,7 @@ static int compat_ptrace_sethbpregs(struct task_struct 
*tsk, compat_long_t num,
 }
 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
 
-long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
+static long compat_a32_ptrace(struct task_struct *child, compat_long_t request,
compat_ulong_t caddr, compat_ulong_t cdata)
 {
unsigned long addr = caddr;
@@ -1191,8 +1192,55 @@ long compat_arch_ptrace(struct task_struct *child, 
compat_long_t request,
 
return ret;
 }
+
+COMPAT_SYSCALL_DEFINE4(aarch32_ptrace, compat_long_t, request, compat_long_t, 
pid,
+  compat_long_t, addr, compat_long_t, data)
+{
+   struct task_struct *child;
+   long ret;
+
+   if (request == PTRACE_TRACEME) {
+   ret = ptrace_traceme();
+   goto out;
+   }
+
+   child = ptrace_get_task_struct(pid);
+   if (IS_ERR(child)) {
+   ret = PTR_ERR(child);
+   goto out;
+   }
+
+   if (request == PTRACE_ATTACH || request == PTRACE_SEIZE) {
+   ret = ptrace_attach(child, request, addr, data);
+   goto out_put_task_struct;
+   }
+
+   ret = ptrace_check_attach(child, request == PTRACE_KILL ||
+ request == PTRACE_INTERRUPT);
+   if (!ret) {
+   ret = compat_a32_ptrace(child, request, addr, data);
+   if (ret || request != PTRACE_DETACH)
+   ptrace_unfreeze_traced(child);
+   }
+
+ out_put_task_struct:
+   put_task_struct(child);
+ out:
+   return ret;
+}
+
 #endif /* CONFIG_AARCH32_EL0 */
 
+#ifdef CONFIG_COMPAT
+
+long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
+   compat_ulong_t caddr, compat_ulong_t cdata)
+{
+   return compat_ptrace_request(child, request, caddr, cdata);
+}
+
+#endif /* CONFIG_COMPAT */
+
 const struct user_regset_view *task_user_regset_view(struct task_struct *task)
 {
 #ifdef CONFIG_AARCH32_EL0
diff --git a/arch/arm64/kernel/sys32.c b/arch/arm64/kernel/sys32.c
index a40b134..3752443 100644
--- a/arch/arm64/kernel/sys32.c
+++ b/arch/arm64/kernel/sys32.c
@@ -38,6 +38,7 @@ asmlinkage long compat_sys_fadvise64_64_wrapper(void);
 asmlinkage long compat_sys_sync_file_range2_wrapper(void);
 asmlinkage long compat_sys_fallocate_wrapper(void);
 asmlinkage long compat_sys_mmap2_wrapper(void);
+asmlinkage long compat_sys_aarch32_ptrace(void);
 
 #undef __SYSCALL
 #define __SYSCALL(nr, sym) [nr] = sym,
diff --git a/include/linux/ptrace.h b/include/linux/ptrace.h
index 504c98a..75887a0 100644
--- a/include/linux/ptrace.h
+++ b/include/linux/ptrace.h
@@ -97,6 +97,12 @@ int generic_ptrace_peekdata(struct task_struct *tsk, 
unsigned long addr,
unsigned long data);
 int generic_ptrace_pokedata(struct task_struct *tsk, unsigned long addr,
unsigned long data);
+int ptrace_traceme(void);
+struct task_struct *ptrace_get_task_struct(pid_t pid);
+int ptrace_attach(struct task_struct *task, long request,
+unsigned long addr, unsigned long flags);
+int ptrace_check_attach(struct task_struct *child, bool ignore_state);
+void ptrace_unfreeze_traced(struct task_struct *task);
 
 /**
  * ptrace_parent - return the task that is tracing the given task
diff --git a/kernel/ptrace.c b/kernel/ptrace.c
index d49bfa1..cadf24c 100644
--- a/kernel/ptrace.c
+++ b/kernel/ptrace.c
@@ -136,7 +136,7 @@ static bool ptrace_freeze_traced(struct task_struct *task)
return ret;
 }
 
-static void ptrace_unfreeze_traced(struct task_struct *task)
+void 

[PATCH 10/19] arm64: introduce binfmt_elf32.c

[Yury Norov]

As we support more than one compat formats, it looks more reasonable
to not use fs/compat_binfmt.c. Custom binfmt_elf32.c allows to move aarch32
specific definitions there and make code more maintainable and readable.

Signed-off-by: Yury Norov 
---
 arch/arm64/Kconfig   |  1 -
 arch/arm64/include/asm/hwcap.h   |  2 --
 arch/arm64/kernel/Makefile   |  2 +-
 arch/arm64/kernel/binfmt_elf32.c | 31 +++
 4 files changed, 32 insertions(+), 4 deletions(-)
 create mode 100644 arch/arm64/kernel/binfmt_elf32.c

diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index aea8e61..f5735ec 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -979,7 +979,6 @@ config AARCH32_EL0
def_bool y
depends on ARM64_4K_PAGES || EXPERT
select COMPAT
-   select COMPAT_BINFMT_ELF
select HAVE_UID16
select OLD_SIGSUSPEND3
select COMPAT_OLD_SIGACTION
diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h
index 2c7fc5d..99dfd92 100644
--- a/arch/arm64/include/asm/hwcap.h
+++ b/arch/arm64/include/asm/hwcap.h
@@ -47,8 +47,6 @@
 #define ELF_HWCAP  (elf_hwcap)
 
 #ifdef CONFIG_AARCH32_EL0
-#define COMPAT_ELF_HWCAP   (compat_elf_hwcap)
-#define COMPAT_ELF_HWCAP2  (compat_elf_hwcap2)
 extern unsigned int compat_elf_hwcap, compat_elf_hwcap2;
 #endif
 
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index 631a118..60d59cb 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -27,7 +27,7 @@ $(obj)/%.stub.o: $(obj)/%.o FORCE
 
 arm64-obj-$(CONFIG_AARCH32_EL0)+= sys32.o kuser32.o signal32.o 
\
   sys_compat.o entry32.o   
\
-  ../../arm/kernel/opcodes.o
+  ../../arm/kernel/opcodes.o 
binfmt_elf32.o
 arm64-obj-$(CONFIG_FUNCTION_TRACER)+= ftrace.o entry-ftrace.o
 arm64-obj-$(CONFIG_MODULES)+= arm64ksyms.o module.o
 arm64-obj-$(CONFIG_ARM64_MODULE_PLTS)  += module-plts.o
diff --git a/arch/arm64/kernel/binfmt_elf32.c b/arch/arm64/kernel/binfmt_elf32.c
new file mode 100644
index 000..aec1c8a
--- /dev/null
+++ b/arch/arm64/kernel/binfmt_elf32.c
@@ -0,0 +1,31 @@
+/*
+ * Support for AArch32 Linux ELF binaries.
+ */
+
+/* AArch32 EABI. */
+#define EF_ARM_EABI_MASK   0xff00
+
+#define compat_start_threadcompat_start_thread
+#define COMPAT_SET_PERSONALITY(ex) \
+do {   \
+   clear_thread_flag(TIF_32BIT_AARCH64);   \
+   set_thread_flag(TIF_32BIT); \
+} while (0)
+
+#define COMPAT_ARCH_DLINFO
+#define COMPAT_ELF_HWCAP   (compat_elf_hwcap)
+#define COMPAT_ELF_HWCAP2  (compat_elf_hwcap2)
+
+#ifdef __AARCH64EB__
+#define COMPAT_ELF_PLATFORM("v8b")
+#else
+#define COMPAT_ELF_PLATFORM("v8l")
+#endif
+
+#define compat_arch_setup_additional_pages \
+   aarch32_setup_vectors_page
+struct linux_binprm;
+extern int aarch32_setup_vectors_page(struct linux_binprm *bprm,
+ int uses_interp);
+
+#include "../../../fs/compat_binfmt_elf.c"
-- 
2.7.4

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[PATCH 11/19] arm64: ilp32: introduce binfmt_ilp32.c

[Yury Norov]

to handle ILP32 binaries

Signed-off-by: Yury Norov 
---
 arch/arm64/include/asm/elf.h |  6 +++
 arch/arm64/kernel/Makefile   |  1 +
 arch/arm64/kernel/binfmt_ilp32.c | 96 
 3 files changed, 103 insertions(+)
 create mode 100644 arch/arm64/kernel/binfmt_ilp32.c

diff --git a/arch/arm64/include/asm/elf.h b/arch/arm64/include/asm/elf.h
index a967726..4dcbcec 100644
--- a/arch/arm64/include/asm/elf.h
+++ b/arch/arm64/include/asm/elf.h
@@ -174,10 +174,16 @@ extern int arch_setup_additional_pages(struct 
linux_binprm *bprm,
 
 #define COMPAT_ELF_ET_DYN_BASE (2 * TASK_SIZE_32 / 3)
 
+#ifndef USE_AARCH64_GREG
 /* AArch32 registers. */
 #define COMPAT_ELF_NGREG   18
 typedef unsigned int   compat_elf_greg_t;
 typedef compat_elf_greg_t  compat_elf_gregset_t[COMPAT_ELF_NGREG];
+#else /* AArch64 registers for AARCH64/ILP32 */
+#define COMPAT_ELF_NGREG   ELF_NGREG
+#define compat_elf_greg_t  elf_greg_t
+#define compat_elf_gregset_t   elf_gregset_t
+#endif
 
 /* AArch32 EABI. */
 #define EF_ARM_EABI_MASK   0xff00
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index 60d59cb..bcdd4b2 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -28,6 +28,7 @@ $(obj)/%.stub.o: $(obj)/%.o FORCE
 arm64-obj-$(CONFIG_AARCH32_EL0)+= sys32.o kuser32.o signal32.o 
\
   sys_compat.o entry32.o   
\
   ../../arm/kernel/opcodes.o 
binfmt_elf32.o
+arm64-obj-$(CONFIG_ARM64_ILP32)+= binfmt_ilp32.o
 arm64-obj-$(CONFIG_FUNCTION_TRACER)+= ftrace.o entry-ftrace.o
 arm64-obj-$(CONFIG_MODULES)+= arm64ksyms.o module.o
 arm64-obj-$(CONFIG_ARM64_MODULE_PLTS)  += module-plts.o
diff --git a/arch/arm64/kernel/binfmt_ilp32.c b/arch/arm64/kernel/binfmt_ilp32.c
new file mode 100644
index 000..416b3f5
--- /dev/null
+++ b/arch/arm64/kernel/binfmt_ilp32.c
@@ -0,0 +1,96 @@
+/*
+ * Support for ILP32 Linux/aarch64 ELF binaries.
+ */
+#define USE_AARCH64_GREG
+
+#include 
+#include 
+
+#undef ELF_CLASS
+#define ELF_CLASS  ELFCLASS32
+
+#undef elfhdr
+#undef elf_phdr
+#undef elf_shdr
+#undef elf_note
+#undef elf_addr_t
+#define elfhdr elf32_hdr
+#define elf_phdr   elf32_phdr
+#define elf_shdr   elf32_shdr
+#define elf_note   elf32_note
+#define elf_addr_t Elf32_Addr
+
+/*
+ * Some data types as stored in coredump.
+ */
+#define user_long_tcompat_long_t
+#define user_siginfo_t compat_siginfo_t
+#define copy_siginfo_to_user   copy_siginfo_to_user32
+
+/*
+ * The machine-dependent core note format types are defined in 
elfcore-compat.h,
+ * which requires asm/elf.h to define compat_elf_gregset_t et al.
+ */
+#define elf_prstatus   compat_elf_prstatus
+#define elf_prpsinfo   compat_elf_prpsinfo
+
+/*
+ * Compat version of cputime_to_compat_timeval, perhaps this
+ * should be an inline in .
+ */
+static void cputime_to_compat_timeval(const cputime_t cputime,
+ struct compat_timeval *value)
+{
+   struct timeval tv;
+   cputime_to_timeval(cputime, );
+   value->tv_sec = tv.tv_sec;
+   value->tv_usec = tv.tv_usec;
+}
+
+#undef cputime_to_timeval
+#define cputime_to_timeval cputime_to_compat_timeval
+
+/* AARCH64 ILP32 EABI. */
+#undef elf_check_arch
+#define elf_check_arch(x)  (((x)->e_machine == EM_AARCH64) \
+   && (x)->e_ident[EI_CLASS] == ELFCLASS32)
+
+#undef SET_PERSONALITY
+#define SET_PERSONALITY(ex)\
+do {   \
+   set_thread_flag(TIF_32BIT_AARCH64); \
+   clear_thread_flag(TIF_32BIT);   \
+} while (0)
+
+#undef ARCH_DLINFO
+#define ARCH_DLINFO\
+do {   \
+   NEW_AUX_ENT(AT_SYSINFO_EHDR,\
+   (elf_addr_t)(long)current->mm->context.vdso);   \
+} while (0)
+
+#undef ELF_PLATFORM
+#ifdef __AARCH64EB__
+#define ELF_PLATFORM   ("aarch64_be:ilp32")
+#else
+#define ELF_PLATFORM   ("aarch64:ilp32")
+#endif
+
+#undef ELF_ET_DYN_BASE
+#define ELF_ET_DYN_BASE COMPAT_ELF_ET_DYN_BASE
+
+#undef ELF_HWCAP
+#undef ELF_HWCAP2
+#define ELF_HWCAP  ((u32) elf_hwcap)
+#define ELF_HWCAP2 ((u32) (elf_hwcap >> 32))
+
+/*
+ * Rename a few of the symbols that binfmt_elf.c will define.
+ * These are all local so the names don't really matter, but it
+ * might make some debugging less confusing not to duplicate them.
+ */
+#define elf_format compat_elf_format
+#define init_elf_binfmt

[PATCH 15/19] arm64: signal: share lp64 signal routines to ilp32

[Yury Norov]

After that, it will be possible to reuse it in ilp32.

Signed-off-by: Yury Norov 
---
 arch/arm64/include/asm/signal_common.h | 33 
 arch/arm64/kernel/signal.c | 93 +-
 2 files changed, 92 insertions(+), 34 deletions(-)
 create mode 100644 arch/arm64/include/asm/signal_common.h

diff --git a/arch/arm64/include/asm/signal_common.h 
b/arch/arm64/include/asm/signal_common.h
new file mode 100644
index 000..756ed2c
--- /dev/null
+++ b/arch/arm64/include/asm/signal_common.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 1995-2009 Russell King
+ * Copyright (C) 2012 ARM Ltd.
+ * Copyright (C) 2016 Cavium Networks.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+#ifndef __ASM_SIGNAL_COMMON_H
+#define __ASM_SIGNAL_COMMON_H
+
+#include 
+#include 
+#include 
+
+int preserve_fpsimd_context(struct fpsimd_context __user *ctx);
+int restore_fpsimd_context(struct fpsimd_context __user *ctx);
+int setup_sigcontext(struct sigcontext __user *uc_mcontext, struct pt_regs 
*regs);
+int restore_sigcontext(struct pt_regs *regs, struct sigcontext __user *sf);
+void setup_return(struct pt_regs *regs, struct k_sigaction *ka,
+   void __user *frame, off_t sigframe_off, int usig);
+
+#endif /* __ASM_SIGNAL_COMMON_H */
diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c
index be02f65..5c73864 100644
--- a/arch/arm64/kernel/signal.c
+++ b/arch/arm64/kernel/signal.c
@@ -34,18 +34,26 @@
 #include 
 #include 
 #include 
+#include 
+
+#define RT_SIGFRAME_FP_POS (offsetof(struct rt_sigframe, sig)  \
+   + offsetof(struct sigframe, fp))
+
+struct sigframe {
+   struct ucontext uc;
+   u64 fp;
+   u64 lr;
+};
 
 /*
  * Do a signal return; undo the signal stack. These are aligned to 128-bit.
  */
 struct rt_sigframe {
struct siginfo info;
-   struct ucontext uc;
-   u64 fp;
-   u64 lr;
+   struct sigframe sig;
 };
 
-static int preserve_fpsimd_context(struct fpsimd_context __user *ctx)
+int preserve_fpsimd_context(struct fpsimd_context __user *ctx)
 {
struct fpsimd_state *fpsimd = >thread.fpsimd_state;
int err;
@@ -65,7 +73,7 @@ static int preserve_fpsimd_context(struct fpsimd_context 
__user *ctx)
return err ? -EFAULT : 0;
 }
 
-static int restore_fpsimd_context(struct fpsimd_context __user *ctx)
+int restore_fpsimd_context(struct fpsimd_context __user *ctx)
 {
struct fpsimd_state fpsimd;
__u32 magic, size;
@@ -93,22 +101,30 @@ static int restore_fpsimd_context(struct fpsimd_context 
__user *ctx)
 }
 
 static int restore_sigframe(struct pt_regs *regs,
-   struct rt_sigframe __user *sf)
+   struct sigframe __user *sf)
 {
sigset_t set;
-   int i, err;
-   void *aux = sf->uc.uc_mcontext.__reserved;
-
+   int err;
err = __copy_from_user(, >uc.uc_sigmask, sizeof(set));
if (err == 0)
set_current_blocked();
 
+   err |= restore_sigcontext(regs, >uc.uc_mcontext);
+   return err;
+}
+
+
+int restore_sigcontext(struct pt_regs *regs, struct sigcontext __user 
*uc_mcontext)
+{
+   int i, err = 0;
+   void *aux = uc_mcontext->__reserved;
+
for (i = 0; i < 31; i++)
-   __get_user_error(regs->regs[i], >uc.uc_mcontext.regs[i],
+   __get_user_error(regs->regs[i], _mcontext->regs[i],
 err);
-   __get_user_error(regs->sp, >uc.uc_mcontext.sp, err);
-   __get_user_error(regs->pc, >uc.uc_mcontext.pc, err);
-   __get_user_error(regs->pstate, >uc.uc_mcontext.pstate, err);
+   __get_user_error(regs->sp, _mcontext->sp, err);
+   __get_user_error(regs->pc, _mcontext->pc, err);
+   __get_user_error(regs->pstate, _mcontext->pstate, err);
 
/*
 * Avoid sys_rt_sigreturn() restarting.
@@ -145,10 +161,10 @@ asmlinkage long sys_rt_sigreturn(struct pt_regs *regs)
if (!access_ok(VERIFY_READ, frame, sizeof (*frame)))
goto badframe;
 
-   if (restore_sigframe(regs, frame))
+   if (restore_sigframe(regs, >sig))
goto badframe;
 
-   if (restore_altstack(>uc.uc_stack))
+   if (restore_altstack(>sig.uc.uc_stack))
goto badframe;
 
return regs->regs[0];
@@ -162,27 +178,36 @@ badframe:
return 0;
 }
 
-static int 

[PATCH 17/19] arm64: ilp32: introduce ilp32-specific handlers for sigframe and ucontext

[Yury Norov]

From: Andrew Pinski 

ILP32 uses AARCH32 compat structures and syscall handlers for signals.
But ILP32 struct rt_sigframe  and ucontext differs from both LP64 and
AARCH32. So some specific mechanism is needed to take care of it.

Signed-off-by: Andrew Pinski 
Signed-off-by: Yury Norov 
---
 arch/arm64/include/asm/signal_ilp32.h |  34 ++
 arch/arm64/kernel/Makefile|   3 +-
 arch/arm64/kernel/entry_ilp32.S   |  23 
 arch/arm64/kernel/signal.c|   3 +
 arch/arm64/kernel/signal_ilp32.c  | 194 ++
 5 files changed, 256 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm64/include/asm/signal_ilp32.h
 create mode 100644 arch/arm64/kernel/entry_ilp32.S
 create mode 100644 arch/arm64/kernel/signal_ilp32.c

diff --git a/arch/arm64/include/asm/signal_ilp32.h 
b/arch/arm64/include/asm/signal_ilp32.h
new file mode 100644
index 000..30eff23
--- /dev/null
+++ b/arch/arm64/include/asm/signal_ilp32.h
@@ -0,0 +1,34 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+#ifndef __ASM_SIGNAL_ILP32_H
+#define __ASM_SIGNAL_ILP32_H
+
+#ifdef CONFIG_ARM64_ILP32
+
+#include 
+
+int ilp32_setup_rt_frame(int usig, struct ksignal *ksig, sigset_t *set,
+ struct pt_regs *regs);
+
+#else
+
+static inline int ilp32_setup_rt_frame(int usig, struct ksignal *ksig, 
sigset_t *set,
+ struct pt_regs *regs)
+{
+   return -ENOSYS;
+}
+
+#endif /* CONFIG_ARM64_ILP32 */
+
+#endif /* __ASM_SIGNAL_ILP32_H */
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index d69bd40..ae8aacb 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -28,7 +28,8 @@ $(obj)/%.stub.o: $(obj)/%.o FORCE
 arm64-obj-$(CONFIG_AARCH32_EL0)+= sys32.o kuser32.o signal32.o 
\
   sys_compat.o entry32.o   
\
   ../../arm/kernel/opcodes.o 
binfmt_elf32.o
-arm64-obj-$(CONFIG_ARM64_ILP32)+= binfmt_ilp32.o sys_ilp32.o
+arm64-obj-$(CONFIG_ARM64_ILP32)+= binfmt_ilp32.o sys_ilp32.o   
\
+  signal_ilp32.o entry_ilp32.o
 arm64-obj-$(CONFIG_COMPAT) += entry32_common.o signal32_common.o
 arm64-obj-$(CONFIG_FUNCTION_TRACER)+= ftrace.o entry-ftrace.o
 arm64-obj-$(CONFIG_MODULES)+= arm64ksyms.o module.o
diff --git a/arch/arm64/kernel/entry_ilp32.S b/arch/arm64/kernel/entry_ilp32.S
new file mode 100644
index 000..5063172
--- /dev/null
+++ b/arch/arm64/kernel/entry_ilp32.S
@@ -0,0 +1,23 @@
+/*
+ * ILP32 system call wrappers
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+#include 
+
+ENTRY(ilp32_sys_rt_sigreturn_wrapper)
+   mov x0, sp
+   b   ilp32_sys_rt_sigreturn
+ENDPROC(ilp32_sys_rt_sigreturn_wrapper)
+
diff --git a/arch/arm64/kernel/signal.c b/arch/arm64/kernel/signal.c
index 5c73864..241bfeb 100644
--- a/arch/arm64/kernel/signal.c
+++ b/arch/arm64/kernel/signal.c
@@ -35,6 +35,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #define RT_SIGFRAME_FP_POS (offsetof(struct rt_sigframe, sig)  \
+ offsetof(struct sigframe, fp))
@@ -325,6 +326,8 @@ static void handle_signal(struct ksignal *ksig, struct 
pt_regs *regs)
ret = compat_setup_rt_frame(usig, ksig, oldset, regs);
else
ret = compat_setup_frame(usig, ksig, oldset, regs);
+   } else if (is_ilp32_compat_task()) {
+   ret = ilp32_setup_rt_frame(usig, ksig, oldset, regs);
} else {
ret = setup_rt_frame(usig, ksig, oldset, regs);
}
diff --git a/arch/arm64/kernel/signal_ilp32.c b/arch/arm64/kernel/signal_ilp32.c
new file mode 100644
index 

[PATCH 03/19] arm64: ilp32: add documentation on the ILP32 ABI for ARM64

[Yury Norov]

Based on Andrew Pinski's patch-series.

Signed-off-by: Yury Norov 
---
 Documentation/arm64/ilp32.txt | 54 +++
 1 file changed, 54 insertions(+)
 create mode 100644 Documentation/arm64/ilp32.txt

diff --git a/Documentation/arm64/ilp32.txt b/Documentation/arm64/ilp32.txt
new file mode 100644
index 000..d5faa31
--- /dev/null
+++ b/Documentation/arm64/ilp32.txt
@@ -0,0 +1,54 @@
+ILP32 AARCH64 SYSCALL ABI
+=
+
+This document describes the ILP32 syscall ABI and where it differs
+from the generic compat linux syscall interface.
+
+AARCH64/ILP32 userspace can potentially access top halves of registers that
+are passed as syscall arguments, so such registers (w0-w7) are deloused.
+
+AARCH64/ILP32 provides next types turned to 64-bit (comparing to AARCH32):
+ino_t   is u64 type.
+off_t   is s64 type.
+blkcnt_tis s64 type.
+fsblkcnt_t  is u64 type.
+fsfilcnt_t  is u64 type.
+
+AARCH64/ILP32 ABI uses standard syscall table which can be found at
+include/uapi/asm-generic/unistd.h, with the exceptions listed below.
+
+Syscalls which pass 64bit values are handled by the code shared from
+AARCH32 and pass that value as a pair. Next syscalls are affected:
+fadvise64_64()
+fallocate()
+ftruncate64()  
+pread64()
+pwrite64()
+readahead()
+sync_file_range()
+truncate64()
+sys_mmap()
+
+ptrace() syscall is handled by compat version.
+
+fcntl64() syscall is handled by non-compat handler as struct flock for ilp32
+is the same as for lp64
+
+shmat() syscall is handled by non-compat handler as aarch64/ilp32 has no
+limitation on 4-pages alignement for shared memory.
+
+Syscalls which take a pointer to stat, stat64, statfs, statfs64
+structures are now routed to native handlers directly, as aarch64/ilp32
+defines userspace ino_t, off_t, blkcnt_t, fsblkcnt_t, fsfilcnt_t types
+as 64-bit and it makes that structures have same layout as lp64.
+Next syscalls are affected:
+fstatat64()
+fstat64()
+statfs64()
+fstatfs64()
+
+struct rt_sigframe is redefined and contains struct compat_siginfo,
+as compat syscalls expects, and struct ilp32_sigframe, to handle
+AARCH64 register set and 32-bit userspace register representation.h
+
+elf_gregset_t is taken from lp64 to handle registers properly.
-- 
2.7.4

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[PATCH 01/19] compat ABI: use non-compat openat and open_by_handle_at variants

[Yury Norov]

The only difference is that non-compat version forces O_LARGEFILE,
and it should be the default behaviour for all architectures, as
we don't support 32-bit off_t. The only exception is tile32, that
continues with compat version of syscalls.

Signed-off-by: Yury Norov 
Acked-by: Arnd Bergmann 
Acked-by: Chris Metcalf  [for tile]
---
 arch/tile/kernel/compat.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/tile/kernel/compat.c b/arch/tile/kernel/compat.c
index 4912084..489ae19 100644
--- a/arch/tile/kernel/compat.c
+++ b/arch/tile/kernel/compat.c
@@ -94,6 +94,9 @@ COMPAT_SYSCALL_DEFINE5(llseek, unsigned int, fd, unsigned 
int, offset_high,
 #define compat_sys_readahead sys32_readahead
 #define sys_llseek compat_sys_llseek
 
+#define sys_openat compat_sys_openat
+#define sys_open_by_handle_at  compat_sys_open_by_handle_at
+
 /* Call the assembly trampolines where necessary. */
 #define compat_sys_rt_sigreturn _compat_sys_rt_sigreturn
 #define sys_clone _sys_clone
-- 
2.7.4

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Re: [PATCH v5 1/1] hwmon: Add support for INA3221 Triple Current/Voltage Monitors

[Andrew F. Davis]

On 06/10/2016 11:44 AM, Guenter Roeck wrote:
> On Fri, Jun 10, 2016 at 10:32:33AM -0500, Andrew F. Davis wrote:
>> Add support for the the INA3221 26v capable, Triple channel,
>> Bi-Directional, Zero-Drift, Low-/High-Side, Current/Voltage Monitor
>> with I2C interface.
>>
>> Signed-off-by: Andrew F. Davis 
> 
> Applied to -next.
> 
> Can you by any chance send me a register dump ? I would like to write
> module test code for the chip.
> 

No problem:

# i2cdump -y 2 0x48
No size specified (using byte-data access)
 0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f0123456789abcdef
00: 18 16 80 00 08 7f 80 7f 80 00 00 00 00 00 00 00???.?...
10: e0 00 00 f0 00 00 03 00 00 7f 00 00 00 00 00 00?..?..?..?..
20: 7f 0a 01 00 00 XX 00 00 00 00 0e 00 00 00 40 00???..X?...@.
30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 55 00..U.
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Re: [kernel-hardening] [PATCH 2/2] security,perf: Allow further restriction of perf_event_open

[Arnaldo Carvalho de Melo]

Em Fri, Jun 17, 2016 at 12:16:47PM -0400, Daniel Micay escreveu:
> On Fri, 2016-06-17 at 08:54 +0200, Peter Zijlstra wrote:
> > This Changelog is completely devoid of information. _WHY_ are you
> > doing this?
 
> Attack surface reduction. It's possible to use seccomp-bpf for some
> limited cases, but it's not flexible enough. There are lots of
> information leaks and local privilege escalation vulnerabilities via
> perf events, yet on most Linux installs it's not ever being used. So
> turning it off by default on those installs is an easy win. The holes
> are reduced to root -> kernel (and that's not a meaningful boundary in
> mainline right now - although as is the case here, Debian has a bunch of
> securelevel patches for that).

Is ptrace also disabled on such systems, or any of the other more recent
syscalls? The same arguments could probably be used to disable those:
reduce attack surface, possibly the new ones have bugs as they are
relatively new and it takes a long time for new syscalls to be more
generally used, if we go on disabling them in such a way, they will
probably never get used :-\

Wouldn't the recent bump in perf_event_paranoid to 2 enough? I.e. only
allow profiling of user tasks?

Or is there something more specific that we should disable/constrain to
reduce such surface contact without using such a big hammer?

- Arnaldo
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Re: [PATCHv3 5/7] EDAC, altera: Add Arria10 ECC memory init functions

[Thor Thayer]

On 06/17/2016 12:21 PM, Borislav Petkov wrote:

On Mon, Jun 13, 2016 at 04:19:10PM -0500, ttha...@opensource.altera.com wrote:

From: Thor Thayer 

In preparation for additional memory module ECCs, add the
memory initialization functions and helper functions used
for memory initialization.

Signed-off-by: Thor Thayer 
---
v2: Specify INTMODE selection -> IRQ on each ECC error.
 Insert functions above memory-specific functions so that function
 declarations are not required.
 Use ERRINTENS & ERRINTENR registers instead of read/modify/write.
v3: Changes for common compatibility string:
 - Pass node instead of compatibility string.
 - New altr_init_a10_ecc_device_type() for peripherals.
 - Add __init to altr_init_a10_ecc_block().
 - Add a10_get_irq_mask().
---
  drivers/edac/altera_edac.c |  197 
  drivers/edac/altera_edac.h |8 ++
  2 files changed, 205 insertions(+)



+/*
+ * This function uses the memory initialization block in the Arria10 ECC
+ * controller to initialize/clear the entire memory data and ECC data.
+ */
+static int altr_init_memory_port(void __iomem *ioaddr, int port)
+{
+   int limit = ALTR_A10_ECC_INIT_WATCHDOG_10US;
+   u32 init_mask = ALTR_A10_ECC_INITA;
+   u32 stat_mask = ALTR_A10_ECC_INITCOMPLETEA;
+   u32 clear_mask = ALTR_A10_ECC_ERRPENA_MASK;
+   int ret = 0;
+
+   if (port) {
+   init_mask = ALTR_A10_ECC_INITB;
+   stat_mask = ALTR_A10_ECC_INITCOMPLETEB;
+   clear_mask = ALTR_A10_ECC_ERRPENB_MASK;
+   }


Do a
u32 init_mask, stat_mask, clear_mask;

if (port) {
init_mask = ALTR_A10_ECC_INITB;
...
} else {
init_mask = ALTR_A10_ECC_INITA;
...
}

so that you don't have to repeat the assignments in the if (port) case.

OK. I only have one PORTB peripheral so normally the if (port) branch 
won't execute but I see your point.



+
+   ecc_set_bits(init_mask, (ioaddr + ALTR_A10_ECC_CTRL_OFST));
+   while (limit--) {
+   if (ecc_test_bits(stat_mask,
+ (ioaddr + ALTR_A10_ECC_INITSTAT_OFST)))
+   break;
+   udelay(1);
+   }
+   if (limit < 0)
+   ret = -EBUSY;
+
+   /* Clear any pending ECC interrupts */
+   writel(clear_mask, (ioaddr + ALTR_A10_ECC_INTSTAT_OFST));
+
+   return ret;
+}
+
+/*
+ * Aside from the L2 ECC, the Arria10 ECC memories have a common register
+ * layout so the following functions can be shared between all peripherals.


I don't understand - we're here under

#if defined(CONFIG_EDAC_ALTERA_ETHERNET)

What sharing do you mean?

I'll be adding a number of peripheral FIFOs in future patches but I 
agree that the comment is misleading in this case. I'll fix it.

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Re: [PATCHv3 6/7] EDAC, altera: Add Arria10 Ethernet EDAC support

[Borislav Petkov]

On Mon, Jun 13, 2016 at 04:19:11PM -0500, ttha...@opensource.altera.com wrote:
> From: Thor Thayer 
> 
> Add Altera Arria10 Ethernet FIFO memory EDAC support. Update
> to support a common compatibility string for all ethernet
> FIFOs in the DT.
> 
> Signed-off-by: Thor Thayer 
> ---
> v2  Remove (void *) cast from altr_edac_device_of_match[]
> Addition of panic flag to ethernet private data.
> v3  Use common compatiblity string.
> Simplify socfpga_init_ethernet_ecc().
> ---
>  drivers/edac/Kconfig   |7 +++
>  drivers/edac/altera_edac.c |   38 --
>  drivers/edac/altera_edac.h |3 +++
>  3 files changed, 46 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
> index 6ca7474..d0c1dab 100644
> --- a/drivers/edac/Kconfig
> +++ b/drivers/edac/Kconfig
> @@ -391,6 +391,13 @@ config EDAC_ALTERA_OCRAM
> Support for error detection and correction on the
> Altera On-Chip RAM Memory for Altera SoCs.
>  
> +config EDAC_ALTERA_ETHERNET
> + bool "Altera Ethernet FIFO ECC"
> + depends on EDAC_ALTERA=y
> + help
> +   Support for error detection and correction on the
> +   Altera Ethernet FIFO Memory for Altera SoCs.
> +
>  config EDAC_SYNOPSYS
>   tristate "Synopsys DDR Memory Controller"
>   depends on EDAC_MM_EDAC && ARCH_ZYNQ
> diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
> index f27bb29..14f99ae 100644
> --- a/drivers/edac/altera_edac.c
> +++ b/drivers/edac/altera_edac.c
> @@ -1260,6 +1260,34 @@ const struct edac_device_prv_data a10_l2ecc_data = {
>  
>  #endif   /* CONFIG_EDAC_ALTERA_L2C */
>  
> +/* Ethernet Device Functions /
> +
> +#ifdef CONFIG_EDAC_ALTERA_ETHERNET
> +
> +const struct edac_device_prv_data a10_enet0rxecc_data = {

This needs to be "static const" and then you don't need to init panic to
false.

Your other edac_device_prv_data things are not static too, please
convert them in a separate patch too.

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Re: [PATCHv3 3/7] EDAC, altera: Share Arria10 check_deps & IRQ functions

[Borislav Petkov]

On Fri, Jun 17, 2016 at 12:09:59PM -0500, Thor Thayer wrote:
> Since each peripheral's EDAC can be individually selected, the build
> generates a warning of an unused function if just L2 cache was selected.
> 
> The ifdeffery is ugly but it removes that warning in the L2 only case.

You could add __maybe_unused to the function definition but I guess you
don't want that code in there if only L2 is selected.

Ok.

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Re: [PATCHv3 2/7] EDAC, altera: Add panic flag check to A10 IRQ

[Borislav Petkov]

On Fri, Jun 17, 2016 at 12:05:41PM -0500, Thor Thayer wrote:
> That is a good question. We have 2 important uses for OCRAM 1) to hold our
> power-down/sleep and resume functions and 2) to hold our FPGA contents
> during sleep. If either of these is corrupted, it is better to panic than to
> load something that would cause incorrect.
> 
> In the cases of the FIFOs such as Ethernet and USB, the plan is to add code
> to drop the packet so that we'll get a re-transmission. In that case, it is
> sort of recoverable.

Much better. Now put that explanation in the code please!

:-)

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Re: [PATCHv3 2/7] EDAC, altera: Add panic flag check to A10 IRQ

[Thor Thayer]

Hi Boris,

On 06/17/2016 11:51 AM, Borislav Petkov wrote:

On Mon, Jun 13, 2016 at 04:19:07PM -0500, ttha...@opensource.altera.com wrote:

From: Thor Thayer 

In preparation for additional memory module ECCs, the
IRQ function will check a panic flag before doing a
kernel panic on double bit errors. ECCs on buffers
will not cause a kernel panic on DBERRs.

Signed-off-by: Thor Thayer 
---
v2  New patch. Add panic flag to IRQ function.
v3  No change
---
  drivers/edac/altera_edac.c |4 +++-
  drivers/edac/altera_edac.h |1 +
  2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 926bcaf..a9d8fa7 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -897,7 +897,8 @@ static irqreturn_t altr_edac_a10_ecc_irq(int irq, void 
*dev_id)
writel(ALTR_A10_ECC_DERRPENA,
   base + ALTR_A10_ECC_INTSTAT_OFST);
edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
-   panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
+   if (dci->data->panic)
+   panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");

return IRQ_HANDLED;
}
@@ -936,6 +937,7 @@ const struct edac_device_prv_data a10_ocramecc_data = {
.set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
.ecc_irq_handler = altr_edac_a10_ecc_irq,
.inject_fops = _edac_a10_device_inject_fops,
+   .panic = true,


So I could use a bit more detailed explanation here why OCRAM must panic
and the others don't. Consider me an external guy who doesn't know the
hardware and is looking at the driver and is wondering why this IP must
panic on double-bit errors and the others don't.

:-)

Thanks.

That is a good question. We have 2 important uses for OCRAM 1) to hold 
our power-down/sleep and resume functions and 2) to hold our FPGA 
contents during sleep. If either of these is corrupted, it is better to 
panic than to load something that would cause incorrect.


In the cases of the FIFOs such as Ethernet and USB, the plan is to add 
code to drop the packet so that we'll get a re-transmission. In that 
case, it is sort of recoverable.


Thor

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Re: [PATCHv3 1/7] EDAC, altera: Check parent status for Arria10 EDAC block

[Borislav Petkov]

On Fri, Jun 17, 2016 at 11:54:04AM -0500, Thor Thayer wrote:
> Yes. Thanks! I will make the change.

No need, already did and applied. You can drop this patch from your
queue.

Thanks.

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Re: [PATCHv3 2/7] EDAC, altera: Add panic flag check to A10 IRQ

[Borislav Petkov]

On Mon, Jun 13, 2016 at 04:19:07PM -0500, ttha...@opensource.altera.com wrote:
> From: Thor Thayer 
> 
> In preparation for additional memory module ECCs, the
> IRQ function will check a panic flag before doing a
> kernel panic on double bit errors. ECCs on buffers
> will not cause a kernel panic on DBERRs.
> 
> Signed-off-by: Thor Thayer 
> ---
> v2  New patch. Add panic flag to IRQ function.
> v3  No change
> ---
>  drivers/edac/altera_edac.c |4 +++-
>  drivers/edac/altera_edac.h |1 +
>  2 files changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
> index 926bcaf..a9d8fa7 100644
> --- a/drivers/edac/altera_edac.c
> +++ b/drivers/edac/altera_edac.c
> @@ -897,7 +897,8 @@ static irqreturn_t altr_edac_a10_ecc_irq(int irq, void 
> *dev_id)
>   writel(ALTR_A10_ECC_DERRPENA,
>  base + ALTR_A10_ECC_INTSTAT_OFST);
>   edac_device_handle_ue(dci->edac_dev, 0, 0, dci->edac_dev_name);
> - panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
> + if (dci->data->panic)
> + panic("\nEDAC:ECC_DEVICE[Uncorrectable errors]\n");
>  
>   return IRQ_HANDLED;
>   }
> @@ -936,6 +937,7 @@ const struct edac_device_prv_data a10_ocramecc_data = {
>   .set_err_ofst = ALTR_A10_ECC_INTTEST_OFST,
>   .ecc_irq_handler = altr_edac_a10_ecc_irq,
>   .inject_fops = _edac_a10_device_inject_fops,
> + .panic = true,

So I could use a bit more detailed explanation here why OCRAM must panic
and the others don't. Consider me an external guy who doesn't know the
hardware and is looking at the driver and is wondering why this IP must
panic on double-bit errors and the others don't.

:-)

Thanks.

-- 
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Boris.

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Re: [PATCHv3 1/7] EDAC, altera: Check parent status for Arria10 EDAC block

[Thor Thayer]

On 06/17/2016 11:46 AM, Borislav Petkov wrote:

On Mon, Jun 13, 2016 at 04:19:06PM -0500, ttha...@opensource.altera.com wrote:

From: Thor Thayer 

In preparation for the Arria10 ECC modules, check the status
of the parent in the device tree to ensure the block is enabled.
Skip if no parent phandle is set in the device tree.

Signed-off-by: Thor Thayer 
---
v2  No change
v3  Move check into validate_parent_available().
---
  drivers/edac/altera_edac.c |   17 +
  1 file changed, 17 insertions(+)

diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
index 6f5d586..926bcaf 100644
--- a/drivers/edac/altera_edac.c
+++ b/drivers/edac/altera_edac.c
@@ -1125,6 +1125,20 @@ static void altr_edac_a10_irq_handler(struct irq_desc 
*desc)
chained_irq_exit(chip, desc);
  }

+static int validate_parent_available(struct device_node *np)
+{
+   struct device_node *parent;
+
+   /* Ensure parent device is enabled if parent node exists */
+   parent = of_parse_phandle(np, "parent", 0);
+   if (parent && !of_device_is_available(parent)) {
+   of_node_put(parent);
+   return -ENODEV;
+   }
+   of_node_put(parent);
+   return 0;
+}


How about this - it is a bit simpler:

static int validate_parent_available(struct device_node *np)
{
 struct device_node *parent;
 int ret = 0;

 /* Ensure parent device is enabled if parent node exists */
 parent = of_parse_phandle(np, "parent", 0);
 if (parent && !of_device_is_available(parent))
 ret = -ENODEV;

 of_node_put(parent);
 return ret;
}

?


Yes. Thanks! I will make the change.
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Re: [PATCHv3 1/7] EDAC, altera: Check parent status for Arria10 EDAC block

[Borislav Petkov]

On Mon, Jun 13, 2016 at 04:19:06PM -0500, ttha...@opensource.altera.com wrote:
> From: Thor Thayer 
> 
> In preparation for the Arria10 ECC modules, check the status
> of the parent in the device tree to ensure the block is enabled.
> Skip if no parent phandle is set in the device tree.
> 
> Signed-off-by: Thor Thayer 
> ---
> v2  No change
> v3  Move check into validate_parent_available().
> ---
>  drivers/edac/altera_edac.c |   17 +
>  1 file changed, 17 insertions(+)
> 
> diff --git a/drivers/edac/altera_edac.c b/drivers/edac/altera_edac.c
> index 6f5d586..926bcaf 100644
> --- a/drivers/edac/altera_edac.c
> +++ b/drivers/edac/altera_edac.c
> @@ -1125,6 +1125,20 @@ static void altr_edac_a10_irq_handler(struct irq_desc 
> *desc)
>   chained_irq_exit(chip, desc);
>  }
>  
> +static int validate_parent_available(struct device_node *np)
> +{
> + struct device_node *parent;
> +
> + /* Ensure parent device is enabled if parent node exists */
> + parent = of_parse_phandle(np, "parent", 0);
> + if (parent && !of_device_is_available(parent)) {
> + of_node_put(parent);
> + return -ENODEV;
> + }
> + of_node_put(parent);
> + return 0;
> +}

How about this - it is a bit simpler:

static int validate_parent_available(struct device_node *np)
{
struct device_node *parent;
int ret = 0;

/* Ensure parent device is enabled if parent node exists */
parent = of_parse_phandle(np, "parent", 0);
if (parent && !of_device_is_available(parent))
ret = -ENODEV;

of_node_put(parent);
return ret;
}

?

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Boris.

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Re: [kernel-hardening] [PATCH 2/2] security,perf: Allow further restriction of perf_event_open

[Daniel Micay]

On Fri, 2016-06-17 at 08:54 +0200, Peter Zijlstra wrote:
> On Thu, Jun 16, 2016 at 03:27:55PM -0700, Kees Cook wrote:
> > Hi guys,
> > 
> > This patch wasn't originally CCed to you (I'm fixing that now).
> > Would
> > you consider taking this into the perf tree? 
> 
> No.
> 
> > It's been in active use
> > in both Debian and Android for a while now.
> 
> Very nice of you all to finally inform us I suppose :/

It was in Debian a lot longer than Android, although the Android feature
came from a downstream variant where it was done much earlier:

https://android-review.googlesource.com/#/c/233736/

> > > > > 
> > > > > access to performance events by users without CAP_SYS_ADMIN.
> > > > > Add a Kconfig symbol CONFIG_SECURITY_PERF_EVENTS_RESTRICT that
> > > > > makes this value the default.
> > > > > 
> > > > > This is based on a similar feature in grsecurity
> > > > > (CONFIG_GRKERNSEC_PERF_HARDEN).  This version doesn't include
> > > > > making
> > > > > the variable read-only.  It also allows enabling further
> > > > > restriction
> > > > > at run-time regardless of whether the default is changed.
> 
> This Changelog is completely devoid of information. _WHY_ are you
> doing
> this?

Attack surface reduction. It's possible to use seccomp-bpf for some
limited cases, but it's not flexible enough. There are lots of
information leaks and local privilege escalation vulnerabilities via
perf events, yet on most Linux installs it's not ever being used. So
turning it off by default on those installs is an easy win. The holes
are reduced to root -> kernel (and that's not a meaningful boundary in
mainline right now - although as is the case here, Debian has a bunch of
securelevel patches for that).

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Re: [RFC PATCH v1 10/18] x86/efi: Access EFI related tables in the clear

[Matt Fleming]

On Thu, 16 Jun, at 09:38:31AM, Tom Lendacky wrote:
> 
> Ok, I think this was happening before the commit to build our own
> EFI page table structures:
> 
> commit 67a9108ed ("x86/efi: Build our own page table structures")
> 
> Before this commit the boot services ended up mapped into the kernel
> page table entries as un-encrypted during efi_map_regions() and I needed
> to change those entries back to encrypted. With your change above,
> this appears to no longer be needed.

Great news! Things are as they should be ;)
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[RFC PATCH-tip/locking/core v3 03/10] locking/rwsem: Make rwsem_spin_on_owner() return a tri-state value

[Waiman Long]

This patch modifies rwsem_spin_on_owner() to return a tri-state value
to better reflect the state of lock holder which enables us to make a
better decision of what to do next.

Signed-off-by: Waiman Long 
---
 kernel/locking/rwsem-xadd.c |   14 +-
 1 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/kernel/locking/rwsem-xadd.c b/kernel/locking/rwsem-xadd.c
index 29027c6..198b732 100644
--- a/kernel/locking/rwsem-xadd.c
+++ b/kernel/locking/rwsem-xadd.c
@@ -360,9 +360,13 @@ done:
 }
 
 /*
- * Return true only if we can still spin on the owner field of the rwsem.
+ * Return the folowing three values depending on the lock owner state.
+ *   1 when owner has changed and no reader is detected yet.
+ *   0 when owner has change and/or owner is a reader.
+ *  -1 when optimistic spinning has to stop because either the owner stops
+ * running or its timeslice has been used up.
  */
-static noinline bool rwsem_spin_on_owner(struct rw_semaphore *sem)
+static noinline int rwsem_spin_on_owner(struct rw_semaphore *sem)
 {
struct task_struct *owner = READ_ONCE(sem->owner);
 
@@ -382,7 +386,7 @@ static noinline bool rwsem_spin_on_owner(struct 
rw_semaphore *sem)
/* abort spinning when need_resched or owner is not running */
if (!owner->on_cpu || need_resched()) {
rcu_read_unlock();
-   return false;
+   return -1;
}
 
cpu_relax_lowlatency();
@@ -393,7 +397,7 @@ out:
 * If there is a new owner or the owner is not set, we continue
 * spinning.
 */
-   return !rwsem_owner_is_reader(READ_ONCE(sem->owner));
+   return rwsem_owner_is_reader(READ_ONCE(sem->owner)) ? 0 : 1;
 }
 
 static bool rwsem_optimistic_spin(struct rw_semaphore *sem)
@@ -416,7 +420,7 @@ static bool rwsem_optimistic_spin(struct rw_semaphore *sem)
 *  2) readers own the lock as we can't determine if they are
 * actively running or not.
 */
-   while (rwsem_spin_on_owner(sem)) {
+   while (rwsem_spin_on_owner(sem) > 0) {
/*
 * Try to acquire the lock
 */
-- 
1.7.1

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[RFC PATCH-tip/locking/core v3 04/10] locking/rwsem: Enable count-based spinning on reader

[Waiman Long]

When the rwsem is owned by reader, writers stop optimistic spinning
simply because there is no easy way to figure out if all the readers
are actively running or not. However, there are scenarios where
the readers are unlikely to sleep and optimistic spinning can help
performance.

This patch provides an autotuning mechanism to find out if a rwsem
can benefit from count-based reader optimistic spinning. A count
(rspin_enabled) in the rwsem data structure is used to track if
optimistic spinning should be enabled. Reader spinning is enabled
by default. Each successful spin (with lock acquisition) will
increment the count by 1 and each unsuccessful spin will decrement
it by 4.  When the count reaches 0, reader spinning is disabled.
Modification of that count is protected by the osq lock. Therefore,
reader spinning will be maintained as long as at least 80% of the
spins are successful.

Both the spinning threshold and the default value for rspin_enabled
can be overridden by architecture specific rwsem.h header file.

Signed-off-by: Waiman Long 
---
 include/linux/rwsem.h   |   19 +++-
 kernel/locking/rwsem-xadd.c |   66 ++
 2 files changed, 77 insertions(+), 8 deletions(-)

diff --git a/include/linux/rwsem.h b/include/linux/rwsem.h
index dd1d142..8978f87 100644
--- a/include/linux/rwsem.h
+++ b/include/linux/rwsem.h
@@ -32,6 +32,8 @@ struct rw_semaphore {
raw_spinlock_t wait_lock;
 #ifdef CONFIG_RWSEM_SPIN_ON_OWNER
struct optimistic_spin_queue osq; /* spinner MCS lock */
+   int rspin_enabled;  /* protected by osq lock */
+
/*
 * Write owner. Used as a speculative check to see
 * if the owner is running on the cpu.
@@ -69,8 +71,23 @@ static inline int rwsem_is_locked(struct rw_semaphore *sem)
 # define __RWSEM_DEP_MAP_INIT(lockname)
 #endif
 
+/*
+ * Each successful reader spin will increment the rspin_enabled by 1.
+ * Each unsuccessful spin, on the other hand, will decrement it by 2.
+ * Reader spinning will be permanently disabled when it reaches 0.
+ */
+#ifndef RWSEM_RSPIN_ENABLED_DEFAULT
+# define RWSEM_RSPIN_ENABLED_DEFAULT   40
+#endif
+#define RWSEM_RSPIN_ENABLED_MAX1024
+
+#ifndef RWSEM_RSPIN_THRESHOLD
+# define RWSEM_RSPIN_THRESHOLD (1 << 12)
+#endif
+
 #ifdef CONFIG_RWSEM_SPIN_ON_OWNER
-#define __RWSEM_OPT_INIT(lockname) , .osq = OSQ_LOCK_UNLOCKED, .owner = NULL
+#define __RWSEM_OPT_INIT(lockname) , .osq = OSQ_LOCK_UNLOCKED, .owner = NULL, \
+   .rspin_enabled = RWSEM_RSPIN_ENABLED_DEFAULT
 #else
 #define __RWSEM_OPT_INIT(lockname)
 #endif
diff --git a/kernel/locking/rwsem-xadd.c b/kernel/locking/rwsem-xadd.c
index 198b732..ce68b54 100644
--- a/kernel/locking/rwsem-xadd.c
+++ b/kernel/locking/rwsem-xadd.c
@@ -85,6 +85,7 @@ void __init_rwsem(struct rw_semaphore *sem, const char *name,
INIT_LIST_HEAD(>wait_list);
 #ifdef CONFIG_RWSEM_SPIN_ON_OWNER
sem->owner = NULL;
+   sem->rspin_enabled = RWSEM_RSPIN_ENABLED_DEFAULT;
osq_lock_init(>osq);
 #endif
 }
@@ -347,9 +348,10 @@ static inline bool rwsem_can_spin_on_owner(struct 
rw_semaphore *sem)
owner = READ_ONCE(sem->owner);
if (!rwsem_owner_is_writer(owner)) {
/*
-* Don't spin if the rwsem is readers owned.
+* Don't spin if the rwsem is readers owned and the
+* reader spinning threshold isn't set.
 */
-   ret = !rwsem_owner_is_reader(owner);
+   ret = !rwsem_owner_is_reader(owner) || sem->rspin_enabled;
goto done;
}
 
@@ -403,6 +405,8 @@ out:
 static bool rwsem_optimistic_spin(struct rw_semaphore *sem)
 {
bool taken = false;
+   int owner_state;/* Lock owner state */
+   int rspin_cnt;  /* Count for reader spinning */
 
preempt_disable();
 
@@ -413,14 +417,16 @@ static bool rwsem_optimistic_spin(struct rw_semaphore 
*sem)
if (!osq_lock(>osq))
goto done;
 
+   rspin_cnt = sem->rspin_enabled ? RWSEM_RSPIN_THRESHOLD : 0;
+
/*
 * Optimistically spin on the owner field and attempt to acquire the
 * lock whenever the owner changes. Spinning will be stopped when:
-*  1) the owning writer isn't running; or
-*  2) readers own the lock as we can't determine if they are
-* actively running or not.
+*  1) the owning writer isn't running,
+*  2) readers own the lock and reader spinning count has reached 0; or
+*  3) its timeslice has been used up.
 */
-   while (rwsem_spin_on_owner(sem) > 0) {
+   while ((owner_state = rwsem_spin_on_owner(sem)) >= 0) {
/*
 * Try to acquire the lock
 */
@@ -430,12 +436,24 @@ static bool rwsem_optimistic_spin(struct rw_semaphore 
*sem)
}
 
/*
+* We only decremnt the 

[RFC PATCH-tip/locking/core v3 06/10] locking/rwsem: Move common rwsem macros to asm-generic/rwsem_types.h

[Waiman Long]

Almost all the macro definitions in the various architecture specific
rwsem.h header files are essentially the same. This patch moves all
of them into a common header asm-generic/rwsem_types.h to eliminate
the duplication.

Suggested-by: Peter Zijlstra (Intel) 
Signed-off-by: Waiman Long 
---
 arch/alpha/include/asm/rwsem.h|8 +---
 arch/ia64/include/asm/rwsem.h |7 ++-
 arch/s390/include/asm/rwsem.h |7 +--
 arch/x86/include/asm/rwsem.h  |   19 +--
 include/asm-generic/rwsem.h   |   16 +---
 include/asm-generic/rwsem_types.h |   26 ++
 6 files changed, 32 insertions(+), 51 deletions(-)
 create mode 100644 include/asm-generic/rwsem_types.h

diff --git a/arch/alpha/include/asm/rwsem.h b/arch/alpha/include/asm/rwsem.h
index 77873d0..f99e39a 100644
--- a/arch/alpha/include/asm/rwsem.h
+++ b/arch/alpha/include/asm/rwsem.h
@@ -13,13 +13,7 @@
 #ifdef __KERNEL__
 
 #include 
-
-#define RWSEM_UNLOCKED_VALUE   0xL
-#define RWSEM_ACTIVE_BIAS  0x0001L
-#define RWSEM_ACTIVE_MASK  0xL
-#define RWSEM_WAITING_BIAS (-0x0001L)
-#define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS
-#define RWSEM_ACTIVE_WRITE_BIAS(RWSEM_WAITING_BIAS + 
RWSEM_ACTIVE_BIAS)
+#include 
 
 static inline void __down_read(struct rw_semaphore *sem)
 {
diff --git a/arch/ia64/include/asm/rwsem.h b/arch/ia64/include/asm/rwsem.h
index 8fa98dd..21a9066 100644
--- a/arch/ia64/include/asm/rwsem.h
+++ b/arch/ia64/include/asm/rwsem.h
@@ -26,13 +26,10 @@
 #endif
 
 #include 
+#include 
 
+#undef  RWSEM_UNLOCKED_VALUE
 #define RWSEM_UNLOCKED_VALUE   __IA64_UL_CONST(0x)
-#define RWSEM_ACTIVE_BIAS  (1L)
-#define RWSEM_ACTIVE_MASK  (0xL)
-#define RWSEM_WAITING_BIAS (-0x1L)
-#define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS
-#define RWSEM_ACTIVE_WRITE_BIAS(RWSEM_WAITING_BIAS + 
RWSEM_ACTIVE_BIAS)
 
 /*
  * lock for reading
diff --git a/arch/s390/include/asm/rwsem.h b/arch/s390/include/asm/rwsem.h
index 597e7e9..13dedc8 100644
--- a/arch/s390/include/asm/rwsem.h
+++ b/arch/s390/include/asm/rwsem.h
@@ -39,12 +39,7 @@
 #error "please don't include asm/rwsem.h directly, use linux/rwsem.h instead"
 #endif
 
-#define RWSEM_UNLOCKED_VALUE   0xL
-#define RWSEM_ACTIVE_BIAS  0x0001L
-#define RWSEM_ACTIVE_MASK  0xL
-#define RWSEM_WAITING_BIAS (-0x0001L)
-#define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS
-#define RWSEM_ACTIVE_WRITE_BIAS(RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
+#include 
 
 /*
  * lock for reading
diff --git a/arch/x86/include/asm/rwsem.h b/arch/x86/include/asm/rwsem.h
index 089ced4..c6d155e 100644
--- a/arch/x86/include/asm/rwsem.h
+++ b/arch/x86/include/asm/rwsem.h
@@ -38,24 +38,7 @@
 
 #ifdef __KERNEL__
 #include 
-
-/*
- * The bias values and the counter type limits the number of
- * potential readers/writers to 32767 for 32 bits and 2147483647
- * for 64 bits.
- */
-
-#ifdef CONFIG_X86_64
-# define RWSEM_ACTIVE_MASK 0xL
-#else
-# define RWSEM_ACTIVE_MASK 0xL
-#endif
-
-#define RWSEM_UNLOCKED_VALUE   0xL
-#define RWSEM_ACTIVE_BIAS  0x0001L
-#define RWSEM_WAITING_BIAS (-RWSEM_ACTIVE_MASK-1)
-#define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS
-#define RWSEM_ACTIVE_WRITE_BIAS(RWSEM_WAITING_BIAS + 
RWSEM_ACTIVE_BIAS)
+#include 
 
 /*
  * lock for reading
diff --git a/include/asm-generic/rwsem.h b/include/asm-generic/rwsem.h
index 5be122e..3cb8d98 100644
--- a/include/asm-generic/rwsem.h
+++ b/include/asm-generic/rwsem.h
@@ -12,21 +12,7 @@
  * Adapted largely from include/asm-i386/rwsem.h
  * by Paul Mackerras .
  */
-
-/*
- * the semaphore definition
- */
-#ifdef CONFIG_64BIT
-# define RWSEM_ACTIVE_MASK 0xL
-#else
-# define RWSEM_ACTIVE_MASK 0xL
-#endif
-
-#define RWSEM_UNLOCKED_VALUE   0xL
-#define RWSEM_ACTIVE_BIAS  0x0001L
-#define RWSEM_WAITING_BIAS (-RWSEM_ACTIVE_MASK-1)
-#define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS
-#define RWSEM_ACTIVE_WRITE_BIAS(RWSEM_WAITING_BIAS + 
RWSEM_ACTIVE_BIAS)
+#include 
 
 /*
  * lock for reading
diff --git a/include/asm-generic/rwsem_types.h 
b/include/asm-generic/rwsem_types.h
new file mode 100644
index 000..093ef6a
--- /dev/null
+++ b/include/asm-generic/rwsem_types.h
@@ -0,0 +1,26 @@
+#ifndef _ASM_GENERIC_RWSEM_TYPES_H
+#define _ASM_GENERIC_RWSEM_TYPES_H
+
+#ifdef __KERNEL__
+
+/*
+ * the semaphore definition
+ *
+ * The bias values and the counter type limits the number of
+ * potential readers/writers to 32767 for 32 bits and 2147483647
+ * for 64 bits.
+ */

[RFC PATCH-tip/locking/core v3 01/10] locking/osq: Make lock/unlock proper acquire/release barrier

[Waiman Long]

The osq_lock() and osq_unlock() function may not provide the necessary
acquire and release barrier in some cases. This patch makes sure
that the proper barriers are provided when osq_lock() is successful
or when osq_unlock() is called.

The change on the unlock side is more for documentation purpose than
is actually needed.

Suggested-by: Peter Zijlstra (Intel) 
Signed-off-by: Waiman Long 
---
 kernel/locking/osq_lock.c |7 ++-
 1 files changed, 6 insertions(+), 1 deletions(-)

diff --git a/kernel/locking/osq_lock.c b/kernel/locking/osq_lock.c
index 05a3785..d957b90 100644
--- a/kernel/locking/osq_lock.c
+++ b/kernel/locking/osq_lock.c
@@ -124,6 +124,11 @@ bool osq_lock(struct optimistic_spin_queue *lock)
 
cpu_relax_lowlatency();
}
+   /*
+* Add an acquire memory barrier for pairing with the release barrier
+* in unlock.
+*/
+   smp_acquire__after_ctrl_dep();
return true;
 
 unqueue:
@@ -198,7 +203,7 @@ void osq_unlock(struct optimistic_spin_queue *lock)
 * Second most likely case.
 */
node = this_cpu_ptr(_node);
-   next = xchg(>next, NULL);
+   next = xchg_release(>next, NULL);
if (next) {
WRITE_ONCE(next->locked, 1);
return;
-- 
1.7.1

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[RFC PATCH-tip/locking/core v3 02/10] locking/rwsem: Stop active read lock ASAP

[Waiman Long]

Currently, when down_read() fails, the active read locking isn't undone
until the rwsem_down_read_failed() function grabs the wait_lock. If the
wait_lock is contended, it may takes a while to get the lock. During
that period, writer lock stealing will be disabled because of the
active read lock.

This patch will release the active read lock ASAP so that writer lock
stealing can happen sooner. The only downside is when the reader is
the first one in the wait queue as it has to issue another atomic
operation to update the count.

On a 4-socket Haswell machine running on a 4.7-rc1 tip-based kernel,
the fio test with multithreaded randrw and randwrite tests on the
same file on a XFS partition on top of a NVDIMM with DAX were run,
the aggregated bandwidths before and after the patch were as follows:

  Test  BW before patch BW after patch  % change
    --- --  
  randrw1210 MB/s  1352 MB/s  +12%
  randwrite 1622 MB/s  1710 MB/s  +5.4%

The write-only microbench also showed improvement because some read
locking was done by the XFS code.

Signed-off-by: Waiman Long 
---
 kernel/locking/rwsem-xadd.c |   19 ++-
 1 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/kernel/locking/rwsem-xadd.c b/kernel/locking/rwsem-xadd.c
index 2031281..29027c6 100644
--- a/kernel/locking/rwsem-xadd.c
+++ b/kernel/locking/rwsem-xadd.c
@@ -230,11 +230,18 @@ __rwsem_mark_wake(struct rw_semaphore *sem,
 __visible
 struct rw_semaphore __sched *rwsem_down_read_failed(struct rw_semaphore *sem)
 {
-   long count, adjustment = -RWSEM_ACTIVE_READ_BIAS;
+   long count, adjustment = 0;
struct rwsem_waiter waiter;
struct task_struct *tsk = current;
WAKE_Q(wake_q);
 
+   /*
+* Undo read bias from down_read operation, stop active locking.
+* Doing that after taking the wait_lock may block writer lock
+* stealing for too long.
+*/
+   atomic_long_add(-RWSEM_ACTIVE_READ_BIAS, >count);
+
/* set up my own style of waitqueue */
waiter.task = tsk;
waiter.type = RWSEM_WAITING_FOR_READ;
@@ -244,8 +251,11 @@ struct rw_semaphore __sched *rwsem_down_read_failed(struct 
rw_semaphore *sem)
adjustment += RWSEM_WAITING_BIAS;
list_add_tail(, >wait_list);
 
-   /* we're now waiting on the lock, but no longer actively locking */
-   count = atomic_long_add_return(adjustment, >count);
+   /* we're now waiting on the lock */
+   if (adjustment)
+   count = atomic_long_add_return(adjustment, >count);
+   else
+   count = atomic_long_read(>count);
 
/* If there are no active locks, wake the front queued process(es).
 *
@@ -253,8 +263,7 @@ struct rw_semaphore __sched *rwsem_down_read_failed(struct 
rw_semaphore *sem)
 * wake our own waiter to join the existing active readers !
 */
if (count == RWSEM_WAITING_BIAS ||
-   (count > RWSEM_WAITING_BIAS &&
-adjustment != -RWSEM_ACTIVE_READ_BIAS))
+   (count > RWSEM_WAITING_BIAS && adjustment))
sem = __rwsem_mark_wake(sem, RWSEM_WAKE_ANY, _q);
 
raw_spin_unlock_irq(>wait_lock);
-- 
1.7.1

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[RFC PATCH-tip/locking/core v3 07/10] locking/rwsem: Change RWSEM_WAITING_BIAS for better disambiguation

[Waiman Long]

When the count value is in between 0 and RWSEM_WAITING_BIAS, there
are 2 possibilities. Either a writer is present and there is no
waiter or there are waiters and readers. There is no easy way to
know which is true unless the wait_lock is taken.

This patch changes the RWSEM_WAITING_BIAS from 0x (32-bit) or
0x (64-bit) to 0xc000 (32-bit) or 0xc000
(64-bit). By doing so, we will be able to determine if writers
are present by looking at the count value alone without taking the
wait_lock.

This patch has the effect of halving the maximum number of writers
that can attempt to take the write lock simultaneously. However,
even the reduced maximum of about 16k (32-bit) or 1G (64-bit) should
be more than enough for the foreseeable future.

With that change, the following identity is now no longer true:

  RWSEM_ACTIVE_WRITE_BIAS = RWSEM_WAITING_BIAS + RWSEM_ACTIVE_READ_BIAS

Signed-off-by: Waiman Long 
---
 arch/alpha/include/asm/rwsem.h|3 ++-
 arch/ia64/include/asm/rwsem.h |2 +-
 arch/s390/include/asm/rwsem.h |2 +-
 arch/x86/include/asm/rwsem.h  |3 ++-
 include/asm-generic/rwsem.h   |4 ++--
 include/asm-generic/rwsem_types.h |   10 ++
 kernel/locking/rwsem-xadd.c   |   32 
 7 files changed, 38 insertions(+), 18 deletions(-)

diff --git a/arch/alpha/include/asm/rwsem.h b/arch/alpha/include/asm/rwsem.h
index f99e39a..dc236a5 100644
--- a/arch/alpha/include/asm/rwsem.h
+++ b/arch/alpha/include/asm/rwsem.h
@@ -179,7 +179,8 @@ static inline void __downgrade_write(struct rw_semaphore 
*sem)
"2: br  1b\n"
".previous"
:"=" (oldcount), "=m" (sem->count), "=" (temp)
-   :"Ir" (-RWSEM_WAITING_BIAS), "m" (sem->count) : "memory");
+   :"Ir" (-RWSEM_ACTIVE_WRITE_BIAS + RWSEM_ACTIVE_READ_BIAS),
+"m" (sem->count) : "memory");
 #endif
if (unlikely(oldcount < 0))
rwsem_downgrade_wake(sem);
diff --git a/arch/ia64/include/asm/rwsem.h b/arch/ia64/include/asm/rwsem.h
index 21a9066..ecea341 100644
--- a/arch/ia64/include/asm/rwsem.h
+++ b/arch/ia64/include/asm/rwsem.h
@@ -141,7 +141,7 @@ __downgrade_write (struct rw_semaphore *sem)
 
do {
old = atomic_long_read(>count);
-   new = old - RWSEM_WAITING_BIAS;
+   new = old - RWSEM_ACTIVE_WRITE_BIAS + RWSEM_ACTIVE_READ_BIAS;
} while (atomic_long_cmpxchg_release(>count, old, new) != old);
 
if (old < 0)
diff --git a/arch/s390/include/asm/rwsem.h b/arch/s390/include/asm/rwsem.h
index 13dedc8..e675a64 100644
--- a/arch/s390/include/asm/rwsem.h
+++ b/arch/s390/include/asm/rwsem.h
@@ -188,7 +188,7 @@ static inline void __downgrade_write(struct rw_semaphore 
*sem)
 {
signed long old, new, tmp;
 
-   tmp = -RWSEM_WAITING_BIAS;
+   tmp = -RWSEM_ACTIVE_WRITE_BIAS + RWSEM_ACTIVE_READ_BIAS;
asm volatile(
"   lg  %0,%2\n"
"0: lgr %1,%0\n"
diff --git a/arch/x86/include/asm/rwsem.h b/arch/x86/include/asm/rwsem.h
index c6d155e..ea36832 100644
--- a/arch/x86/include/asm/rwsem.h
+++ b/arch/x86/include/asm/rwsem.h
@@ -192,7 +192,8 @@ static inline void __downgrade_write(struct rw_semaphore 
*sem)
 "1:\n\t"
 "# ending __downgrade_write\n"
 : "+m" (sem->count)
-: "a" (sem), "er" (-RWSEM_WAITING_BIAS)
+: "a" (sem), "er" (-RWSEM_ACTIVE_WRITE_BIAS +
+RWSEM_ACTIVE_READ_BIAS)
 : "memory", "cc");
 }
 
diff --git a/include/asm-generic/rwsem.h b/include/asm-generic/rwsem.h
index 3cb8d98..962e75b 100644
--- a/include/asm-generic/rwsem.h
+++ b/include/asm-generic/rwsem.h
@@ -106,8 +106,8 @@ static inline void __downgrade_write(struct rw_semaphore 
*sem)
 * read-locked region is ok to be re-ordered into the
 * write side. As such, rely on RELEASE semantics.
 */
-   tmp = atomic_long_add_return_release(-RWSEM_WAITING_BIAS,
-(atomic_long_t *)>count);
+   tmp = atomic_long_add_return_release(-RWSEM_ACTIVE_WRITE_BIAS +
+   RWSEM_ACTIVE_READ_BIAS, (atomic_long_t *)>count);
if (tmp < 0)
rwsem_downgrade_wake(sem);
 }
diff --git a/include/asm-generic/rwsem_types.h 
b/include/asm-generic/rwsem_types.h
index 093ef6a..6d55d25 100644
--- a/include/asm-generic/rwsem_types.h
+++ b/include/asm-generic/rwsem_types.h
@@ -7,20 +7,22 @@
  * the semaphore definition
  *
  * The bias values and the counter type limits the number of
- * potential readers/writers to 32767 for 32 bits and 2147483647
- * for 64 bits.
+ * potential writers to 16383 for 32 bits and 1073741823 for 64 bits.
+ * The combined readers and writers can go up to 65534 for 32-bits and
+ * 4294967294 for 64-bits.
  */
 #ifdef CONFIG_64BIT
 # define RWSEM_ACTIVE_MASK   

[RFC PATCH-tip/locking/core v3 05/10] locking/rwsem: move down rwsem_down_read_failed function

[Waiman Long]

Move the rwsem_down_read_failed() function down to below the
optimistic spinning section before enabling optimistic spinning for
the readers. It is because the rwsem_down_read_failed() function will
call rwsem_optimistic_spin() in later patch.

There is no change in code.

Signed-off-by: Waiman Long 
---
 kernel/locking/rwsem-xadd.c |  116 +-
 1 files changed, 58 insertions(+), 58 deletions(-)

diff --git a/kernel/locking/rwsem-xadd.c b/kernel/locking/rwsem-xadd.c
index ce68b54..5fd689e 100644
--- a/kernel/locking/rwsem-xadd.c
+++ b/kernel/locking/rwsem-xadd.c
@@ -226,64 +226,6 @@ __rwsem_mark_wake(struct rw_semaphore *sem,
 }
 
 /*
- * Wait for the read lock to be granted
- */
-__visible
-struct rw_semaphore __sched *rwsem_down_read_failed(struct rw_semaphore *sem)
-{
-   long count, adjustment = 0;
-   struct rwsem_waiter waiter;
-   struct task_struct *tsk = current;
-   WAKE_Q(wake_q);
-
-   /*
-* Undo read bias from down_read operation, stop active locking.
-* Doing that after taking the wait_lock may block writer lock
-* stealing for too long.
-*/
-   atomic_long_add(-RWSEM_ACTIVE_READ_BIAS, >count);
-
-   /* set up my own style of waitqueue */
-   waiter.task = tsk;
-   waiter.type = RWSEM_WAITING_FOR_READ;
-
-   raw_spin_lock_irq(>wait_lock);
-   if (list_empty(>wait_list))
-   adjustment += RWSEM_WAITING_BIAS;
-   list_add_tail(, >wait_list);
-
-   /* we're now waiting on the lock */
-   if (adjustment)
-   count = atomic_long_add_return(adjustment, >count);
-   else
-   count = atomic_long_read(>count);
-
-   /* If there are no active locks, wake the front queued process(es).
-*
-* If there are no writers and we are first in the queue,
-* wake our own waiter to join the existing active readers !
-*/
-   if (count == RWSEM_WAITING_BIAS ||
-   (count > RWSEM_WAITING_BIAS && adjustment))
-   sem = __rwsem_mark_wake(sem, RWSEM_WAKE_ANY, _q);
-
-   raw_spin_unlock_irq(>wait_lock);
-   wake_up_q(_q);
-
-   /* wait to be given the lock */
-   while (true) {
-   set_task_state(tsk, TASK_UNINTERRUPTIBLE);
-   if (!waiter.task)
-   break;
-   schedule();
-   }
-
-   __set_task_state(tsk, TASK_RUNNING);
-   return sem;
-}
-EXPORT_SYMBOL(rwsem_down_read_failed);
-
-/*
  * This function must be called with the sem->wait_lock held to prevent
  * race conditions between checking the rwsem wait list and setting the
  * sem->count accordingly.
@@ -525,6 +467,64 @@ static inline bool reader_spinning_enabled(struct 
rw_semaphore *sem)
 #endif
 
 /*
+ * Wait for the read lock to be granted
+ */
+__visible
+struct rw_semaphore __sched * rwsem_down_read_failed(struct rw_semaphore *sem)
+{
+   long count, adjustment = 0;
+   struct rwsem_waiter waiter;
+   struct task_struct *tsk = current;
+   WAKE_Q(wake_q);
+
+   /*
+* Undo read bias from down_read operation, stop active locking.
+* Doing that after taking the wait_lock may block writer lock
+* stealing for too long.
+*/
+   atomic_long_add(-RWSEM_ACTIVE_READ_BIAS, >count);
+
+   /* set up my own style of waitqueue */
+   waiter.task = tsk;
+   waiter.type = RWSEM_WAITING_FOR_READ;
+
+   raw_spin_lock_irq(>wait_lock);
+   if (list_empty(>wait_list))
+   adjustment += RWSEM_WAITING_BIAS;
+   list_add_tail(, >wait_list);
+
+   /* we're now waiting on the lock */
+   if (adjustment)
+   count = atomic_long_add_return(adjustment, >count);
+   else
+   count = atomic_long_read(>count);
+
+   /* If there are no active locks, wake the front queued process(es).
+*
+* If there are no writers and we are first in the queue,
+* wake our own waiter to join the existing active readers !
+*/
+   if (count == RWSEM_WAITING_BIAS ||
+   (count > RWSEM_WAITING_BIAS && adjustment))
+   sem = __rwsem_mark_wake(sem, RWSEM_WAKE_ANY, _q);
+
+   raw_spin_unlock_irq(>wait_lock);
+   wake_up_q(_q);
+
+   /* wait to be given the lock */
+   while (true) {
+   set_task_state(tsk, TASK_UNINTERRUPTIBLE);
+   if (!waiter.task)
+   break;
+   schedule();
+   }
+
+   __set_task_state(tsk, TASK_RUNNING);
+   return sem;
+}
+EXPORT_SYMBOL(rwsem_down_read_failed);
+
+/*
  * Wait until we successfully acquire the write lock
  */
 static inline struct rw_semaphore *
-- 
1.7.1

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[RFC PATCH-tip/locking/core v3 08/10] locking/rwsem: Enable spinning readers

[Waiman Long]

This patch enables readers to optimistically spin when the
rspin_threshold is non-zero. That threshold value should only
be set when the lock owners of the rwsem are unlikely to go to
sleep. Otherwise enabling reader spinning may make the performance
worse in some cases.

On a 4-socket Haswell machine running on a 4.7-rc1 tip-based kernel,
the fio test with multithreaded randrw and randwrite tests on the
same file on a XFS partition on top of a NVDIMM with DAX were run,
the aggregated bandwidths before and after the reader optimistic
spinning patchset were as follows:

  Test  BW before patch BW after patch  % change
    --- --  
  randrw1352 MB/s  2164 MB/s  +60%
  randwrite 1710 MB/s  2550 MB/s  +49%

Signed-off-by: Waiman Long 
---
 kernel/locking/rwsem-xadd.c |   48 --
 1 files changed, 41 insertions(+), 7 deletions(-)

diff --git a/kernel/locking/rwsem-xadd.c b/kernel/locking/rwsem-xadd.c
index 3330c0a..42c8dda 100644
--- a/kernel/locking/rwsem-xadd.c
+++ b/kernel/locking/rwsem-xadd.c
@@ -83,6 +83,12 @@
  *  (2) WAITING_BIAS - ACTIVE_WRITE_BIAS < count < 0
  */
 
+static inline bool count_has_writer(long count)
+{
+   return (count < RWSEM_WAITING_BIAS) || ((count < 0) &&
+  (count > RWSEM_WAITING_BIAS - RWSEM_ACTIVE_WRITE_BIAS));
+}
+
 /*
  * Initialize an rwsem:
  */
@@ -294,6 +300,25 @@ static inline bool rwsem_try_write_lock_unqueued(struct 
rw_semaphore *sem)
}
 }
 
+/*
+ * Try to acquire read lock before the reader is put on wait queue
+ */
+static inline bool rwsem_try_read_lock_unqueued(struct rw_semaphore *sem)
+{
+   long count = atomic_long_read(>count);
+
+   if (count_has_writer(count))
+   return false;
+   count = atomic_long_add_return_acquire(RWSEM_ACTIVE_READ_BIAS,
+  >count);
+   if (!count_has_writer(count))
+   return true;
+
+   /* Back out the change */
+   atomic_long_add(-RWSEM_ACTIVE_READ_BIAS, >count);
+   return false;
+}
+
 static inline bool rwsem_can_spin_on_owner(struct rw_semaphore *sem)
 {
struct task_struct *owner;
@@ -360,7 +385,8 @@ out:
return rwsem_owner_is_reader(READ_ONCE(sem->owner)) ? 0 : 1;
 }
 
-static bool rwsem_optimistic_spin(struct rw_semaphore *sem)
+static bool rwsem_optimistic_spin(struct rw_semaphore *sem,
+ enum rwsem_waiter_type type)
 {
bool taken = false;
int owner_state;/* Lock owner state */
@@ -388,10 +414,11 @@ static bool rwsem_optimistic_spin(struct rw_semaphore 
*sem)
/*
 * Try to acquire the lock
 */
-   if (rwsem_try_write_lock_unqueued(sem)) {
-   taken = true;
+   taken = (type == RWSEM_WAITING_FOR_WRITE)
+ ? rwsem_try_write_lock_unqueued(sem)
+ : rwsem_try_read_lock_unqueued(sem);
+   if (taken)
break;
-   }
 
/*
 * We only decremnt the rspin_cnt when the lock is owned
@@ -426,7 +453,8 @@ static bool rwsem_optimistic_spin(struct rw_semaphore *sem)
 * Check the success or failure of writer spinning on reader so as
 * to adjust the rspin_enabled count accordingly.
 */
-   if (rwsem_owner_is_reader(sem->owner)) {
+   if ((type == RWSEM_WAITING_FOR_WRITE) &&
+   rwsem_owner_is_reader(sem->owner)) {
/*
 * Update rspin_enabled for reader spinning.
 *
@@ -466,7 +494,8 @@ static inline bool reader_spinning_enabled(struct 
rw_semaphore *sem)
return sem->rspin_enabled;
 }
 #else
-static bool rwsem_optimistic_spin(struct rw_semaphore *sem)
+static bool rwsem_optimistic_spin(struct rw_semaphore *sem,
+ enum rwsem_waiter_type type)
 {
return false;
 }
@@ -500,6 +529,11 @@ struct rw_semaphore __sched * 
rwsem_down_read_failed(struct rw_semaphore *sem)
 */
atomic_long_add(-RWSEM_ACTIVE_READ_BIAS, >count);
 
+   /* do optimistic spinning and steal lock if possible */
+   if (reader_spinning_enabled(sem) &&
+   rwsem_optimistic_spin(sem, RWSEM_WAITING_FOR_READ))
+   return sem;
+
/* set up my own style of waitqueue */
waiter.task = tsk;
waiter.type = RWSEM_WAITING_FOR_READ;
@@ -556,7 +590,7 @@ __rwsem_down_write_failed_common(struct rw_semaphore *sem, 
int state)
count = atomic_long_sub_return(RWSEM_ACTIVE_WRITE_BIAS, >count);
 
/* do optimistic spinning and steal lock if possible */
-   if (rwsem_optimistic_spin(sem))
+   if (rwsem_optimistic_spin(sem, RWSEM_WAITING_FOR_WRITE))
return sem;
 
/*
-- 
1.7.1

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[RFC PATCH-tip/locking/core v3 10/10] locking/rwsem: Add a boot parameter to reader spinning threshold

[Waiman Long]

The default reader spining threshold is current set to 4096. However,
the right reader spinning threshold may vary from one system to
another and among the different architectures. This patch adds a new
kernel boot parameter to modify the threshold value. This enables
better tailoring to the needs of different systems as well as for
testing purposes.

Signed-off-by: Waiman Long 
---
 Documentation/kernel-parameters.txt |3 +++
 kernel/locking/rwsem-xadd.c |   14 +-
 2 files changed, 16 insertions(+), 1 deletions(-)

diff --git a/Documentation/kernel-parameters.txt 
b/Documentation/kernel-parameters.txt
index 82b42c9..3bee995 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -3645,6 +3645,9 @@ bytes respectively. Such letter suffixes can also be 
entirely omitted.
 
rw  [KNL] Mount root device read-write on boot
 
+   rwsem_rspin_threshold=
+   [KNL] Set rw semaphore reader spinning threshold
+
S   [KNL] Run init in single mode
 
s390_iommu= [HW,S390]
diff --git a/kernel/locking/rwsem-xadd.c b/kernel/locking/rwsem-xadd.c
index c6b6105..6360180 100644
--- a/kernel/locking/rwsem-xadd.c
+++ b/kernel/locking/rwsem-xadd.c
@@ -280,6 +280,18 @@ static inline bool rwsem_try_write_lock(long count, struct 
rw_semaphore *sem)
 
 #ifdef CONFIG_RWSEM_SPIN_ON_OWNER
 /*
+ * Reader spinning threshold
+ */
+static int __read_mostly rspin_threshold = RWSEM_RSPIN_THRESHOLD;
+
+static int __init set_rspin_threshold(char *str)
+{
+   get_option(, _threshold);
+   return 0;
+}
+early_param("rwsem_rspin_threshold", set_rspin_threshold);
+
+/*
  * Try to acquire write lock before the writer has been put on wait queue.
  */
 static inline bool rwsem_try_write_lock_unqueued(struct rw_semaphore *sem)
@@ -402,7 +414,7 @@ static bool rwsem_optimistic_spin(struct rw_semaphore *sem,
if (!osq_lock(>osq))
goto done;
 
-   rspin_cnt = sem->rspin_enabled ? RWSEM_RSPIN_THRESHOLD : 0;
+   rspin_cnt = sem->rspin_enabled ? rspin_threshold : 0;
 
/*
 * Optimistically spin on the owner field and attempt to acquire the
-- 
1.7.1

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Re: [kernel-hardening] Re: [PATCH 2/2] security,perf: Allow further restriction of perf_event_open

[Daniel Micay]

> As a debian user, is this a good place to complain? Because it does
> get
> it the way.

It would be relevant to whether or not it should be set to 3 by default
in the kernel without explicit configuration, but there's no proposal to
do that. Debian has to pick a trade-off beyond security and a tiny
roadblock for developers. It's not always the case though.

In Android, there's userspace integration allowing it to be toggled by
the Android Debugging Bridge shell user so profiling tools are being
taught to automatically toggle it. Enabling ADB and then using it for
profiling is an implicit opt-in.

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Re: [PATCH V3 1/2] i2c: core: add devm apis for i2c_new_dummy()

[kbuild test robot]

Hi,

[auto build test WARNING on wsa/i2c/for-next]
[also build test WARNING on next-20160617]
[cannot apply to v4.7-rc3]
[if your patch is applied to the wrong git tree, please drop us a note to help 
improve the system]

url:
https://github.com/0day-ci/linux/commits/Laxman-Dewangan/i2c-core-add-devm-apis-for-i2c_new_dummy/20160617-215840
base:   https://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux i2c/for-next
reproduce: make htmldocs

All warnings (new ones prefixed by >>):

   include/linux/init.h:1: warning: no structured comments found
   kernel/sched/core.c:2079: warning: No description found for parameter 
'cookie'
   kernel/sys.c:1: warning: no structured comments found
   drivers/dma-buf/seqno-fence.c:1: warning: no structured comments found
>> drivers/i2c/i2c-core.c:1159: warning: bad line: 

vim +1159 drivers/i2c/i2c-core.c

  1143  
  1144  return i2c_new_device(adapter, );
  1145  }
  1146  EXPORT_SYMBOL_GPL(i2c_new_dummy);
  1147  
  1148  static void devm_i2c_dummy_release(struct device *dev, void *res)
  1149  {
  1150  i2c_unregister_device(*(struct i2c_client **)res);
  1151  }
  1152  
  1153  /**
  1154   * devm_i2c_new_dummy - Resource managed version of i2c_new_dummy().
  1155   * @dev:Device handle for which this resouce belongs to.
  1156   * @adapter:the adapter managing the device
  1157   * @address:seven bit address to be used
  1158   * Context: can sleep
> 1159  
  1160   * Please refer the details of i2c_new_dummy() for more information.
  1161   *
  1162   * This returns the new i2c client on success; or NULL to indicate an 
error.
  1163   * The new i2c_client will be automatically released when the device is 
unbound.
  1164   */
  1165  struct i2c_client *devm_i2c_new_dummy(struct device *dev,
  1166struct i2c_adapter *adapter,
  1167u16 address)

---
0-DAY kernel test infrastructureOpen Source Technology Center
https://lists.01.org/pipermail/kbuild-all   Intel Corporation


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Description: Binary data

[PATCH V3 2/2] i2c: Add devm_i2c_new_dummy() in managed list

[Laxman Dewangan]

i2c_new_dummy() gained their devm_ wrappers. Add the
devm_i2c_new_dummy() in managed APIs list.

Signed-off-by: Laxman Dewangan 
---
Changes form V2:
- Drop the devm_i2c_unregister_device()

 Documentation/driver-model/devres.txt | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/driver-model/devres.txt 
b/Documentation/driver-model/devres.txt
index f5e5223..472e446 100644
--- a/Documentation/driver-model/devres.txt
+++ b/Documentation/driver-model/devres.txt
@@ -259,6 +259,9 @@ GPIO
   devm_gpio_request_one()
   devm_gpio_free()
 
+I2C
+  devm_i2c_new_dummy()
+
 IIO
   devm_iio_device_alloc()
   devm_iio_device_free()
-- 
2.1.4

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[PATCH V3 1/2] i2c: core: add devm apis for i2c_new_dummy()

[Laxman Dewangan]

Add resource managed version of i2c_new_dummy().

This helps in:
 1. reducing the code size in error path to explicitly unregister
the new dummy client.
 2. Sometime, need of the remove callback on client driver to just
unregister the new i2c dummy client.

Signed-off-by: Laxman Dewangan 

---
Changes from V1:
- Got review comment on similar change for pinctrl and taken care of
 the same on this patch as V1 has similar issue.
- Add the new devm_ APIs in the Documentation/driver-model/devres.txt
- Will push the change for using this new APIs later once this is
  applied as most of consumer for these APIs are in other subsystem like
  MFD/RTC.

Changes from V2:
- Drop devm_i2c_unregister_device() as it is not used in general.
---
 drivers/i2c/i2c-core.c | 41 +
 include/linux/i2c.h|  4 
 2 files changed, 45 insertions(+)

diff --git a/drivers/i2c/i2c-core.c b/drivers/i2c/i2c-core.c
index 952d2f0..dc30b9b 100644
--- a/drivers/i2c/i2c-core.c
+++ b/drivers/i2c/i2c-core.c
@@ -1145,6 +1145,47 @@ struct i2c_client *i2c_new_dummy(struct i2c_adapter 
*adapter, u16 address)
 }
 EXPORT_SYMBOL_GPL(i2c_new_dummy);
 
+static void devm_i2c_dummy_release(struct device *dev, void *res)
+{
+   i2c_unregister_device(*(struct i2c_client **)res);
+}
+
+/**
+ * devm_i2c_new_dummy - Resource managed version of i2c_new_dummy().
+ * @dev:   Device handle for which this resouce belongs to.
+ * @adapter:   the adapter managing the device
+ * @address:   seven bit address to be used
+ * Context:can sleep
+
+ * Please refer the details of i2c_new_dummy() for more information.
+ *
+ * This returns the new i2c client on success; or NULL to indicate an error.
+ * The new i2c_client will be automatically released when the device is 
unbound.
+ */
+struct i2c_client *devm_i2c_new_dummy(struct device *dev,
+ struct i2c_adapter *adapter,
+ u16 address)
+{
+   struct i2c_client **ptr, *i2c_dummy;
+
+   ptr = devres_alloc(devm_i2c_dummy_release, sizeof(*ptr),
+  GFP_KERNEL);
+   if (!ptr)
+   return NULL;
+
+   i2c_dummy = i2c_new_dummy(adapter, address);
+   if (!i2c_dummy) {
+   devres_free(ptr);
+   return NULL;
+   }
+
+   *ptr = i2c_dummy;
+   devres_add(dev, ptr);
+
+   return i2c_dummy;
+}
+EXPORT_SYMBOL_GPL(devm_i2c_new_dummy);
+
 /**
  * i2c_new_secondary_device - Helper to get the instantiated secondary address
  * and create the associated device
diff --git a/include/linux/i2c.h b/include/linux/i2c.h
index 6df7bad..257b239 100644
--- a/include/linux/i2c.h
+++ b/include/linux/i2c.h
@@ -355,6 +355,10 @@ i2c_new_secondary_device(struct i2c_client *client,
u16 default_addr);
 
 extern void i2c_unregister_device(struct i2c_client *);
+
+extern struct i2c_client *
+devm_i2c_new_dummy(struct device *dev, struct i2c_adapter *adap, u16 address);
+
 #endif /* I2C */
 
 /* Mainboard arch_initcall() code should register all its I2C devices.
-- 
2.1.4

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Re: [PATCH v8 1/4] i2c: add a protocol parameter to the alert callback

[Wolfram Sang]

On Thu, Jun 09, 2016 at 04:53:47PM +0200, Benjamin Tissoires wrote:
> .alert() is meant to be generic, but there is currently no way
> for the device driver to know which protocol generated the alert.
> Add a parameter in .alert() to help the device driver to understand
> what is given in data.
> 
> This patch is required to have the support of SMBus Host Notify protocol
> through .alert().
> 
> Tested-by: Andrew Duggan 
> For hwmon:
> Acked-by: Guenter Roeck 
> For IPMI:
> Acked-by: Corey Minyard 
> Signed-off-by: Benjamin Tissoires 

Applied to for-next, thanks!



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Re: [PATCH v8 2/4] i2c-smbus: add SMBus Host Notify support

[Wolfram Sang]

On Thu, Jun 09, 2016 at 04:53:48PM +0200, Benjamin Tissoires wrote:
> SMBus Host Notify allows a slave device to act as a master on a bus to
> notify the host of an interrupt. On Intel chipsets, the functionality
> is directly implemented in the firmware. We just need to export a
> function to call .alert() on the proper device driver.
> 
> i2c_handle_smbus_host_notify() behaves like i2c_handle_smbus_alert().
> When called, it schedules a task that will be able to sleep to go through
> the list of devices attached to the adapter.
> 
> The current implementation allows one Host Notification to be scheduled
> while an other is running.
> 
> Tested-by: Andrew Duggan 
> Signed-off-by: Benjamin Tissoires 

Applied to for-next, thanks!



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Re: [RFC v1 3/4] x86, boot: Implement ASLR for kernel memory sections (x86_64)

[Ingo Molnar]

* Ingo Molnar  wrote:

> 
> * Thomas Garnier  wrote:
> 
> >  arch/x86/include/asm/kaslr.h|  12 +++
> 
> Hm, what tree is this patch against? asm/kaslr.h does not exist upstream or 
> in the 
> x86 tree.

So the problem is that this file gets introduced by:

  [PATCH v5 1/4] x86, boot: Refactor KASLR entropy functions

... but that patch did not get carried over into this series:

  [PATCH v6 0/3] x86/mm: memory area address KASLR

Thanks,

Ingo
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Re: [RFC v1 3/4] x86, boot: Implement ASLR for kernel memory sections (x86_64)

[Ingo Molnar]

* Ingo Molnar  wrote:

> 
> * Thomas Garnier  wrote:
> 
> >  arch/x86/include/asm/kaslr.h|  12 +++
> 
> Hm, what tree is this patch against? asm/kaslr.h does not exist upstream or 
> in the 
> x86 tree.

Ah, never mind, introduced by the first patch.

Thanks,

Ingo
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Re: [RFC v1 3/4] x86, boot: Implement ASLR for kernel memory sections (x86_64)

[Ingo Molnar]

* Thomas Garnier  wrote:

>  arch/x86/include/asm/kaslr.h|  12 +++

Hm, what tree is this patch against? asm/kaslr.h does not exist upstream or in 
the 
x86 tree.

Thanks,

Ingo
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Re: [PATCH Documentation/memory-barriers.txt] Clarify limited control-dependency scope

[Ingo Molnar]

* Paul E. McKenney  wrote:

> Nothing in the control-dependencies section of memory-barriers.txt
> says that control dependencies don't extend beyond the end of the
> if-statement containing the control dependency.  Worse yet, in many
> situations, they do extend beyond that if-statement.  In particular,
> the compiler cannot destroy the control dependency given proper use of
> READ_ONCE() and WRITE_ONCE().  However, a weakly ordered system having
> a conditional-move instruction provides the control-dependency guarantee
> only to code within the scope of the if-statement itself.
> 
> This commit therefore adds words and an example demonstrating this
> limitation of control dependencies.
> 
> Reported-by: Will Deacon 
> Signed-off-by: Paul E. McKenney 
> Acked-by: Peter Zijlstra (Intel) 
> 
> diff --git a/Documentation/memory-barriers.txt 
> b/Documentation/memory-barriers.txt
> index 147ae8ec836f..a4d0a99de04d 100644
> --- a/Documentation/memory-barriers.txt
> +++ b/Documentation/memory-barriers.txt
> @@ -806,6 +806,41 @@ out-guess your code.  More generally, although 
> READ_ONCE() does force
>  the compiler to actually emit code for a given load, it does not force
>  the compiler to use the results.
>  
> +In addition, control dependencies apply only to the then-clause and
> +else-clause of the if-statement in question.  In particular, it does
> +not necessarily apply to code following the if-statement:
> +
> + q = READ_ONCE(a);
> + if (q) {
> + WRITE_ONCE(b, p);
> + } else {
> + WRITE_ONCE(b, r);
> + }
> + WRITE_ONCE(c, 1);  /* BUG: No ordering against the read from "a". */
> +
> +It is tempting to argue that there in fact is ordering because the
> +compiler cannot reorder volatile accesses and also cannot reorder
> +the writes to "b" with the condition.  Unfortunately for this line
> +of reasoning, the compiler might compile the two writes to "b" as
> +conditional-move instructions, as in this fanciful pseudo-assembly
> +language:

While CMOV would be the typical situation, even without CMOV the compiler could 
also internally transform it to:

> + if (q)
> + WRITE_ONCE(b, p);
> + if (!q)
> + WRITE_ONCE(b, r);

... and CPU speculation flow could get past the two branches without seeing any 
ordering constraint with the writes to 'b'.

I.e. conditions are not 'atomic', they can be 'torn' by the compiler just as 
much 
as reads or writes can be torn.

Thanks,

Ingo
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Re: [kernel-hardening] [PATCH 2/2] security,perf: Allow further restriction of perf_event_open

[Peter Zijlstra]

On Thu, Jun 16, 2016 at 03:27:55PM -0700, Kees Cook wrote:
> Hi guys,
> 
> This patch wasn't originally CCed to you (I'm fixing that now). Would
> you consider taking this into the perf tree? 

No.

> It's been in active use
> in both Debian and Android for a while now.

Very nice of you all to finally inform us I suppose :/

> >>> When kernel.perf_event_open is set to 3 (or greater), disallow all
> >>> access to performance events by users without CAP_SYS_ADMIN.
> >>> Add a Kconfig symbol CONFIG_SECURITY_PERF_EVENTS_RESTRICT that
> >>> makes this value the default.
> >>>
> >>> This is based on a similar feature in grsecurity
> >>> (CONFIG_GRKERNSEC_PERF_HARDEN).  This version doesn't include making
> >>> the variable read-only.  It also allows enabling further restriction
> >>> at run-time regardless of whether the default is changed.

This Changelog is completely devoid of information. _WHY_ are you doing
this?

Also, hate the CONFIG.
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