Re: [PATCH 0/1] Documentation: convert sh interfaces to RST

[Rob Landley]

On 02/12/2017 05:35 PM, Jonathan Corbet wrote:
> On Fri, 20 Jan 2017 09:06:41 +1100
> Steve Kowalik  wrote:
> 
>> The following patch converts the SuperH interfaces DocBook into RST,
>> however, I've not added it to the toctree, since I'm not 100% clear
>> where it best fits.
> 
> So I have to apologize, this fell through the cracks in the disaster that
> is my inbox.
> 
> The conversion itself looks mostly OK.  There is, however, a copyright
> assertion in the original template file that should really be preserved
> in the new file as well; usually I put those in as comments at the top of
> the RST file.
> 
> As for where it fits; it seems maybe we need a subbook for
> architecture-specific stuff.  Documentation/arch or /arch-guide?

Documentation/arch mirrors the kernel source layout, and I actually
submitted patches to collate the various arch directories under that
many moons ago. You may remember:

  https://lwn.net/Articles/28/

> Thanks,
> 
> jon

Rob
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[RFC][PATCH] cpufreq: User/admin documentation update and consolidation

[Rafael J. Wysocki]

From: Rafael J. Wysocki 

The user/admin documentation of cpufreq is badly outdated.  It
conains stale and/or inaccurate information along with things
that are not particularly useful.  Also, some of the important
pieces are missing from it.

For this reason, add a new user/admin document for cpufreq
containing current information to admin-guide and drop the old
outdated .txt documents it is replacing.

Since there will be more PM documents in admin-guide going forward,
create a separate directory for them and put the cpufreq document
in there right away.

Signed-off-by: Rafael J. Wysocki 
---

Something I've been working on for quite a while recently.

Comments welcome.  In particular, please check if the information in the new
doc is as accurate as it should be (please note that it documents the current
state, so new code changes under discussion are not reflected by it).

Thanks,
Rafael

---
 Documentation/admin-guide/index.rst  |1 
 Documentation/admin-guide/pm/cpufreq.rst |  699 +++
 Documentation/admin-guide/pm/index.rst   |   15 
 Documentation/cpu-freq/boost.txt |   93 
 Documentation/cpu-freq/governors.txt |  301 -
 Documentation/cpu-freq/user-guide.txt|  226 --
 6 files changed, 715 insertions(+), 620 deletions(-)

Index: linux-pm/Documentation/admin-guide/pm/cpufreq.rst
===
--- /dev/null
+++ linux-pm/Documentation/admin-guide/pm/cpufreq.rst
@@ -0,0 +1,699 @@
+.. |struct| replace:: :c:type:`struct`
+
+===
+CPU Performance Scaling
+===
+
+::
+
+ Copyright (c) 2017 Intel Corp., Rafael J. Wysocki 
+
+The Concept of CPU Performance Scaling
+==
+
+The majority of modern processors are capable of operating in a number of
+different clock frequency and voltage configurations, often referred to as
+Operating Performance Points or P-states (in ACPI terminology).  As a rule,
+the higher the clock frequency and the higher the voltage, the more 
instructions
+can be retired by the CPU over a unit of time, but also the higher the clock
+frequency and the higher the voltage, the more energy is consumed over a unit 
of
+time (or the more power is drawn) by the CPU in the given P-state.  Therefore
+there is a natural tradeoff between the CPU capacity (the number of 
instructions
+that can be executed over a unit of time) and the power drawn by the CPU.
+
+In some situations it is desirable or even necessary to run the program as fast
+as possible and then there is no reason to use any P-states different from the
+highest one (i.e. the highest-performance frequency/voltage configuration
+available).  In some other cases, however, it may not be necessary to execute
+instructions so quickly and maintaining the highest available CPU capacity for 
a
+relatively long time without utilizing it entirely may be regarded as wasteful.
+It also may not be physically possible to maintain maximum CPU capacity for too
+long for thermal or power supply capacity reasons or similar.  To cover those
+cases, there are hardware interfaces allowing CPUs to be switched between
+different frequency/voltage configurations or (in the ACPI terminology) to be
+put into different P-states.
+
+Typically, they are used along with algorithms to estimate the required CPU
+capacity, so as to decide which P-states to put the CPUs into.  Of course, 
since
+the utilization of the system generally changes over time, that has to be done
+repeatedly on a regular basis.  The activity by which this happens is referred
+to as CPU performance scaling or CPU frequency scaling (because it involves
+adjusting the CPU clock frequency).
+
+
+CPU Performance Scaling in Linux
+
+
+The Linux kernel supports CPU performance scaling by means of the ``CPUFreq``
+(CPU Frequency scaling) subsystem that consists of three layers of code: the
+core, scaling governors and scaling drivers.
+
+The ``CPUFreq`` core provides the common code infrastructure and user space
+interfaces for all platforms that support CPU performance scaling.  It defines
+the basic framework in which the other components operate.
+
+Scaling governors implement algorithms to estimate the required CPU capacity.
+As a rule, each governor implements one, possibly parametrized, scaling
+algorithm.
+
+Scaling drivers talk to the hardware.  They provide scaling governors with
+information on the available P-states (or P-state ranges in some cases) and
+access platform-specific hardware interfaces to change CPU P-states as 
requested
+by scaling governors.
+
+In principle, all available scaling governors can be used with every scaling
+driver.  That design is based on the observation that the information used by
+performance scaling algorithms for P-state selection can be represented in a
+platform-independent form in the majority of cases, so it should be possib

Re: [PATCH v4 1/4] x86/mm: Adapt MODULES_END based on Fixmap section size

[Thomas Garnier]

This patch aligns MODULES_END to the beginning of the Fixmap section.
It optimizes the space available for both sections. The address is
pre-computed based on the number of pages required by the Fixmap
section.

It will allow GDT remapping in the Fixmap section. The current
MODULES_END static address does not provide enough space for the kernel
to support a large number of processors.

Signed-off-by: Thomas Garnier 
---
Based on next-20170213
Fixed fixmap dependencies on random configurations.
---
 Documentation/x86/x86_64/mm.txt | 5 -
 arch/x86/include/asm/pgtable_64_types.h | 3 ++-
 arch/x86/kernel/module.c| 1 +
 arch/x86/mm/dump_pagetables.c   | 1 +
 arch/x86/mm/kasan_init_64.c | 1 +
 mm/vmalloc.c| 1 +
 6 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/Documentation/x86/x86_64/mm.txt b/Documentation/x86/x86_64/mm.txt
index 5724092db811..ee3f9c30957c 100644
--- a/Documentation/x86/x86_64/mm.txt
+++ b/Documentation/x86/x86_64/mm.txt
@@ -19,7 +19,7 @@ ff00 - ff7f (=39 bits) %esp
fixup stacks
 ffef - fffe (=64 GB) EFI region mapping space
 ... unused hole ...
 8000 - 9fff (=512 MB)  kernel text mapping, from phys 0
-a000 - ff5f (=1526 MB) module mapping space
+a000 - ff5f (=1526 MB) module mapping space (variable)
 ff60 - ffdf (=8 MB) vsyscalls
 ffe0 -  (=2 MB) unused hole

@@ -39,6 +39,9 @@ memory window (this size is arbitrary, it can be
raised later if needed).
 The mappings are not part of any other kernel PGD and are only available
 during EFI runtime calls.

+The module mapping space size changes based on the CONFIG requirements for the
+following fixmap section.
+
 Note that if CONFIG_RANDOMIZE_MEMORY is enabled, the direct mapping of all
 physical memory, vmalloc/ioremap space and virtual memory map are randomized.
 Their order is preserved but their base will be offset early at boot time.
diff --git a/arch/x86/include/asm/pgtable_64_types.h
b/arch/x86/include/asm/pgtable_64_types.h
index 3a264200c62f..bb05e21cf3c7 100644
--- a/arch/x86/include/asm/pgtable_64_types.h
+++ b/arch/x86/include/asm/pgtable_64_types.h
@@ -67,7 +67,8 @@ typedef struct { pteval_t pte; } pte_t;
 #endif /* CONFIG_RANDOMIZE_MEMORY */
 #define VMALLOC_END (VMALLOC_START + _AC((VMALLOC_SIZE_TB << 40) - 1, UL))
 #define MODULES_VADDR(__START_KERNEL_map + KERNEL_IMAGE_SIZE)
-#define MODULES_END  _AC(0xff00, UL)
+/* The module sections ends with the start of the fixmap */
+#define MODULES_END   __fix_to_virt(__end_of_fixed_addresses + 1)
 #define MODULES_LEN   (MODULES_END - MODULES_VADDR)
 #define ESPFIX_PGD_ENTRY _AC(-2, UL)
 #define ESPFIX_BASE_ADDR (ESPFIX_PGD_ENTRY << PGDIR_SHIFT)
diff --git a/arch/x86/kernel/module.c b/arch/x86/kernel/module.c
index 477ae806c2fa..fad61caac75e 100644
--- a/arch/x86/kernel/module.c
+++ b/arch/x86/kernel/module.c
@@ -35,6 +35,7 @@
 #include 
 #include 
 #include 
+#include 

 #if 0
 #define DEBUGP(fmt, ...) \
diff --git a/arch/x86/mm/dump_pagetables.c b/arch/x86/mm/dump_pagetables.c
index 8aa6bea1cd6c..90170415f08a 100644
--- a/arch/x86/mm/dump_pagetables.c
+++ b/arch/x86/mm/dump_pagetables.c
@@ -19,6 +19,7 @@
 #include 

 #include 
+#include 

 /*
  * The dumper groups pagetable entries of the same type into one, and for
diff --git a/arch/x86/mm/kasan_init_64.c b/arch/x86/mm/kasan_init_64.c
index 0493c17b8a51..34f167cf3316 100644
--- a/arch/x86/mm/kasan_init_64.c
+++ b/arch/x86/mm/kasan_init_64.c
@@ -8,6 +8,7 @@

 #include 
 #include 
+#include 

 extern pgd_t early_level4_pgt[PTRS_PER_PGD];
 extern struct range pfn_mapped[E820_X_MAX];
diff --git a/mm/vmalloc.c b/mm/vmalloc.c
index 011b446f8758..84e637f2fa49 100644
--- a/mm/vmalloc.c
+++ b/mm/vmalloc.c
@@ -35,6 +35,7 @@
 #include 
 #include 
 #include 
+#include 

 #include "internal.h"

-- 
2.11.0.483.g087da7b7c-goog

On Fri, Feb 17, 2017 at 8:00 AM, Thomas Garnier  wrote:
> I will send an update patch on this thread to fix the fixmap dependencies.
>
> On Thu, Feb 16, 2017 at 4:45 PM, kbuild test robot  wrote:
>>
>> Hi Thomas,
>>
>> [auto build test ERROR on next-20170216]
>> [also build test ERROR on v4.10-rc8]
>> [cannot apply to tip/x86/core kvm/linux-next tip/auto-latest v4.9-rc8
>> v4.9-rc7 v4.9-rc6]
>> [if your patch is applied to the wrong git tree, please drop us a note to
>> help improve the system]
>>
>> url:
>> https://github.com/0day-ci/linux/commits/Thomas-Garnier/x86-mm-Adapt-MODULES_END-based-on-Fixmap-section-size/20170217-072759
>> config: x86_64-randconfig-s4-02170325 (attached as .config)
>> compiler: gcc-6 (Debian 6.2.0-3) 6.2.0 20160901
>> reproduce:
>> # save the attached .config to linux build tree
>>

Re: [PATCH v2 0/4] New Microsemi PCI Switch Management Driver

[Logan Gunthorpe]

Hi Bjorn,

Can you give us an idea of when you might be able to comment on our
patchset? We've addressed all the outstanding issues and have a couple
of reviewed and tested tags. So we'd like to see this move forward as
soon as possible.

I can do a respin with the tags collected or address any concerns you
may have, just please let us know.

Thanks,

Logan

On 02/02/17 11:05 AM, Logan Gunthorpe wrote:
> Changes since v1:
> 
> * Rebased onto 4.10-rc6 (cleanly)
> * Split the patch into a few more easily digestible patches (as
>   suggested by Greg Kroah-Hartman)
> * Folded switchtec.c into switchtec.h (per Greg)
> * Fixed a bunch of 32bit build warnings caught by the kbuild test robot
> * Fixed some issues in the documentation so it has a proper
>   reStructredText format (as noted by Jonathan Corbet)
> * Fixed padding and sizes in the IOCTL structures as noticed by Emil
>   Velikov and used pahole to verify their consistency across 32 and 64
>   bit builds
> * Reworked one of the IOCTL interfaces to be more future proof (per
>   Emil).
> 
> Changes since RFC:
> 
> * Fixed incorrect use of the drive model as pointed out by Greg
>   Kroah-Hartman
> * Used devm functions as suggested by Keith Busch
> * Added a handful of sysfs attributes to the switchtec class
> * Added a handful of IOCTLs to the switchtec device
> * A number of miscellaneous bug fixes
> 
> --
> 
> Hi,
> 
> This is a continuation of the RFC we posted lasted month [1] which
> proposes a management driver for Microsemi's Switchtec line of PCI
> switches. This hardware is still looking to be used in the Open
> Compute Platform
> 
> To make this entirely clear: the Switchtec products are compliant
> with the PCI specifications and are supported today with the standard
> in-kernel driver. However, these devices also expose a management endpoint
> on a separate PCI function address which can be used to perform some
> advanced operations. This is a driver for that function. See the patch
> for more information.
> 
> Since the RFC, we've made the changes requested by Greg Kroah-Hartman
> and Keith Busch, and we've also fleshed out a number of features. We've
> added a couple of IOCTLs and sysfs attributes which are documented in
> the patch. Significant work has also been done on the userspace tool
> which is available under a GPL license at [2]. We've also had testing
> done by some of the interested parties.
> 
> We hope to see this work included in either 4.11 or 4.12 assuming a
> smooth review process.
> 
> The patch is based off of the v4.10-rc6 release.
> 
> Thanks for your review,
> 
> Logan
> 
> [1] https://www.spinics.net/lists/linux-pci/msg56897.html
> [2] https://github.com/sbates130272/switchtec-user
> 
> --
> 
> Logan Gunthorpe (4):
>   MicroSemi Switchtec management interface driver
>   switchtec: Add user interface documentation
>   switchtec: Add sysfs attributes to the Switchtec driver
>   switchtec: Add IOCTLs to the Switchtec driver
> 
>  Documentation/ABI/testing/sysfs-class-switchtec |   96 ++
>  Documentation/ioctl/ioctl-number.txt|1 +
>  Documentation/switchtec.txt |   80 ++
>  MAINTAINERS |   11 +
>  drivers/pci/Kconfig |1 +
>  drivers/pci/Makefile|1 +
>  drivers/pci/switch/Kconfig  |   13 +
>  drivers/pci/switch/Makefile |1 +
>  drivers/pci/switch/switchtec.c  | 1608 
> +++
>  include/uapi/linux/switchtec_ioctl.h|  132 ++
>  10 files changed, 1944 insertions(+)
>  create mode 100644 Documentation/ABI/testing/sysfs-class-switchtec
>  create mode 100644 Documentation/switchtec.txt
>  create mode 100644 drivers/pci/switch/Kconfig
>  create mode 100644 drivers/pci/switch/Makefile
>  create mode 100644 drivers/pci/switch/switchtec.c
>  create mode 100644 include/uapi/linux/switchtec_ioctl.h
> 
> --
> 2.1.4
> 
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Re: [PATCHv3 2/2] arch: Rename CONFIG_DEBUG_RODATA and CONFIG_DEBUG_MODULE_RONX

[Mark Rutland]

On Thu, Feb 16, 2017 at 05:08:20PM -0800, Kees Cook wrote:
> On Thu, Feb 16, 2017 at 2:25 PM, Pavel Machek  wrote:
> > Hi!
> >
> >>
> >> -config DEBUG_RODATA
> >> +config STRICT_KERNEL_RWX
> >>   bool "Make kernel text and rodata read-only" if 
> >> ARCH_OPTIONAL_KERNEL_RWX
> >>   depends on ARCH_HAS_STRICT_KERNEL_RWX
> >>   default !ARCH_OPTIONAL_KERNEL_RWX ||
> >
> > Debug features are expected to have runtime cost, so kconfig help is
> > silent about those. But there are runtime costs, right? It would be
> > nice to mention them in the help text...
> 
> It depends on the architecture. The prior help text for arm said:
> 
>  The tradeoff is that each region is padded to section-size (1MiB)
>  boundaries (because their permissions are different and splitting
>  the 1M pages into 4K ones causes TLB performance problems), which
>  can waste memory.
> 
> parisc (somewhat inaccurately) said:
> 
>  This option may have a slight performance impact because a
>  portion of the kernel code won't be covered by a TLB anymore.
> 
> IIUC, arm64 does what parisc is hinting at: mappings at the end are
> broken down to PAGE_SIZE. On x86, IIUC, there's actually no change to
> TLB performance due to how the mappings are already set up.

On arm64, we split down to page granularity if needed, but use the
largest possible mapping we can (e.g. if we can use a 2M block, we do).

Because of the way we freed the init area, we already couldn't use
larger mappings anyway. Applying the strict permissions didn't come at a
measureable overhead in any real testing.

> I'm not sure the best way to express this in the new help text. Do you
> have some suggestions on wording? Personally, I don't really think
> it's worth mentioning this in Kconfig help, which, in theory, is
> supposed to limit how technical it gets. And I think the performance
> impact is almost entirely negligible compared to the risks addressed.

I also don't see much point in describing some hypothetical architecture
specific overhead here. In most cases this can't be turned off (so there
isn't anything to comapre it to, and hence no cost). Where people want
to turn it off, they already know why they wish to do so.

Thanks,
Mark.
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Re: [PATCH] Documentation: Note QDF2400 SoC Erratum 44

[Will Deacon]

On Wed, Feb 15, 2017 at 04:54:07PM -0500, Christopher Covington wrote:
> The Qualcomm Datacenter Technologies QDF2400 family of SoCs contains a
> custom (non-PrimeCell) implementation of the SBSA UART. Occasionally the
> BUSY bit in the Flag Register gets stuck as 1, erratum 44 for both 2432v1
> and 2400v1 SoCs.Checking that the Transmit FIFO Empty (TXFE) bit is 0,
> instead of checking that the BUSY bit is 1, works around the issue. Note
> this in the customary location. To minimize conflicts, this documentation
> update is separate from the code changes, "tty: pl011: Work around QDF2400
> E44 stuck BUSY bit".
> 
> Signed-off-by: Christopher Covington 
> Acked-by: Russell King 
> Acked-by: Mark Rutland 
> Acked-by: Timur Tabi 
> ---
> Documentation to go with https://patchwork.kernel.org/patch/9575103/

Please poke me when that goes into -next. I don't want to merge the doc
until the patch is queued too.

Thanks,

Will
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Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support

[Joao Pinto]

Às 9:50 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
> Add endpoint mode support to designware driver. This uses the
> EP Core layer introduced recently to add endpoint mode support.
> *Any* function driver can now use this designware device
> in order to achieve the EP functionality.
> 
> Signed-off-by: Kishon Vijay Abraham I 
> ---
>  drivers/pci/dwc/Kconfig  |5 +
>  drivers/pci/dwc/Makefile |1 +
>  drivers/pci/dwc/pcie-designware-ep.c |  342 
> ++
>  drivers/pci/dwc/pcie-designware.c|   51 +
>  drivers/pci/dwc/pcie-designware.h|   72 +++
>  5 files changed, 471 insertions(+)
>  create mode 100644 drivers/pci/dwc/pcie-designware-ep.c
> 
> diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig
> index dfb8a69..00335c7 100644
> --- a/drivers/pci/dwc/Kconfig
> +++ b/drivers/pci/dwc/Kconfig
> @@ -9,6 +9,11 @@ config PCIE_DW_HOST
>   depends on PCI_MSI_IRQ_DOMAIN
>  select PCIE_DW
>  
> +config PCIE_DW_EP
> + bool
> + depends on PCI_ENDPOINT
> + select PCIE_DW
> +
>  config PCI_DRA7XX
>   bool "TI DRA7xx PCIe controller"
>   depends on PCI
> diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile
> index a2df13c..b38425d 100644
> --- a/drivers/pci/dwc/Makefile
> +++ b/drivers/pci/dwc/Makefile
> @@ -1,5 +1,6 @@
>  obj-$(CONFIG_PCIE_DW) += pcie-designware.o
>  obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
> +obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
>  obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
>  obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
>  obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
> diff --git a/drivers/pci/dwc/pcie-designware-ep.c 
> b/drivers/pci/dwc/pcie-designware-ep.c
> new file mode 100644
> index 000..e465c5e
> --- /dev/null
> +++ b/drivers/pci/dwc/pcie-designware-ep.c
> @@ -0,0 +1,342 @@
> +/**
> + * Synopsys Designware PCIe Endpoint controller driver
> + *
> + * Copyright (C) 2017 Texas Instruments
> + * Author: Kishon Vijay Abraham I 
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 of
> + * the License as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see 
>   >.
> + */
> +
> +#include 
> +
> +#include "pcie-designware.h"
> +#include 
> +#include 
> +
> +void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
> +{
> + struct pci_epc *epc = ep->epc;
> + struct pci_epf *epf;
> +
> + list_for_each_entry(epf, &epc->pci_epf, list)
> + pci_epf_linkup(epf);
> +}
> +
> +static void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
> +{
> + u32 reg;
> +
> + reg = PCI_BASE_ADDRESS_0 + (4 * bar);
> + dw_pcie_write_dbi(pci, pci->dbi_base2, reg, 0x4, 0x0);
> + dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x4, 0x0);
> +}
> +
> +static int dw_pcie_ep_write_header(struct pci_epc *epc,
> +struct pci_epf_header *hdr)
> +{
> + struct dw_pcie_ep *ep = epc_get_drvdata(epc);
> + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> + void __iomem *base = pci->dbi_base;
> +
> + dw_pcie_write_dbi(pci, base, PCI_VENDOR_ID, 0x2, hdr->vendorid);
> + dw_pcie_write_dbi(pci, base, PCI_DEVICE_ID, 0x2, hdr->deviceid);
> + dw_pcie_write_dbi(pci, base, PCI_REVISION_ID, 0x1, hdr->revid);
> + dw_pcie_write_dbi(pci, base, PCI_CLASS_PROG, 0x1, hdr->progif_code);
> + dw_pcie_write_dbi(pci, base, PCI_CLASS_DEVICE, 0x2,
> +   hdr->subclass_code | hdr->baseclass_code << 8);
> + dw_pcie_write_dbi(pci, base, PCI_CACHE_LINE_SIZE, 0x1,
> +   hdr->cache_line_size);
> + dw_pcie_write_dbi(pci, base, PCI_SUBSYSTEM_VENDOR_ID, 0x2,
> +   hdr->subsys_vendor_id);
> + dw_pcie_write_dbi(pci, base, PCI_SUBSYSTEM_ID, 0x2, hdr->subsys_id);
> + dw_pcie_write_dbi(pci, base, PCI_INTERRUPT_PIN, 0x1,
> +   hdr->interrupt_pin);
> +
> + return 0;
> +}
> +
> +static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, enum pci_barno bar,
> +   dma_addr_t cpu_addr,
> +   enum dw_pcie_as_type as_type)
> +{
> + int ret;
> + u32 free_win;
> + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> +
> + free_win = find_first_zero_bit(&ep->ib

Re: [PATCH v2 04/22] Documentation: PCI: Guide to use pci endpoint configfs

[Christoph Hellwig]

I'm commenting on the configfs layout here instead of the patch with the
code as the issues are easier to explain that way.  I think the layout
is a bit confusing and could be cleaner by making use of pre-created
entries and symlinks.  Here is my suggestion:

/sys/kernel/config/pci_ep/functions/
.. test/# a directory for each function 
driver
   ... user-specified-name1/
   ... user-specified-name2
.. nvme/
   ... user-specified-name42/   

Each directory under /sys/kernel/config/pci_ep/functions/ is owned
by a function drivers.  Under that function driver's directory you
can create a directory for each instance of a function driver.  The
configfs layout is controlled by the function driver.  E.g. your current
EPF fields would move into the test function driver, while the nvme
function would expose totally different fields.


/sys/kernel/config/pci_ep/controllers/
... dwc-0/
... function
... dwc-1/
... function
... vhost-0/
... function

Here you have a directory for each controller that can be bound
to a function.  The directories are pre-created for each
controller port that is EP capable.
Function is a symlink to the function instance above.
Additional parameters might also be present depending on the
EPC driver.

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Re: [PATCH v2 03/22] PCI: endpoint: Introduce configfs entry for configuring EP functions

[Christoph Hellwig]

On Fri, Feb 17, 2017 at 03:20:23PM +0530, Kishon Vijay Abraham I wrote:
> Introduce a new configfs entry to configure the EP function (like
> configuring the standard configuration header entries) and to
> bind the EP function with EP controller.
> 
> Signed-off-by: Kishon Vijay Abraham I 
> ---
>  drivers/pci/endpoint/Kconfig  |   14 +-
>  drivers/pci/endpoint/Makefile |1 +
>  drivers/pci/endpoint/pci-ep-cfs.c |  427 
> +
>  3 files changed, 440 insertions(+), 2 deletions(-)
>  create mode 100644 drivers/pci/endpoint/pci-ep-cfs.c
> 
> diff --git a/drivers/pci/endpoint/Kconfig b/drivers/pci/endpoint/Kconfig
> index 7eb1c79..8470f0b 100644
> --- a/drivers/pci/endpoint/Kconfig
> +++ b/drivers/pci/endpoint/Kconfig
> @@ -6,7 +6,6 @@ menu "PCI Endpoint"
>  
>  config PCI_ENDPOINT
>   bool "PCI Endpoint Support"
> - select CONFIGFS_FS
>   help
>  Enable this configuration option to support configurable PCI
>  endpoint. This should be enabled if the platform has a PCI
> @@ -14,8 +13,19 @@ config PCI_ENDPOINT
>  
>  Enabling this option will build the endpoint library, which
>  includes endpoint controller library and endpoint function
> -library.
> +library. This will also enable the configfs entry required to
> +configure the endpoint function and used to bind the
> +function with a endpoint controller.
>  
>  If in doubt, say "N" to disable Endpoint support.
>  
> +config PCI_ENDPOINT_CONFIGFS
> + bool "PCI Endpoint Configfs Support"
> + depends on PCI_ENDPOINT
> + select CONFIGFS_FS
> + help
> +This will enable the configfs entry that can be used to
> +configure the endpoint function and used to bind the
> +function with a endpoint controller.
> +
>  endmenu
> diff --git a/drivers/pci/endpoint/Makefile b/drivers/pci/endpoint/Makefile
> index dc1bc16..dd9163c 100644
> --- a/drivers/pci/endpoint/Makefile
> +++ b/drivers/pci/endpoint/Makefile
> @@ -4,3 +4,4 @@
>  
>  obj-$(CONFIG_PCI_ENDPOINT)   += pci-epc-core.o pci-epf-core.o\
>  pci-epc-mem.o
> +obj-$(CONFIG_PCI_ENDPOINT_CONFIGFS)  += pci-ep-cfs.o
> diff --git a/drivers/pci/endpoint/pci-ep-cfs.c 
> b/drivers/pci/endpoint/pci-ep-cfs.c
> new file mode 100644
> index 000..ed0f8c2
> --- /dev/null
> +++ b/drivers/pci/endpoint/pci-ep-cfs.c
> @@ -0,0 +1,427 @@
> +/**
> + * configfs to configure the PCI endpoint
> + *
> + * Copyright (C) 2017 Texas Instruments
> + * Author: Kishon Vijay Abraham I 
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 of
> + * the License as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see .
> + */
> +
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +
> +struct pci_epf_info {
> + struct config_group group;
> + struct list_head list;
> + struct pci_epf *epf;
> +};
> +
> +struct pci_ep_info {
> + struct config_group group;
> + struct config_group pci_epf_group;
> + /* mutex to protect pci_epf list */
> + struct mutex lock;
> + struct list_head pci_epf;
> + const char *epc_name;
> + struct pci_epc *epc;
> +};
> +
> +static inline struct pci_epf_info *to_pci_epf_info(struct config_item *item)
> +{
> + return container_of(to_config_group(item), struct pci_epf_info, group);
> +}
> +
> +static inline struct pci_ep_info *to_pci_ep_info(struct config_item *item)
> +{
> + return container_of(to_config_group(item), struct pci_ep_info, group);
> +}
> +
> +#define PCI_EPF_HEADER_R(_name)  
>\
> +static ssize_t pci_epf_##_name##_show(struct config_item *item,  char 
> *page)\
> +{   \
> + struct pci_epf *epf = to_pci_epf_info(item)->epf;  \
> + if (!epf->header) {\
> + WARN_ON_ONCE("epf device not bound to function driver\n"); \

WARN_ON_ONCE takes a string to evaluate as argument, not a message

> + return 0;   

and if we return 0 here the callers will retry because that is
interpreted as a short read.  The code should be something like:

if (WARN_ON_ONCE(!epf->header))
return -EINVAL;

> + if (!epf->header) {\
>

Re: [RFC PATCH v4 19/28] swiotlb: Add warnings for use of bounce buffers with SME

[Tom Lendacky]

On 2/17/2017 9:59 AM, Konrad Rzeszutek Wilk wrote:

On Thu, Feb 16, 2017 at 09:46:19AM -0600, Tom Lendacky wrote:

Add warnings to let the user know when bounce buffers are being used for
DMA when SME is active.  Since the bounce buffers are not in encrypted
memory, these notifications are to allow the user to determine some
appropriate action - if necessary.

Signed-off-by: Tom Lendacky 
---
 arch/x86/include/asm/mem_encrypt.h |   11 +++
 include/linux/dma-mapping.h|   11 +++
 include/linux/mem_encrypt.h|6 ++
 lib/swiotlb.c  |3 +++
 4 files changed, 31 insertions(+)

diff --git a/arch/x86/include/asm/mem_encrypt.h 
b/arch/x86/include/asm/mem_encrypt.h
index 87e816f..5a17f1b 100644
--- a/arch/x86/include/asm/mem_encrypt.h
+++ b/arch/x86/include/asm/mem_encrypt.h
@@ -26,6 +26,11 @@ static inline bool sme_active(void)
return (sme_me_mask) ? true : false;
 }

+static inline u64 sme_dma_mask(void)
+{
+   return ((u64)sme_me_mask << 1) - 1;
+}
+
 void __init sme_early_encrypt(resource_size_t paddr,
  unsigned long size);
 void __init sme_early_decrypt(resource_size_t paddr,
@@ -53,6 +58,12 @@ static inline bool sme_active(void)
 {
return false;
 }
+
+static inline u64 sme_dma_mask(void)
+{
+   return 0ULL;
+}
+
 #endif

 static inline void __init sme_early_encrypt(resource_size_t paddr,
diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h
index 10c5a17..130bef7 100644
--- a/include/linux/dma-mapping.h
+++ b/include/linux/dma-mapping.h
@@ -10,6 +10,7 @@
 #include 
 #include 
 #include 
+#include 

 /**
  * List of possible attributes associated with a DMA mapping. The semantics
@@ -557,6 +558,11 @@ static inline int dma_set_mask(struct device *dev, u64 
mask)

if (!dev->dma_mask || !dma_supported(dev, mask))
return -EIO;
+
+   if (sme_active() && (mask < sme_dma_mask()))
+   dev_warn(dev,
+"SME is active, device will require DMA bounce 
buffers\n");


You can make it one line. But I am wondering if you should use
printk_ratelimit as this may fill the console up.


I thought the use of dma_set_mask() was mostly a one time probe/setup
thing so I didn't think we would get that many of these messages. If
dma_set_mask() is called much more often that that I can change this
to a printk_ratelimit().  I'll look into it further.




+
*dev->dma_mask = mask;
return 0;
 }
@@ -576,6 +582,11 @@ static inline int dma_set_coherent_mask(struct device 
*dev, u64 mask)
 {
if (!dma_supported(dev, mask))
return -EIO;
+
+   if (sme_active() && (mask < sme_dma_mask()))
+   dev_warn(dev,
+"SME is active, device will require DMA bounce 
buffers\n");


Ditto.

+
dev->coherent_dma_mask = mask;
return 0;
 }
diff --git a/include/linux/mem_encrypt.h b/include/linux/mem_encrypt.h
index 14a7b9f..6829ff1 100644
--- a/include/linux/mem_encrypt.h
+++ b/include/linux/mem_encrypt.h
@@ -28,6 +28,12 @@ static inline bool sme_active(void)
 {
return false;
 }
+
+static inline u64 sme_dma_mask(void)
+{
+   return 0ULL;
+}
+
 #endif

 #endif /* CONFIG_AMD_MEM_ENCRYPT */
diff --git a/lib/swiotlb.c b/lib/swiotlb.c
index c463067..aff9353 100644
--- a/lib/swiotlb.c
+++ b/lib/swiotlb.c
@@ -509,6 +509,9 @@ phys_addr_t swiotlb_tbl_map_single(struct device *hwdev,
if (no_iotlb_memory)
panic("Can not allocate SWIOTLB buffer earlier and can't now provide 
you with the DMA bounce buffer");

+   WARN_ONCE(sme_active(),
+ "SME is active and system is using DMA bounce buffers\n");


How does that help?

As in what can the user do with this?


It's meant just to notify the user about the condition. The user could
then decide to use an alternative device that supports a greater DMA
range (I can probably change it to a dev_warn_once() so that a device
is identified).  I would be nice if I could issue this message once per
device that experienced this.  I didn't see anything that would do
that, though.

Thanks,
Tom


+
mask = dma_get_seg_boundary(hwdev);

tbl_dma_addr &= mask;


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Re: [RFC PATCH v4 26/28] x86: Allow kexec to be used with SME

[Tom Lendacky]

On 2/17/2017 9:57 AM, Konrad Rzeszutek Wilk wrote:

On Thu, Feb 16, 2017 at 09:47:55AM -0600, Tom Lendacky wrote:

Provide support so that kexec can be used to boot a kernel when SME is
enabled.


Is the point of kexec and kdump to ehh, dump memory ? But if the
rest of the memory is encrypted you won't get much, will you?


Kexec can be used to reboot a system without going back through BIOS.
So you can use kexec without using kdump.

For kdump, just taking a quick look, the option to enable memory
encryption can be provided on the crash kernel command line and then
crash kernel can would be able to copy the memory decrypted if the
pagetable is set up properly. It looks like currently ioremap_cache()
is used to map the old memory page.  That might be able to be changed
to a memremap() so that the encryption bit is set in the mapping. That
will mean that memory that is not marked encrypted (EFI tables, swiotlb
memory, etc) would not be read correctly.



Would it make sense to include some printk to the user if they
are setting up kdump that they won't get anything out of it?


Probably a good idea to add something like that.

Thanks,
Tom



Thanks.


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Re: [RFC PATCH v4 19/28] swiotlb: Add warnings for use of bounce buffers with SME

[Konrad Rzeszutek Wilk]

On Thu, Feb 16, 2017 at 09:46:19AM -0600, Tom Lendacky wrote:
> Add warnings to let the user know when bounce buffers are being used for
> DMA when SME is active.  Since the bounce buffers are not in encrypted
> memory, these notifications are to allow the user to determine some
> appropriate action - if necessary.
> 
> Signed-off-by: Tom Lendacky 
> ---
>  arch/x86/include/asm/mem_encrypt.h |   11 +++
>  include/linux/dma-mapping.h|   11 +++
>  include/linux/mem_encrypt.h|6 ++
>  lib/swiotlb.c  |3 +++
>  4 files changed, 31 insertions(+)
> 
> diff --git a/arch/x86/include/asm/mem_encrypt.h 
> b/arch/x86/include/asm/mem_encrypt.h
> index 87e816f..5a17f1b 100644
> --- a/arch/x86/include/asm/mem_encrypt.h
> +++ b/arch/x86/include/asm/mem_encrypt.h
> @@ -26,6 +26,11 @@ static inline bool sme_active(void)
>   return (sme_me_mask) ? true : false;
>  }
>  
> +static inline u64 sme_dma_mask(void)
> +{
> + return ((u64)sme_me_mask << 1) - 1;
> +}
> +
>  void __init sme_early_encrypt(resource_size_t paddr,
> unsigned long size);
>  void __init sme_early_decrypt(resource_size_t paddr,
> @@ -53,6 +58,12 @@ static inline bool sme_active(void)
>  {
>   return false;
>  }
> +
> +static inline u64 sme_dma_mask(void)
> +{
> + return 0ULL;
> +}
> +
>  #endif
>  
>  static inline void __init sme_early_encrypt(resource_size_t paddr,
> diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h
> index 10c5a17..130bef7 100644
> --- a/include/linux/dma-mapping.h
> +++ b/include/linux/dma-mapping.h
> @@ -10,6 +10,7 @@
>  #include 
>  #include 
>  #include 
> +#include 
>  
>  /**
>   * List of possible attributes associated with a DMA mapping. The semantics
> @@ -557,6 +558,11 @@ static inline int dma_set_mask(struct device *dev, u64 
> mask)
>  
>   if (!dev->dma_mask || !dma_supported(dev, mask))
>   return -EIO;
> +
> + if (sme_active() && (mask < sme_dma_mask()))
> + dev_warn(dev,
> +  "SME is active, device will require DMA bounce 
> buffers\n");

You can make it one line. But I am wondering if you should use
printk_ratelimit as this may fill the console up.

> +
>   *dev->dma_mask = mask;
>   return 0;
>  }
> @@ -576,6 +582,11 @@ static inline int dma_set_coherent_mask(struct device 
> *dev, u64 mask)
>  {
>   if (!dma_supported(dev, mask))
>   return -EIO;
> +
> + if (sme_active() && (mask < sme_dma_mask()))
> + dev_warn(dev,
> +  "SME is active, device will require DMA bounce 
> buffers\n");

Ditto.
> +
>   dev->coherent_dma_mask = mask;
>   return 0;
>  }
> diff --git a/include/linux/mem_encrypt.h b/include/linux/mem_encrypt.h
> index 14a7b9f..6829ff1 100644
> --- a/include/linux/mem_encrypt.h
> +++ b/include/linux/mem_encrypt.h
> @@ -28,6 +28,12 @@ static inline bool sme_active(void)
>  {
>   return false;
>  }
> +
> +static inline u64 sme_dma_mask(void)
> +{
> + return 0ULL;
> +}
> +
>  #endif
>  
>  #endif   /* CONFIG_AMD_MEM_ENCRYPT */
> diff --git a/lib/swiotlb.c b/lib/swiotlb.c
> index c463067..aff9353 100644
> --- a/lib/swiotlb.c
> +++ b/lib/swiotlb.c
> @@ -509,6 +509,9 @@ phys_addr_t swiotlb_tbl_map_single(struct device *hwdev,
>   if (no_iotlb_memory)
>   panic("Can not allocate SWIOTLB buffer earlier and can't now 
> provide you with the DMA bounce buffer");
>  
> + WARN_ONCE(sme_active(),
> +   "SME is active and system is using DMA bounce buffers\n");

How does that help?

As in what can the user do with this?
> +
>   mask = dma_get_seg_boundary(hwdev);
>  
>   tbl_dma_addr &= mask;
> 
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Re: [RFC PATCH v4 26/28] x86: Allow kexec to be used with SME

[Konrad Rzeszutek Wilk]

On Thu, Feb 16, 2017 at 09:47:55AM -0600, Tom Lendacky wrote:
> Provide support so that kexec can be used to boot a kernel when SME is
> enabled.

Is the point of kexec and kdump to ehh, dump memory ? But if the
rest of the memory is encrypted you won't get much, will you?

Would it make sense to include some printk to the user if they
are setting up kdump that they won't get anything out of it?

Thanks.
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Re: [RFC PATCH v4 02/28] x86: Set the write-protect cache mode for full PAT support

[Tom Lendacky]

On 2/17/2017 5:07 AM, Borislav Petkov wrote:

On Thu, Feb 16, 2017 at 09:42:25AM -0600, Tom Lendacky wrote:

For processors that support PAT, set the write-protect cache mode
(_PAGE_CACHE_MODE_WP) entry to the actual write-protect value (x05).

Acked-by: Borislav Petkov 
Signed-off-by: Tom Lendacky 


Just a nit:

Subject should have "x86/mm/pat: " prefix but that can be fixed when
applying.


I'll go through the series and verify/fix the prefix for each patch.

Thanks,
Tom




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Re: [PATCH v2 08/22] PCI: dwc: designware: Add EP mode support

[Kishon Vijay Abraham I]

Hi,

On Friday 17 February 2017 03:20 PM, Kishon Vijay Abraham I wrote:
> Add endpoint mode support to designware driver. This uses the
> EP Core layer introduced recently to add endpoint mode support.
> *Any* function driver can now use this designware device
> in order to achieve the EP functionality.
> 
> Signed-off-by: Kishon Vijay Abraham I 
> ---
>  drivers/pci/dwc/Kconfig  |5 +
>  drivers/pci/dwc/Makefile |1 +
>  drivers/pci/dwc/pcie-designware-ep.c |  342 
> ++
>  drivers/pci/dwc/pcie-designware.c|   51 +
>  drivers/pci/dwc/pcie-designware.h|   72 +++
>  5 files changed, 471 insertions(+)
>  create mode 100644 drivers/pci/dwc/pcie-designware-ep.c
> 
> diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig
> index dfb8a69..00335c7 100644
> --- a/drivers/pci/dwc/Kconfig
> +++ b/drivers/pci/dwc/Kconfig
> @@ -9,6 +9,11 @@ config PCIE_DW_HOST
>   depends on PCI_MSI_IRQ_DOMAIN
>  select PCIE_DW
>  
> +config PCIE_DW_EP
> + bool
> + depends on PCI_ENDPOINT
> + select PCIE_DW
> +
>  config PCI_DRA7XX
>   bool "TI DRA7xx PCIe controller"
>   depends on PCI
> diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile
> index a2df13c..b38425d 100644
> --- a/drivers/pci/dwc/Makefile
> +++ b/drivers/pci/dwc/Makefile
> @@ -1,5 +1,6 @@
>  obj-$(CONFIG_PCIE_DW) += pcie-designware.o
>  obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
> +obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
>  obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
>  obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
>  obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
> diff --git a/drivers/pci/dwc/pcie-designware-ep.c 
> b/drivers/pci/dwc/pcie-designware-ep.c
> new file mode 100644
> index 000..e465c5e
> --- /dev/null
> +++ b/drivers/pci/dwc/pcie-designware-ep.c
> @@ -0,0 +1,342 @@
> +/**
> + * Synopsys Designware PCIe Endpoint controller driver
> + *
> + * Copyright (C) 2017 Texas Instruments
> + * Author: Kishon Vijay Abraham I 
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 of
> + * the License as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see .
> + */
> +
> +#include 
> +
> +#include "pcie-designware.h"
> +#include 
> +#include 
> +
> +void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
> +{
> + struct pci_epc *epc = ep->epc;
> + struct pci_epf *epf;
> +
> + list_for_each_entry(epf, &epc->pci_epf, list)
> + pci_epf_linkup(epf);

Just notices, the right place to use this list should be pci-epc-core. Will fix
this in the next revision.

Thanks
Kishon
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Re: [PATCH v2 04/22] Documentation: PCI: Guide to use pci endpoint configfs

[Joao Pinto]

Às 9:50 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
> Add Documentation to help users use pci endpoint to configure
> pci endpoint function and to bind the endpoint function
> with endpoint controller.
> 
> Signed-off-by: Kishon Vijay Abraham I 
> ---
>  Documentation/PCI/00-INDEX  |2 +
>  Documentation/PCI/endpoint/pci-endpoint-cfs.txt |   84 
> +++
>  2 files changed, 86 insertions(+)
>  create mode 100644 Documentation/PCI/endpoint/pci-endpoint-cfs.txt
> 
> diff --git a/Documentation/PCI/00-INDEX b/Documentation/PCI/00-INDEX
> index ba950b2..f84a23c 100644
> --- a/Documentation/PCI/00-INDEX
> +++ b/Documentation/PCI/00-INDEX
> @@ -14,3 +14,5 @@ pcieaer-howto.txt
>   - the PCI Express Advanced Error Reporting Driver Guide HOWTO
>  endpoint/pci-endpoint.txt
>   - guide to add endpoint controller driver and endpoint function driver.
> +endpoint/pci-endpoint-cfs.txt
> + - guide to use configfs to configure the pci endpoint function.
> diff --git a/Documentation/PCI/endpoint/pci-endpoint-cfs.txt 
> b/Documentation/PCI/endpoint/pci-endpoint-cfs.txt
> new file mode 100644
> index 000..d9f8734
> --- /dev/null
> +++ b/Documentation/PCI/endpoint/pci-endpoint-cfs.txt
> @@ -0,0 +1,84 @@
> +   CONFIGURING PCI ENDPOINT USING CONFIGFS
> +Kishon Vijay Abraham I 
> +
> +The PCI Endpoint Core exposes configfs entry (pci_ep) in order to configure 
> the
> +PCI endpoint function and in order to bind the endpoint function
> +with the endpoint controller. (For introducing other mechanisms to
> +configure the PCI Endpoint Function refer [1]).
> +
> +*) Mounting configfs
> +
> +The PCI Endpoint Core layer creates pci_ep directory in the mounted configfs
> +directory. configfs can be mounted using the following command.
> +
> + mount -t configfs none /sys/kernel/config
> +
> +*) Directory Structure
> +
> +The pci_ep configfs directory structure has been created to reflect the
> +natural tree like structure of PCI devices. So every directory created
> +inside pci_ep represents a EPC device and every directory created inside
> +epf directory represents EPF device.
> +
> +/sys/kernel/config/pci_ep/
> +  | / --> [2]
> + | epc
> + | epf/
> +  | / --> [3]
> + | vendorid
> + | deviceid
> + | revid
> + | progif_code
> + | subclass_code
> + | baseclass_code
> + | cache_line_size
> + | subsys_vendor_id
> + | subsys_id
> + | interrupt_pin
> + | function
> +
> +*) Creating configfs entry for EPC
> +
> +Any directory created inside *pci_ep* represents an EPC device. In the above
> +directory structure [2] represents an EPC device. It consists of
> +
> + *) epc: Use it to associate the configfs entry to an actual EPC device.
> + The list of valid entries for this field can be obtained from
> + ls /sys/class/pci_epc/
> +
> + *) epf: Directory that contains all the endpoint functions. The name
> + of the created directory determines the driver this particular
> + epf device will be bound to. The name can be obtained either
> + from the function binding documentation [4] or
> + ls /sys/bus/pci-epf/drivers
> +
> + If more than one endpoint function device has to be bound to
> + the same driver, then the directory should be created using
> + the following notation
> + mkdir .
> +
> +*) Creating configfs entry for EPF
> +
> +Any directory created inside *epf* directory represents an EPF device. In the
> +above directory structure, [3] represents an EPF device. It consists of the
> +following entries that can be used to configure the standard configuration
> +header of the endpoint function. (These entries are created by the
> +framework when any new directory is created inside epf directory.)
> +
> +| vendorid
> +| deviceid
> +| revid
> +| progif_code
> +| subclass_code
> +| baseclass_code
> +| cache_line_size
> +| subsys_vendor_id
> +| subsys_id
> +| interrupt_pin
> +
> +The following entry identifies the function driver that is bound to the
> +function device
> + | function
> +
> +[1] -> Documentation/PCI/endpoint/pci-endpoint.txt
> +[4] -> Documentation/PCI/endpoint/function/binding/
> 

Good content.

Acked-By: 

Re: [PATCH v2 03/22] PCI: endpoint: Introduce configfs entry for configuring EP functions

[Kishon Vijay Abraham I]

Hi,

On Friday 17 February 2017 03:20 PM, Kishon Vijay Abraham I wrote:
> Introduce a new configfs entry to configure the EP function (like
> configuring the standard configuration header entries) and to
> bind the EP function with EP controller.
> 
> Signed-off-by: Kishon Vijay Abraham I 
> ---
>  drivers/pci/endpoint/Kconfig  |   14 +-
>  drivers/pci/endpoint/Makefile |1 +
>  drivers/pci/endpoint/pci-ep-cfs.c |  427 
> +
>  3 files changed, 440 insertions(+), 2 deletions(-)
>  create mode 100644 drivers/pci/endpoint/pci-ep-cfs.c
> 
> diff --git a/drivers/pci/endpoint/Kconfig b/drivers/pci/endpoint/Kconfig
> index 7eb1c79..8470f0b 100644
> --- a/drivers/pci/endpoint/Kconfig
> +++ b/drivers/pci/endpoint/Kconfig
> @@ -6,7 +6,6 @@ menu "PCI Endpoint"
>  
>  config PCI_ENDPOINT
>   bool "PCI Endpoint Support"
> - select CONFIGFS_FS
>   help
>  Enable this configuration option to support configurable PCI
>  endpoint. This should be enabled if the platform has a PCI
> @@ -14,8 +13,19 @@ config PCI_ENDPOINT
>  
>  Enabling this option will build the endpoint library, which
>  includes endpoint controller library and endpoint function
> -library.
> +library. This will also enable the configfs entry required to
> +configure the endpoint function and used to bind the
> +function with a endpoint controller.

This chunk shouldn't be added. I've missed removing this (it's added below).
I'll wait to get other review comments before sending a new revision.

Thanks
Kishon
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Re: [RFC PATCH v4 05/28] x86: Add Secure Memory Encryption (SME) support

[Borislav Petkov]

On Thu, Feb 16, 2017 at 09:43:07AM -0600, Tom Lendacky wrote:
> Add support for Secure Memory Encryption (SME). This initial support
> provides a Kconfig entry to build the SME support into the kernel and
> defines the memory encryption mask that will be used in subsequent
> patches to mark pages as encrypted.
> 
> Signed-off-by: Tom Lendacky 
> ---
>  arch/x86/Kconfig   |   22 +++
>  arch/x86/include/asm/mem_encrypt.h |   42 
> 
>  arch/x86/mm/Makefile   |1 +
>  arch/x86/mm/mem_encrypt.c  |   21 ++
>  include/linux/mem_encrypt.h|   37 
>  5 files changed, 123 insertions(+)
>  create mode 100644 arch/x86/include/asm/mem_encrypt.h
>  create mode 100644 arch/x86/mm/mem_encrypt.c
>  create mode 100644 include/linux/mem_encrypt.h
> 
> diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
> index f8fbfc5..a3b8c71 100644
> --- a/arch/x86/Kconfig
> +++ b/arch/x86/Kconfig
> @@ -1395,6 +1395,28 @@ config X86_DIRECT_GBPAGES
> supports them), so don't confuse the user by printing
> that we have them enabled.
>  
> +config AMD_MEM_ENCRYPT
> + bool "AMD Secure Memory Encryption (SME) support"
> + depends on X86_64 && CPU_SUP_AMD
> + ---help---
> +   Say yes to enable support for the encryption of system memory.
> +   This requires an AMD processor that supports Secure Memory
> +   Encryption (SME).
> +
> +config AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT
> + bool "Activate AMD Secure Memory Encryption (SME) by default"
> + default y
> + depends on AMD_MEM_ENCRYPT
> + ---help---
> +   Say yes to have system memory encrypted by default if running on
> +   an AMD processor that supports Secure Memory Encryption (SME).
> +
> +   If set to Y, then the encryption of system memory can be
> +   deactivated with the mem_encrypt=off command line option.
> +
> +   If set to N, then the encryption of system memory can be
> +   activated with the mem_encrypt=on command line option.

Good.

-- 
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Boris.

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Re: [PATCH v2 01/22] PCI: endpoint: Add EP core layer to enable EP controller and EP functions

[Joao Pinto]

Às 11:37 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
> Hi Joao,
> 
> On Friday 17 February 2017 04:56 PM, Joao Pinto wrote:
>>
>> Hi Kishon,
>>
>> Às 9:50 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
>>> Introduce a new EP core layer in order to support endpoint functions
>>> in linux kernel. This comprises of EPC library
>>> (Endpoint Controller Library) and EPF library (Endpoint
>>> Function Library). EPC library implements functions that is specific
>>> to an endpoint controller and EPF library implements functions
>>> that is specific to an endpoint function.
>>>
>>> Signed-off-by: Kishon Vijay Abraham I 
>>> ---
>>>  drivers/Makefile|2 +
>>>  drivers/pci/Kconfig |1 +
>>>  drivers/pci/endpoint/Kconfig|   21 ++
>>>  drivers/pci/endpoint/Makefile   |6 +
>>>  drivers/pci/endpoint/pci-epc-core.c |  548 
>>> +++
>>>  drivers/pci/endpoint/pci-epc-mem.c  |  143 +
>>>  drivers/pci/endpoint/pci-epf-core.c |  347 ++
>>>  include/linux/mod_devicetable.h |   10 +
>>>  include/linux/pci-epc.h |  141 +
>>>  include/linux/pci-epf.h |  160 ++
>>>  10 files changed, 1379 insertions(+)
>>>  create mode 100644 drivers/pci/endpoint/Kconfig
>>>  create mode 100644 drivers/pci/endpoint/Makefile
>>>  create mode 100644 drivers/pci/endpoint/pci-epc-core.c
>>>  create mode 100644 drivers/pci/endpoint/pci-epc-mem.c
>>>  create mode 100644 drivers/pci/endpoint/pci-epf-core.c
>>>  create mode 100644 include/linux/pci-epc.h
>>>  create mode 100644 include/linux/pci-epf.h
>>>
>>> diff --git a/drivers/Makefile b/drivers/Makefile
>>> index f521cb0..a300bb1 100644
>>> --- a/drivers/Makefile
>>> +++ b/drivers/Makefile
>>> @@ -14,7 +14,9 @@ obj-$(CONFIG_GENERIC_PHY) += phy/
>>>  obj-$(CONFIG_PINCTRL)  += pinctrl/
>>>  obj-$(CONFIG_GPIOLIB)  += gpio/
>>>  obj-y  += pwm/
>>> +
>>>  obj-$(CONFIG_PCI)  += pci/
>>> +obj-$(CONFIG_PCI_ENDPOINT) += pci/endpoint/
>>>  # PCI dwc controller drivers
>>>  obj-y  += pci/dwc/
>>
>> Any special reason to include pci/endpoint and pci/dwc in drivers/Makefile
>> instead of being inside pci/Makefile? pci/host is still inside pci/Makefile.
> 
> CONFIG_PCI enables all the pcie host support. Endpoint support should be
> enabled independent of the host support. Moving pci/endpoint inside
> pci/Makefile will build endpoint support only if CONFIG_PCI is enabled. For 
> the
> same reason kept pci/dwc in drivers/Makefile since dwc drivers can be used
> either in host mode or device mode (or both).

Good point! Very well.

Acked-By: Joao Pinto 

> 
> Thanks
> Kishon
> 

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Re: [PATCH v2 02/22] Documentation: PCI: Guide to use PCI Endpoint Core Layer

[Joao Pinto]

Às 9:50 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
> Add Documentation to help users use endpoint library to enable endpoint
> mode in the PCI controller and add new PCI endpoint functions.
> 
> Signed-off-by: Kishon Vijay Abraham I 
> ---
>  Documentation/PCI/00-INDEX  |2 +
>  Documentation/PCI/endpoint/pci-endpoint.txt |  190 
> +++
>  2 files changed, 192 insertions(+)
>  create mode 100644 Documentation/PCI/endpoint/pci-endpoint.txt
> 
> diff --git a/Documentation/PCI/00-INDEX b/Documentation/PCI/00-INDEX
> index 147231f..ba950b2 100644
> --- a/Documentation/PCI/00-INDEX
> +++ b/Documentation/PCI/00-INDEX
> @@ -12,3 +12,5 @@ pci.txt
>   - info on the PCI subsystem for device driver authors
>  pcieaer-howto.txt
>   - the PCI Express Advanced Error Reporting Driver Guide HOWTO
> +endpoint/pci-endpoint.txt
> + - guide to add endpoint controller driver and endpoint function driver.
> diff --git a/Documentation/PCI/endpoint/pci-endpoint.txt 
> b/Documentation/PCI/endpoint/pci-endpoint.txt
> new file mode 100644
> index 000..68a7839
> --- /dev/null
> +++ b/Documentation/PCI/endpoint/pci-endpoint.txt
> @@ -0,0 +1,190 @@
> + PCI ENDPOINT FRAMEWORK
> + Kishon Vijay Abraham I 
> +
> +This document is a guide to use the PCI Endpoint Framework in order to create
> +endpoint controller driver, endpoint function driver and using configfs
> +interface to bind the function driver to the controller driver.
> +
> +1. Introduction
> +
> +*Linux* has a comprehensive PCI subsystem to support PCI controllers that
> +operates in Root Complex mode. The subsystem has capability to scan PCI bus,
> +assign memory resources and irq resources, load PCI driver (based on
> +vendorid, deviceid), support other services like hot-plug, power management,
> +advanced error reporting and virtual channels.
> +
> +However PCI controller IPs integrated in certain SoC is capable of operating
> +either in Root Complex mode or Endpoint mode. PCI Endpoint Framework will
> +add endpoint mode support in *Linux*. This will help to run Linux in an
> +EP system which can have a wide variety of use cases from testing or
> +validation, co-processor accelerator etc..
> +
> +2. PCI Endpoint Core
> +
> +The PCI Endpoint Core layer comprises of 3 components: the Endpoint 
> Controller
> +library, the Endpoint Function library and the configfs layer to bind the
> +endpoint function with the endpoint controller.
> +
> +2.1 PCI Endpoint Controller(EPC) Library
> +
> +The EPC library provides APIs to be used by the controller that can operate
> +in endpoint mode. It also provides APIs to be used by function driver/library
> +in order to implement a particular endpoint function.
> +
> +2.1.1 APIs for the PCI controller Driver
> +
> +This section lists the APIs that the PCI Endpoint core provides to be used
> +by the PCI controller driver.
> +
> +*) devm_pci_epc_create()/pci_epc_create()
> +
> +   The PCI controller driver should implement the following ops:
> +  * write_header: ops to populate configuration space header
> +  * set_bar: ops to configure the BAR
> +  * clear_bar: ops to reset the BAR
> +  * alloc_addr_space: ops to allocate *in* PCI controller address space
> +  * free_addr_space: ops to free the allocated address space
> +  * raise_irq: ops to raise a legacy or MSI interrupt
> +  * start: ops to start the PCI link
> +  * stop: ops to stop the PCI link
> +
> +   The PCI controller driver can then create a new EPC device by invoking
> +   devm_pci_epc_create/pci_epc_create.
> +
> +*) devm_pci_epc_destroy()/pci_epc_destroy()
> +
> +   The PCI controller driver can destroy the EPC device created by either
> +   devm_pci_epc_create or pci_epc_create using devm_pci_epc_destroy() or
> +   /pci_epc_destroy()
> +
> +2.1.2 APIs for the PCI Endpoint Function Driver
> +
> +This section lists the APIs that the PCI Endpoint core provides to be used
> +by the PCI endpoint function driver.
> +
> +*) pci_epc_write_header()
> +
> +   The PCI endpoint function driver should use pci_epc_write_header() to
> +   write the standard configuration header to the endpoint controller.
> +
> +*) pci_epc_set_bar()
> +
> +   The PCI endpoint function driver should use pci_epc_set_bar() to configure
> +   the Base Address Register in order for the host to assign PCI addr space.
> +   Register space of the function driver is usually configured
> +   using this API.
> +
> +*) pci_epc_clear_bar()
> +
> +   The PCI endpoint function driver should use pci_epc_clear_bar() to reset
> +   the BAR.
> +
> +*) pci_epc_raise_irq()
> +
> +   The PCI endpoint function driver should use pci_epc_raise_irq() to raise
> +   Legacy Interrupt or MSI Interrupt.
> +
> +*) pci_epc_start()
> +
> +   The PCI endpoint function driver should invoke pci_epc_start() once it
> +   has configured the endpoint function and wants to start the PCI link.
> +
> +*) pci_epc_sto

Re: [PATCH v2 01/22] PCI: endpoint: Add EP core layer to enable EP controller and EP functions

[Kishon Vijay Abraham I]

Hi Joao,

On Friday 17 February 2017 04:56 PM, Joao Pinto wrote:
> 
> Hi Kishon,
> 
> Às 9:50 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
>> Introduce a new EP core layer in order to support endpoint functions
>> in linux kernel. This comprises of EPC library
>> (Endpoint Controller Library) and EPF library (Endpoint
>> Function Library). EPC library implements functions that is specific
>> to an endpoint controller and EPF library implements functions
>> that is specific to an endpoint function.
>>
>> Signed-off-by: Kishon Vijay Abraham I 
>> ---
>>  drivers/Makefile|2 +
>>  drivers/pci/Kconfig |1 +
>>  drivers/pci/endpoint/Kconfig|   21 ++
>>  drivers/pci/endpoint/Makefile   |6 +
>>  drivers/pci/endpoint/pci-epc-core.c |  548 
>> +++
>>  drivers/pci/endpoint/pci-epc-mem.c  |  143 +
>>  drivers/pci/endpoint/pci-epf-core.c |  347 ++
>>  include/linux/mod_devicetable.h |   10 +
>>  include/linux/pci-epc.h |  141 +
>>  include/linux/pci-epf.h |  160 ++
>>  10 files changed, 1379 insertions(+)
>>  create mode 100644 drivers/pci/endpoint/Kconfig
>>  create mode 100644 drivers/pci/endpoint/Makefile
>>  create mode 100644 drivers/pci/endpoint/pci-epc-core.c
>>  create mode 100644 drivers/pci/endpoint/pci-epc-mem.c
>>  create mode 100644 drivers/pci/endpoint/pci-epf-core.c
>>  create mode 100644 include/linux/pci-epc.h
>>  create mode 100644 include/linux/pci-epf.h
>>
>> diff --git a/drivers/Makefile b/drivers/Makefile
>> index f521cb0..a300bb1 100644
>> --- a/drivers/Makefile
>> +++ b/drivers/Makefile
>> @@ -14,7 +14,9 @@ obj-$(CONFIG_GENERIC_PHY)  += phy/
>>  obj-$(CONFIG_PINCTRL)   += pinctrl/
>>  obj-$(CONFIG_GPIOLIB)   += gpio/
>>  obj-y   += pwm/
>> +
>>  obj-$(CONFIG_PCI)   += pci/
>> +obj-$(CONFIG_PCI_ENDPOINT)  += pci/endpoint/
>>  # PCI dwc controller drivers
>>  obj-y   += pci/dwc/
> 
> Any special reason to include pci/endpoint and pci/dwc in drivers/Makefile
> instead of being inside pci/Makefile? pci/host is still inside pci/Makefile.

CONFIG_PCI enables all the pcie host support. Endpoint support should be
enabled independent of the host support. Moving pci/endpoint inside
pci/Makefile will build endpoint support only if CONFIG_PCI is enabled. For the
same reason kept pci/dwc in drivers/Makefile since dwc drivers can be used
either in host mode or device mode (or both).

Thanks
Kishon
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Re: [PATCH v2 01/22] PCI: endpoint: Add EP core layer to enable EP controller and EP functions

[Joao Pinto]

Hi Kishon,

Às 9:50 AM de 2/17/2017, Kishon Vijay Abraham I escreveu:
> Introduce a new EP core layer in order to support endpoint functions
> in linux kernel. This comprises of EPC library
> (Endpoint Controller Library) and EPF library (Endpoint
> Function Library). EPC library implements functions that is specific
> to an endpoint controller and EPF library implements functions
> that is specific to an endpoint function.
> 
> Signed-off-by: Kishon Vijay Abraham I 
> ---
>  drivers/Makefile|2 +
>  drivers/pci/Kconfig |1 +
>  drivers/pci/endpoint/Kconfig|   21 ++
>  drivers/pci/endpoint/Makefile   |6 +
>  drivers/pci/endpoint/pci-epc-core.c |  548 
> +++
>  drivers/pci/endpoint/pci-epc-mem.c  |  143 +
>  drivers/pci/endpoint/pci-epf-core.c |  347 ++
>  include/linux/mod_devicetable.h |   10 +
>  include/linux/pci-epc.h |  141 +
>  include/linux/pci-epf.h |  160 ++
>  10 files changed, 1379 insertions(+)
>  create mode 100644 drivers/pci/endpoint/Kconfig
>  create mode 100644 drivers/pci/endpoint/Makefile
>  create mode 100644 drivers/pci/endpoint/pci-epc-core.c
>  create mode 100644 drivers/pci/endpoint/pci-epc-mem.c
>  create mode 100644 drivers/pci/endpoint/pci-epf-core.c
>  create mode 100644 include/linux/pci-epc.h
>  create mode 100644 include/linux/pci-epf.h
> 
> diff --git a/drivers/Makefile b/drivers/Makefile
> index f521cb0..a300bb1 100644
> --- a/drivers/Makefile
> +++ b/drivers/Makefile
> @@ -14,7 +14,9 @@ obj-$(CONFIG_GENERIC_PHY)   += phy/
>  obj-$(CONFIG_PINCTRL)+= pinctrl/
>  obj-$(CONFIG_GPIOLIB)+= gpio/
>  obj-y+= pwm/
> +
>  obj-$(CONFIG_PCI)+= pci/
> +obj-$(CONFIG_PCI_ENDPOINT)   += pci/endpoint/
>  # PCI dwc controller drivers
>  obj-y+= pci/dwc/

Any special reason to include pci/endpoint and pci/dwc in drivers/Makefile
instead of being inside pci/Makefile? pci/host is still inside pci/Makefile.

>  
> diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
> index df14142..9747c1e 100644
> --- a/drivers/pci/Kconfig
> +++ b/drivers/pci/Kconfig
> @@ -134,3 +134,4 @@ config PCI_HYPERV
>  source "drivers/pci/hotplug/Kconfig"
>  source "drivers/pci/dwc/Kconfig"
>  source "drivers/pci/host/Kconfig"
> +source "drivers/pci/endpoint/Kconfig"
> diff --git a/drivers/pci/endpoint/Kconfig b/drivers/pci/endpoint/Kconfig
> new file mode 100644
> index 000..7eb1c79
> --- /dev/null
> +++ b/drivers/pci/endpoint/Kconfig
> @@ -0,0 +1,21 @@
> +#
> +# PCI Endpoint Support
> +#
> +
> +menu "PCI Endpoint"
> +
> +config PCI_ENDPOINT
> + bool "PCI Endpoint Support"
> + select CONFIGFS_FS
> + help
> +Enable this configuration option to support configurable PCI
> +endpoint. This should be enabled if the platform has a PCI
> +controller that can operate in endpoint mode.
> +
> +Enabling this option will build the endpoint library, which
> +includes endpoint controller library and endpoint function
> +library.
> +
> +If in doubt, say "N" to disable Endpoint support.
> +
> +endmenu
> diff --git a/drivers/pci/endpoint/Makefile b/drivers/pci/endpoint/Makefile
> new file mode 100644
> index 000..dc1bc16
> --- /dev/null
> +++ b/drivers/pci/endpoint/Makefile
> @@ -0,0 +1,6 @@
> +#
> +# Makefile for PCI Endpoint Support
> +#
> +
> +obj-$(CONFIG_PCI_ENDPOINT)   += pci-epc-core.o pci-epf-core.o\
> +pci-epc-mem.o
> diff --git a/drivers/pci/endpoint/pci-epc-core.c 
> b/drivers/pci/endpoint/pci-epc-core.c
> new file mode 100644
> index 000..2c33e8a
> --- /dev/null
> +++ b/drivers/pci/endpoint/pci-epc-core.c
> @@ -0,0 +1,548 @@
> +/**
> + * PCI Endpoint *Controller* (EPC) library
> + *
> + * Copyright (C) 2017 Texas Instruments
> + * Author: Kishon Vijay Abraham I 
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 of
> + * the License as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program.  If not, see 
>   >.
> + */
> +
> +#include 
> +#include 
> +#include 
> +#include 
> +
> +#include 
> +#include 
> +
> +static struct class *pci_

Re: [RFC PATCH v4 02/28] x86: Set the write-protect cache mode for full PAT support

[Borislav Petkov]

On Thu, Feb 16, 2017 at 09:42:25AM -0600, Tom Lendacky wrote:
> For processors that support PAT, set the write-protect cache mode
> (_PAGE_CACHE_MODE_WP) entry to the actual write-protect value (x05).
> 
> Acked-by: Borislav Petkov 
> Signed-off-by: Tom Lendacky 

Just a nit:

Subject should have "x86/mm/pat: " prefix but that can be fixed when
applying.

-- 
Regards/Gruss,
Boris.

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Re: [RFC PATCH v4 04/28] x86: Handle reduction in physical address size with SME

[Borislav Petkov]

On Thu, Feb 16, 2017 at 09:42:54AM -0600, Tom Lendacky wrote:
> When System Memory Encryption (SME) is enabled, the physical address
> space is reduced. Adjust the x86_phys_bits value to reflect this
> reduction.
> 
> Signed-off-by: Tom Lendacky 
> ---
>  arch/x86/kernel/cpu/common.c |   10 +++---
>  1 file changed, 7 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
> index b33bc06..358208d7 100644
> --- a/arch/x86/kernel/cpu/common.c
> +++ b/arch/x86/kernel/cpu/common.c
> @@ -771,11 +771,15 @@ void get_cpu_cap(struct cpuinfo_x86 *c)
>   u64 msr;
>  
>   /*
> -  * For SME, BIOS support is required. If BIOS has not
> -  * enabled SME don't advertise the feature.
> +  * For SME, BIOS support is required. If BIOS has
> +  * enabled SME adjust x86_phys_bits by the SME
> +  * physical address space reduction value. If BIOS
> +  * has not enabled SME don't advertise the feature.
>*/
>   rdmsrl(MSR_K8_SYSCFG, msr);
> - if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
> + if (msr & MSR_K8_SYSCFG_MEM_ENCRYPT)
> + c->x86_phys_bits -= (ebx >> 6) & 0x3f;
> + else
>   eax &= ~0x01;

Right, as I mentioned yesterday, this should go to arch/x86/kernel/cpu/amd.c

-- 
Regards/Gruss,
Boris.

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[PATCH v2 00/22] PCI: Support for configurable PCI endpoint

[Kishon Vijay Abraham I]

This patch series
 *) add PCI endpoint core layer
 *) modify designware/dra7xx driver to be configured in EP mode
 *) add a PCI endpoint *test* function driver and corresponding host
driver

Changes from v1:
*) The preparation patches for adding EP support is removed and is sent
   separately
*) Added device ID for DRA74x/DRA72x and used it instead of
   using "PCI_ANY_ID"
*) Added userguide for PCI endpoint test function

Major Improvements from RFC:
 *) support multi-function devices (hw supported not virtual)
 *) Access host side buffers
 *) Raise MSI interrupts
 *) Add user space program to use the host side PCI driver
 *) Adapt all other users of designware to use the new design (only
compile tested. Since I have only dra7xx boards, the new design
has only been tested in dra7xx. I'd require the help of others
to test the platforms they have access to).

The patch series is created after applying
https://lkml.org/lkml/2017/2/16/270

I've also pushed the tree to
git://git.kernel.org/pub/scm/linux/kernel/git/kishon/pci-endpoint.git next

Kishon Vijay Abraham I (22):
  PCI: endpoint: Add EP core layer to enable EP controller and EP
functions
  Documentation: PCI: Guide to use PCI Endpoint Core Layer
  PCI: endpoint: Introduce configfs entry for configuring EP functions
  Documentation: PCI: Guide to use pci endpoint configfs
  Documentation: PCI: Add specification for the *pci test* function
device
  PCI: endpoint: functions: Add an EP function to test PCI
  Documentation: PCI: Add binding documentation for pci-test endpoint
function
  PCI: dwc: designware: Add EP mode support
  dt-bindings: PCI: Add dt bindings for pci designware EP mode
  PCI: dwc: dra7xx: Facilitate wrapper and msi interrupts to be enabled
independently
  PCI: dwc: dra7xx: Add EP mode support
  dt-bindings: PCI: dra7xx: Add dt bindings for pci dra7xx EP mode
  PCI: dwc: dra7xx: Workaround for errata id i870
  dt-bindings: PCI: dra7xx: Add dt bindings to enable legacy mode
  PCI: Add device IDs for DRA74x and DRA72x
  misc: Add host side pci driver for pci test function device
  Documentation: misc-devices: Add Documentation for pci-endpoint-test
driver
  tools: PCI: Add a userspace tool to test PCI endpoint
  tools: PCI: Add sample test script to invoke pcitest
  Documentation: PCI: Add userguide for PCI endpoint test function
  MAINTAINERS: add PCI EP maintainer
  ARM: DRA7: clockdomain: Change the CLKTRCTRL of CM_PCIE_CLKSTCTRL to
SW_WKUP

 Documentation/PCI/00-INDEX |8 +
 .../PCI/endpoint/function/binding/pci-test.txt |   17 +
 Documentation/PCI/endpoint/pci-endpoint-cfs.txt|   84 +++
 Documentation/PCI/endpoint/pci-endpoint.txt|  190 +++
 Documentation/PCI/endpoint/pci-test-function.txt   |   66 +++
 Documentation/PCI/endpoint/pci-test-howto.txt  |  167 ++
 .../devicetree/bindings/pci/designware-pcie.txt|   26 +-
 Documentation/devicetree/bindings/pci/ti-pci.txt   |   41 +-
 Documentation/misc-devices/pci-endpoint-test.txt   |   35 ++
 MAINTAINERS|9 +
 arch/arm/mach-omap2/clockdomains7xx_data.c |2 +-
 drivers/Makefile   |2 +
 drivers/misc/Kconfig   |7 +
 drivers/misc/Makefile  |1 +
 drivers/misc/pci_endpoint_test.c   |  534 +++
 drivers/pci/Kconfig|1 +
 drivers/pci/dwc/Kconfig|   36 +-
 drivers/pci/dwc/Makefile   |5 +-
 drivers/pci/dwc/pci-dra7xx.c   |  271 +-
 drivers/pci/dwc/pcie-designware-ep.c   |  342 
 drivers/pci/dwc/pcie-designware.c  |   51 ++
 drivers/pci/dwc/pcie-designware.h  |   79 +++
 drivers/pci/endpoint/Kconfig   |   33 ++
 drivers/pci/endpoint/Makefile  |7 +
 drivers/pci/endpoint/functions/Kconfig |   12 +
 drivers/pci/endpoint/functions/Makefile|5 +
 drivers/pci/endpoint/functions/pci-epf-test.c  |  513 ++
 drivers/pci/endpoint/pci-ep-cfs.c  |  427 +++
 drivers/pci/endpoint/pci-epc-core.c|  548 
 drivers/pci/endpoint/pci-epc-mem.c |  143 +
 drivers/pci/endpoint/pci-epf-core.c|  347 +
 include/linux/mod_devicetable.h|   10 +
 include/linux/pci-epc.h|  141 +
 include/linux/pci-epf.h|  160 ++
 include/linux/pci_ids.h|2 +
 include/uapi/linux/Kbuild  |1 +
 include/uapi/linux/pcitest.h   |   19 +
 tools/pci/pcitest.c|  186 +++
 tools/pci/pcitest.sh

[PATCH v2 02/22] Documentation: PCI: Guide to use PCI Endpoint Core Layer

[Kishon Vijay Abraham I]

Add Documentation to help users use endpoint library to enable endpoint
mode in the PCI controller and add new PCI endpoint functions.

Signed-off-by: Kishon Vijay Abraham I 
---
 Documentation/PCI/00-INDEX  |2 +
 Documentation/PCI/endpoint/pci-endpoint.txt |  190 +++
 2 files changed, 192 insertions(+)
 create mode 100644 Documentation/PCI/endpoint/pci-endpoint.txt

diff --git a/Documentation/PCI/00-INDEX b/Documentation/PCI/00-INDEX
index 147231f..ba950b2 100644
--- a/Documentation/PCI/00-INDEX
+++ b/Documentation/PCI/00-INDEX
@@ -12,3 +12,5 @@ pci.txt
- info on the PCI subsystem for device driver authors
 pcieaer-howto.txt
- the PCI Express Advanced Error Reporting Driver Guide HOWTO
+endpoint/pci-endpoint.txt
+   - guide to add endpoint controller driver and endpoint function driver.
diff --git a/Documentation/PCI/endpoint/pci-endpoint.txt 
b/Documentation/PCI/endpoint/pci-endpoint.txt
new file mode 100644
index 000..68a7839
--- /dev/null
+++ b/Documentation/PCI/endpoint/pci-endpoint.txt
@@ -0,0 +1,190 @@
+   PCI ENDPOINT FRAMEWORK
+   Kishon Vijay Abraham I 
+
+This document is a guide to use the PCI Endpoint Framework in order to create
+endpoint controller driver, endpoint function driver and using configfs
+interface to bind the function driver to the controller driver.
+
+1. Introduction
+
+*Linux* has a comprehensive PCI subsystem to support PCI controllers that
+operates in Root Complex mode. The subsystem has capability to scan PCI bus,
+assign memory resources and irq resources, load PCI driver (based on
+vendorid, deviceid), support other services like hot-plug, power management,
+advanced error reporting and virtual channels.
+
+However PCI controller IPs integrated in certain SoC is capable of operating
+either in Root Complex mode or Endpoint mode. PCI Endpoint Framework will
+add endpoint mode support in *Linux*. This will help to run Linux in an
+EP system which can have a wide variety of use cases from testing or
+validation, co-processor accelerator etc..
+
+2. PCI Endpoint Core
+
+The PCI Endpoint Core layer comprises of 3 components: the Endpoint Controller
+library, the Endpoint Function library and the configfs layer to bind the
+endpoint function with the endpoint controller.
+
+2.1 PCI Endpoint Controller(EPC) Library
+
+The EPC library provides APIs to be used by the controller that can operate
+in endpoint mode. It also provides APIs to be used by function driver/library
+in order to implement a particular endpoint function.
+
+2.1.1 APIs for the PCI controller Driver
+
+This section lists the APIs that the PCI Endpoint core provides to be used
+by the PCI controller driver.
+
+*) devm_pci_epc_create()/pci_epc_create()
+
+   The PCI controller driver should implement the following ops:
+* write_header: ops to populate configuration space header
+* set_bar: ops to configure the BAR
+* clear_bar: ops to reset the BAR
+* alloc_addr_space: ops to allocate *in* PCI controller address space
+* free_addr_space: ops to free the allocated address space
+* raise_irq: ops to raise a legacy or MSI interrupt
+* start: ops to start the PCI link
+* stop: ops to stop the PCI link
+
+   The PCI controller driver can then create a new EPC device by invoking
+   devm_pci_epc_create/pci_epc_create.
+
+*) devm_pci_epc_destroy()/pci_epc_destroy()
+
+   The PCI controller driver can destroy the EPC device created by either
+   devm_pci_epc_create or pci_epc_create using devm_pci_epc_destroy() or
+   /pci_epc_destroy()
+
+2.1.2 APIs for the PCI Endpoint Function Driver
+
+This section lists the APIs that the PCI Endpoint core provides to be used
+by the PCI endpoint function driver.
+
+*) pci_epc_write_header()
+
+   The PCI endpoint function driver should use pci_epc_write_header() to
+   write the standard configuration header to the endpoint controller.
+
+*) pci_epc_set_bar()
+
+   The PCI endpoint function driver should use pci_epc_set_bar() to configure
+   the Base Address Register in order for the host to assign PCI addr space.
+   Register space of the function driver is usually configured
+   using this API.
+
+*) pci_epc_clear_bar()
+
+   The PCI endpoint function driver should use pci_epc_clear_bar() to reset
+   the BAR.
+
+*) pci_epc_raise_irq()
+
+   The PCI endpoint function driver should use pci_epc_raise_irq() to raise
+   Legacy Interrupt or MSI Interrupt.
+
+*) pci_epc_start()
+
+   The PCI endpoint function driver should invoke pci_epc_start() once it
+   has configured the endpoint function and wants to start the PCI link.
+
+*) pci_epc_stop()
+
+   The PCI endpoint function driver should invoke pci_epc_stop() to stop
+   the PCI LINK.
+
+2.1.3 Other APIs
+
+There are other APIs provided by the EPC library. These are used for binding
+the epf device with epc device. pci-ep-cfs.c can be used as reference for
+us

[PATCH v2 07/22] Documentation: PCI: Add binding documentation for pci-test endpoint function

[Kishon Vijay Abraham I]

Add binding documentation for pci-test endpoint function that helps in
adding and configuring pci-test endpoint function.

Signed-off-by: Kishon Vijay Abraham I 
---
 Documentation/PCI/00-INDEX |2 ++
 .../PCI/endpoint/function/binding/pci-test.txt |   17 +
 2 files changed, 19 insertions(+)
 create mode 100644 Documentation/PCI/endpoint/function/binding/pci-test.txt

diff --git a/Documentation/PCI/00-INDEX b/Documentation/PCI/00-INDEX
index 4e5a283..53717b7 100644
--- a/Documentation/PCI/00-INDEX
+++ b/Documentation/PCI/00-INDEX
@@ -18,3 +18,5 @@ endpoint/pci-endpoint-cfs.txt
- guide to use configfs to configure the pci endpoint function.
 endpoint/pci-test-function.txt
- specification of *pci test* function device.
+endpoint/function/binding/
+   - binding documentation for pci endpoint function
diff --git a/Documentation/PCI/endpoint/function/binding/pci-test.txt 
b/Documentation/PCI/endpoint/function/binding/pci-test.txt
new file mode 100644
index 000..7358240
--- /dev/null
+++ b/Documentation/PCI/endpoint/function/binding/pci-test.txt
@@ -0,0 +1,17 @@
+PCI TEST ENDPOINT FUNCTION
+
+name: Should be "pci_epf_test" to bind to the pci_epf_test driver.
+
+Configurable Fields:
+vendorid: should be 0x104c
+deviceid: should be 0x
+revid   : dont't care
+progif_code : don't care
+subclass_code   : don't care
+baseclass_code  : should be 0xff
+cache_line_size : don't care
+subsys_vendor_id : don't care
+subsys_id   : don't care
+interrupt_pin   : Should be 1 - INTA, 2 - INTB, 3 - INTC, 4 -INTD
+msi_interrupts  : Should be 1 to 32 depending on the number of msi interrupts
+  to test
-- 
1.7.9.5

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[PATCH v2 05/22] Documentation: PCI: Add specification for the *pci test* function device

[Kishon Vijay Abraham I]

Add specification for the *pci test* virtual function device. The endpoint
function driver and the host pci driver should be created based on this
specification.

Signed-off-by: Kishon Vijay Abraham I 
---
 Documentation/PCI/00-INDEX   |2 +
 Documentation/PCI/endpoint/pci-test-function.txt |   66 ++
 2 files changed, 68 insertions(+)
 create mode 100644 Documentation/PCI/endpoint/pci-test-function.txt

diff --git a/Documentation/PCI/00-INDEX b/Documentation/PCI/00-INDEX
index f84a23c..4e5a283 100644
--- a/Documentation/PCI/00-INDEX
+++ b/Documentation/PCI/00-INDEX
@@ -16,3 +16,5 @@ endpoint/pci-endpoint.txt
- guide to add endpoint controller driver and endpoint function driver.
 endpoint/pci-endpoint-cfs.txt
- guide to use configfs to configure the pci endpoint function.
+endpoint/pci-test-function.txt
+   - specification of *pci test* function device.
diff --git a/Documentation/PCI/endpoint/pci-test-function.txt 
b/Documentation/PCI/endpoint/pci-test-function.txt
new file mode 100644
index 000..1324376
--- /dev/null
+++ b/Documentation/PCI/endpoint/pci-test-function.txt
@@ -0,0 +1,66 @@
+   PCI TEST
+   Kishon Vijay Abraham I 
+
+Traditionally PCI RC has always been validated by using standard
+PCI cards like ethernet PCI cards or USB PCI cards or SATA PCI cards.
+However with the addition of EP-core in linux kernel, it is possible
+to configure a PCI controller that can operate in EP mode to work as
+a test device.
+
+The PCI endpoint test device is a virtual device (defined in software)
+used to test the endpoint functionality and serve as a sample driver
+for other PCI endpoint devices (to use the EP framework).
+
+The PCI endpoint test device has the following registers:
+
+   1) PCI_ENDPOINT_TEST_MAGIC
+   2) PCI_ENDPOINT_TEST_COMMAND
+   3) PCI_ENDPOINT_TEST_STATUS
+   4) PCI_ENDPOINT_TEST_SRC_ADDR
+   5) PCI_ENDPOINT_TEST_DST_ADDR
+   6) PCI_ENDPOINT_TEST_SIZE
+   7) PCI_ENDPOINT_TEST_CHECKSUM
+
+*) PCI_ENDPOINT_TEST_MAGIC
+
+This register will be used to test BAR0. A known pattern will be written
+and read back from MAGIC register to verify BAR0.
+
+*) PCI_ENDPOINT_TEST_COMMAND:
+
+This register will be used by the host driver to indicate the function
+that the endpoint device must perform.
+
+Bitfield Description:
+  Bit 0: raise legacy irq
+  Bit 1: raise MSI irq
+  Bit 2 - 7: MSI interrupt number
+  Bit 8: read command (read data from RC buffer)
+  Bit 9: write command (write data to RC buffer)
+  Bit 10   : copy command (copy data from one RC buffer to another
+ RC buffer)
+
+*) PCI_ENDPOINT_TEST_STATUS
+
+This register reflects the status of the PCI endpoint device.
+
+Bitfield Description:
+  Bit 0: read success
+  Bit 1: read fail
+  Bit 2: write success
+  Bit 3: write fail
+  Bit 4: copy success
+  Bit 5: copy fail
+  Bit 6: irq raised
+  Bit 7: source address is invalid
+  Bit 8: destination address is invalid
+
+*) PCI_ENDPOINT_TEST_SRC_ADDR
+
+This register contains the source address (RC buffer address) for the
+COPY/READ command.
+
+*) PCI_ENDPOINT_TEST_DST_ADDR
+
+This register contains the destination address (RC buffer address) for
+the COPY/WRITE command.
-- 
1.7.9.5

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[PATCH v2 03/22] PCI: endpoint: Introduce configfs entry for configuring EP functions

[Kishon Vijay Abraham I]

Introduce a new configfs entry to configure the EP function (like
configuring the standard configuration header entries) and to
bind the EP function with EP controller.

Signed-off-by: Kishon Vijay Abraham I 
---
 drivers/pci/endpoint/Kconfig  |   14 +-
 drivers/pci/endpoint/Makefile |1 +
 drivers/pci/endpoint/pci-ep-cfs.c |  427 +
 3 files changed, 440 insertions(+), 2 deletions(-)
 create mode 100644 drivers/pci/endpoint/pci-ep-cfs.c

diff --git a/drivers/pci/endpoint/Kconfig b/drivers/pci/endpoint/Kconfig
index 7eb1c79..8470f0b 100644
--- a/drivers/pci/endpoint/Kconfig
+++ b/drivers/pci/endpoint/Kconfig
@@ -6,7 +6,6 @@ menu "PCI Endpoint"
 
 config PCI_ENDPOINT
bool "PCI Endpoint Support"
-   select CONFIGFS_FS
help
   Enable this configuration option to support configurable PCI
   endpoint. This should be enabled if the platform has a PCI
@@ -14,8 +13,19 @@ config PCI_ENDPOINT
 
   Enabling this option will build the endpoint library, which
   includes endpoint controller library and endpoint function
-  library.
+  library. This will also enable the configfs entry required to
+  configure the endpoint function and used to bind the
+  function with a endpoint controller.
 
   If in doubt, say "N" to disable Endpoint support.
 
+config PCI_ENDPOINT_CONFIGFS
+   bool "PCI Endpoint Configfs Support"
+   depends on PCI_ENDPOINT
+   select CONFIGFS_FS
+   help
+  This will enable the configfs entry that can be used to
+  configure the endpoint function and used to bind the
+  function with a endpoint controller.
+
 endmenu
diff --git a/drivers/pci/endpoint/Makefile b/drivers/pci/endpoint/Makefile
index dc1bc16..dd9163c 100644
--- a/drivers/pci/endpoint/Makefile
+++ b/drivers/pci/endpoint/Makefile
@@ -4,3 +4,4 @@
 
 obj-$(CONFIG_PCI_ENDPOINT) += pci-epc-core.o pci-epf-core.o\
   pci-epc-mem.o
+obj-$(CONFIG_PCI_ENDPOINT_CONFIGFS)+= pci-ep-cfs.o
diff --git a/drivers/pci/endpoint/pci-ep-cfs.c 
b/drivers/pci/endpoint/pci-ep-cfs.c
new file mode 100644
index 000..ed0f8c2
--- /dev/null
+++ b/drivers/pci/endpoint/pci-ep-cfs.c
@@ -0,0 +1,427 @@
+/**
+ * configfs to configure the PCI endpoint
+ *
+ * Copyright (C) 2017 Texas Instruments
+ * Author: Kishon Vijay Abraham I 
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+struct pci_epf_info {
+   struct config_group group;
+   struct list_head list;
+   struct pci_epf *epf;
+};
+
+struct pci_ep_info {
+   struct config_group group;
+   struct config_group pci_epf_group;
+   /* mutex to protect pci_epf list */
+   struct mutex lock;
+   struct list_head pci_epf;
+   const char *epc_name;
+   struct pci_epc *epc;
+};
+
+static inline struct pci_epf_info *to_pci_epf_info(struct config_item *item)
+{
+   return container_of(to_config_group(item), struct pci_epf_info, group);
+}
+
+static inline struct pci_ep_info *to_pci_ep_info(struct config_item *item)
+{
+   return container_of(to_config_group(item), struct pci_ep_info, group);
+}
+
+#define PCI_EPF_HEADER_R(_name)
   \
+static ssize_t pci_epf_##_name##_show(struct config_item *item,char 
*page)\
+{ \
+   struct pci_epf *epf = to_pci_epf_info(item)->epf;  \
+   if (!epf->header) {\
+   WARN_ON_ONCE("epf device not bound to function driver\n"); \
+   return 0;  \
+   }  \
+   return sprintf(page, "0x%04x\n", epf->header->_name);  \
+}
+
+#define PCI_EPF_HEADER_W_u32(_name)   \
+static ssize_t pci_epf_##_name##_store(struct config_item *item,  \
+  const char *page, size_t len)   \
+{ \
+   u32 val;   \
+  

[PATCH v2 09/22] dt-bindings: PCI: Add dt bindings for pci designware EP mode

[Kishon Vijay Abraham I]

Add device tree binding documentation for pci designware EP mode.

Acked-by: Rob Herring 
Signed-off-by: Kishon Vijay Abraham I 
---
 .../devicetree/bindings/pci/designware-pcie.txt|   26 ++--
 1 file changed, 18 insertions(+), 8 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt 
b/Documentation/devicetree/bindings/pci/designware-pcie.txt
index 1392c70..b2480dd 100644
--- a/Documentation/devicetree/bindings/pci/designware-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt
@@ -6,30 +6,40 @@ Required properties:
 - reg-names: Must be "config" for the PCIe configuration space.
 (The old way of getting the configuration address space from "ranges"
 is deprecated and should be avoided.)
+- num-lanes: number of lanes to use
+RC mode:
 - #address-cells: set to <3>
 - #size-cells: set to <2>
 - device_type: set to "pci"
 - ranges: ranges for the PCI memory and I/O regions
 - #interrupt-cells: set to <1>
-- interrupt-map-mask and interrupt-map: standard PCI properties
-   to define the mapping of the PCIe interface to interrupt
+- interrupt-map-mask and interrupt-map: standard PCI
+   properties to define the mapping of the PCIe interface to interrupt
numbers.
-- num-lanes: number of lanes to use
+EP mode:
+- num-ib-windows: number of inbound address translation
+windows
+- num-ob-windows: number of outbound address translation
+windows
 
 Optional properties:
-- num-viewport: number of view ports configured in hardware.  If a platform
-  does not specify it, the driver assumes 2.
 - num-lanes: number of lanes to use (this property should be specified unless
   the link is brought already up in BIOS)
 - reset-gpio: gpio pin number of power good signal
-- bus-range: PCI bus numbers covered (it is recommended for new devicetrees to
-  specify this property, to keep backwards compatibility a range of 0x00-0xff
-  is assumed if not present)
 - clocks: Must contain an entry for each entry in clock-names.
See ../clocks/clock-bindings.txt for details.
 - clock-names: Must include the following entries:
- "pcie"
- "pcie_bus"
+RC mode:
+- num-viewport: number of view ports configured in
+  hardware. If a platform does not specify it, the driver assumes 2.
+- bus-range: PCI bus numbers covered (it is recommended
+  for new devicetrees to specify this property, to keep backwards
+  compatibility a range of 0x00-0xff is assumed if not present)
+EP mode:
+- max-functions: maximum number of functions that can be
+  configured
 
 Example configuration:
 
-- 
1.7.9.5

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[PATCH v2 10/22] PCI: dwc: dra7xx: Facilitate wrapper and msi interrupts to be enabled independently

[Kishon Vijay Abraham I]

No functional change. Split dra7xx_pcie_enable_interrupts into
dra7xx_pcie_enable_wrapper_interrupts and dra7xx_pcie_enable_msi_interrupts
so that wrapper interrupts and msi interrupts can be enabled independently.
This is in preparation for adding EP mode support to dra7xx driver since
EP mode doesn't have to enable msi_interrupts.

Signed-off-by: Kishon Vijay Abraham I 
---
 drivers/pci/dwc/pci-dra7xx.c |   24 ++--
 1 file changed, 18 insertions(+), 6 deletions(-)

diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
index c6fef0a..8d2d02f 100644
--- a/drivers/pci/dwc/pci-dra7xx.c
+++ b/drivers/pci/dwc/pci-dra7xx.c
@@ -140,18 +140,30 @@ static int dra7xx_pcie_establish_link(struct dra7xx_pcie 
*dra7xx)
return dw_pcie_wait_for_link(pci);
 }
 
-static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
+static void dra7xx_pcie_enable_msi_interrupts(struct dra7xx_pcie *dra7xx)
 {
-   dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
-  ~INTERRUPTS);
-   dra7xx_pcie_writel(dra7xx,
-  PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN, INTERRUPTS);
dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MSI,
   ~LEG_EP_INTERRUPTS & ~MSI);
-   dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI,
+
+   dra7xx_pcie_writel(dra7xx,
+  PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MSI,
   MSI | LEG_EP_INTERRUPTS);
 }
 
+static void dra7xx_pcie_enable_wrapper_interrupts(struct dra7xx_pcie *dra7xx)
+{
+   dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQSTATUS_MAIN,
+  ~INTERRUPTS);
+   dra7xx_pcie_writel(dra7xx, PCIECTRL_DRA7XX_CONF_IRQENABLE_SET_MAIN,
+  INTERRUPTS);
+}
+
+static void dra7xx_pcie_enable_interrupts(struct dra7xx_pcie *dra7xx)
+{
+   dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
+   dra7xx_pcie_enable_msi_interrupts(dra7xx);
+}
+
 static void dra7xx_pcie_host_init(struct pcie_port *pp)
 {
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
-- 
1.7.9.5

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[PATCH v2 14/22] dt-bindings: PCI: dra7xx: Add dt bindings to enable legacy mode

[Kishon Vijay Abraham I]

Update device tree binding documentation of TI's dra7xx PCI
controller to include property for enabling legacy mode.

Signed-off-by: Kishon Vijay Abraham I 
---
 Documentation/devicetree/bindings/pci/ti-pci.txt |4 
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt 
b/Documentation/devicetree/bindings/pci/ti-pci.txt
index 190828a..72ebe2b 100644
--- a/Documentation/devicetree/bindings/pci/ti-pci.txt
+++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
@@ -39,6 +39,10 @@ DEVICE MODE
  - interrupts : one interrupt entries must be specified for main interrupt.
  - num-ib-windows : number of inbound address translation windows
  - num-ob-windows : number of outbound address translation windows
+ - syscon-legacy-mode: phandle to the syscon dt node. The 1st argument should
+  contain the register offset within syscon and the 2nd
+  argument should contain the bit field for setting the
+  legacy mode
 
 Optional Property:
  - gpios : Should be added if a gpio line is required to drive PERST# line
-- 
1.7.9.5

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[PATCH v2 11/22] PCI: dwc: dra7xx: Add EP mode support

[Kishon Vijay Abraham I]

The PCIe controller integrated in dra7xx SoCs is capable of operating
in endpoint mode. Add endpoint mode support to dra7xx driver.

Signed-off-by: Kishon Vijay Abraham I 
---
 drivers/pci/dwc/Kconfig   |   31 +-
 drivers/pci/dwc/Makefile  |4 +-
 drivers/pci/dwc/pci-dra7xx.c  |  197 ++---
 drivers/pci/dwc/pcie-designware.h |7 ++
 4 files changed, 221 insertions(+), 18 deletions(-)

diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig
index 00335c7..96e6d17 100644
--- a/drivers/pci/dwc/Kconfig
+++ b/drivers/pci/dwc/Kconfig
@@ -16,14 +16,37 @@ config PCIE_DW_EP
 
 config PCI_DRA7XX
bool "TI DRA7xx PCIe controller"
-   depends on PCI
+   depends on (PCI && PCI_MSI_IRQ_DOMAIN) || PCI_ENDPOINT
depends on OF && HAS_IOMEM && TI_PIPE3
+   help
+Enables support for the PCIe controller in the DRA7xx SoC. There
+are two instances of PCIe controller in DRA7xx. This controller can
+work either as EP or RC. In order to enable host specific features
+PCI_DRA7XX_HOST must be selected and in order to enable device
+specific features PCI_DRA7XX_EP must be selected. This uses
+the Designware core.
+
+if PCI_DRA7XX
+
+config PCI_DRA7XX_HOST
+   bool "PCI DRA7xx Host Mode"
+   depends on PCI
depends on PCI_MSI_IRQ_DOMAIN
select PCIE_DW_HOST
+   default y
help
-Enables support for the PCIe controller in the DRA7xx SoC.  There
-are two instances of PCIe controller in DRA7xx.  This controller can
-act both as EP and RC.  This reuses the Designware core.
+Enables support for the PCIe controller in the DRA7xx SoC to work in
+host mode.
+
+config PCI_DRA7XX_EP
+   bool "PCI DRA7xx Endpoint Mode"
+   depends on PCI_ENDPOINT
+   select PCIE_DW_EP
+   help
+Enables support for the PCIe controller in the DRA7xx SoC to work in
+endpoint mode.
+
+endif
 
 config PCIE_DW_PLAT
bool "Platform bus based DesignWare PCIe Controller"
diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile
index b38425d..f31a859 100644
--- a/drivers/pci/dwc/Makefile
+++ b/drivers/pci/dwc/Makefile
@@ -2,7 +2,9 @@ obj-$(CONFIG_PCIE_DW) += pcie-designware.o
 obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
 obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
 obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
-obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
+ifneq ($(filter y,$(CONFIG_PCI_DRA7XX_HOST) $(CONFIG_PCI_DRA7XX_EP)),)
+obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
+endif
 obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
 obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
 obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
index 8d2d02f..47bb563 100644
--- a/drivers/pci/dwc/pci-dra7xx.c
+++ b/drivers/pci/dwc/pci-dra7xx.c
@@ -10,12 +10,14 @@
  * published by the Free Software Foundation.
  */
 
+#include 
 #include 
 #include 
 #include 
 #include 
 #include 
 #include 
+#include 
 #include 
 #include 
 #include 
@@ -57,6 +59,11 @@
 #defineMSI BIT(4)
 #defineLEG_EP_INTERRUPTS (INTA | INTB | INTC | INTD)
 
+#definePCIECTRL_TI_CONF_DEVICE_TYPE0x0100
+#defineDEVICE_TYPE_EP  0x0
+#defineDEVICE_TYPE_LEG_EP  0x1
+#defineDEVICE_TYPE_RC  0x4
+
 #definePCIECTRL_DRA7XX_CONF_DEVICE_CMD 0x0104
 #defineLTSSM_EN0x1
 
@@ -66,6 +73,13 @@
 
 #define EXP_CAP_ID_OFFSET  0x70
 
+#definePCIECTRL_TI_CONF_INTX_ASSERT0x0124
+#definePCIECTRL_TI_CONF_INTX_DEASSERT  0x0128
+
+#definePCIECTRL_TI_CONF_MSI_XMT0x012c
+#define MSI_REQ_GRANT  BIT(0)
+#define MSI_VECTOR_SHIFT   7
+
 struct dra7xx_pcie {
struct dw_pcie  *pci;
void __iomem*base;  /* DT ti_conf */
@@ -73,6 +87,11 @@ struct dra7xx_pcie {
struct phy  **phy;
int link_gen;
struct irq_domain   *irq_domain;
+   enum dw_pcie_device_mode mode;
+};
+
+struct dra7xx_pcie_of_data {
+   enum dw_pcie_device_mode mode;
 };
 
 #define to_dra7xx_pcie(x)  dev_get_drvdata((x)->dev)
@@ -101,9 +120,19 @@ static int dra7xx_pcie_link_up(struct dw_pcie *pci)
return !!(reg & LINK_UP);
 }
 
-static int dra7xx_pcie_establish_link(struct dra7xx_pcie *dra7xx)
+static void dra7xx_pcie_stop_link(struct dw_pcie *pci)
 {
-   struct dw_pcie *pci = dra7xx->pci;
+   struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
+   u32 reg;
+
+   reg = dra7xx_pcie_readl(dra7xx, PCI

[PATCH v2 12/22] dt-bindings: PCI: dra7xx: Add dt bindings for pci dra7xx EP mode

[Kishon Vijay Abraham I]

Add device tree binding documentation for pci dra7xx EP mode.

Acked-by: Rob Herring 
Signed-off-by: Kishon Vijay Abraham I 
---
 Documentation/devicetree/bindings/pci/ti-pci.txt |   37 ++
 1 file changed, 30 insertions(+), 7 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/ti-pci.txt 
b/Documentation/devicetree/bindings/pci/ti-pci.txt
index 60e2516..190828a 100644
--- a/Documentation/devicetree/bindings/pci/ti-pci.txt
+++ b/Documentation/devicetree/bindings/pci/ti-pci.txt
@@ -1,17 +1,22 @@
 TI PCI Controllers
 
 PCIe Designware Controller
- - compatible: Should be "ti,dra7-pcie""
- - reg : Two register ranges as listed in the reg-names property
- - reg-names : The first entry must be "ti-conf" for the TI specific registers
-  The second entry must be "rc-dbics" for the designware pcie
-  registers
-  The third entry must be "config" for the PCIe configuration space
+ - compatible: Should be "ti,dra7-pcie" for RC
+  Should be "ti,dra7-pcie-ep" for EP
  - phys : list of PHY specifiers (used by generic PHY framework)
  - phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
   number of PHYs as specified in *phys* property.
  - ti,hwmods : Name of the hwmod associated to the pcie, "pcie",
   where  is the instance number of the pcie from the HW spec.
+ - num-lanes as specified in ../designware-pcie.txt
+
+HOST MODE
+=
+ - reg : Two register ranges as listed in the reg-names property
+ - reg-names : The first entry must be "ti-conf" for the TI specific registers
+  The second entry must be "rc-dbics" for the designware pcie
+  registers
+  The third entry must be "config" for the PCIe configuration space
  - interrupts : Two interrupt entries must be specified. The first one is for
main interrupt line and the second for MSI interrupt line.
  - #address-cells,
@@ -19,13 +24,31 @@ PCIe Designware Controller
#interrupt-cells,
device_type,
ranges,
-   num-lanes,
interrupt-map-mask,
interrupt-map : as specified in ../designware-pcie.txt
 
+DEVICE MODE
+===
+ - reg : Four register ranges as listed in the reg-names property
+ - reg-names : "ti-conf" for the TI specific registers
+  "ep_dbics" for the standard configuration registers as
+   they are locally accessed within the DIF CS space
+  "ep_dbics2" for the standard configuration registers as
+   they are locally accessed within the DIF CS2 space
+  "addr_space" used to map remote RC address space
+ - interrupts : one interrupt entries must be specified for main interrupt.
+ - num-ib-windows : number of inbound address translation windows
+ - num-ob-windows : number of outbound address translation windows
+
 Optional Property:
  - gpios : Should be added if a gpio line is required to drive PERST# line
 
+NOTE: Two dt nodes may be added for each PCI controller; one for host
+mode and another for device mode. So in order for PCI to
+work in host mode, EP mode dt node should be disabled and in order to PCI to
+work in EP mode, host mode dt node should be disabled. And host mode and EP
+mode are mutually exclusive.
+
 Example:
 axi {
compatible = "simple-bus";
-- 
1.7.9.5

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[PATCH v2 13/22] PCI: dwc: dra7xx: Workaround for errata id i870

[Kishon Vijay Abraham I]

According to errata i870, access to the PCIe slave port
that are not 32-bit aligned will result in incorrect mapping
to TLP Address and Byte enable fields.

Accessing non 32-bit aligned data causes incorrect data in the target
buffer if memcpy is used. Implement the workaround for this
errata here.

Signed-off-by: Kishon Vijay Abraham I 
---
 drivers/pci/dwc/pci-dra7xx.c |   50 ++
 1 file changed, 50 insertions(+)

diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
index 47bb563..df11a49 100644
--- a/drivers/pci/dwc/pci-dra7xx.c
+++ b/drivers/pci/dwc/pci-dra7xx.c
@@ -26,6 +26,8 @@
 #include 
 #include 
 #include 
+#include 
+#include 
 
 #include "pcie-designware.h"
 
@@ -528,6 +530,48 @@ static int dra7xx_pcie_enable_phy(struct dra7xx_pcie 
*dra7xx)
{},
 };
 
+/*
+ * dra7xx_pcie_ep_legacy_mode: workaround for AM572x/AM571x Errata i870
+ * @dra7xx: the dra7xx device where the workaround should be applied
+ *
+ * Access to the PCIe slave port that are not 32-bit aligned will result
+ * in incorrect mapping to TLP Address and Byte enable fields. Therefore,
+ * byte and half-word accesses are not possible to byte offset 0x1, 0x2, or
+ * 0x3.
+ *
+ * To avoid this issue set PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE to 1.
+ */
+static int dra7xx_pcie_ep_legacy_mode(struct device *dev)
+{
+   int ret;
+   struct device_node *np = dev->of_node;
+   struct regmap *regmap;
+   unsigned int reg;
+   unsigned int field;
+
+   regmap = syscon_regmap_lookup_by_phandle(np, "syscon-legacy-mode");
+   if (IS_ERR(regmap)) {
+   dev_dbg(dev, "can't get syscon-legacy-mode\n");
+   return -EINVAL;
+   }
+
+   if (of_property_read_u32_index(np, "syscon-legacy-mode", 1, ®)) {
+   dev_err(dev, "couldn't get legacy mode register offset\n");
+   return -EINVAL;
+   }
+
+   if (of_property_read_u32_index(np, "syscon-legacy-mode", 2, &field)) {
+   dev_err(dev, "can't get bit field for setting legacy mode\n");
+   return -EINVAL;
+   }
+
+   ret = regmap_update_bits(regmap, reg, field, field);
+   if (ret)
+   dev_err(dev, "failed to set legacy mode\n");
+
+   return ret;
+}
+
 static int __init dra7xx_pcie_probe(struct platform_device *pdev)
 {
u32 reg;
@@ -644,6 +688,7 @@ static int __init dra7xx_pcie_probe(struct platform_device 
*pdev)
case DW_PCIE_RC_TYPE:
dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
   DEVICE_TYPE_RC);
+
ret = dra7xx_add_pcie_port(dra7xx, pdev);
if (ret < 0)
goto err_gpio;
@@ -651,6 +696,11 @@ static int __init dra7xx_pcie_probe(struct platform_device 
*pdev)
case DW_PCIE_EP_TYPE:
dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
   DEVICE_TYPE_EP);
+
+   ret = dra7xx_pcie_ep_legacy_mode(dev);
+   if (ret)
+   goto err_gpio;
+
ret = dra7xx_add_pcie_ep(dra7xx, pdev);
if (ret < 0)
goto err_gpio;
-- 
1.7.9.5

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[PATCH v2 15/22] PCI: Add device IDs for DRA74x and DRA72x

[Kishon Vijay Abraham I]

Add device IDs for DRA74x and DRA72x devices. These devices have
configurable PCI endpoint.

Signed-off-by: Kishon Vijay Abraham I 
---
 include/linux/pci_ids.h |2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 73dda0e..e8bbc4b 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -862,6 +862,8 @@
 #define PCI_DEVICE_ID_TI_X620  0xac8d
 #define PCI_DEVICE_ID_TI_X420  0xac8e
 #define PCI_DEVICE_ID_TI_XX20_FM   0xac8f
+#define PCI_DEVICE_ID_TI_DRA74x0xb500
+#define PCI_DEVICE_ID_TI_DRA72x0xb501
 
 #define PCI_VENDOR_ID_SONY 0x104d
 
-- 
1.7.9.5

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[PATCH v2 17/22] Documentation: misc-devices: Add Documentation for pci-endpoint-test driver

[Kishon Vijay Abraham I]

Add Documentation for pci-endpoint-test driver.

Signed-off-by: Kishon Vijay Abraham I 
---
 Documentation/misc-devices/pci-endpoint-test.txt |   35 ++
 1 file changed, 35 insertions(+)
 create mode 100644 Documentation/misc-devices/pci-endpoint-test.txt

diff --git a/Documentation/misc-devices/pci-endpoint-test.txt 
b/Documentation/misc-devices/pci-endpoint-test.txt
new file mode 100644
index 000..4385718
--- /dev/null
+++ b/Documentation/misc-devices/pci-endpoint-test.txt
@@ -0,0 +1,35 @@
+Driver for PCI Endpoint Test Function
+
+This driver should be used as a host side driver if the root complex is
+connected to a configurable pci endpoint running *pci_epf_test* function
+driver configured according to [1].
+
+The "pci_endpoint_test" driver can be used to perform the following tests.
+
+The PCI driver for the test device performs the following tests
+   *) verifying addresses programmed in BAR
+   *) raise legacy IRQ
+   *) raise MSI IRQ
+   *) read data
+   *) write data
+   *) copy data
+
+This misc driver creates /dev/pci-endpoint-test. for every
+*pci_epf_test* function connected to the root complex and "ioctls"
+should be used to perform the above tests.
+
+ioctl
+-
+ PCITEST_BAR: Tests the BAR. The number of the BAR that has to be tested
+ should be passed as argument.
+ PCITEST_LEGACY_IRQ: Tests legacy IRQ
+ PCITEST_MSI: Tests message signalled interrupts. The MSI number that has
+ to be tested should be passed as argument.
+ PCITEST_WRITE: Perform write tests. The size of the buffer should be passed
+   as argument.
+ PCITEST_READ: Perform read tests. The size of the buffer should be passed
+  as argument.
+ PCITEST_COPY: Perform read tests. The size of the buffer should be passed
+  as argument.
+
+[1] -> Documentation/PCI/endpoint/function/binding/pci-test.txt
-- 
1.7.9.5

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[PATCH v2 04/22] Documentation: PCI: Guide to use pci endpoint configfs

[Kishon Vijay Abraham I]

Add Documentation to help users use pci endpoint to configure
pci endpoint function and to bind the endpoint function
with endpoint controller.

Signed-off-by: Kishon Vijay Abraham I 
---
 Documentation/PCI/00-INDEX  |2 +
 Documentation/PCI/endpoint/pci-endpoint-cfs.txt |   84 +++
 2 files changed, 86 insertions(+)
 create mode 100644 Documentation/PCI/endpoint/pci-endpoint-cfs.txt

diff --git a/Documentation/PCI/00-INDEX b/Documentation/PCI/00-INDEX
index ba950b2..f84a23c 100644
--- a/Documentation/PCI/00-INDEX
+++ b/Documentation/PCI/00-INDEX
@@ -14,3 +14,5 @@ pcieaer-howto.txt
- the PCI Express Advanced Error Reporting Driver Guide HOWTO
 endpoint/pci-endpoint.txt
- guide to add endpoint controller driver and endpoint function driver.
+endpoint/pci-endpoint-cfs.txt
+   - guide to use configfs to configure the pci endpoint function.
diff --git a/Documentation/PCI/endpoint/pci-endpoint-cfs.txt 
b/Documentation/PCI/endpoint/pci-endpoint-cfs.txt
new file mode 100644
index 000..d9f8734
--- /dev/null
+++ b/Documentation/PCI/endpoint/pci-endpoint-cfs.txt
@@ -0,0 +1,84 @@
+   CONFIGURING PCI ENDPOINT USING CONFIGFS
+Kishon Vijay Abraham I 
+
+The PCI Endpoint Core exposes configfs entry (pci_ep) in order to configure the
+PCI endpoint function and in order to bind the endpoint function
+with the endpoint controller. (For introducing other mechanisms to
+configure the PCI Endpoint Function refer [1]).
+
+*) Mounting configfs
+
+The PCI Endpoint Core layer creates pci_ep directory in the mounted configfs
+directory. configfs can be mounted using the following command.
+
+   mount -t configfs none /sys/kernel/config
+
+*) Directory Structure
+
+The pci_ep configfs directory structure has been created to reflect the
+natural tree like structure of PCI devices. So every directory created
+inside pci_ep represents a EPC device and every directory created inside
+epf directory represents EPF device.
+
+/sys/kernel/config/pci_ep/
+| / --> [2]
+   | epc
+   | epf/
+| / --> [3]
+   | vendorid
+   | deviceid
+   | revid
+   | progif_code
+   | subclass_code
+   | baseclass_code
+   | cache_line_size
+   | subsys_vendor_id
+   | subsys_id
+   | interrupt_pin
+   | function
+
+*) Creating configfs entry for EPC
+
+Any directory created inside *pci_ep* represents an EPC device. In the above
+directory structure [2] represents an EPC device. It consists of
+
+   *) epc: Use it to associate the configfs entry to an actual EPC device.
+   The list of valid entries for this field can be obtained from
+   ls /sys/class/pci_epc/
+
+   *) epf: Directory that contains all the endpoint functions. The name
+   of the created directory determines the driver this particular
+   epf device will be bound to. The name can be obtained either
+   from the function binding documentation [4] or
+   ls /sys/bus/pci-epf/drivers
+
+   If more than one endpoint function device has to be bound to
+   the same driver, then the directory should be created using
+   the following notation
+   mkdir .
+
+*) Creating configfs entry for EPF
+
+Any directory created inside *epf* directory represents an EPF device. In the
+above directory structure, [3] represents an EPF device. It consists of the
+following entries that can be used to configure the standard configuration
+header of the endpoint function. (These entries are created by the
+framework when any new directory is created inside epf directory.)
+
+| vendorid
+| deviceid
+| revid
+| progif_code
+| subclass_code
+| baseclass_code
+| cache_line_size
+| subsys_vendor_id
+| subsys_id
+| interrupt_pin
+
+The following entry identifies the function driver that is bound to the
+function device
+   | function
+
+[1] -> Documentation/PCI/endpoint/pci-endpoint.txt
+[4] -> Documentation/PCI/endpoint/function/binding/
-- 
1.7.9.5

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[PATCH v2 01/22] PCI: endpoint: Add EP core layer to enable EP controller and EP functions

[Kishon Vijay Abraham I]

Introduce a new EP core layer in order to support endpoint functions
in linux kernel. This comprises of EPC library
(Endpoint Controller Library) and EPF library (Endpoint
Function Library). EPC library implements functions that is specific
to an endpoint controller and EPF library implements functions
that is specific to an endpoint function.

Signed-off-by: Kishon Vijay Abraham I 
---
 drivers/Makefile|2 +
 drivers/pci/Kconfig |1 +
 drivers/pci/endpoint/Kconfig|   21 ++
 drivers/pci/endpoint/Makefile   |6 +
 drivers/pci/endpoint/pci-epc-core.c |  548 +++
 drivers/pci/endpoint/pci-epc-mem.c  |  143 +
 drivers/pci/endpoint/pci-epf-core.c |  347 ++
 include/linux/mod_devicetable.h |   10 +
 include/linux/pci-epc.h |  141 +
 include/linux/pci-epf.h |  160 ++
 10 files changed, 1379 insertions(+)
 create mode 100644 drivers/pci/endpoint/Kconfig
 create mode 100644 drivers/pci/endpoint/Makefile
 create mode 100644 drivers/pci/endpoint/pci-epc-core.c
 create mode 100644 drivers/pci/endpoint/pci-epc-mem.c
 create mode 100644 drivers/pci/endpoint/pci-epf-core.c
 create mode 100644 include/linux/pci-epc.h
 create mode 100644 include/linux/pci-epf.h

diff --git a/drivers/Makefile b/drivers/Makefile
index f521cb0..a300bb1 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -14,7 +14,9 @@ obj-$(CONFIG_GENERIC_PHY) += phy/
 obj-$(CONFIG_PINCTRL)  += pinctrl/
 obj-$(CONFIG_GPIOLIB)  += gpio/
 obj-y  += pwm/
+
 obj-$(CONFIG_PCI)  += pci/
+obj-$(CONFIG_PCI_ENDPOINT) += pci/endpoint/
 # PCI dwc controller drivers
 obj-y  += pci/dwc/
 
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index df14142..9747c1e 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -134,3 +134,4 @@ config PCI_HYPERV
 source "drivers/pci/hotplug/Kconfig"
 source "drivers/pci/dwc/Kconfig"
 source "drivers/pci/host/Kconfig"
+source "drivers/pci/endpoint/Kconfig"
diff --git a/drivers/pci/endpoint/Kconfig b/drivers/pci/endpoint/Kconfig
new file mode 100644
index 000..7eb1c79
--- /dev/null
+++ b/drivers/pci/endpoint/Kconfig
@@ -0,0 +1,21 @@
+#
+# PCI Endpoint Support
+#
+
+menu "PCI Endpoint"
+
+config PCI_ENDPOINT
+   bool "PCI Endpoint Support"
+   select CONFIGFS_FS
+   help
+  Enable this configuration option to support configurable PCI
+  endpoint. This should be enabled if the platform has a PCI
+  controller that can operate in endpoint mode.
+
+  Enabling this option will build the endpoint library, which
+  includes endpoint controller library and endpoint function
+  library.
+
+  If in doubt, say "N" to disable Endpoint support.
+
+endmenu
diff --git a/drivers/pci/endpoint/Makefile b/drivers/pci/endpoint/Makefile
new file mode 100644
index 000..dc1bc16
--- /dev/null
+++ b/drivers/pci/endpoint/Makefile
@@ -0,0 +1,6 @@
+#
+# Makefile for PCI Endpoint Support
+#
+
+obj-$(CONFIG_PCI_ENDPOINT) += pci-epc-core.o pci-epf-core.o\
+  pci-epc-mem.o
diff --git a/drivers/pci/endpoint/pci-epc-core.c 
b/drivers/pci/endpoint/pci-epc-core.c
new file mode 100644
index 000..2c33e8a
--- /dev/null
+++ b/drivers/pci/endpoint/pci-epc-core.c
@@ -0,0 +1,548 @@
+/**
+ * PCI Endpoint *Controller* (EPC) library
+ *
+ * Copyright (C) 2017 Texas Instruments
+ * Author: Kishon Vijay Abraham I 
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+static struct class *pci_epc_class;
+
+static void devm_pci_epc_release(struct device *dev, void *res)
+{
+   struct pci_epc *epc = *(struct pci_epc **)res;
+
+   pci_epc_destroy(epc);
+}
+
+static int devm_pci_epc_match(struct device *dev, void *res, void *match_data)
+{
+   struct pci_epc **epc = res;
+
+   return *epc == match_data;
+}
+
+/**
+ * pci_epc_get() - get the pci endpoint controller
+ * @epc_name: device name of the endpoint controller
+ *
+ * Invoke to get struct pci_epc * corresponding to the device name of the
+ * endpoint controller
+ */
+struct pci_epc *pci_epc_get(char *epc_name)
+{
+   int ret = -EINVAL;
+   struct pci_epc *epc;
+   struct device *dev;
+   struct

[PATCH v2 16/22] misc: Add host side pci driver for pci test function device

[Kishon Vijay Abraham I]

Add PCI endpoint test driver that can verify base address
register, legacy interrupt/MSI interrupt and read/write/copy
buffers between host and device. The corresponding pci-epf-test
function driver should be used on the EP side.

Signed-off-by: Kishon Vijay Abraham I 
---
 drivers/misc/Kconfig |7 +
 drivers/misc/Makefile|1 +
 drivers/misc/pci_endpoint_test.c |  534 ++
 include/uapi/linux/Kbuild|1 +
 include/uapi/linux/pcitest.h |   19 ++
 5 files changed, 562 insertions(+)
 create mode 100644 drivers/misc/pci_endpoint_test.c
 create mode 100644 include/uapi/linux/pcitest.h

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 64971ba..14a95a6 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -766,6 +766,13 @@ config PANEL_BOOT_MESSAGE
  An empty message will only clear the display at driver init time. Any 
other
  printf()-formatted message is valid with newline and escape codes.
 
+config PCI_ENDPOINT_TEST
+   depends on PCI || COMPILE_TEST
+   tristate "PCI Endpoint Test driver"
+   ---help---
+   Enable this configuration option to enable the host side test driver
+   for PCI Endpoint.
+
 source "drivers/misc/c2port/Kconfig"
 source "drivers/misc/eeprom/Kconfig"
 source "drivers/misc/cb710/Kconfig"
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 3198336..64a532ac2 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -53,6 +53,7 @@ obj-$(CONFIG_ECHO)+= echo/
 obj-$(CONFIG_VEXPRESS_SYSCFG)  += vexpress-syscfg.o
 obj-$(CONFIG_CXL_BASE) += cxl/
 obj-$(CONFIG_PANEL) += panel.o
+obj-$(CONFIG_PCI_ENDPOINT_TEST)+= pci_endpoint_test.o
 
 lkdtm-$(CONFIG_LKDTM)  += lkdtm_core.o
 lkdtm-$(CONFIG_LKDTM)  += lkdtm_bugs.o
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
new file mode 100644
index 000..8239ace
--- /dev/null
+++ b/drivers/misc/pci_endpoint_test.c
@@ -0,0 +1,534 @@
+/**
+ * Host side test driver to test endpoint functionality
+ *
+ * Copyright (C) 2017 Texas Instruments
+ * Author: Kishon Vijay Abraham I 
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include 
+
+#define DRV_MODULE_NAME"pci-endpoint-test"
+
+#define PCI_ENDPOINT_TEST_MAGIC0x0
+
+#define PCI_ENDPOINT_TEST_COMMAND  0x4
+#define COMMAND_RAISE_LEGACY_IRQ   BIT(0)
+#define COMMAND_RAISE_MSI_IRQ  BIT(1)
+#define MSI_NUMBER_SHIFT   2
+/* 6 bits for MSI number */
+#define COMMAND_READBIT(8)
+#define COMMAND_WRITE   BIT(9)
+#define COMMAND_COPYBIT(10)
+
+#define PCI_ENDPOINT_TEST_STATUS   0x8
+#define STATUS_READ_SUCCESS BIT(0)
+#define STATUS_READ_FAILBIT(1)
+#define STATUS_WRITE_SUCCESSBIT(2)
+#define STATUS_WRITE_FAIL   BIT(3)
+#define STATUS_COPY_SUCCESS BIT(4)
+#define STATUS_COPY_FAILBIT(5)
+#define STATUS_IRQ_RAISED   BIT(6)
+#define STATUS_SRC_ADDR_INVALID BIT(7)
+#define STATUS_DST_ADDR_INVALID BIT(8)
+
+#define PCI_ENDPOINT_TEST_LOWER_SRC_ADDR   0xc
+#define PCI_ENDPOINT_TEST_UPPER_SRC_ADDR   0x10
+
+#define PCI_ENDPOINT_TEST_LOWER_DST_ADDR   0x14
+#define PCI_ENDPOINT_TEST_UPPER_DST_ADDR   0x18
+
+#define PCI_ENDPOINT_TEST_SIZE 0x1c
+#define PCI_ENDPOINT_TEST_CHECKSUM 0x20
+
+static DEFINE_IDA(pci_endpoint_test_ida);
+
+#define to_endpoint_test(priv) container_of((priv), struct pci_endpoint_test, \
+   miscdev)
+enum pci_barno {
+   BAR_0,
+   BAR_1,
+   BAR_2,
+   BAR_3,
+   BAR_4,
+   BAR_5,
+};
+
+struct pci_endpoint_test {
+   struct pci_dev  *pdev;
+   void __iomem*base;
+   void __iomem*bar[6];
+   struct completion irq_raised;
+   int last_irq;
+   /* mutex to protect the ioctls */
+   struct mutexmutex;
+   struct miscdevice miscdev;
+};
+
+static int bar_size[] = { 4, 512, 1024, 16384, 131072, 1048576 };
+
+static inline u32 pci_endpoint_test_readl(struct pci_endpo

[PATCH v2 19/22] tools: PCI: Add sample test script to invoke pcitest

[Kishon Vijay Abraham I]

Add a simple test script that invokes the pcitest userspace tool
to perform all the PCI endpoint tests (BAR tests, interrupt tests,
read tests, write tests and copy tests).

Signed-off-by: Kishon Vijay Abraham I 
---
 tools/pci/pcitest.sh |   56 ++
 1 file changed, 56 insertions(+)
 create mode 100644 tools/pci/pcitest.sh

diff --git a/tools/pci/pcitest.sh b/tools/pci/pcitest.sh
new file mode 100644
index 000..5442bbe
--- /dev/null
+++ b/tools/pci/pcitest.sh
@@ -0,0 +1,56 @@
+#!/bin/sh
+
+echo "BAR tests"
+echo
+
+bar=0
+
+while [ $bar -lt 6 ]
+do
+   pcitest -b $bar
+   bar=`expr $bar + 1`
+done
+echo
+
+echo "Interrupt tests"
+echo
+
+pcitest -l
+msi=1
+
+while [ $msi -lt 33 ]
+do
+pcitest -m $msi
+msi=`expr $msi + 1`
+done
+echo
+
+echo "Read Tests"
+echo
+
+pcitest -r -s 1
+pcitest -r -s 1024
+pcitest -r -s 1025
+pcitest -r -s 1024000
+pcitest -r -s 1024001
+echo
+
+echo "Write Tests"
+echo
+
+pcitest -w -s 1
+pcitest -w -s 1024
+pcitest -w -s 1025
+pcitest -w -s 1024000
+pcitest -w -s 1024001
+echo
+
+echo "Copy Tests"
+echo
+
+pcitest -c -s 1
+pcitest -c -s 1024
+pcitest -c -s 1025
+pcitest -c -s 1024000
+pcitest -c -s 1024001
+echo
-- 
1.7.9.5

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[PATCH v2 20/22] Documentation: PCI: Add userguide for PCI endpoint test function

[Kishon Vijay Abraham I]

Add documentation to help users use pci-epf-test function driver
and pci_endpoint_test host driver for testing PCI.

Signed-off-by: Kishon Vijay Abraham I 
---
 Documentation/PCI/endpoint/pci-test-howto.txt |  167 +
 1 file changed, 167 insertions(+)
 create mode 100644 Documentation/PCI/endpoint/pci-test-howto.txt

diff --git a/Documentation/PCI/endpoint/pci-test-howto.txt 
b/Documentation/PCI/endpoint/pci-test-howto.txt
new file mode 100644
index 000..4141b2b
--- /dev/null
+++ b/Documentation/PCI/endpoint/pci-test-howto.txt
@@ -0,0 +1,167 @@
+   PCI TEST USERGUIDE
+   Kishon Vijay Abraham I 
+
+This document is a guide to help users use pci-epf-test function driver
+and pci_endpoint_test host driver for testing PCI. The list of steps to
+be followed in the host side and EP side is given below.
+
+1. Endpoint Device
+
+1.1 Endpoint Controller Devices
+
+To find the list of endpoint controller devices in the system:
+
+   # ls /sys/class/pci_epc/
+ 5100.pcie_ep
+
+1.2 Endpoint Function Drivers
+
+To find the list of endpoint function drivers in the system:
+
+   # ls /sys/bus/pci-epf/drivers
+ pci_epf_test
+
+1.3 Creating pci-epf-test Device
+
+PCI endpoint function device can be created using the configfs. To create
+pci-epf-test device, the following commands can be used
+
+   # mount -t configfs none /sys/kernel/config
+   # cd /sys/kernel/config/pci_ep/
+   # mkdir dev
+   # mkdir dev/epf/pci_epf_test.0
+
+The "mkdir dev/epf/pci_epf_test.0" above creates the pci-epf-test function
+device. The name given to the directory preceding '.' should match with the
+name of the driver listed in '/sys/bus/pci-epf/drivers' in order for the
+device to be bound to the driver.
+
+The PCI endpoint framework populates the directory with configurable fields.
+
+   # ls dev/epf/pci_epf_test.0/
+ baseclass_codefunctionrevid   vendorid
+ cache_line_size   interrupt_pin   subclass_code
+ deviceid  peripheral  subsys_id
+ epc   progif_code subsys_vendor_id
+
+The pci endpoint function driver populates these entries with default values
+when the device is bound to the driver. The pci-epf-test driver populates
+vendorid with 0x and interrupt_pin with 0x0001
+
+   # cat dev/epf/pci_epf_test.0/vendorid
+ 0x
+   # cat dev/epf/pci_epf_test.0/interrupt_pin
+ 0x0001
+
+1.4 Configuring pci-epf-test Device
+
+The user can configure the pci-epf-test device using configfs entry. In order
+to change the vendorid and the number of MSI interrupts used by the function
+device, the following commands can be used.
+
+   # echo 0x104c > dev/epf/pci_epf_test.0/vendorid
+   # echo 0xb500 > dev/epf/pci_epf_test.0/deviceid
+   # echo 16 >  dev/epf/pci_epf_test.0/msi_interrupts
+
+1.5 Binding pci-epf-test Device to EP Controller
+
+In order for the endpoint function device to be useful, it has to be bound to
+a PCI endpoint controller driver. Use the configfs to bind the function
+device to one of the controller driver present in the system.
+
+   # echo "5100.pcie_ep" > dev/epc
+
+Once the above step is completed, the PCI endpoint is ready to establish a link
+with the host.
+
+2. Endpoint Device
+
+2.1 lspci Output
+
+Note that the devices listed here correspond to the value populated in 1.4 
above
+
+   00:00.0 PCI bridge: Texas Instruments Device  (rev 01)
+   01:00.0 Unassigned class [ff00]: Texas Instruments Device b500
+
+2.2 Using Endpoint Test function Device
+
+pcitest.sh added in tools/pci/ can be used to run all the default PCI endpoint
+tests. Before pcitest.sh can be used pcitest.c should be compiled using the
+following commands.
+
+   cd 
+   make headers_install ARCH=arm
+   arm-linux-gnueabihf-gcc -Iusr/include tools/pci/pcitest.c -o pcitest
+   cp pcitest  /usr/sbin/
+   cp tools/pci/pcitest.sh 
+
+2.2.1 pcitest.sh Output
+   # ./pcitest.sh
+   BAR tests
+
+   BAR0:   OKAY
+   BAR1:   OKAY
+   BAR2:   OKAY
+   BAR3:   OKAY
+   BAR4:   NOT OKAY
+   BAR5:   NOT OKAY
+
+   Interrupt tests
+
+   LEGACY IRQ: NOT OKAY
+   MSI1:   OKAY
+   MSI2:   OKAY
+   MSI3:   OKAY
+   MSI4:   OKAY
+   MSI5:   OKAY
+   MSI6:   OKAY
+   MSI7:   OKAY
+   MSI8:   OKAY
+   MSI9:   OKAY
+   MSI10:  OKAY
+   MSI11:  OKAY
+   MSI12:  OKAY
+   MSI13:  OKAY
+   MSI14:  OKAY
+   MSI15:  OKAY
+   MSI16:  OKAY
+   MSI17:  NOT OKAY
+   MSI18:  NOT OKAY
+   MSI19:  NOT OKAY
+   MSI20:  NOT OKAY
+   MSI21:  NOT OKAY
+   MSI22:  

[PATCH v2 18/22] tools: PCI: Add a userspace tool to test PCI endpoint

[Kishon Vijay Abraham I]

Add a userspace tool to invoke the ioctls exposed by the
PCI endpoint test driver to perform various PCI tests.

Signed-off-by: Kishon Vijay Abraham I 
---
 tools/pci/pcitest.c |  186 +++
 1 file changed, 186 insertions(+)
 create mode 100644 tools/pci/pcitest.c

diff --git a/tools/pci/pcitest.c b/tools/pci/pcitest.c
new file mode 100644
index 000..39b5b0b
--- /dev/null
+++ b/tools/pci/pcitest.c
@@ -0,0 +1,186 @@
+/**
+ * Userspace PCI Endpoint Test Module
+ *
+ * Copyright (C) 2017 Texas Instruments
+ * Author: Kishon Vijay Abraham I 
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#define BILLION 1E9
+
+static char *result[] = { "NOT OKAY", "OKAY" };
+
+struct pci_test {
+   char*device;
+   charbarnum;
+   boollegacyirq;
+   unsigned intmsinum;
+   boolread;
+   boolwrite;
+   boolcopy;
+   unsigned long   size;
+};
+
+static int run_test(struct pci_test *test)
+{
+   long ret;
+   int fd;
+   struct timespec start, end;
+   double time;
+
+   fd = open(test->device, O_RDWR);
+   if (fd < 0) {
+   perror("can't open PCI Endpoint Test device");
+   return fd;
+   }
+
+   if (test->barnum >= 0 && test->barnum <= 5) {
+   ret = ioctl(fd, PCITEST_BAR, test->barnum);
+   fprintf(stdout, "BAR%d:\t\t", test->barnum);
+   if (ret < 0)
+   fprintf(stdout, "TEST FAILED\n");
+   else
+   fprintf(stdout, "%s\n", result[ret]);
+   }
+
+   if (test->legacyirq) {
+   ret = ioctl(fd, PCITEST_LEGACY_IRQ, 0);
+   fprintf(stdout, "LEGACY IRQ:\t");
+   if (ret < 0)
+   fprintf(stdout, "TEST FAILED\n");
+   else
+   fprintf(stdout, "%s\n", result[ret]);
+   }
+
+   if (test->msinum > 0 && test->msinum <= 32) {
+   ret = ioctl(fd, PCITEST_MSI, test->msinum);
+   fprintf(stdout, "MSI%d:\t\t", test->msinum);
+   if (ret < 0)
+   fprintf(stdout, "TEST FAILED\n");
+   else
+   fprintf(stdout, "%s\n", result[ret]);
+   }
+
+   if (test->write) {
+   ret = ioctl(fd, PCITEST_WRITE, test->size);
+   fprintf(stdout, "WRITE (%7ld bytes):\t\t", test->size);
+   if (ret < 0)
+   fprintf(stdout, "TEST FAILED\n");
+   else
+   fprintf(stdout, "%s\n", result[ret]);
+   }
+
+   if (test->read) {
+   ret = ioctl(fd, PCITEST_READ, test->size);
+   fprintf(stdout, "READ (%7ld bytes):\t\t", test->size);
+   if (ret < 0)
+   fprintf(stdout, "TEST FAILED\n");
+   else
+   fprintf(stdout, "%s\n", result[ret]);
+   }
+
+   if (test->copy) {
+   ret = ioctl(fd, PCITEST_COPY, test->size);
+   fprintf(stdout, "COPY (%7ld bytes):\t\t", test->size);
+   if (ret < 0)
+   fprintf(stdout, "TEST FAILED\n");
+   else
+   fprintf(stdout, "%s\n", result[ret]);
+   }
+
+   fflush(stdout);
+}
+
+int main(int argc, char **argv)
+{
+   int c;
+   struct pci_test *test;
+
+   test = calloc(1, sizeof(*test));
+   if (!test) {
+   perror("Fail to allocate memory for pci_test\n");
+   return -ENOMEM;
+   }
+
+   /* since '0' is a valid BAR number, initialize it to -1 */
+   test->barnum = -1;
+
+   /* set default size as 100KB */
+   test->size = 0x19000;
+
+   /* set default endpoint device */
+   test->device = "/dev/pci-endpoint-test.0";
+
+   while ((c = getopt(argc, argv, "D:b:m:lrwcs:")) != EOF)
+   switch (c) {
+   case 'D':
+   test->device = optarg;
+   continue;
+   case 'b':
+   test->barnum = atoi(optarg);
+   if (test->barnum < 0 || test->barnum > 5)
+   goto usage;
+   continue;
+   case 'l':
+   test->legacyirq = true;
+   cont

[PATCH v2 08/22] PCI: dwc: designware: Add EP mode support

[Kishon Vijay Abraham I]

Add endpoint mode support to designware driver. This uses the
EP Core layer introduced recently to add endpoint mode support.
*Any* function driver can now use this designware device
in order to achieve the EP functionality.

Signed-off-by: Kishon Vijay Abraham I 
---
 drivers/pci/dwc/Kconfig  |5 +
 drivers/pci/dwc/Makefile |1 +
 drivers/pci/dwc/pcie-designware-ep.c |  342 ++
 drivers/pci/dwc/pcie-designware.c|   51 +
 drivers/pci/dwc/pcie-designware.h|   72 +++
 5 files changed, 471 insertions(+)
 create mode 100644 drivers/pci/dwc/pcie-designware-ep.c

diff --git a/drivers/pci/dwc/Kconfig b/drivers/pci/dwc/Kconfig
index dfb8a69..00335c7 100644
--- a/drivers/pci/dwc/Kconfig
+++ b/drivers/pci/dwc/Kconfig
@@ -9,6 +9,11 @@ config PCIE_DW_HOST
depends on PCI_MSI_IRQ_DOMAIN
 select PCIE_DW
 
+config PCIE_DW_EP
+   bool
+   depends on PCI_ENDPOINT
+   select PCIE_DW
+
 config PCI_DRA7XX
bool "TI DRA7xx PCIe controller"
depends on PCI
diff --git a/drivers/pci/dwc/Makefile b/drivers/pci/dwc/Makefile
index a2df13c..b38425d 100644
--- a/drivers/pci/dwc/Makefile
+++ b/drivers/pci/dwc/Makefile
@@ -1,5 +1,6 @@
 obj-$(CONFIG_PCIE_DW) += pcie-designware.o
 obj-$(CONFIG_PCIE_DW_HOST) += pcie-designware-host.o
+obj-$(CONFIG_PCIE_DW_EP) += pcie-designware-ep.o
 obj-$(CONFIG_PCIE_DW_PLAT) += pcie-designware-plat.o
 obj-$(CONFIG_PCI_DRA7XX) += pci-dra7xx.o
 obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
diff --git a/drivers/pci/dwc/pcie-designware-ep.c 
b/drivers/pci/dwc/pcie-designware-ep.c
new file mode 100644
index 000..e465c5e
--- /dev/null
+++ b/drivers/pci/dwc/pcie-designware-ep.c
@@ -0,0 +1,342 @@
+/**
+ * Synopsys Designware PCIe Endpoint controller driver
+ *
+ * Copyright (C) 2017 Texas Instruments
+ * Author: Kishon Vijay Abraham I 
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+#include 
+
+#include "pcie-designware.h"
+#include 
+#include 
+
+void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
+{
+   struct pci_epc *epc = ep->epc;
+   struct pci_epf *epf;
+
+   list_for_each_entry(epf, &epc->pci_epf, list)
+   pci_epf_linkup(epf);
+}
+
+static void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
+{
+   u32 reg;
+
+   reg = PCI_BASE_ADDRESS_0 + (4 * bar);
+   dw_pcie_write_dbi(pci, pci->dbi_base2, reg, 0x4, 0x0);
+   dw_pcie_write_dbi(pci, pci->dbi_base, reg, 0x4, 0x0);
+}
+
+static int dw_pcie_ep_write_header(struct pci_epc *epc,
+  struct pci_epf_header *hdr)
+{
+   struct dw_pcie_ep *ep = epc_get_drvdata(epc);
+   struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+   void __iomem *base = pci->dbi_base;
+
+   dw_pcie_write_dbi(pci, base, PCI_VENDOR_ID, 0x2, hdr->vendorid);
+   dw_pcie_write_dbi(pci, base, PCI_DEVICE_ID, 0x2, hdr->deviceid);
+   dw_pcie_write_dbi(pci, base, PCI_REVISION_ID, 0x1, hdr->revid);
+   dw_pcie_write_dbi(pci, base, PCI_CLASS_PROG, 0x1, hdr->progif_code);
+   dw_pcie_write_dbi(pci, base, PCI_CLASS_DEVICE, 0x2,
+ hdr->subclass_code | hdr->baseclass_code << 8);
+   dw_pcie_write_dbi(pci, base, PCI_CACHE_LINE_SIZE, 0x1,
+ hdr->cache_line_size);
+   dw_pcie_write_dbi(pci, base, PCI_SUBSYSTEM_VENDOR_ID, 0x2,
+ hdr->subsys_vendor_id);
+   dw_pcie_write_dbi(pci, base, PCI_SUBSYSTEM_ID, 0x2, hdr->subsys_id);
+   dw_pcie_write_dbi(pci, base, PCI_INTERRUPT_PIN, 0x1,
+ hdr->interrupt_pin);
+
+   return 0;
+}
+
+static int dw_pcie_ep_inbound_atu(struct dw_pcie_ep *ep, enum pci_barno bar,
+ dma_addr_t cpu_addr,
+ enum dw_pcie_as_type as_type)
+{
+   int ret;
+   u32 free_win;
+   struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+
+   free_win = find_first_zero_bit(&ep->ib_window_map,
+  sizeof(ep->ib_window_map));
+   if (free_win >= ep->num_ib_windows) {
+   dev_err(pci->dev, "no free inbound window\n");
+   return -EINVAL;
+   }
+
+   ret = dw_pcie_prog_inbound_atu(pci, free_win, bar, cpu_addr,
+  as_type);
+   if (ret < 0) {
+   dev_err(pci->dev, "Failed to program IB window\n");
+   retu

[PATCH v2 21/22] MAINTAINERS: add PCI EP maintainer

[Kishon Vijay Abraham I]

Add maintainer for the newly introduced PCI EP framework.

Signed-off-by: Kishon Vijay Abraham I 
---
 MAINTAINERS |9 +
 1 file changed, 9 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 8672f18..62b86af 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9407,6 +9407,15 @@ F:   include/linux/pci*
 F: arch/x86/pci/
 F: arch/x86/kernel/quirks.c
 
+PCI EP SUBSYSTEM
+M: Kishon Vijay Abraham I 
+L: linux-...@vger.kernel.org
+T: git 
git://git.kernel.org/pub/scm/linux/kernel/git/kishon/pci-endpoint.git
+S: Supported
+F: drivers/pci/endpoint/
+F: drivers/misc/pci_endpoint_test.c
+F: tools/pci/
+
 PCI DRIVER FOR ALTERA PCIE IP
 M: Ley Foon Tan 
 L: r...@lists.rocketboards.org (moderated for non-subscribers)
-- 
1.7.9.5

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[PATCH v2 22/22] ARM: DRA7: clockdomain: Change the CLKTRCTRL of CM_PCIE_CLKSTCTRL to SW_WKUP

[Kishon Vijay Abraham I]

The PCIe programming sequence in TRM suggests CLKSTCTRL of PCIe should
be set to SW_WKUP. There are no issues when CLKSTCTRL is set to HW_AUTO
in RC mode. However in EP mode, the host system is not able to access the
MEMSPACE and setting the CLKSTCTRL to SW_WKUP fixes it.

Acked-by: Tony Lindgren 
Signed-off-by: Kishon Vijay Abraham I 
---
 arch/arm/mach-omap2/clockdomains7xx_data.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/mach-omap2/clockdomains7xx_data.c 
b/arch/arm/mach-omap2/clockdomains7xx_data.c
index 6c67965..67ebff8 100644
--- a/arch/arm/mach-omap2/clockdomains7xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains7xx_data.c
@@ -524,7 +524,7 @@
.dep_bit  = DRA7XX_PCIE_STATDEP_SHIFT,
.wkdep_srcs   = pcie_wkup_sleep_deps,
.sleepdep_srcs= pcie_wkup_sleep_deps,
-   .flags= CLKDM_CAN_HWSUP_SWSUP,
+   .flags= CLKDM_CAN_SWSUP,
 };
 
 static struct clockdomain atl_7xx_clkdm = {
-- 
1.7.9.5

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[PATCH v2 06/22] PCI: endpoint: functions: Add an EP function to test PCI

[Kishon Vijay Abraham I]

Adds a new endpoint function driver (to program the virtual
test device) making use of the EP-core library.

Signed-off-by: Kishon Vijay Abraham I 
---
 drivers/pci/endpoint/Kconfig  |2 +
 drivers/pci/endpoint/Makefile |2 +-
 drivers/pci/endpoint/functions/Kconfig|   12 +
 drivers/pci/endpoint/functions/Makefile   |5 +
 drivers/pci/endpoint/functions/pci-epf-test.c |  513 +
 5 files changed, 533 insertions(+), 1 deletion(-)
 create mode 100644 drivers/pci/endpoint/functions/Kconfig
 create mode 100644 drivers/pci/endpoint/functions/Makefile
 create mode 100644 drivers/pci/endpoint/functions/pci-epf-test.c

diff --git a/drivers/pci/endpoint/Kconfig b/drivers/pci/endpoint/Kconfig
index 8470f0b..f8455d7 100644
--- a/drivers/pci/endpoint/Kconfig
+++ b/drivers/pci/endpoint/Kconfig
@@ -28,4 +28,6 @@ config PCI_ENDPOINT_CONFIGFS
   configure the endpoint function and used to bind the
   function with a endpoint controller.
 
+source "drivers/pci/endpoint/functions/Kconfig"
+
 endmenu
diff --git a/drivers/pci/endpoint/Makefile b/drivers/pci/endpoint/Makefile
index dd9163c..a3d4c57 100644
--- a/drivers/pci/endpoint/Makefile
+++ b/drivers/pci/endpoint/Makefile
@@ -3,5 +3,5 @@
 #
 
 obj-$(CONFIG_PCI_ENDPOINT) += pci-epc-core.o pci-epf-core.o\
-  pci-epc-mem.o
+  pci-epc-mem.o functions/
 obj-$(CONFIG_PCI_ENDPOINT_CONFIGFS)+= pci-ep-cfs.o
diff --git a/drivers/pci/endpoint/functions/Kconfig 
b/drivers/pci/endpoint/functions/Kconfig
new file mode 100644
index 000..175edad
--- /dev/null
+++ b/drivers/pci/endpoint/functions/Kconfig
@@ -0,0 +1,12 @@
+#
+# PCI Endpoint Functions
+#
+
+config PCI_EPF_TEST
+   tristate "PCI Endpoint Test driver"
+   depends on PCI_ENDPOINT
+   help
+  Enable this configuration option to enable the test driver
+  for PCI Endpoint.
+
+  If in doubt, say "N" to disable Endpoint test driver.
diff --git a/drivers/pci/endpoint/functions/Makefile 
b/drivers/pci/endpoint/functions/Makefile
new file mode 100644
index 000..6d94a48
--- /dev/null
+++ b/drivers/pci/endpoint/functions/Makefile
@@ -0,0 +1,5 @@
+#
+# Makefile for PCI Endpoint Functions
+#
+
+obj-$(CONFIG_PCI_EPF_TEST) += pci-epf-test.o
diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c 
b/drivers/pci/endpoint/functions/pci-epf-test.c
new file mode 100644
index 000..bbac323
--- /dev/null
+++ b/drivers/pci/endpoint/functions/pci-epf-test.c
@@ -0,0 +1,513 @@
+/**
+ * Test driver to test endpoint functionality
+ *
+ * Copyright (C) 2017 Texas Instruments
+ * Author: Kishon Vijay Abraham I 
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see .
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+
+#define COMMAND_RAISE_LEGACY_IRQ   BIT(0)
+#define COMMAND_RAISE_MSI_IRQ  BIT(1)
+#define MSI_NUMBER_SHIFT   2
+#define MSI_NUMBER_MASK(0x3f << MSI_NUMBER_SHIFT)
+#define COMMAND_READ   BIT(8)
+#define COMMAND_WRITE  BIT(9)
+#define COMMAND_COPY   BIT(10)
+
+#define STATUS_READ_SUCCESSBIT(0)
+#define STATUS_READ_FAIL   BIT(1)
+#define STATUS_WRITE_SUCCESS   BIT(2)
+#define STATUS_WRITE_FAIL  BIT(3)
+#define STATUS_COPY_SUCCESSBIT(4)
+#define STATUS_COPY_FAIL   BIT(5)
+#define STATUS_IRQ_RAISED  BIT(6)
+#define STATUS_SRC_ADDR_INVALIDBIT(7)
+#define STATUS_DST_ADDR_INVALIDBIT(8)
+
+#define TIMER_RESOLUTION   1
+
+static struct workqueue_struct *kpcitest_workqueue;
+
+struct pci_epf_test {
+   void*reg[6];
+   struct pci_epf  *epf;
+   struct delayed_work cmd_handler;
+};
+
+struct pci_epf_test_reg {
+   u32 magic;
+   u32 command;
+   u32 status;
+   u64 src_addr;
+   u64 dst_addr;
+   u32 size;
+   u32 checksum;
+} __packed;
+
+static struct pci_epf_header test_header = {
+   .vendorid   = PCI_ANY_ID,
+   .deviceid   = PCI_ANY_ID,
+   .baseclass_code = PCI_CLASS_OTHERS,
+   .interrupt_pin  = PCI_INTERRUPT_INTA,
+};
+
+static int bar_size[] = { 512, 

Re: [PATCHv3 2/2] arch: Rename CONFIG_DEBUG_RODATA and CONFIG_DEBUG_MODULE_RONX

[Helge Deller]

On 17.02.2017 02:08, Kees Cook wrote:
> On Thu, Feb 16, 2017 at 2:25 PM, Pavel Machek  wrote:
>> Hi!
>>
>>>
>>> -config DEBUG_RODATA
>>> +config STRICT_KERNEL_RWX
>>>   bool "Make kernel text and rodata read-only" if 
>>> ARCH_OPTIONAL_KERNEL_RWX
>>>   depends on ARCH_HAS_STRICT_KERNEL_RWX
>>>   default !ARCH_OPTIONAL_KERNEL_RWX ||
>>
>> Debug features are expected to have runtime cost, so kconfig help is
>> silent about those. But there are runtime costs, right? It would be
>> nice to mention them in the help text...
> 
> It depends on the architecture. The prior help text for arm said:
> 
>  The tradeoff is that each region is padded to section-size (1MiB)
>  boundaries (because their permissions are different and splitting
>  the 1M pages into 4K ones causes TLB performance problems), which
>  can waste memory.
> 
> parisc (somewhat inaccurately) said:
> 
>  This option may have a slight performance impact because a
>  portion of the kernel code won't be covered by a TLB anymore.

The logic on parisc is actually:
If huge page support is enabled, we map 1MB pages (and behave like arm wrt 
alignments).
If huge page support is disabled we stay at 4k/PAGE_SIZE pages (without 1M 
alignment).
 
> IIUC, arm64 does what parisc is hinting at: mappings at the end are
> broken down to PAGE_SIZE. 

On parisc we never implemented that.

> On x86, IIUC, there's actually no change to
> TLB performance due to how the mappings are already set up.
> 
> I'm not sure the best way to express this in the new help text. Do you
> have some suggestions on wording? Personally, I don't really think
> it's worth mentioning this in Kconfig help,

I agree on this.

> which, in theory, is
> supposed to limit how technical it gets. And I think the performance
> impact is almost entirely negligible compared to the risks addressed.

Helge
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